Commit | Line | Data |
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1361b83a LT |
1 | /* |
2 | * Copyright (C) 1994 Linus Torvalds | |
3 | * | |
4 | * Pentium III FXSR, SSE support | |
5 | * General FPU state handling cleanups | |
6 | * Gareth Hughes <gareth@valinux.com>, May 2000 | |
7 | * x86-64 work by Andi Kleen 2002 | |
8 | */ | |
9 | ||
78f7f1e5 IM |
10 | #ifndef _ASM_X86_FPU_INTERNAL_H |
11 | #define _ASM_X86_FPU_INTERNAL_H | |
1361b83a | 12 | |
050902c0 | 13 | #include <linux/compat.h> |
952f07ec | 14 | #include <linux/sched.h> |
1361b83a | 15 | #include <linux/slab.h> |
f89e32e0 | 16 | |
1361b83a | 17 | #include <asm/user.h> |
df6b35f4 | 18 | #include <asm/fpu/api.h> |
669ebabb | 19 | #include <asm/fpu/xstate.h> |
cd4d09ec | 20 | #include <asm/cpufeature.h> |
d1898b73 | 21 | #include <asm/trace/fpu.h> |
1361b83a | 22 | |
6ffc152e IM |
23 | /* |
24 | * High level FPU state handling functions: | |
25 | */ | |
2ce03d85 | 26 | extern void fpu__initialize(struct fpu *fpu); |
369a036d IM |
27 | extern void fpu__prepare_read(struct fpu *fpu); |
28 | extern void fpu__prepare_write(struct fpu *fpu); | |
6ffc152e | 29 | extern void fpu__save(struct fpu *fpu); |
e1884d69 | 30 | extern void fpu__restore(struct fpu *fpu); |
82c0e45e | 31 | extern int fpu__restore_sig(void __user *buf, int ia32_frame); |
6ffc152e IM |
32 | extern void fpu__drop(struct fpu *fpu); |
33 | extern int fpu__copy(struct fpu *dst_fpu, struct fpu *src_fpu); | |
04c8e01d | 34 | extern void fpu__clear(struct fpu *fpu); |
b1b64dc3 IM |
35 | extern int fpu__exception_code(struct fpu *fpu, int trap_nr); |
36 | extern int dump_fpu(struct pt_regs *ptregs, struct user_i387_struct *fpstate); | |
6ffc152e | 37 | |
b1b64dc3 IM |
38 | /* |
39 | * Boot time FPU initialization functions: | |
40 | */ | |
41 | extern void fpu__init_cpu(void); | |
42 | extern void fpu__init_system_xstate(void); | |
43 | extern void fpu__init_cpu_xstate(void); | |
44 | extern void fpu__init_system(struct cpuinfo_x86 *c); | |
952f07ec IM |
45 | extern void fpu__init_check_bugs(void); |
46 | extern void fpu__resume_cpu(void); | |
a5fe93a5 | 47 | extern u64 fpu__get_supported_xfeatures_mask(void); |
952f07ec | 48 | |
e97131a8 IM |
49 | /* |
50 | * Debugging facility: | |
51 | */ | |
52 | #ifdef CONFIG_X86_DEBUG_FPU | |
53 | # define WARN_ON_FPU(x) WARN_ON_ONCE(x) | |
54 | #else | |
83242c51 | 55 | # define WARN_ON_FPU(x) ({ (void)(x); 0; }) |
e97131a8 IM |
56 | #endif |
57 | ||
1c927eea | 58 | /* |
b1b64dc3 | 59 | * FPU related CPU feature flag helper routines: |
1c927eea | 60 | */ |
1361b83a LT |
61 | static __always_inline __pure bool use_xsaveopt(void) |
62 | { | |
bc696ca0 | 63 | return static_cpu_has(X86_FEATURE_XSAVEOPT); |
1361b83a LT |
64 | } |
65 | ||
66 | static __always_inline __pure bool use_xsave(void) | |
67 | { | |
bc696ca0 | 68 | return static_cpu_has(X86_FEATURE_XSAVE); |
1361b83a LT |
69 | } |
70 | ||
71 | static __always_inline __pure bool use_fxsr(void) | |
72 | { | |
bc696ca0 | 73 | return static_cpu_has(X86_FEATURE_FXSR); |
1361b83a LT |
74 | } |
75 | ||
b1b64dc3 IM |
76 | /* |
77 | * fpstate handling functions: | |
78 | */ | |
79 | ||
80 | extern union fpregs_state init_fpstate; | |
81 | ||
82 | extern void fpstate_init(union fpregs_state *state); | |
83 | #ifdef CONFIG_MATH_EMULATION | |
84 | extern void fpstate_init_soft(struct swregs_state *soft); | |
85 | #else | |
86 | static inline void fpstate_init_soft(struct swregs_state *soft) {} | |
87 | #endif | |
a5828ed3 YY |
88 | |
89 | static inline void fpstate_init_xstate(struct xregs_state *xsave) | |
90 | { | |
91 | /* | |
92 | * XRSTORS requires these bits set in xcomp_bv, or it will | |
93 | * trigger #GP: | |
94 | */ | |
95 | xsave->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT | xfeatures_mask; | |
96 | } | |
97 | ||
b1b64dc3 IM |
98 | static inline void fpstate_init_fxstate(struct fxregs_state *fx) |
99 | { | |
100 | fx->cwd = 0x37f; | |
101 | fx->mxcsr = MXCSR_DEFAULT; | |
102 | } | |
36e49e7f | 103 | extern void fpstate_sanitize_xstate(struct fpu *fpu); |
1361b83a | 104 | |
49b8c695 PA |
105 | #define user_insn(insn, output, input...) \ |
106 | ({ \ | |
107 | int err; \ | |
108 | asm volatile(ASM_STAC "\n" \ | |
109 | "1:" #insn "\n\t" \ | |
110 | "2: " ASM_CLAC "\n" \ | |
111 | ".section .fixup,\"ax\"\n" \ | |
112 | "3: movl $-1,%[err]\n" \ | |
113 | " jmp 2b\n" \ | |
114 | ".previous\n" \ | |
115 | _ASM_EXTABLE(1b, 3b) \ | |
116 | : [err] "=r" (err), output \ | |
117 | : "0"(0), input); \ | |
118 | err; \ | |
119 | }) | |
120 | ||
d5c8028b | 121 | #define kernel_insn(insn, output, input...) \ |
0ca5bd0d SS |
122 | asm volatile("1:" #insn "\n\t" \ |
123 | "2:\n" \ | |
d5c8028b EB |
124 | _ASM_EXTABLE_HANDLE(1b, 2b, ex_handler_fprestore) \ |
125 | : output : input) | |
0ca5bd0d | 126 | |
c47ada30 | 127 | static inline int copy_fregs_to_user(struct fregs_state __user *fx) |
1361b83a | 128 | { |
49b8c695 | 129 | return user_insn(fnsave %[fx]; fwait, [fx] "=m" (*fx), "m" (*fx)); |
1361b83a LT |
130 | } |
131 | ||
c47ada30 | 132 | static inline int copy_fxregs_to_user(struct fxregs_state __user *fx) |
1361b83a | 133 | { |
97f2645f | 134 | if (IS_ENABLED(CONFIG_X86_32)) |
49b8c695 | 135 | return user_insn(fxsave %[fx], [fx] "=m" (*fx), "m" (*fx)); |
97f2645f | 136 | else if (IS_ENABLED(CONFIG_AS_FXSAVEQ)) |
49b8c695 | 137 | return user_insn(fxsaveq %[fx], [fx] "=m" (*fx), "m" (*fx)); |
1361b83a | 138 | |
c6813144 | 139 | /* See comment in copy_fxregs_to_kernel() below. */ |
49b8c695 | 140 | return user_insn(rex64/fxsave (%[fx]), "=m" (*fx), [fx] "R" (fx)); |
1361b83a LT |
141 | } |
142 | ||
9ccc27a5 | 143 | static inline void copy_kernel_to_fxregs(struct fxregs_state *fx) |
1361b83a | 144 | { |
97f2645f | 145 | if (IS_ENABLED(CONFIG_X86_32)) { |
d5c8028b | 146 | kernel_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
43b287b3 | 147 | } else { |
97f2645f | 148 | if (IS_ENABLED(CONFIG_AS_FXSAVEQ)) { |
d5c8028b | 149 | kernel_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); |
43b287b3 IM |
150 | } else { |
151 | /* See comment in copy_fxregs_to_kernel() below. */ | |
d5c8028b | 152 | kernel_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), "m" (*fx)); |
43b287b3 IM |
153 | } |
154 | } | |
1361b83a LT |
155 | } |
156 | ||
c47ada30 | 157 | static inline int copy_user_to_fxregs(struct fxregs_state __user *fx) |
e139e955 | 158 | { |
97f2645f | 159 | if (IS_ENABLED(CONFIG_X86_32)) |
e139e955 | 160 | return user_insn(fxrstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
97f2645f | 161 | else if (IS_ENABLED(CONFIG_AS_FXSAVEQ)) |
e139e955 PA |
162 | return user_insn(fxrstorq %[fx], "=m" (*fx), [fx] "m" (*fx)); |
163 | ||
c6813144 | 164 | /* See comment in copy_fxregs_to_kernel() below. */ |
e139e955 PA |
165 | return user_insn(rex64/fxrstor (%[fx]), "=m" (*fx), [fx] "R" (fx), |
166 | "m" (*fx)); | |
167 | } | |
168 | ||
9ccc27a5 | 169 | static inline void copy_kernel_to_fregs(struct fregs_state *fx) |
1361b83a | 170 | { |
d5c8028b | 171 | kernel_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); |
e139e955 PA |
172 | } |
173 | ||
c47ada30 | 174 | static inline int copy_user_to_fregs(struct fregs_state __user *fx) |
e139e955 PA |
175 | { |
176 | return user_insn(frstor %[fx], "=m" (*fx), [fx] "m" (*fx)); | |
1361b83a LT |
177 | } |
178 | ||
c6813144 | 179 | static inline void copy_fxregs_to_kernel(struct fpu *fpu) |
1361b83a | 180 | { |
97f2645f | 181 | if (IS_ENABLED(CONFIG_X86_32)) |
7366ed77 | 182 | asm volatile( "fxsave %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
97f2645f | 183 | else if (IS_ENABLED(CONFIG_AS_FXSAVEQ)) |
7366ed77 | 184 | asm volatile("fxsaveq %[fx]" : [fx] "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
185 | else { |
186 | /* Using "rex64; fxsave %0" is broken because, if the memory | |
187 | * operand uses any extended registers for addressing, a second | |
188 | * REX prefix will be generated (to the assembler, rex64 | |
189 | * followed by semicolon is a separate instruction), and hence | |
190 | * the 64-bitness is lost. | |
191 | * | |
192 | * Using "fxsaveq %0" would be the ideal choice, but is only | |
193 | * supported starting with gas 2.16. | |
194 | * | |
195 | * Using, as a workaround, the properly prefixed form below | |
196 | * isn't accepted by any binutils version so far released, | |
197 | * complaining that the same type of prefix is used twice if | |
198 | * an extended register is needed for addressing (fix submitted | |
199 | * to mainline 2005-11-21). | |
200 | * | |
7366ed77 | 201 | * asm volatile("rex64/fxsave %0" : "=m" (fpu->state.fxsave)); |
0ca5bd0d SS |
202 | * |
203 | * This, however, we can work around by forcing the compiler to | |
204 | * select an addressing mode that doesn't require extended | |
205 | * registers. | |
206 | */ | |
207 | asm volatile( "rex64/fxsave (%[fx])" | |
7366ed77 IM |
208 | : "=m" (fpu->state.fxsave) |
209 | : [fx] "R" (&fpu->state.fxsave)); | |
0ca5bd0d | 210 | } |
1361b83a LT |
211 | } |
212 | ||
fd169b05 IM |
213 | /* These macros all use (%edi)/(%rdi) as the single memory argument. */ |
214 | #define XSAVE ".byte " REX_PREFIX "0x0f,0xae,0x27" | |
215 | #define XSAVEOPT ".byte " REX_PREFIX "0x0f,0xae,0x37" | |
216 | #define XSAVES ".byte " REX_PREFIX "0x0f,0xc7,0x2f" | |
217 | #define XRSTOR ".byte " REX_PREFIX "0x0f,0xae,0x2f" | |
218 | #define XRSTORS ".byte " REX_PREFIX "0x0f,0xc7,0x1f" | |
219 | ||
b74a0cf1 BP |
220 | #define XSTATE_OP(op, st, lmask, hmask, err) \ |
221 | asm volatile("1:" op "\n\t" \ | |
222 | "xor %[err], %[err]\n" \ | |
223 | "2:\n\t" \ | |
224 | ".pushsection .fixup,\"ax\"\n\t" \ | |
225 | "3: movl $-2,%[err]\n\t" \ | |
226 | "jmp 2b\n\t" \ | |
227 | ".popsection\n\t" \ | |
228 | _ASM_EXTABLE(1b, 3b) \ | |
229 | : [err] "=r" (err) \ | |
230 | : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ | |
231 | : "memory") | |
232 | ||
b7106fa0 BP |
233 | /* |
234 | * If XSAVES is enabled, it replaces XSAVEOPT because it supports a compact | |
235 | * format and supervisor states in addition to modified optimization in | |
236 | * XSAVEOPT. | |
237 | * | |
238 | * Otherwise, if XSAVEOPT is enabled, XSAVEOPT replaces XSAVE because XSAVEOPT | |
239 | * supports modified optimization which is not supported by XSAVE. | |
240 | * | |
241 | * We use XSAVE as a fallback. | |
242 | * | |
243 | * The 661 label is defined in the ALTERNATIVE* macros as the address of the | |
244 | * original instruction which gets replaced. We need to use it here as the | |
245 | * address of the instruction where we might get an exception at. | |
246 | */ | |
247 | #define XSTATE_XSAVE(st, lmask, hmask, err) \ | |
248 | asm volatile(ALTERNATIVE_2(XSAVE, \ | |
249 | XSAVEOPT, X86_FEATURE_XSAVEOPT, \ | |
250 | XSAVES, X86_FEATURE_XSAVES) \ | |
251 | "\n" \ | |
252 | "xor %[err], %[err]\n" \ | |
253 | "3:\n" \ | |
254 | ".pushsection .fixup,\"ax\"\n" \ | |
255 | "4: movl $-2, %[err]\n" \ | |
256 | "jmp 3b\n" \ | |
257 | ".popsection\n" \ | |
258 | _ASM_EXTABLE(661b, 4b) \ | |
259 | : [err] "=r" (err) \ | |
260 | : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ | |
261 | : "memory") | |
262 | ||
263 | /* | |
264 | * Use XRSTORS to restore context if it is enabled. XRSTORS supports compact | |
265 | * XSAVE area format. | |
266 | */ | |
d5c8028b | 267 | #define XSTATE_XRESTORE(st, lmask, hmask) \ |
b7106fa0 BP |
268 | asm volatile(ALTERNATIVE(XRSTOR, \ |
269 | XRSTORS, X86_FEATURE_XSAVES) \ | |
270 | "\n" \ | |
b7106fa0 | 271 | "3:\n" \ |
d5c8028b EB |
272 | _ASM_EXTABLE_HANDLE(661b, 3b, ex_handler_fprestore)\ |
273 | : \ | |
b7106fa0 BP |
274 | : "D" (st), "m" (*st), "a" (lmask), "d" (hmask) \ |
275 | : "memory") | |
b74a0cf1 | 276 | |
fd169b05 IM |
277 | /* |
278 | * This function is called only during boot time when x86 caps are not set | |
279 | * up and alternative can not be used yet. | |
280 | */ | |
8c05f05e | 281 | static inline void copy_xregs_to_kernel_booting(struct xregs_state *xstate) |
fd169b05 IM |
282 | { |
283 | u64 mask = -1; | |
284 | u32 lmask = mask; | |
285 | u32 hmask = mask >> 32; | |
b74a0cf1 | 286 | int err; |
fd169b05 IM |
287 | |
288 | WARN_ON(system_state != SYSTEM_BOOTING); | |
289 | ||
bc696ca0 | 290 | if (static_cpu_has(X86_FEATURE_XSAVES)) |
b74a0cf1 | 291 | XSTATE_OP(XSAVES, xstate, lmask, hmask, err); |
fd169b05 | 292 | else |
b74a0cf1 | 293 | XSTATE_OP(XSAVE, xstate, lmask, hmask, err); |
8c05f05e IM |
294 | |
295 | /* We should never fault when copying to a kernel buffer: */ | |
296 | WARN_ON_FPU(err); | |
fd169b05 IM |
297 | } |
298 | ||
299 | /* | |
300 | * This function is called only during boot time when x86 caps are not set | |
301 | * up and alternative can not be used yet. | |
302 | */ | |
d65fcd60 | 303 | static inline void copy_kernel_to_xregs_booting(struct xregs_state *xstate) |
fd169b05 | 304 | { |
d65fcd60 | 305 | u64 mask = -1; |
fd169b05 IM |
306 | u32 lmask = mask; |
307 | u32 hmask = mask >> 32; | |
b74a0cf1 | 308 | int err; |
fd169b05 IM |
309 | |
310 | WARN_ON(system_state != SYSTEM_BOOTING); | |
311 | ||
bc696ca0 | 312 | if (static_cpu_has(X86_FEATURE_XSAVES)) |
b74a0cf1 | 313 | XSTATE_OP(XRSTORS, xstate, lmask, hmask, err); |
fd169b05 | 314 | else |
b74a0cf1 | 315 | XSTATE_OP(XRSTOR, xstate, lmask, hmask, err); |
8c05f05e | 316 | |
d5c8028b EB |
317 | /* |
318 | * We should never fault when copying from a kernel buffer, and the FPU | |
319 | * state we set at boot time should be valid. | |
320 | */ | |
8c05f05e | 321 | WARN_ON_FPU(err); |
fd169b05 IM |
322 | } |
323 | ||
324 | /* | |
325 | * Save processor xstate to xsave area. | |
326 | */ | |
8c05f05e | 327 | static inline void copy_xregs_to_kernel(struct xregs_state *xstate) |
fd169b05 IM |
328 | { |
329 | u64 mask = -1; | |
330 | u32 lmask = mask; | |
331 | u32 hmask = mask >> 32; | |
b7106fa0 | 332 | int err; |
fd169b05 | 333 | |
03eaec81 | 334 | WARN_ON_FPU(!alternatives_patched); |
fd169b05 | 335 | |
b7106fa0 | 336 | XSTATE_XSAVE(xstate, lmask, hmask, err); |
fd169b05 | 337 | |
8c05f05e IM |
338 | /* We should never fault when copying to a kernel buffer: */ |
339 | WARN_ON_FPU(err); | |
fd169b05 IM |
340 | } |
341 | ||
342 | /* | |
343 | * Restore processor xstate from xsave area. | |
344 | */ | |
8c05f05e | 345 | static inline void copy_kernel_to_xregs(struct xregs_state *xstate, u64 mask) |
fd169b05 | 346 | { |
fd169b05 IM |
347 | u32 lmask = mask; |
348 | u32 hmask = mask >> 32; | |
fd169b05 | 349 | |
d5c8028b | 350 | XSTATE_XRESTORE(xstate, lmask, hmask); |
fd169b05 IM |
351 | } |
352 | ||
353 | /* | |
354 | * Save xstate to user space xsave area. | |
355 | * | |
356 | * We don't use modified optimization because xrstor/xrstors might track | |
357 | * a different application. | |
358 | * | |
359 | * We don't use compacted format xsave area for | |
360 | * backward compatibility for old applications which don't understand | |
361 | * compacted format of xsave area. | |
362 | */ | |
363 | static inline int copy_xregs_to_user(struct xregs_state __user *buf) | |
364 | { | |
365 | int err; | |
366 | ||
367 | /* | |
368 | * Clear the xsave header first, so that reserved fields are | |
369 | * initialized to zero. | |
370 | */ | |
371 | err = __clear_user(&buf->header, sizeof(buf->header)); | |
372 | if (unlikely(err)) | |
373 | return -EFAULT; | |
374 | ||
b74a0cf1 BP |
375 | stac(); |
376 | XSTATE_OP(XSAVE, buf, -1, -1, err); | |
377 | clac(); | |
378 | ||
fd169b05 IM |
379 | return err; |
380 | } | |
381 | ||
382 | /* | |
383 | * Restore xstate from user space xsave area. | |
384 | */ | |
385 | static inline int copy_user_to_xregs(struct xregs_state __user *buf, u64 mask) | |
386 | { | |
fd169b05 IM |
387 | struct xregs_state *xstate = ((__force struct xregs_state *)buf); |
388 | u32 lmask = mask; | |
389 | u32 hmask = mask >> 32; | |
b74a0cf1 BP |
390 | int err; |
391 | ||
392 | stac(); | |
393 | XSTATE_OP(XRSTOR, xstate, lmask, hmask, err); | |
394 | clac(); | |
fd169b05 | 395 | |
fd169b05 IM |
396 | return err; |
397 | } | |
398 | ||
1361b83a LT |
399 | /* |
400 | * These must be called with preempt disabled. Returns | |
4f836347 IM |
401 | * 'true' if the FPU state is still intact and we can |
402 | * keep registers active. | |
403 | * | |
404 | * The legacy FNSAVE instruction cleared all FPU state | |
405 | * unconditionally, so registers are essentially destroyed. | |
406 | * Modern FPU state can be kept in registers, if there are | |
1bc6b056 | 407 | * no pending FP exceptions. |
1361b83a | 408 | */ |
4f836347 | 409 | static inline int copy_fpregs_to_fpstate(struct fpu *fpu) |
1361b83a | 410 | { |
1bc6b056 | 411 | if (likely(use_xsave())) { |
c6813144 | 412 | copy_xregs_to_kernel(&fpu->state.xsave); |
1bc6b056 IM |
413 | return 1; |
414 | } | |
1361b83a | 415 | |
1bc6b056 | 416 | if (likely(use_fxsr())) { |
c6813144 | 417 | copy_fxregs_to_kernel(fpu); |
1bc6b056 | 418 | return 1; |
1361b83a LT |
419 | } |
420 | ||
421 | /* | |
1bc6b056 IM |
422 | * Legacy FPU register saving, FNSAVE always clears FPU registers, |
423 | * so we have to mark them inactive: | |
1361b83a | 424 | */ |
87dafd41 | 425 | asm volatile("fnsave %[fp]; fwait" : [fp] "=m" (fpu->state.fsave)); |
4f836347 | 426 | |
4f836347 | 427 | return 0; |
1361b83a LT |
428 | } |
429 | ||
38cfd5e3 | 430 | static inline void __copy_kernel_to_fpregs(union fpregs_state *fpstate, u64 mask) |
1361b83a | 431 | { |
8c05f05e | 432 | if (use_xsave()) { |
38cfd5e3 | 433 | copy_kernel_to_xregs(&fpstate->xsave, mask); |
8c05f05e IM |
434 | } else { |
435 | if (use_fxsr()) | |
003e2e8b | 436 | copy_kernel_to_fxregs(&fpstate->fxsave); |
8c05f05e | 437 | else |
003e2e8b | 438 | copy_kernel_to_fregs(&fpstate->fsave); |
8c05f05e | 439 | } |
1361b83a LT |
440 | } |
441 | ||
003e2e8b | 442 | static inline void copy_kernel_to_fpregs(union fpregs_state *fpstate) |
1361b83a | 443 | { |
6ca7a8a1 BP |
444 | /* |
445 | * AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception is | |
446 | * pending. Clear the x87 state here by setting it to fixed values. | |
447 | * "m" is a random variable that should be in L1. | |
448 | */ | |
bc696ca0 | 449 | if (unlikely(static_cpu_has_bug(X86_BUG_FXSAVE_LEAK))) { |
26bef131 LT |
450 | asm volatile( |
451 | "fnclex\n\t" | |
452 | "emms\n\t" | |
453 | "fildl %P[addr]" /* set F?P to defined value */ | |
003e2e8b | 454 | : : [addr] "m" (fpstate)); |
26bef131 | 455 | } |
1361b83a | 456 | |
38cfd5e3 | 457 | __copy_kernel_to_fpregs(fpstate, -1); |
1361b83a LT |
458 | } |
459 | ||
87dafd41 | 460 | extern int copy_fpstate_to_sigframe(void __user *buf, void __user *fp, int size); |
b1b64dc3 IM |
461 | |
462 | /* | |
463 | * FPU context switch related helper methods: | |
464 | */ | |
465 | ||
466 | DECLARE_PER_CPU(struct fpu *, fpu_fpregs_owner_ctx); | |
467 | ||
468 | /* | |
25d83b53 RR |
469 | * The in-register FPU state for an FPU context on a CPU is assumed to be |
470 | * valid if the fpu->last_cpu matches the CPU, and the fpu_fpregs_owner_ctx | |
471 | * matches the FPU. | |
472 | * | |
473 | * If the FPU register state is valid, the kernel can skip restoring the | |
474 | * FPU state from memory. | |
475 | * | |
476 | * Any code that clobbers the FPU registers or updates the in-memory | |
477 | * FPU state for a task MUST let the rest of the kernel know that the | |
317b622c | 478 | * FPU registers are no longer valid for this task. |
25d83b53 | 479 | * |
317b622c RR |
480 | * Either one of these invalidation functions is enough. Invalidate |
481 | * a resource you control: CPU if using the CPU for something else | |
482 | * (with preemption disabled), FPU for the current task, or a task that | |
483 | * is prevented from running by the current task. | |
b1b64dc3 | 484 | */ |
317b622c | 485 | static inline void __cpu_invalidate_fpregs_state(void) |
b1b64dc3 | 486 | { |
317b622c | 487 | __this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
b1b64dc3 IM |
488 | } |
489 | ||
25d83b53 RR |
490 | static inline void __fpu_invalidate_fpregs_state(struct fpu *fpu) |
491 | { | |
492 | fpu->last_cpu = -1; | |
493 | } | |
494 | ||
495 | static inline int fpregs_state_valid(struct fpu *fpu, unsigned int cpu) | |
b1b64dc3 IM |
496 | { |
497 | return fpu == this_cpu_read_stable(fpu_fpregs_owner_ctx) && cpu == fpu->last_cpu; | |
498 | } | |
499 | ||
66f314ef RR |
500 | /* |
501 | * These generally need preemption protection to work, | |
502 | * do try to avoid using these on their own: | |
503 | */ | |
504 | static inline void fpregs_deactivate(struct fpu *fpu) | |
1361b83a | 505 | { |
36b544dc | 506 | this_cpu_write(fpu_fpregs_owner_ctx, NULL); |
d1898b73 | 507 | trace_x86_fpu_regs_deactivated(fpu); |
1361b83a LT |
508 | } |
509 | ||
66f314ef | 510 | static inline void fpregs_activate(struct fpu *fpu) |
1361b83a | 511 | { |
c0311f63 | 512 | this_cpu_write(fpu_fpregs_owner_ctx, fpu); |
d1898b73 | 513 | trace_x86_fpu_regs_activated(fpu); |
1361b83a LT |
514 | } |
515 | ||
1361b83a LT |
516 | /* |
517 | * FPU state switching for scheduling. | |
518 | * | |
519 | * This is a two-stage process: | |
520 | * | |
c474e507 RR |
521 | * - switch_fpu_prepare() saves the old state. |
522 | * This is done within the context of the old process. | |
1361b83a LT |
523 | * |
524 | * - switch_fpu_finish() restores the new state as | |
525 | * necessary. | |
526 | */ | |
c474e507 RR |
527 | static inline void |
528 | switch_fpu_prepare(struct fpu *old_fpu, int cpu) | |
1361b83a | 529 | { |
e4a81bfc | 530 | if (old_fpu->initialized) { |
4f836347 | 531 | if (!copy_fpregs_to_fpstate(old_fpu)) |
cb8818b6 | 532 | old_fpu->last_cpu = -1; |
1361ef29 | 533 | else |
cb8818b6 | 534 | old_fpu->last_cpu = cpu; |
1361ef29 | 535 | |
36b544dc | 536 | /* But leave fpu_fpregs_owner_ctx! */ |
d1898b73 | 537 | trace_x86_fpu_regs_deactivated(old_fpu); |
9ad93fe3 RR |
538 | } else |
539 | old_fpu->last_cpu = -1; | |
1361b83a LT |
540 | } |
541 | ||
b1b64dc3 IM |
542 | /* |
543 | * Misc helper functions: | |
544 | */ | |
545 | ||
1361b83a | 546 | /* |
c474e507 RR |
547 | * Set up the userspace FPU context for the new task, if the task |
548 | * has used the FPU. | |
1361b83a | 549 | */ |
c474e507 | 550 | static inline void switch_fpu_finish(struct fpu *new_fpu, int cpu) |
1361b83a | 551 | { |
c474e507 | 552 | bool preload = static_cpu_has(X86_FEATURE_FPU) && |
e4a81bfc | 553 | new_fpu->initialized; |
c474e507 RR |
554 | |
555 | if (preload) { | |
556 | if (!fpregs_state_valid(new_fpu, cpu)) | |
557 | copy_kernel_to_fpregs(&new_fpu->state); | |
558 | fpregs_activate(new_fpu); | |
559 | } | |
1361b83a LT |
560 | } |
561 | ||
1361b83a | 562 | /* |
fb14b4ea | 563 | * Needs to be preemption-safe. |
1361b83a | 564 | * |
377ffbcc | 565 | * NOTE! user_fpu_begin() must be used only immediately before restoring |
fb14b4ea ON |
566 | * the save state. It does not do any saving/restoring on its own. In |
567 | * lazy FPU mode, it is just an optimization to avoid a #NM exception, | |
568 | * the task can lose the FPU right after preempt_enable(). | |
1361b83a | 569 | */ |
1361b83a LT |
570 | static inline void user_fpu_begin(void) |
571 | { | |
4540d3fa IM |
572 | struct fpu *fpu = ¤t->thread.fpu; |
573 | ||
1361b83a | 574 | preempt_disable(); |
6cf4edbe | 575 | fpregs_activate(fpu); |
1361b83a LT |
576 | preempt_enable(); |
577 | } | |
578 | ||
b1b64dc3 IM |
579 | /* |
580 | * MXCSR and XCR definitions: | |
581 | */ | |
582 | ||
583 | extern unsigned int mxcsr_feature_mask; | |
584 | ||
585 | #define XCR_XFEATURE_ENABLED_MASK 0x00000000 | |
586 | ||
587 | static inline u64 xgetbv(u32 index) | |
588 | { | |
589 | u32 eax, edx; | |
590 | ||
591 | asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */ | |
592 | : "=a" (eax), "=d" (edx) | |
593 | : "c" (index)); | |
594 | return eax + ((u64)edx << 32); | |
595 | } | |
596 | ||
597 | static inline void xsetbv(u32 index, u64 value) | |
598 | { | |
599 | u32 eax = value; | |
600 | u32 edx = value >> 32; | |
601 | ||
602 | asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */ | |
603 | : : "a" (eax), "d" (edx), "c" (index)); | |
604 | } | |
605 | ||
78f7f1e5 | 606 | #endif /* _ASM_X86_FPU_INTERNAL_H */ |