[linux-2.6-block.git] / arch / x86 / include / asm / desc.h

#ifndef _ASM_X86_DESC_H
#define _ASM_X86_DESC_H

#include <asm/desc_defs.h>
#include <asm/ldt.h>
#include <asm/mmu.h>

#include <linux/smp.h>

static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
{
	desc->limit0		= info->limit & 0x0ffff;

	desc->base0		= (info->base_addr & 0x0000ffff);
	desc->base1		= (info->base_addr & 0x00ff0000) >> 16;

	desc->type		= (info->read_exec_only ^ 1) << 1;
	desc->type	       |= info->contents << 2;

	desc->s			= 1;
	desc->dpl		= 0x3;
	desc->p			= info->seg_not_present ^ 1;
	desc->limit		= (info->limit & 0xf0000) >> 16;
	desc->avl		= info->useable;
	desc->d			= info->seg_32bit;
	desc->g			= info->limit_in_pages;

	desc->base2		= (info->base_addr & 0xff000000) >> 24;
	/*
	 * Don't allow setting of the lm bit. It would confuse
	 * user_64bit_mode and would get overridden by sysret anyway.
	 */
	desc->l			= 0;
}

extern struct desc_ptr idt_descr;
extern gate_desc idt_table[];
extern struct desc_ptr nmi_idt_descr;
extern gate_desc nmi_idt_table[];

struct gdt_page {
	struct desc_struct gdt[GDT_ENTRIES];
} __attribute__((aligned(PAGE_SIZE)));

DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);

static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
{
	return per_cpu(gdt_page, cpu).gdt;
}

#ifdef CONFIG_X86_64

static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate->offset_low	= PTR_LOW(func);
	gate->segment		= __KERNEL_CS;
	gate->ist		= ist;
	gate->p			= 1;
	gate->dpl		= dpl;
	gate->zero0		= 0;
	gate->zero1		= 0;
	gate->type		= type;
	gate->offset_middle	= PTR_MIDDLE(func);
	gate->offset_high	= PTR_HIGH(func);
}

#else
static inline void pack_gate(gate_desc *gate, unsigned char type,
			     unsigned long base, unsigned dpl, unsigned flags,
			     unsigned short seg)
{
	gate->a = (seg << 16) | (base & 0xffff);
	gate->b = (base & 0xffff0000) | (((0x80 | type | (dpl << 5)) & 0xff) << 8);
}

#endif

static inline int desc_empty(const void *ptr)
{
	const u32 *desc = ptr;

	return !(desc[0] | desc[1]);
}

#ifdef CONFIG_PARAVIRT
#include <asm/paravirt.h>
#else
#define load_TR_desc()				native_load_tr_desc()
#define load_gdt(dtr)				native_load_gdt(dtr)
#define load_idt(dtr)				native_load_idt(dtr)
#define load_tr(tr)				asm volatile("ltr %0"::"m" (tr))
#define load_ldt(ldt)				asm volatile("lldt %0"::"m" (ldt))

#define store_gdt(dtr)				native_store_gdt(dtr)
#define store_idt(dtr)				native_store_idt(dtr)
#define store_tr(tr)				(tr = native_store_tr())

#define load_TLS(t, cpu)			native_load_tls(t, cpu)
#define set_ldt					native_set_ldt

#define write_ldt_entry(dt, entry, desc)	native_write_ldt_entry(dt, entry, desc)
#define write_gdt_entry(dt, entry, desc, type)	native_write_gdt_entry(dt, entry, desc, type)
#define write_idt_entry(dt, entry, g)		native_write_idt_entry(dt, entry, g)

static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
{
}

static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
{
}
#endif	/* CONFIG_PARAVIRT */

#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))

static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
{
	memcpy(&idt[entry], gate, sizeof(*gate));
}

static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
{
	memcpy(&ldt[entry], desc, 8);
}

static inline void
native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
{
	unsigned int size;

	switch (type) {
	case DESC_TSS:	size = sizeof(tss_desc);	break;
	case DESC_LDT:	size = sizeof(ldt_desc);	break;
	default:	size = sizeof(*gdt);		break;
	}

	memcpy(&gdt[entry], desc, size);
}

static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
				   unsigned long limit, unsigned char type,
				   unsigned char flags)
{
	desc->a = ((base & 0xffff) << 16) | (limit & 0xffff);
	desc->b = (base & 0xff000000) | ((base & 0xff0000) >> 16) |
		(limit & 0x000f0000) | ((type & 0xff) << 8) |
		((flags & 0xf) << 20);
	desc->p = 1;
}


static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)
{
#ifdef CONFIG_X86_64
	struct ldttss_desc64 *desc = d;

	memset(desc, 0, sizeof(*desc));

	desc->limit0		= size & 0xFFFF;
	desc->base0		= PTR_LOW(addr);
	desc->base1		= PTR_MIDDLE(addr) & 0xFF;
	desc->type		= type;
	desc->p			= 1;
	desc->limit1		= (size >> 16) & 0xF;
	desc->base2		= (PTR_MIDDLE(addr) >> 8) & 0xFF;
	desc->base3		= PTR_HIGH(addr);
#else
	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 | type, 0);
#endif
}

static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
{
	struct desc_struct *d = get_cpu_gdt_table(cpu);
	tss_desc tss;

	/*
	 * sizeof(unsigned long) coming from an extra "long" at the end
	 * of the iobitmap. See tss_struct definition in processor.h
	 *
	 * -1? seg base+limit should be pointing to the address of the
	 * last valid byte
	 */
	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
			      IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
			      sizeof(unsigned long) - 1);
	write_gdt_entry(d, entry, &tss, DESC_TSS);
}

#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)

static inline void native_set_ldt(const void *addr, unsigned int entries)
{
	if (likely(entries == 0))
		asm volatile("lldt %w0"::"q" (0));
	else {
		unsigned cpu = smp_processor_id();
		ldt_desc ldt;

		set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
				      entries * LDT_ENTRY_SIZE - 1);
		write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
				&ldt, DESC_LDT);
		asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
	}
}

static inline void native_load_tr_desc(void)
{
	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
}

static inline void native_load_gdt(const struct desc_ptr *dtr)
{
	asm volatile("lgdt %0"::"m" (*dtr));
}

static inline void native_load_idt(const struct desc_ptr *dtr)
{
	asm volatile("lidt %0"::"m" (*dtr));
}

static inline void native_store_gdt(struct desc_ptr *dtr)
{
	asm volatile("sgdt %0":"=m" (*dtr));
}

static inline void native_store_idt(struct desc_ptr *dtr)
{
	asm volatile("sidt %0":"=m" (*dtr));
}

static inline unsigned long native_store_tr(void)
{
	unsigned long tr;

	asm volatile("str %0":"=r" (tr));

	return tr;
}

static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
{
	struct desc_struct *gdt = get_cpu_gdt_table(cpu);
	unsigned int i;

	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
		gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
}

#define _LDT_empty(info)				\
	((info)->base_addr		== 0	&&	\
	 (info)->limit			== 0	&&	\
	 (info)->contents		== 0	&&	\
	 (info)->read_exec_only		== 1	&&	\
	 (info)->seg_32bit		== 0	&&	\
	 (info)->limit_in_pages		== 0	&&	\
	 (info)->seg_not_present	== 1	&&	\
	 (info)->useable		== 0)

#ifdef CONFIG_X86_64
#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
#else
#define LDT_empty(info) (_LDT_empty(info))
#endif

static inline void clear_LDT(void)
{
	set_ldt(NULL, 0);
}

/*
 * load one particular LDT into the current CPU
 */
static inline void load_LDT_nolock(mm_context_t *pc)
{
	set_ldt(pc->ldt, pc->size);
}

static inline void load_LDT(mm_context_t *pc)
{
	preempt_disable();
	load_LDT_nolock(pc);
	preempt_enable();
}

static inline unsigned long get_desc_base(const struct desc_struct *desc)
{
	return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
}

static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
{
	desc->base0 = base & 0xffff;
	desc->base1 = (base >> 16) & 0xff;
	desc->base2 = (base >> 24) & 0xff;
}

static inline unsigned long get_desc_limit(const struct desc_struct *desc)
{
	return desc->limit0 | (desc->limit << 16);
}

static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
{
	desc->limit0 = limit & 0xffff;
	desc->limit = (limit >> 16) & 0xf;
}

#ifdef CONFIG_X86_64
static inline void set_nmi_gate(int gate, void *addr)
{
	gate_desc s;

	pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
	write_idt_entry(nmi_idt_table, gate, &s);
}
#endif

static inline void _set_gate(int gate, unsigned type, void *addr,
			     unsigned dpl, unsigned ist, unsigned seg)
{
	gate_desc s;

	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	/*
	 * does not need to be atomic because it is only done once at
	 * setup time
	 */
	write_idt_entry(idt_table, gate, &s);
}

/*
 * This needs to use 'idt_table' rather than 'idt', and
 * thus use the _nonmapped_ version of the IDT, as the
 * Pentium F0 0F bugfix can have resulted in the mapped
 * IDT being write-protected.
 */
static inline void set_intr_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
}

extern int first_system_vector;
/* used_vectors is BITMAP for irq is not managed by percpu vector_irq */
extern unsigned long used_vectors[];

static inline void alloc_system_vector(int vector)
{
	if (!test_bit(vector, used_vectors)) {
		set_bit(vector, used_vectors);
		if (first_system_vector > vector)
			first_system_vector = vector;
	} else {
		BUG();
	}
}

static inline void alloc_intr_gate(unsigned int n, void *addr)
{
	alloc_system_vector(n);
	set_intr_gate(n, addr);
}

/*
 * This routine sets up an interrupt gate at directory privilege level 3.
 */
static inline void set_system_intr_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
}

static inline void set_system_trap_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
}

static inline void set_trap_gate(unsigned int n, void *addr)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
}

static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
}

static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
}

static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
{
	BUG_ON((unsigned)n > 0xFF);
	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
}

#endif /* _ASM_X86_DESC_H */
Commit	Line	Data
1965aae3 PA	1	#ifndef _ASM_X86_DESC_H
1965aae3 PA	2	#define _ASM_X86_DESC_H
80fbb69a	3
80fbb69a GOC	4	#include <asm/desc_defs.h>
80fbb69a GOC	5	#include <asm/ldt.h>
881c2975	6	#include <asm/mmu.h>
9a3865b1	7
54cd0eac	8	#include <linux/smp.h>
80fbb69a	9
9a3865b1 IM	10	static inline void fill_ldt(struct desc_struct desc, const struct user_desc info)
	11	{
	12	desc->limit0 = info->limit & 0x0ffff;
	13
	14	desc->base0 = (info->base_addr & 0x0000ffff);
	15	desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
	16
	17	desc->type = (info->read_exec_only ^ 1) << 1;
	18	desc->type \|= info->contents << 2;
	19
	20	desc->s = 1;
	21	desc->dpl = 0x3;
	22	desc->p = info->seg_not_present ^ 1;
	23	desc->limit = (info->limit & 0xf0000) >> 16;
	24	desc->avl = info->useable;
	25	desc->d = info->seg_32bit;
	26	desc->g = info->limit_in_pages;
	27
	28	desc->base2 = (info->base_addr & 0xff000000) >> 24;
64f53a04	29	/*
318f5a2a AL	30	* Don't allow setting of the lm bit. It would confuse
318f5a2a AL	31	* user_64bit_mode and would get overridden by sysret anyway.
64f53a04	32	*/
9a3865b1	33	desc->l = 0;
80fbb69a GOC	34	}
80fbb69a GOC	35
881c2975 GOC	36	extern struct desc_ptr idt_descr;
881c2975 GOC	37	extern gate_desc idt_table[];
228bdaa9 SR	38	extern struct desc_ptr nmi_idt_descr;
228bdaa9 SR	39	extern gate_desc nmi_idt_table[];
80fbb69a	40
a939098a GC	41	struct gdt_page {
	42	struct desc_struct gdt[GDT_ENTRIES];
	43	} __attribute__((aligned(PAGE_SIZE)));
9a3865b1	44
9b8de747	45	DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
a939098a GC	46
	47	static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
	48	{
	49	return per_cpu(gdt_page, cpu).gdt;
	50	}
	51
54cd0eac	52	#ifdef CONFIG_X86_64
507f90c9 GOC	53
	54	static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
	55	unsigned dpl, unsigned ist, unsigned seg)
	56	{
9a3865b1 IM	57	gate->offset_low = PTR_LOW(func);
	58	gate->segment = __KERNEL_CS;
	59	gate->ist = ist;
	60	gate->p = 1;
	61	gate->dpl = dpl;
	62	gate->zero0 = 0;
	63	gate->zero1 = 0;
	64	gate->type = type;
	65	gate->offset_middle = PTR_MIDDLE(func);
	66	gate->offset_high = PTR_HIGH(func);
507f90c9 GOC	67	}
507f90c9 GOC	68
54cd0eac	69	#else
507f90c9	70	static inline void pack_gate(gate_desc *gate, unsigned char type,
c1773a16 JP	71	unsigned long base, unsigned dpl, unsigned flags,
c1773a16 JP	72	unsigned short seg)
507f90c9 GOC	73	{
507f90c9 GOC	74	gate->a = (seg << 16) \| (base & 0xffff);
9a3865b1	75	gate->b = (base & 0xffff0000) \| (((0x80 \| type \| (dpl << 5)) & 0xff) << 8);
507f90c9 GOC	76	}
507f90c9 GOC	77
54cd0eac GOC	78	#endif
54cd0eac GOC	79
746ff60f GOC	80	static inline int desc_empty(const void *ptr)
	81	{
	82	const u32 *desc = ptr;
9a3865b1	83
746ff60f GOC	84	return !(desc[0] \| desc[1]);
	85	}
	86
54cd0eac GOC	87	#ifdef CONFIG_PARAVIRT
	88	#include <asm/paravirt.h>
	89	#else
9a3865b1 IM	90	#define load_TR_desc() native_load_tr_desc()
	91	#define load_gdt(dtr) native_load_gdt(dtr)
	92	#define load_idt(dtr) native_load_idt(dtr)
	93	#define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
	94	#define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
	95
	96	#define store_gdt(dtr) native_store_gdt(dtr)
	97	#define store_idt(dtr) native_store_idt(dtr)
	98	#define store_tr(tr) (tr = native_store_tr())
	99
	100	#define load_TLS(t, cpu) native_load_tls(t, cpu)
	101	#define set_ldt native_set_ldt
	102
	103	#define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc)
	104	#define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type)
	105	#define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
38ffbe66 JF	106
	107	static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
	108	{
	109	}
	110
	111	static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
	112	{
	113	}
	114	#endif /* CONFIG_PARAVIRT */
54cd0eac	115
8229d754 JSR	116	#define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
8229d754 JSR	117
9a3865b1	118	static inline void native_write_idt_entry(gate_desc idt, int entry, const gate_desc gate)
54cd0eac GOC	119	{
	120	memcpy(&idt[entry], gate, sizeof(*gate));
	121	}
	122
9a3865b1	123	static inline void native_write_ldt_entry(struct desc_struct ldt, int entry, const void desc)
54cd0eac GOC	124	{
	125	memcpy(&ldt[entry], desc, 8);
	126	}
	127
9a3865b1 IM	128	static inline void
9a3865b1 IM	129	native_write_gdt_entry(struct desc_struct gdt, int entry, const void desc, int type)
54cd0eac GOC	130	{
54cd0eac GOC	131	unsigned int size;
9a3865b1	132
54cd0eac	133	switch (type) {
9a3865b1 IM	134	case DESC_TSS: size = sizeof(tss_desc); break;
	135	case DESC_LDT: size = sizeof(ldt_desc); break;
	136	default: size = sizeof(*gdt); break;
54cd0eac	137	}
9a3865b1	138
54cd0eac GOC	139	memcpy(&gdt[entry], desc, size);
	140	}
	141
54cd0eac GOC	142	static inline void pack_descriptor(struct desc_struct *desc, unsigned long base,
	143	unsigned long limit, unsigned char type,
	144	unsigned char flags)
	145	{
	146	desc->a = ((base & 0xffff) << 16) \| (limit & 0xffff);
	147	desc->b = (base & 0xff000000) \| ((base & 0xff0000) >> 16) \|
c1773a16 JP	148	(limit & 0x000f0000) \| ((type & 0xff) << 8) \|
c1773a16 JP	149	((flags & 0xf) << 20);
54cd0eac GOC	150	desc->p = 1;
	151	}
	152
54cd0eac	153
9a3865b1	154	static inline void set_tssldt_descriptor(void *d, unsigned long addr, unsigned type, unsigned size)
c81c6ca4 GOC	155	{
c81c6ca4 GOC	156	#ifdef CONFIG_X86_64
f6e0eba1	157	struct ldttss_desc64 *desc = d;
9a3865b1	158
f6e0eba1	159	memset(desc, 0, sizeof(*desc));
9a3865b1 IM	160
	161	desc->limit0 = size & 0xFFFF;
	162	desc->base0 = PTR_LOW(addr);
	163	desc->base1 = PTR_MIDDLE(addr) & 0xFF;
	164	desc->type = type;
	165	desc->p = 1;
	166	desc->limit1 = (size >> 16) & 0xF;
	167	desc->base2 = (PTR_MIDDLE(addr) >> 8) & 0xFF;
	168	desc->base3 = PTR_HIGH(addr);
c81c6ca4	169	#else
f6e0eba1	170	pack_descriptor((struct desc_struct *)d, addr, size, 0x80 \| type, 0);
c81c6ca4 GOC	171	#endif
	172	}
	173
	174	static inline void __set_tss_desc(unsigned cpu, unsigned int entry, void *addr)
	175	{
	176	struct desc_struct *d = get_cpu_gdt_table(cpu);
	177	tss_desc tss;
	178
	179	/*
	180	* sizeof(unsigned long) coming from an extra "long" at the end
	181	* of the iobitmap. See tss_struct definition in processor.h
	182	*
	183	* -1? seg base+limit should be pointing to the address of the
	184	* last valid byte
	185	*/
f6e0eba1	186	set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
c1773a16 JP	187	IO_BITMAP_OFFSET + IO_BITMAP_BYTES +
c1773a16 JP	188	sizeof(unsigned long) - 1);
c81c6ca4 GOC	189	write_gdt_entry(d, entry, &tss, DESC_TSS);
	190	}
	191
	192	#define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
	193
54cd0eac GOC	194	static inline void native_set_ldt(const void *addr, unsigned int entries)
	195	{
	196	if (likely(entries == 0))
c1773a16	197	asm volatile("lldt %w0"::"q" (0));
54cd0eac GOC	198	else {
	199	unsigned cpu = smp_processor_id();
	200	ldt_desc ldt;
	201
5ac37f87 MK	202	set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
5ac37f87 MK	203	entries * LDT_ENTRY_SIZE - 1);
54cd0eac GOC	204	write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
54cd0eac GOC	205	&ldt, DESC_LDT);
c1773a16	206	asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
54cd0eac GOC	207	}
	208	}
	209
	210	static inline void native_load_tr_desc(void)
	211	{
	212	asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
	213	}
	214
	215	static inline void native_load_gdt(const struct desc_ptr *dtr)
	216	{
	217	asm volatile("lgdt %0"::"m" (*dtr));
	218	}
	219
	220	static inline void native_load_idt(const struct desc_ptr *dtr)
	221	{
	222	asm volatile("lidt %0"::"m" (*dtr));
	223	}
	224
	225	static inline void native_store_gdt(struct desc_ptr *dtr)
	226	{
	227	asm volatile("sgdt %0":"=m" (*dtr));
	228	}
	229
	230	static inline void native_store_idt(struct desc_ptr *dtr)
	231	{
	232	asm volatile("sidt %0":"=m" (*dtr));
	233	}
	234
	235	static inline unsigned long native_store_tr(void)
	236	{
	237	unsigned long tr;
9a3865b1	238
54cd0eac	239	asm volatile("str %0":"=r" (tr));
9a3865b1	240
54cd0eac GOC	241	return tr;
	242	}
	243
	244	static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
	245	{
54cd0eac	246	struct desc_struct *gdt = get_cpu_gdt_table(cpu);
9a3865b1	247	unsigned int i;
54cd0eac GOC	248
	249	for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
	250	gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
	251	}
	252
c1773a16 JP	253	#define _LDT_empty(info) \
	254	((info)->base_addr == 0 && \
	255	(info)->limit == 0 && \
	256	(info)->contents == 0 && \
	257	(info)->read_exec_only == 1 && \
	258	(info)->seg_32bit == 0 && \
	259	(info)->limit_in_pages == 0 && \
	260	(info)->seg_not_present == 1 && \
	261	(info)->useable == 0)
881c2975 GOC	262
	263	#ifdef CONFIG_X86_64
	264	#define LDT_empty(info) (_LDT_empty(info) && ((info)->lm == 0))
	265	#else
	266	#define LDT_empty(info) (_LDT_empty(info))
	267	#endif
	268
	269	static inline void clear_LDT(void)
	270	{
	271	set_ldt(NULL, 0);
	272	}
	273
	274	/*
	275	* load one particular LDT into the current CPU
	276	*/
	277	static inline void load_LDT_nolock(mm_context_t *pc)
	278	{
	279	set_ldt(pc->ldt, pc->size);
	280	}
	281
	282	static inline void load_LDT(mm_context_t *pc)
	283	{
	284	preempt_disable();
	285	load_LDT_nolock(pc);
	286	preempt_enable();
	287	}
	288
1bd5718c	289	static inline unsigned long get_desc_base(const struct desc_struct *desc)
cc697852	290	{
2c75910f	291	return (unsigned)(desc->base0 \| ((desc->base1) << 16) \| ((desc->base2) << 24));
cc697852	292	}
1bd5718c	293
57594742 AM	294	static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
	295	{
	296	desc->base0 = base & 0xffff;
	297	desc->base1 = (base >> 16) & 0xff;
	298	desc->base2 = (base >> 24) & 0xff;
	299	}
	300
1bd5718c RM	301	static inline unsigned long get_desc_limit(const struct desc_struct *desc)
	302	{
	303	return desc->limit0 \| (desc->limit << 16);
	304	}
	305
57594742 AM	306	static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
	307	{
	308	desc->limit0 = limit & 0xffff;
	309	desc->limit = (limit >> 16) & 0xf;
	310	}
	311
228bdaa9 SR	312	#ifdef CONFIG_X86_64
	313	static inline void set_nmi_gate(int gate, void *addr)
	314	{
	315	gate_desc s;
	316
	317	pack_gate(&s, GATE_INTERRUPT, (unsigned long)addr, 0, 0, __KERNEL_CS);
	318	write_idt_entry(nmi_idt_table, gate, &s);
	319	}
	320	#endif
	321
507f90c9	322	static inline void _set_gate(int gate, unsigned type, void *addr,
c1773a16	323	unsigned dpl, unsigned ist, unsigned seg)
507f90c9 GOC	324	{
507f90c9 GOC	325	gate_desc s;
9a3865b1	326
507f90c9 GOC	327	pack_gate(&s, type, (unsigned long)addr, dpl, ist, seg);
	328	/*
	329	* does not need to be atomic because it is only done once at
	330	* setup time
	331	*/
	332	write_idt_entry(idt_table, gate, &s);
	333	}
	334
	335	/*
	336	* This needs to use 'idt_table' rather than 'idt', and
	337	* thus use the _nonmapped_ version of the IDT, as the
	338	* Pentium F0 0F bugfix can have resulted in the mapped
	339	* IDT being write-protected.
	340	*/
	341	static inline void set_intr_gate(unsigned int n, void *addr)
	342	{
	343	BUG_ON((unsigned)n > 0xFF);
	344	_set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
	345	}
	346
305b92a2	347	extern int first_system_vector;
b77b881f YL	348	/* used_vectors is BITMAP for irq is not managed by percpu vector_irq */
b77b881f YL	349	extern unsigned long used_vectors[];
305b92a2 AM	350
	351	static inline void alloc_system_vector(int vector)
	352	{
b77b881f YL	353	if (!test_bit(vector, used_vectors)) {
b77b881f YL	354	set_bit(vector, used_vectors);
305b92a2 AM	355	if (first_system_vector > vector)
305b92a2 AM	356	first_system_vector = vector;
9a3865b1	357	} else {
305b92a2	358	BUG();
9a3865b1	359	}
305b92a2 AM	360	}
	361
	362	static inline void alloc_intr_gate(unsigned int n, void *addr)
	363	{
	364	alloc_system_vector(n);
	365	set_intr_gate(n, addr);
	366	}
	367
507f90c9 GOC	368	/*
	369	* This routine sets up an interrupt gate at directory privilege level 3.
	370	*/
	371	static inline void set_system_intr_gate(unsigned int n, void *addr)
	372	{
	373	BUG_ON((unsigned)n > 0xFF);
	374	_set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
	375	}
	376
699d2937	377	static inline void set_system_trap_gate(unsigned int n, void *addr)
507f90c9 GOC	378	{
507f90c9 GOC	379	BUG_ON((unsigned)n > 0xFF);
699d2937	380	_set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
507f90c9 GOC	381	}
507f90c9 GOC	382
699d2937	383	static inline void set_trap_gate(unsigned int n, void *addr)
507f90c9 GOC	384	{
507f90c9 GOC	385	BUG_ON((unsigned)n > 0xFF);
699d2937	386	_set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
507f90c9 GOC	387	}
	388
	389	static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
	390	{
	391	BUG_ON((unsigned)n > 0xFF);
	392	_set_gate(n, GATE_TASK, (void *)0, 0, 0, (gdt_entry<<3));
	393	}
	394
	395	static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
	396	{
	397	BUG_ON((unsigned)n > 0xFF);
	398	_set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
	399	}
	400
699d2937	401	static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
507f90c9 GOC	402	{
	403	BUG_ON((unsigned)n > 0xFF);
	404	_set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
	405	}
cc697852	406
1965aae3	407	#endif /* _ASM_X86_DESC_H */