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1965aae3 PA |
1 | #ifndef _ASM_X86_CPUFEATURE_H |
2 | #define _ASM_X86_CPUFEATURE_H | |
7b11fb51 | 3 | |
cd4d09ec | 4 | #include <asm/processor.h> |
e2604b49 | 5 | |
fa1408e4 PA |
6 | #if defined(__KERNEL__) && !defined(__ASSEMBLY__) |
7 | ||
a3c8acd0 | 8 | #include <asm/asm.h> |
fa1408e4 PA |
9 | #include <linux/bitops.h> |
10 | ||
39c06df4 BP |
11 | enum cpuid_leafs |
12 | { | |
13 | CPUID_1_EDX = 0, | |
14 | CPUID_8000_0001_EDX, | |
15 | CPUID_8086_0001_EDX, | |
16 | CPUID_LNX_1, | |
17 | CPUID_1_ECX, | |
18 | CPUID_C000_0001_EDX, | |
19 | CPUID_8000_0001_ECX, | |
20 | CPUID_LNX_2, | |
21 | CPUID_LNX_3, | |
22 | CPUID_7_0_EBX, | |
23 | CPUID_D_1_EAX, | |
24 | CPUID_F_0_EDX, | |
25 | CPUID_F_1_EDX, | |
26 | CPUID_8000_0008_EBX, | |
27 | CPUID_6_EAX, | |
28 | CPUID_8000_000A_EDX, | |
dfb4a70f | 29 | CPUID_7_ECX, |
39c06df4 BP |
30 | }; |
31 | ||
9def39be | 32 | #ifdef CONFIG_X86_FEATURE_NAMES |
fa1408e4 PA |
33 | extern const char * const x86_cap_flags[NCAPINTS*32]; |
34 | extern const char * const x86_power_flags[32]; | |
9def39be JT |
35 | #define X86_CAP_FMT "%s" |
36 | #define x86_cap_flag(flag) x86_cap_flags[flag] | |
37 | #else | |
38 | #define X86_CAP_FMT "%d:%d" | |
39 | #define x86_cap_flag(flag) ((flag) >> 5), ((flag) & 31) | |
40 | #endif | |
fa1408e4 | 41 | |
80a208bd BP |
42 | /* |
43 | * In order to save room, we index into this array by doing | |
44 | * X86_BUG_<name> - NCAPINTS*32. | |
45 | */ | |
46 | extern const char * const x86_bug_flags[NBUGINTS*32]; | |
47 | ||
0f8d2b92 IM |
48 | #define test_cpu_cap(c, bit) \ |
49 | test_bit(bit, (unsigned long *)((c)->x86_capability)) | |
50 | ||
349c004e | 51 | #define REQUIRED_MASK_BIT_SET(bit) \ |
dfb4a70f DH |
52 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & REQUIRED_MASK0 )) || \ |
53 | (((bit)>>5)==1 && (1UL<<((bit)&31) & REQUIRED_MASK1 )) || \ | |
54 | (((bit)>>5)==2 && (1UL<<((bit)&31) & REQUIRED_MASK2 )) || \ | |
55 | (((bit)>>5)==3 && (1UL<<((bit)&31) & REQUIRED_MASK3 )) || \ | |
56 | (((bit)>>5)==4 && (1UL<<((bit)&31) & REQUIRED_MASK4 )) || \ | |
57 | (((bit)>>5)==5 && (1UL<<((bit)&31) & REQUIRED_MASK5 )) || \ | |
58 | (((bit)>>5)==6 && (1UL<<((bit)&31) & REQUIRED_MASK6 )) || \ | |
59 | (((bit)>>5)==7 && (1UL<<((bit)&31) & REQUIRED_MASK7 )) || \ | |
60 | (((bit)>>5)==8 && (1UL<<((bit)&31) & REQUIRED_MASK8 )) || \ | |
61 | (((bit)>>5)==9 && (1UL<<((bit)&31) & REQUIRED_MASK9 )) || \ | |
62 | (((bit)>>5)==10 && (1UL<<((bit)&31) & REQUIRED_MASK10)) || \ | |
63 | (((bit)>>5)==11 && (1UL<<((bit)&31) & REQUIRED_MASK11)) || \ | |
64 | (((bit)>>5)==12 && (1UL<<((bit)&31) & REQUIRED_MASK12)) || \ | |
65 | (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK13)) || \ | |
66 | (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK14)) || \ | |
67 | (((bit)>>5)==13 && (1UL<<((bit)&31) & REQUIRED_MASK15)) || \ | |
68 | (((bit)>>5)==14 && (1UL<<((bit)&31) & REQUIRED_MASK16)) ) | |
349c004e | 69 | |
381aa07a | 70 | #define DISABLED_MASK_BIT_SET(bit) \ |
dfb4a70f DH |
71 | ( (((bit)>>5)==0 && (1UL<<((bit)&31) & DISABLED_MASK0 )) || \ |
72 | (((bit)>>5)==1 && (1UL<<((bit)&31) & DISABLED_MASK1 )) || \ | |
73 | (((bit)>>5)==2 && (1UL<<((bit)&31) & DISABLED_MASK2 )) || \ | |
74 | (((bit)>>5)==3 && (1UL<<((bit)&31) & DISABLED_MASK3 )) || \ | |
75 | (((bit)>>5)==4 && (1UL<<((bit)&31) & DISABLED_MASK4 )) || \ | |
76 | (((bit)>>5)==5 && (1UL<<((bit)&31) & DISABLED_MASK5 )) || \ | |
77 | (((bit)>>5)==6 && (1UL<<((bit)&31) & DISABLED_MASK6 )) || \ | |
78 | (((bit)>>5)==7 && (1UL<<((bit)&31) & DISABLED_MASK7 )) || \ | |
79 | (((bit)>>5)==8 && (1UL<<((bit)&31) & DISABLED_MASK8 )) || \ | |
80 | (((bit)>>5)==9 && (1UL<<((bit)&31) & DISABLED_MASK9 )) || \ | |
81 | (((bit)>>5)==10 && (1UL<<((bit)&31) & DISABLED_MASK10)) || \ | |
82 | (((bit)>>5)==11 && (1UL<<((bit)&31) & DISABLED_MASK11)) || \ | |
83 | (((bit)>>5)==12 && (1UL<<((bit)&31) & DISABLED_MASK12)) || \ | |
84 | (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK13)) || \ | |
85 | (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK14)) || \ | |
86 | (((bit)>>5)==13 && (1UL<<((bit)&31) & DISABLED_MASK15)) || \ | |
87 | (((bit)>>5)==14 && (1UL<<((bit)&31) & DISABLED_MASK16)) ) | |
381aa07a | 88 | |
349c004e CL |
89 | #define cpu_has(c, bit) \ |
90 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ | |
0f8d2b92 IM |
91 | test_cpu_cap(c, bit)) |
92 | ||
349c004e CL |
93 | #define this_cpu_has(bit) \ |
94 | (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ | |
95 | x86_this_cpu_test_bit(bit, (unsigned long *)&cpu_info.x86_capability)) | |
96 | ||
381aa07a DH |
97 | /* |
98 | * This macro is for detection of features which need kernel | |
99 | * infrastructure to be used. It may *not* directly test the CPU | |
100 | * itself. Use the cpu_has() family if you want true runtime | |
101 | * testing of CPU features, like in hypervisor code where you are | |
102 | * supporting a possible guest feature where host support for it | |
103 | * is not relevant. | |
104 | */ | |
105 | #define cpu_feature_enabled(bit) \ | |
f2cc8e07 | 106 | (__builtin_constant_p(bit) && DISABLED_MASK_BIT_SET(bit) ? 0 : static_cpu_has(bit)) |
381aa07a | 107 | |
7b11fb51 PA |
108 | #define boot_cpu_has(bit) cpu_has(&boot_cpu_data, bit) |
109 | ||
53756d37 JF |
110 | #define set_cpu_cap(c, bit) set_bit(bit, (unsigned long *)((c)->x86_capability)) |
111 | #define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) | |
7d851c8d AK |
112 | #define setup_clear_cpu_cap(bit) do { \ |
113 | clear_cpu_cap(&boot_cpu_data, bit); \ | |
3e0c3737 | 114 | set_bit(bit, (unsigned long *)cpu_caps_cleared); \ |
7d851c8d | 115 | } while (0) |
404ee5b1 AK |
116 | #define setup_force_cpu_cap(bit) do { \ |
117 | set_cpu_cap(&boot_cpu_data, bit); \ | |
3e0c3737 | 118 | set_bit(bit, (unsigned long *)cpu_caps_set); \ |
404ee5b1 | 119 | } while (0) |
53756d37 | 120 | |
7b11fb51 | 121 | #define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) |
7b11fb51 | 122 | #define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC) |
7b11fb51 | 123 | #define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC) |
7b11fb51 PA |
124 | #define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR) |
125 | #define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM) | |
66be8951 | 126 | #define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX) |
f1240c00 | 127 | #define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE) |
6229ad27 | 128 | #define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES) |
362f924b | 129 | /* |
bc696ca0 | 130 | * Do not add any more of those clumsy macros - use static_cpu_has() for |
362f924b BP |
131 | * fast paths and boot_cpu_has() otherwise! |
132 | */ | |
7b11fb51 | 133 | |
a362bf9f | 134 | #if defined(CC_HAVE_ASM_GOTO) && defined(CONFIG_X86_FAST_FEATURE_TESTS) |
a3c8acd0 PA |
135 | /* |
136 | * Static testing of CPU features. Used the same as boot_cpu_has(). | |
a362bf9f BP |
137 | * These will statically patch the target code for additional |
138 | * performance. | |
a3c8acd0 | 139 | */ |
bc696ca0 | 140 | static __always_inline __pure bool _static_cpu_has(u16 bit) |
4a90a99c | 141 | { |
2476f2fa | 142 | asm_volatile_goto("1: jmp 6f\n" |
4a90a99c | 143 | "2:\n" |
4332195c BP |
144 | ".skip -(((5f-4f) - (2b-1b)) > 0) * " |
145 | "((5f-4f) - (2b-1b)),0x90\n" | |
146 | "3:\n" | |
4a90a99c BP |
147 | ".section .altinstructions,\"a\"\n" |
148 | " .long 1b - .\n" /* src offset */ | |
4332195c | 149 | " .long 4f - .\n" /* repl offset */ |
4a90a99c | 150 | " .word %P1\n" /* always replace */ |
4332195c BP |
151 | " .byte 3b - 1b\n" /* src len */ |
152 | " .byte 5f - 4f\n" /* repl len */ | |
153 | " .byte 3b - 2b\n" /* pad len */ | |
4a90a99c BP |
154 | ".previous\n" |
155 | ".section .altinstr_replacement,\"ax\"\n" | |
48c7a250 | 156 | "4: jmp %l[t_no]\n" |
4332195c | 157 | "5:\n" |
4a90a99c BP |
158 | ".previous\n" |
159 | ".section .altinstructions,\"a\"\n" | |
160 | " .long 1b - .\n" /* src offset */ | |
161 | " .long 0\n" /* no replacement */ | |
162 | " .word %P0\n" /* feature bit */ | |
4332195c | 163 | " .byte 3b - 1b\n" /* src len */ |
4a90a99c | 164 | " .byte 0\n" /* repl len */ |
4332195c | 165 | " .byte 0\n" /* pad len */ |
4a90a99c | 166 | ".previous\n" |
2476f2fa BG |
167 | ".section .altinstr_aux,\"ax\"\n" |
168 | "6:\n" | |
169 | " testb %[bitnum],%[cap_byte]\n" | |
170 | " jnz %l[t_yes]\n" | |
171 | " jmp %l[t_no]\n" | |
172 | ".previous\n" | |
173 | : : "i" (bit), "i" (X86_FEATURE_ALWAYS), | |
174 | [bitnum] "i" (1 << (bit & 7)), | |
175 | [cap_byte] "m" (((const char *)boot_cpu_data.x86_capability)[bit >> 3]) | |
176 | : : t_yes, t_no); | |
177 | t_yes: | |
4a90a99c BP |
178 | return true; |
179 | t_no: | |
180 | return false; | |
4a90a99c BP |
181 | } |
182 | ||
bc696ca0 | 183 | #define static_cpu_has(bit) \ |
4a90a99c BP |
184 | ( \ |
185 | __builtin_constant_p(boot_cpu_has(bit)) ? \ | |
186 | boot_cpu_has(bit) : \ | |
bc696ca0 | 187 | _static_cpu_has(bit) \ |
4a90a99c | 188 | ) |
1ba4f22c PA |
189 | #else |
190 | /* | |
a362bf9f BP |
191 | * Fall back to dynamic for gcc versions which don't support asm goto. Should be |
192 | * a minority now anyway. | |
1ba4f22c | 193 | */ |
4a90a99c | 194 | #define static_cpu_has(bit) boot_cpu_has(bit) |
1ba4f22c | 195 | #endif |
a3c8acd0 | 196 | |
9b13a93d BP |
197 | #define cpu_has_bug(c, bit) cpu_has(c, (bit)) |
198 | #define set_cpu_bug(c, bit) set_cpu_cap(c, (bit)) | |
199 | #define clear_cpu_bug(c, bit) clear_cpu_cap(c, (bit)) | |
65fc985b | 200 | |
9b13a93d | 201 | #define static_cpu_has_bug(bit) static_cpu_has((bit)) |
9b13a93d | 202 | #define boot_cpu_has_bug(bit) cpu_has_bug(&boot_cpu_data, (bit)) |
65fc985b | 203 | |
9b13a93d BP |
204 | #define MAX_CPU_FEATURES (NCAPINTS * 32) |
205 | #define cpu_have_feature boot_cpu_has | |
2b9c1f03 | 206 | |
9b13a93d BP |
207 | #define CPU_FEATURE_TYPEFMT "x86,ven%04Xfam%04Xmod%04X" |
208 | #define CPU_FEATURE_TYPEVAL boot_cpu_data.x86_vendor, boot_cpu_data.x86, \ | |
209 | boot_cpu_data.x86_model | |
2b9c1f03 | 210 | |
fa1408e4 | 211 | #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */ |
1965aae3 | 212 | #endif /* _ASM_X86_CPUFEATURE_H */ |