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1965aae3 PA |
1 | #ifndef _ASM_X86_APICDEF_H |
2 | #define _ASM_X86_APICDEF_H | |
2d539553 TG |
3 | |
4 | /* | |
5 | * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) | |
6 | * | |
7 | * Alan Cox <Alan.Cox@linux.org>, 1995. | |
8 | * Ingo Molnar <mingo@redhat.com>, 1999, 2000 | |
9 | */ | |
10 | ||
8f3e1df4 CG |
11 | #define IO_APIC_DEFAULT_PHYS_BASE 0xfec00000 |
12 | #define APIC_DEFAULT_PHYS_BASE 0xfee00000 | |
2d539553 | 13 | |
e79c65a9 CG |
14 | /* |
15 | * This is the IO-APIC register space as specified | |
16 | * by Intel docs: | |
17 | */ | |
18 | #define IO_APIC_SLOT_SIZE 1024 | |
19 | ||
2d539553 TG |
20 | #define APIC_ID 0x20 |
21 | ||
2d539553 TG |
22 | #define APIC_LVR 0x30 |
23 | #define APIC_LVR_MASK 0xFF00FF | |
fc61b800 | 24 | #define APIC_LVR_DIRECTED_EOI (1 << 24) |
79a4a961 JP |
25 | #define GET_APIC_VERSION(x) ((x) & 0xFFu) |
26 | #define GET_APIC_MAXLVT(x) (((x) >> 16) & 0xFFu) | |
ac56ef61 | 27 | #ifdef CONFIG_X86_32 |
79a4a961 | 28 | # define APIC_INTEGRATED(x) ((x) & 0xF0u) |
ac56ef61 GOC |
29 | #else |
30 | # define APIC_INTEGRATED(x) (1) | |
31 | #endif | |
2d539553 | 32 | #define APIC_XAPIC(x) ((x) >= 0x14) |
97a52714 | 33 | #define APIC_EXT_SPACE(x) ((x) & 0x80000000) |
2d539553 TG |
34 | #define APIC_TASKPRI 0x80 |
35 | #define APIC_TPRI_MASK 0xFFu | |
36 | #define APIC_ARBPRI 0x90 | |
37 | #define APIC_ARBPRI_MASK 0xFFu | |
38 | #define APIC_PROCPRI 0xA0 | |
39 | #define APIC_EOI 0xB0 | |
40 | #define APIC_EIO_ACK 0x0 | |
41 | #define APIC_RRR 0xC0 | |
42 | #define APIC_LDR 0xD0 | |
79a4a961 JP |
43 | #define APIC_LDR_MASK (0xFFu << 24) |
44 | #define GET_APIC_LOGICAL_ID(x) (((x) >> 24) & 0xFFu) | |
45 | #define SET_APIC_LOGICAL_ID(x) (((x) << 24)) | |
2d539553 TG |
46 | #define APIC_ALL_CPUS 0xFFu |
47 | #define APIC_DFR 0xE0 | |
48 | #define APIC_DFR_CLUSTER 0x0FFFFFFFul | |
49 | #define APIC_DFR_FLAT 0xFFFFFFFFul | |
50 | #define APIC_SPIV 0xF0 | |
fc61b800 | 51 | #define APIC_SPIV_DIRECTED_EOI (1 << 12) |
79a4a961 JP |
52 | #define APIC_SPIV_FOCUS_DISABLED (1 << 9) |
53 | #define APIC_SPIV_APIC_ENABLED (1 << 8) | |
2d539553 TG |
54 | #define APIC_ISR 0x100 |
55 | #define APIC_ISR_NR 0x8 /* Number of 32 bit ISR registers. */ | |
56 | #define APIC_TMR 0x180 | |
57 | #define APIC_IRR 0x200 | |
58 | #define APIC_ESR 0x280 | |
59 | #define APIC_ESR_SEND_CS 0x00001 | |
60 | #define APIC_ESR_RECV_CS 0x00002 | |
61 | #define APIC_ESR_SEND_ACC 0x00004 | |
62 | #define APIC_ESR_RECV_ACC 0x00008 | |
63 | #define APIC_ESR_SENDILL 0x00020 | |
64 | #define APIC_ESR_RECVILL 0x00040 | |
65 | #define APIC_ESR_ILLREGA 0x00080 | |
03195c6b | 66 | #define APIC_LVTCMCI 0x2f0 |
2d539553 TG |
67 | #define APIC_ICR 0x300 |
68 | #define APIC_DEST_SELF 0x40000 | |
69 | #define APIC_DEST_ALLINC 0x80000 | |
70 | #define APIC_DEST_ALLBUT 0xC0000 | |
71 | #define APIC_ICR_RR_MASK 0x30000 | |
72 | #define APIC_ICR_RR_INVALID 0x00000 | |
73 | #define APIC_ICR_RR_INPROG 0x10000 | |
74 | #define APIC_ICR_RR_VALID 0x20000 | |
75 | #define APIC_INT_LEVELTRIG 0x08000 | |
76 | #define APIC_INT_ASSERT 0x04000 | |
77 | #define APIC_ICR_BUSY 0x01000 | |
78 | #define APIC_DEST_LOGICAL 0x00800 | |
79 | #define APIC_DEST_PHYSICAL 0x00000 | |
80 | #define APIC_DM_FIXED 0x00000 | |
81 | #define APIC_DM_LOWEST 0x00100 | |
82 | #define APIC_DM_SMI 0x00200 | |
83 | #define APIC_DM_REMRD 0x00300 | |
84 | #define APIC_DM_NMI 0x00400 | |
85 | #define APIC_DM_INIT 0x00500 | |
86 | #define APIC_DM_STARTUP 0x00600 | |
87 | #define APIC_DM_EXTINT 0x00700 | |
88 | #define APIC_VECTOR_MASK 0x000FF | |
89 | #define APIC_ICR2 0x310 | |
79a4a961 JP |
90 | #define GET_APIC_DEST_FIELD(x) (((x) >> 24) & 0xFF) |
91 | #define SET_APIC_DEST_FIELD(x) ((x) << 24) | |
2d539553 TG |
92 | #define APIC_LVTT 0x320 |
93 | #define APIC_LVTTHMR 0x330 | |
94 | #define APIC_LVTPC 0x340 | |
95 | #define APIC_LVT0 0x350 | |
79a4a961 JP |
96 | #define APIC_LVT_TIMER_BASE_MASK (0x3 << 18) |
97 | #define GET_APIC_TIMER_BASE(x) (((x) >> 18) & 0x3) | |
98 | #define SET_APIC_TIMER_BASE(x) (((x) << 18)) | |
2d539553 TG |
99 | #define APIC_TIMER_BASE_CLKIN 0x0 |
100 | #define APIC_TIMER_BASE_TMBASE 0x1 | |
101 | #define APIC_TIMER_BASE_DIV 0x2 | |
79a4a961 JP |
102 | #define APIC_LVT_TIMER_PERIODIC (1 << 17) |
103 | #define APIC_LVT_MASKED (1 << 16) | |
104 | #define APIC_LVT_LEVEL_TRIGGER (1 << 15) | |
105 | #define APIC_LVT_REMOTE_IRR (1 << 14) | |
106 | #define APIC_INPUT_POLARITY (1 << 13) | |
107 | #define APIC_SEND_PENDING (1 << 12) | |
2d539553 | 108 | #define APIC_MODE_MASK 0x700 |
79a4a961 JP |
109 | #define GET_APIC_DELIVERY_MODE(x) (((x) >> 8) & 0x7) |
110 | #define SET_APIC_DELIVERY_MODE(x, y) (((x) & ~0x700) | ((y) << 8)) | |
2d539553 TG |
111 | #define APIC_MODE_FIXED 0x0 |
112 | #define APIC_MODE_NMI 0x4 | |
113 | #define APIC_MODE_EXTINT 0x7 | |
114 | #define APIC_LVT1 0x360 | |
115 | #define APIC_LVTERR 0x370 | |
116 | #define APIC_TMICT 0x380 | |
117 | #define APIC_TMCCT 0x390 | |
118 | #define APIC_TDCR 0x3E0 | |
13c88fb5 | 119 | #define APIC_SELF_IPI 0x3F0 |
79a4a961 | 120 | #define APIC_TDR_DIV_TMBASE (1 << 2) |
2d539553 TG |
121 | #define APIC_TDR_DIV_1 0xB |
122 | #define APIC_TDR_DIV_2 0x0 | |
123 | #define APIC_TDR_DIV_4 0x1 | |
124 | #define APIC_TDR_DIV_8 0x2 | |
125 | #define APIC_TDR_DIV_16 0x3 | |
126 | #define APIC_TDR_DIV_32 0x8 | |
127 | #define APIC_TDR_DIV_64 0x9 | |
128 | #define APIC_TDR_DIV_128 0xA | |
97a52714 AH |
129 | #define APIC_EFEAT 0x400 |
130 | #define APIC_ECTRL 0x410 | |
131 | #define APIC_EILVTn(n) (0x500 + 0x10 * n) | |
79a4a961 | 132 | #define APIC_EILVT_NR_AMD_K8 1 /* # of extended interrupts */ |
7b83dae7 | 133 | #define APIC_EILVT_NR_AMD_10H 4 |
a68c439b | 134 | #define APIC_EILVT_NR_MAX APIC_EILVT_NR_AMD_10H |
79a4a961 | 135 | #define APIC_EILVT_LVTOFF(x) (((x) >> 4) & 0xF) |
7b83dae7 RR |
136 | #define APIC_EILVT_MSG_FIX 0x0 |
137 | #define APIC_EILVT_MSG_SMI 0x2 | |
138 | #define APIC_EILVT_MSG_NMI 0x4 | |
139 | #define APIC_EILVT_MSG_EXT 0x7 | |
79a4a961 | 140 | #define APIC_EILVT_MASKED (1 << 16) |
cff90dbf | 141 | |
2d539553 | 142 | #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) |
13c88fb5 SS |
143 | #define APIC_BASE_MSR 0x800 |
144 | #define X2APIC_ENABLE (1UL << 10) | |
2d539553 | 145 | |
96a388de | 146 | #ifdef CONFIG_X86_32 |
2d539553 | 147 | # define MAX_IO_APICS 64 |
56d91f13 | 148 | # define MAX_LOCAL_APIC 256 |
96a388de | 149 | #else |
2d539553 | 150 | # define MAX_IO_APICS 128 |
a65d1d64 | 151 | # define MAX_LOCAL_APIC 32768 |
2d539553 TG |
152 | #endif |
153 | ||
154 | /* | |
155 | * All x86-64 systems are xAPIC compatible. | |
156 | * In the following, "apicid" is a physical APIC ID. | |
157 | */ | |
158 | #define XAPIC_DEST_CPUS_SHIFT 4 | |
159 | #define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1) | |
160 | #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT) | |
161 | #define APIC_CLUSTER(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK) | |
162 | #define APIC_CLUSTERID(apicid) (APIC_CLUSTER(apicid) >> XAPIC_DEST_CPUS_SHIFT) | |
163 | #define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK) | |
164 | #define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT) | |
165 | ||
166 | /* | |
167 | * the local APIC register structure, memory mapped. Not terribly well | |
168 | * tested, but we might eventually use this one in the future - the | |
169 | * problem why we cannot use it right now is the P5 APIC, it has an | |
170 | * errata which cannot take 8-bit reads and writes, only 32-bit ones ... | |
171 | */ | |
172 | #define u32 unsigned int | |
173 | ||
174 | struct local_apic { | |
175 | ||
176 | /*000*/ struct { u32 __reserved[4]; } __reserved_01; | |
177 | ||
178 | /*010*/ struct { u32 __reserved[4]; } __reserved_02; | |
179 | ||
180 | /*020*/ struct { /* APIC ID Register */ | |
181 | u32 __reserved_1 : 24, | |
182 | phys_apic_id : 4, | |
183 | __reserved_2 : 4; | |
184 | u32 __reserved[3]; | |
185 | } id; | |
186 | ||
187 | /*030*/ const | |
188 | struct { /* APIC Version Register */ | |
189 | u32 version : 8, | |
190 | __reserved_1 : 8, | |
191 | max_lvt : 8, | |
192 | __reserved_2 : 8; | |
193 | u32 __reserved[3]; | |
194 | } version; | |
195 | ||
196 | /*040*/ struct { u32 __reserved[4]; } __reserved_03; | |
197 | ||
198 | /*050*/ struct { u32 __reserved[4]; } __reserved_04; | |
199 | ||
200 | /*060*/ struct { u32 __reserved[4]; } __reserved_05; | |
201 | ||
202 | /*070*/ struct { u32 __reserved[4]; } __reserved_06; | |
203 | ||
204 | /*080*/ struct { /* Task Priority Register */ | |
205 | u32 priority : 8, | |
206 | __reserved_1 : 24; | |
207 | u32 __reserved_2[3]; | |
208 | } tpr; | |
209 | ||
210 | /*090*/ const | |
211 | struct { /* Arbitration Priority Register */ | |
212 | u32 priority : 8, | |
213 | __reserved_1 : 24; | |
214 | u32 __reserved_2[3]; | |
215 | } apr; | |
216 | ||
217 | /*0A0*/ const | |
218 | struct { /* Processor Priority Register */ | |
219 | u32 priority : 8, | |
220 | __reserved_1 : 24; | |
221 | u32 __reserved_2[3]; | |
222 | } ppr; | |
223 | ||
224 | /*0B0*/ struct { /* End Of Interrupt Register */ | |
225 | u32 eoi; | |
226 | u32 __reserved[3]; | |
227 | } eoi; | |
228 | ||
229 | /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; | |
230 | ||
231 | /*0D0*/ struct { /* Logical Destination Register */ | |
232 | u32 __reserved_1 : 24, | |
233 | logical_dest : 8; | |
234 | u32 __reserved_2[3]; | |
235 | } ldr; | |
236 | ||
237 | /*0E0*/ struct { /* Destination Format Register */ | |
238 | u32 __reserved_1 : 28, | |
239 | model : 4; | |
240 | u32 __reserved_2[3]; | |
241 | } dfr; | |
242 | ||
243 | /*0F0*/ struct { /* Spurious Interrupt Vector Register */ | |
244 | u32 spurious_vector : 8, | |
245 | apic_enabled : 1, | |
246 | focus_cpu : 1, | |
247 | __reserved_2 : 22; | |
248 | u32 __reserved_3[3]; | |
249 | } svr; | |
250 | ||
251 | /*100*/ struct { /* In Service Register */ | |
252 | /*170*/ u32 bitfield; | |
253 | u32 __reserved[3]; | |
254 | } isr [8]; | |
255 | ||
256 | /*180*/ struct { /* Trigger Mode Register */ | |
257 | /*1F0*/ u32 bitfield; | |
258 | u32 __reserved[3]; | |
259 | } tmr [8]; | |
260 | ||
261 | /*200*/ struct { /* Interrupt Request Register */ | |
262 | /*270*/ u32 bitfield; | |
263 | u32 __reserved[3]; | |
264 | } irr [8]; | |
265 | ||
266 | /*280*/ union { /* Error Status Register */ | |
267 | struct { | |
268 | u32 send_cs_error : 1, | |
269 | receive_cs_error : 1, | |
270 | send_accept_error : 1, | |
271 | receive_accept_error : 1, | |
272 | __reserved_1 : 1, | |
273 | send_illegal_vector : 1, | |
274 | receive_illegal_vector : 1, | |
275 | illegal_register_address : 1, | |
276 | __reserved_2 : 24; | |
277 | u32 __reserved_3[3]; | |
278 | } error_bits; | |
279 | struct { | |
280 | u32 errors; | |
281 | u32 __reserved_3[3]; | |
282 | } all_errors; | |
283 | } esr; | |
284 | ||
285 | /*290*/ struct { u32 __reserved[4]; } __reserved_08; | |
286 | ||
287 | /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; | |
288 | ||
289 | /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; | |
290 | ||
291 | /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; | |
292 | ||
293 | /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; | |
294 | ||
295 | /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; | |
296 | ||
297 | /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; | |
298 | ||
299 | /*300*/ struct { /* Interrupt Command Register 1 */ | |
300 | u32 vector : 8, | |
301 | delivery_mode : 3, | |
302 | destination_mode : 1, | |
303 | delivery_status : 1, | |
304 | __reserved_1 : 1, | |
305 | level : 1, | |
306 | trigger : 1, | |
307 | __reserved_2 : 2, | |
308 | shorthand : 2, | |
309 | __reserved_3 : 12; | |
310 | u32 __reserved_4[3]; | |
311 | } icr1; | |
312 | ||
313 | /*310*/ struct { /* Interrupt Command Register 2 */ | |
314 | union { | |
315 | u32 __reserved_1 : 24, | |
316 | phys_dest : 4, | |
317 | __reserved_2 : 4; | |
318 | u32 __reserved_3 : 24, | |
319 | logical_dest : 8; | |
320 | } dest; | |
321 | u32 __reserved_4[3]; | |
322 | } icr2; | |
323 | ||
324 | /*320*/ struct { /* LVT - Timer */ | |
325 | u32 vector : 8, | |
326 | __reserved_1 : 4, | |
327 | delivery_status : 1, | |
328 | __reserved_2 : 3, | |
329 | mask : 1, | |
330 | timer_mode : 1, | |
331 | __reserved_3 : 14; | |
332 | u32 __reserved_4[3]; | |
333 | } lvt_timer; | |
334 | ||
335 | /*330*/ struct { /* LVT - Thermal Sensor */ | |
336 | u32 vector : 8, | |
337 | delivery_mode : 3, | |
338 | __reserved_1 : 1, | |
339 | delivery_status : 1, | |
340 | __reserved_2 : 3, | |
341 | mask : 1, | |
342 | __reserved_3 : 15; | |
343 | u32 __reserved_4[3]; | |
344 | } lvt_thermal; | |
345 | ||
346 | /*340*/ struct { /* LVT - Performance Counter */ | |
347 | u32 vector : 8, | |
348 | delivery_mode : 3, | |
349 | __reserved_1 : 1, | |
350 | delivery_status : 1, | |
351 | __reserved_2 : 3, | |
352 | mask : 1, | |
353 | __reserved_3 : 15; | |
354 | u32 __reserved_4[3]; | |
355 | } lvt_pc; | |
356 | ||
357 | /*350*/ struct { /* LVT - LINT0 */ | |
358 | u32 vector : 8, | |
359 | delivery_mode : 3, | |
360 | __reserved_1 : 1, | |
361 | delivery_status : 1, | |
362 | polarity : 1, | |
363 | remote_irr : 1, | |
364 | trigger : 1, | |
365 | mask : 1, | |
366 | __reserved_2 : 15; | |
367 | u32 __reserved_3[3]; | |
368 | } lvt_lint0; | |
369 | ||
370 | /*360*/ struct { /* LVT - LINT1 */ | |
371 | u32 vector : 8, | |
372 | delivery_mode : 3, | |
373 | __reserved_1 : 1, | |
374 | delivery_status : 1, | |
375 | polarity : 1, | |
376 | remote_irr : 1, | |
377 | trigger : 1, | |
378 | mask : 1, | |
379 | __reserved_2 : 15; | |
380 | u32 __reserved_3[3]; | |
381 | } lvt_lint1; | |
382 | ||
383 | /*370*/ struct { /* LVT - Error */ | |
384 | u32 vector : 8, | |
385 | __reserved_1 : 4, | |
386 | delivery_status : 1, | |
387 | __reserved_2 : 3, | |
388 | mask : 1, | |
389 | __reserved_3 : 15; | |
390 | u32 __reserved_4[3]; | |
391 | } lvt_error; | |
392 | ||
393 | /*380*/ struct { /* Timer Initial Count Register */ | |
394 | u32 initial_count; | |
395 | u32 __reserved_2[3]; | |
396 | } timer_icr; | |
397 | ||
398 | /*390*/ const | |
399 | struct { /* Timer Current Count Register */ | |
400 | u32 curr_count; | |
401 | u32 __reserved_2[3]; | |
402 | } timer_ccr; | |
403 | ||
404 | /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; | |
405 | ||
406 | /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; | |
407 | ||
408 | /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; | |
409 | ||
410 | /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; | |
411 | ||
412 | /*3E0*/ struct { /* Timer Divide Configuration Register */ | |
413 | u32 divisor : 4, | |
414 | __reserved_1 : 28; | |
415 | u32 __reserved_2[3]; | |
416 | } timer_dcr; | |
417 | ||
418 | /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; | |
419 | ||
420 | } __attribute__ ((packed)); | |
421 | ||
422 | #undef u32 | |
423 | ||
a65d1d64 JS |
424 | #ifdef CONFIG_X86_32 |
425 | #define BAD_APICID 0xFFu | |
426 | #else | |
427 | #define BAD_APICID 0xFFFFu | |
428 | #endif | |
4e034b24 HK |
429 | |
430 | enum ioapic_irq_destination_types { | |
431 | dest_Fixed = 0, | |
432 | dest_LowestPrio = 1, | |
433 | dest_SMI = 2, | |
434 | dest__reserved_1 = 3, | |
435 | dest_NMI = 4, | |
436 | dest_INIT = 5, | |
437 | dest__reserved_2 = 6, | |
438 | dest_ExtINT = 7 | |
439 | }; | |
440 | ||
1965aae3 | 441 | #endif /* _ASM_X86_APICDEF_H */ |