x86/apic: Make cpu_mask_to_apicid() operations return error code
[linux-2.6-block.git] / arch / x86 / include / asm / apic.h
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1#ifndef _ASM_X86_APIC_H
2#define _ASM_X86_APIC_H
67c5fc5c 3
e2780a68 4#include <linux/cpumask.h>
e2780a68 5#include <linux/pm.h>
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6
7#include <asm/alternative.h>
e2780a68 8#include <asm/cpufeature.h>
67c5fc5c 9#include <asm/processor.h>
e2780a68 10#include <asm/apicdef.h>
60063497 11#include <linux/atomic.h>
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12#include <asm/fixmap.h>
13#include <asm/mpspec.h>
13c88fb5 14#include <asm/msr.h>
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15
16#define ARCH_APICTIMER_STOPS_ON_C3 1
17
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18/*
19 * Debugging macros
20 */
21#define APIC_QUIET 0
22#define APIC_VERBOSE 1
23#define APIC_DEBUG 2
24
25/*
26 * Define the default level of output to be very little
27 * This can be turned up by using apic=verbose for more
28 * information and apic=debug for _lots_ of information.
29 * apic_verbosity is defined in apic.c
30 */
31#define apic_printk(v, s, a...) do { \
32 if ((v) <= apic_verbosity) \
33 printk(s, ##a); \
34 } while (0)
35
36
160d8dac 37#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
67c5fc5c 38extern void generic_apic_probe(void);
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39#else
40static inline void generic_apic_probe(void)
41{
42}
43#endif
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44
45#ifdef CONFIG_X86_LOCAL_APIC
46
baa13188 47extern unsigned int apic_verbosity;
67c5fc5c 48extern int local_apic_timer_c2_ok;
67c5fc5c 49
3c999f14 50extern int disable_apic;
1ade93ef 51extern unsigned int lapic_timer_frequency;
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52
53#ifdef CONFIG_SMP
54extern void __inquire_remote_apic(int apicid);
55#else /* CONFIG_SMP */
56static inline void __inquire_remote_apic(int apicid)
57{
58}
59#endif /* CONFIG_SMP */
60
61static inline void default_inquire_remote_apic(int apicid)
62{
63 if (apic_verbosity >= APIC_DEBUG)
64 __inquire_remote_apic(apicid);
65}
66
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67/*
68 * With 82489DX we can't rely on apic feature bit
69 * retrieved via cpuid but still have to deal with
70 * such an apic chip so we assume that SMP configuration
71 * is found from MP table (64bit case uses ACPI mostly
72 * which set smp presence flag as well so we are safe
73 * to use this helper too).
74 */
75static inline bool apic_from_smp_config(void)
76{
77 return smp_found_config && !disable_apic;
78}
79
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80/*
81 * Basic functions accessing APICs.
82 */
83#ifdef CONFIG_PARAVIRT
84#include <asm/paravirt.h>
96a388de 85#endif
67c5fc5c 86
70511134 87#ifdef CONFIG_X86_64
aa7d8e25 88extern int is_vsmp_box(void);
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89#else
90static inline int is_vsmp_box(void)
91{
92 return 0;
93}
94#endif
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95extern void xapic_wait_icr_idle(void);
96extern u32 safe_xapic_wait_icr_idle(void);
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97extern void xapic_icr_write(u32, u32);
98extern int setup_profiling_timer(unsigned int);
aa7d8e25 99
1b374e4d 100static inline void native_apic_mem_write(u32 reg, u32 v)
67c5fc5c 101{
593f4a78 102 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
67c5fc5c 103
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104 alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP,
105 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
106 ASM_OUTPUT2("0" (v), "m" (*addr)));
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107}
108
1b374e4d 109static inline u32 native_apic_mem_read(u32 reg)
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110{
111 return *((volatile u32 *)(APIC_BASE + reg));
112}
113
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114extern void native_apic_wait_icr_idle(void);
115extern u32 native_safe_apic_wait_icr_idle(void);
116extern void native_apic_icr_write(u32 low, u32 id);
117extern u64 native_apic_icr_read(void);
118
fc1edaf9 119extern int x2apic_mode;
b24696bc 120
d0b03bd1 121#ifdef CONFIG_X86_X2APIC
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122/*
123 * Make previous memory operations globally visible before
124 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
125 * mfence for this.
126 */
127static inline void x2apic_wrmsr_fence(void)
128{
129 asm volatile("mfence" : : : "memory");
130}
131
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132static inline void native_apic_msr_write(u32 reg, u32 v)
133{
134 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
135 reg == APIC_LVR)
136 return;
137
138 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
139}
140
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141static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
142{
143 wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
144}
145
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146static inline u32 native_apic_msr_read(u32 reg)
147{
0059b243 148 u64 msr;
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149
150 if (reg == APIC_DFR)
151 return -1;
152
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153 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
154 return (u32)msr;
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155}
156
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157static inline void native_x2apic_wait_icr_idle(void)
158{
159 /* no need to wait for icr idle in x2apic */
160 return;
161}
162
163static inline u32 native_safe_x2apic_wait_icr_idle(void)
164{
165 /* no need to wait for icr idle in x2apic */
166 return 0;
167}
168
169static inline void native_x2apic_icr_write(u32 low, u32 id)
170{
171 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
172}
173
174static inline u64 native_x2apic_icr_read(void)
175{
176 unsigned long val;
177
178 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
179 return val;
180}
181
fc1edaf9 182extern int x2apic_phys;
fb209bd8 183extern int x2apic_preenabled;
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184extern void check_x2apic(void);
185extern void enable_x2apic(void);
6e1cb38a 186extern void x2apic_icr_write(u32 low, u32 id);
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187static inline int x2apic_enabled(void)
188{
0059b243 189 u64 msr;
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190
191 if (!cpu_has_x2apic)
192 return 0;
193
0059b243 194 rdmsrl(MSR_IA32_APICBASE, msr);
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195 if (msr & X2APIC_ENABLE)
196 return 1;
197 return 0;
198}
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199
200#define x2apic_supported() (cpu_has_x2apic)
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201static inline void x2apic_force_phys(void)
202{
203 x2apic_phys = 1;
204}
a11b5abe 205#else
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206static inline void disable_x2apic(void)
207{
208}
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209static inline void check_x2apic(void)
210{
211}
212static inline void enable_x2apic(void)
213{
214}
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215static inline int x2apic_enabled(void)
216{
217 return 0;
218}
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219static inline void x2apic_force_phys(void)
220{
221}
cf6567fe 222
a31bc327 223#define nox2apic 0
93758238 224#define x2apic_preenabled 0
fc1edaf9 225#define x2apic_supported() 0
c535b6a1 226#endif
1b374e4d 227
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228extern void enable_IR_x2apic(void);
229
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230extern int get_physical_broadcast(void);
231
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232extern int lapic_get_maxlvt(void);
233extern void clear_local_APIC(void);
234extern void connect_bsp_APIC(void);
235extern void disconnect_bsp_APIC(int virt_wire_setup);
236extern void disable_local_APIC(void);
237extern void lapic_shutdown(void);
238extern int verify_local_APIC(void);
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239extern void sync_Arb_IDs(void);
240extern void init_bsp_APIC(void);
241extern void setup_local_APIC(void);
739f33b3 242extern void end_local_APIC_setup(void);
2fb270f3 243extern void bsp_end_local_APIC_setup(void);
67c5fc5c 244extern void init_apic_mappings(void);
c0104d38 245void register_lapic_address(unsigned long address);
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246extern void setup_boot_APIC_clock(void);
247extern void setup_secondary_APIC_clock(void);
248extern int APIC_init_uniprocessor(void);
a906fdaa 249extern int apic_force_enable(unsigned long addr);
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250
251/*
252 * On 32bit this is mach-xxx local
253 */
254#ifdef CONFIG_X86_64
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255extern int apic_is_clustered_box(void);
256#else
257static inline int apic_is_clustered_box(void)
258{
259 return 0;
260}
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261#endif
262
27afdf20 263extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
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264
265#else /* !CONFIG_X86_LOCAL_APIC */
266static inline void lapic_shutdown(void) { }
267#define local_apic_timer_c2_ok 1
f3294a33 268static inline void init_apic_mappings(void) { }
d3ec5cae 269static inline void disable_local_APIC(void) { }
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270# define setup_boot_APIC_clock x86_init_noop
271# define setup_secondary_APIC_clock x86_init_noop
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272#endif /* !CONFIG_X86_LOCAL_APIC */
273
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274#ifdef CONFIG_X86_64
275#define SET_APIC_ID(x) (apic->set_apic_id(x))
276#else
277
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278#endif
279
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280/*
281 * Copyright 2004 James Cleverdon, IBM.
282 * Subject to the GNU Public License, v.2
283 *
284 * Generic APIC sub-arch data struct.
285 *
286 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
287 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
288 * James Cleverdon.
289 */
be163a15 290struct apic {
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291 char *name;
292
293 int (*probe)(void);
294 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
fa63030e 295 int (*apic_id_valid)(int apicid);
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296 int (*apic_id_registered)(void);
297
298 u32 irq_delivery_mode;
299 u32 irq_dest_mode;
300
301 const struct cpumask *(*target_cpus)(void);
302
303 int disable_esr;
304
305 int dest_logical;
7abc0753 306 unsigned long (*check_apicid_used)(physid_mask_t *map, int apicid);
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307 unsigned long (*check_apicid_present)(int apicid);
308
8637e38a 309 bool (*vector_allocation_domain)(int cpu, struct cpumask *retmask);
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310 void (*init_apic_ldr)(void);
311
7abc0753 312 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
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313
314 void (*setup_apic_routing)(void);
315 int (*multi_timer_check)(int apic, int irq);
e2780a68 316 int (*cpu_present_to_apicid)(int mps_cpu);
7abc0753 317 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
e2780a68 318 void (*setup_portio_remap)(void);
e11dadab 319 int (*check_phys_apicid_present)(int phys_apicid);
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320 void (*enable_apic_mode)(void);
321 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
322
323 /*
be163a15 324 * When one of the next two hooks returns 1 the apic
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325 * is switched to this. Essentially they are additional
326 * probe functions:
327 */
328 int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid);
329
330 unsigned int (*get_apic_id)(unsigned long x);
331 unsigned long (*set_apic_id)(unsigned int id);
332 unsigned long apic_id_mask;
333
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334 int (*cpu_mask_to_apicid)(const struct cpumask *cpumask,
335 unsigned int *apicid);
336 int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask,
337 const struct cpumask *andmask,
338 unsigned int *apicid);
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339
340 /* ipi */
341 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
342 void (*send_IPI_mask_allbutself)(const struct cpumask *mask,
343 int vector);
344 void (*send_IPI_allbutself)(int vector);
345 void (*send_IPI_all)(int vector);
346 void (*send_IPI_self)(int vector);
347
348 /* wakeup_secondary_cpu */
1f5bcabf 349 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
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350
351 int trampoline_phys_low;
352 int trampoline_phys_high;
353
354 void (*wait_for_init_deassert)(atomic_t *deassert);
355 void (*smp_callin_clear_local_apic)(void);
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356 void (*inquire_remote_apic)(int apicid);
357
358 /* apic ops */
359 u32 (*read)(u32 reg);
360 void (*write)(u32 reg, u32 v);
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361 /*
362 * ->eoi_write() has the same signature as ->write().
363 *
364 * Drivers can support both ->eoi_write() and ->write() by passing the same
365 * callback value. Kernel can override ->eoi_write() and fall back
366 * on write for EOI.
367 */
368 void (*eoi_write)(u32 reg, u32 v);
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369 u64 (*icr_read)(void);
370 void (*icr_write)(u32 low, u32 high);
371 void (*wait_icr_idle)(void);
372 u32 (*safe_wait_icr_idle)(void);
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373
374#ifdef CONFIG_X86_32
375 /*
376 * Called very early during boot from get_smp_config(). It should
377 * return the logical apicid. x86_[bios]_cpu_to_apicid is
378 * initialized before this function is called.
379 *
380 * If logical apicid can't be determined that early, the function
381 * may return BAD_APICID. Logical apicid will be configured after
382 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
383 * won't be applied properly during early boot in this case.
384 */
385 int (*x86_32_early_logical_apicid)(int cpu);
89e5dc21 386
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387 /*
388 * Optional method called from setup_local_APIC() after logical
389 * apicid is guaranteed to be known to initialize apicid -> node
390 * mapping if NUMA initialization hasn't done so already. Don't
391 * add new users.
392 */
89e5dc21 393 int (*x86_32_numa_cpu_node)(int cpu);
acb8bc09 394#endif
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395};
396
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397/*
398 * Pointer to the local APIC driver in use on this system (there's
399 * always just one such driver in use - the kernel decides via an
400 * early probing process which one it picks - and then sticks to it):
401 */
be163a15 402extern struct apic *apic;
0917c01f 403
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404/*
405 * APIC drivers are probed based on how they are listed in the .apicdrivers
406 * section. So the order is important and enforced by the ordering
407 * of different apic driver files in the Makefile.
408 *
409 * For the files having two apic drivers, we use apic_drivers()
410 * to enforce the order with in them.
411 */
412#define apic_driver(sym) \
413 static struct apic *__apicdrivers_##sym __used \
414 __aligned(sizeof(struct apic *)) \
415 __section(.apicdrivers) = { &sym }
416
417#define apic_drivers(sym1, sym2) \
418 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
419 __aligned(sizeof(struct apic *)) \
420 __section(.apicdrivers) = { &sym1, &sym2 }
421
422extern struct apic *__apicdrivers[], *__apicdrivers_end[];
423
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424/*
425 * APIC functionality to boot other CPUs - only used on SMP:
426 */
427#ifdef CONFIG_SMP
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428extern atomic_t init_deasserted;
429extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
0917c01f 430#endif
e2780a68 431
d674cd19 432#ifdef CONFIG_X86_LOCAL_APIC
346b46be 433
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434static inline u32 apic_read(u32 reg)
435{
436 return apic->read(reg);
437}
438
439static inline void apic_write(u32 reg, u32 val)
440{
441 apic->write(reg, val);
442}
443
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444static inline void apic_eoi(void)
445{
446 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
447}
448
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449static inline u64 apic_icr_read(void)
450{
451 return apic->icr_read();
452}
453
454static inline void apic_icr_write(u32 low, u32 high)
455{
456 apic->icr_write(low, high);
457}
458
459static inline void apic_wait_icr_idle(void)
460{
461 apic->wait_icr_idle();
462}
463
464static inline u32 safe_apic_wait_icr_idle(void)
465{
466 return apic->safe_wait_icr_idle();
467}
468
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469#else /* CONFIG_X86_LOCAL_APIC */
470
471static inline u32 apic_read(u32 reg) { return 0; }
472static inline void apic_write(u32 reg, u32 val) { }
2a43195d 473static inline void apic_eoi(void) { }
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474static inline u64 apic_icr_read(void) { return 0; }
475static inline void apic_icr_write(u32 low, u32 high) { }
476static inline void apic_wait_icr_idle(void) { }
477static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
478
479#endif /* CONFIG_X86_LOCAL_APIC */
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480
481static inline void ack_APIC_irq(void)
482{
483 /*
484 * ack_APIC_irq() actually gets compiled as a single instruction
485 * ... yummie.
486 */
2a43195d 487 apic_eoi();
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488}
489
490static inline unsigned default_get_apic_id(unsigned long x)
491{
492 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
493
42937e81 494 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
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495 return (x >> 24) & 0xFF;
496 else
497 return (x >> 24) & 0x0F;
498}
499
500/*
501 * Warm reset vector default position:
502 */
503#define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467
504#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
505
2b6163bf 506#ifdef CONFIG_X86_64
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507extern int default_acpi_madt_oem_check(char *, char *);
508
509extern void apic_send_IPI_self(int vector);
510
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511DECLARE_PER_CPU(int, x2apic_extra_bits);
512
513extern int default_cpu_present_to_apicid(int mps_cpu);
e11dadab 514extern int default_check_phys_apicid_present(int phys_apicid);
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515#endif
516
517static inline void default_wait_for_init_deassert(atomic_t *deassert)
518{
519 while (!atomic_read(deassert))
520 cpu_relax();
521 return;
522}
523
838312be 524extern void generic_bigsmp_probe(void);
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525
526
527#ifdef CONFIG_X86_LOCAL_APIC
528
529#include <asm/smp.h>
530
531#define APIC_DFR_VALUE (APIC_DFR_FLAT)
532
533static inline const struct cpumask *default_target_cpus(void)
534{
535#ifdef CONFIG_SMP
536 return cpu_online_mask;
537#else
538 return cpumask_of(0);
539#endif
540}
541
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542static inline const struct cpumask *online_target_cpus(void)
543{
544 return cpu_online_mask;
545}
546
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547DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
548
549
550static inline unsigned int read_apic_id(void)
551{
552 unsigned int reg;
553
554 reg = apic_read(APIC_ID);
555
556 return apic->get_apic_id(reg);
557}
558
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559static inline int default_apic_id_valid(int apicid)
560{
b7157acf 561 return (apicid < 255);
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562}
563
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564extern void default_setup_apic_routing(void);
565
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566extern struct apic apic_noop;
567
e2780a68 568#ifdef CONFIG_X86_32
2c1b284e 569
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570static inline int noop_x86_32_early_logical_apicid(int cpu)
571{
572 return BAD_APICID;
573}
574
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575/*
576 * Set up the logical destination ID.
577 *
578 * Intel recommends to set DFR, LDR and TPR before enabling
579 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
580 * document number 292116). So here it goes...
581 */
582extern void default_init_apic_ldr(void);
583
584static inline int default_apic_id_registered(void)
585{
586 return physid_isset(read_apic_id(), phys_cpu_present_map);
587}
588
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589static inline int default_phys_pkg_id(int cpuid_apic, int index_msb)
590{
591 return cpuid_apic >> index_msb;
592}
593
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594#endif
595
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596static inline int
597__flat_cpu_mask_to_apicid(unsigned long cpu_mask, unsigned int *apicid)
e2780a68 598{
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599 cpu_mask &= APIC_ALL_CPUS;
600 if (likely(cpu_mask)) {
601 *apicid = (unsigned int)cpu_mask;
602 return 0;
603 } else {
604 return -EINVAL;
605 }
606}
607
608static inline int
609flat_cpu_mask_to_apicid(const struct cpumask *cpumask,
610 unsigned int *apicid)
611{
612 return __flat_cpu_mask_to_apicid(cpumask_bits(cpumask)[0], apicid);
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613}
614
ff164324 615static inline int
6398268d 616flat_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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617 const struct cpumask *andmask,
618 unsigned int *apicid)
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619{
620 unsigned long mask1 = cpumask_bits(cpumask)[0];
621 unsigned long mask2 = cpumask_bits(andmask)[0];
622 unsigned long mask3 = cpumask_bits(cpu_online_mask)[0];
623
ff164324 624 return __flat_cpu_mask_to_apicid(mask1 & mask2 & mask3, apicid);
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625}
626
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627extern int
628default_cpu_mask_to_apicid(const struct cpumask *cpumask,
629 unsigned int *apicid);
6398268d 630
ff164324 631extern int
6398268d 632default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
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633 const struct cpumask *andmask,
634 unsigned int *apicid);
6398268d 635
8637e38a 636static inline bool
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637flat_vector_allocation_domain(int cpu, struct cpumask *retmask)
638{
639 /* Careful. Some cpus do not strictly honor the set of cpus
640 * specified in the interrupt destination when using lowest
641 * priority interrupt delivery mode.
642 *
643 * In particular there was a hyperthreading cpu observed to
644 * deliver interrupts to the wrong hyperthread when only one
645 * hyperthread was specified in the interrupt desitination.
646 */
647 cpumask_clear(retmask);
648 cpumask_bits(retmask)[0] = APIC_ALL_CPUS;
8637e38a 649 return false;
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650}
651
8637e38a 652static inline bool
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653default_vector_allocation_domain(int cpu, struct cpumask *retmask)
654{
655 cpumask_copy(retmask, cpumask_of(cpu));
8637e38a 656 return true;
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657}
658
7abc0753 659static inline unsigned long default_check_apicid_used(physid_mask_t *map, int apicid)
e2780a68 660{
7abc0753 661 return physid_isset(apicid, *map);
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662}
663
664static inline unsigned long default_check_apicid_present(int bit)
665{
666 return physid_isset(bit, phys_cpu_present_map);
667}
668
7abc0753 669static inline void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap)
e2780a68 670{
7abc0753 671 *retmap = *phys_map;
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672}
673
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674static inline int __default_cpu_present_to_apicid(int mps_cpu)
675{
676 if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu))
677 return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu);
678 else
679 return BAD_APICID;
680}
681
682static inline int
e11dadab 683__default_check_phys_apicid_present(int phys_apicid)
e2780a68 684{
e11dadab 685 return physid_isset(phys_apicid, phys_cpu_present_map);
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686}
687
688#ifdef CONFIG_X86_32
689static inline int default_cpu_present_to_apicid(int mps_cpu)
690{
691 return __default_cpu_present_to_apicid(mps_cpu);
692}
693
694static inline int
e11dadab 695default_check_phys_apicid_present(int phys_apicid)
e2780a68 696{
e11dadab 697 return __default_check_phys_apicid_present(phys_apicid);
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698}
699#else
700extern int default_cpu_present_to_apicid(int mps_cpu);
e11dadab 701extern int default_check_phys_apicid_present(int phys_apicid);
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702#endif
703
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704#endif /* CONFIG_X86_LOCAL_APIC */
705
1965aae3 706#endif /* _ASM_X86_APIC_H */