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1965aae3 PA |
1 | #ifndef _ASM_X86_APIC_H |
2 | #define _ASM_X86_APIC_H | |
67c5fc5c | 3 | |
e2780a68 | 4 | #include <linux/cpumask.h> |
67c5fc5c | 5 | #include <linux/delay.h> |
e2780a68 | 6 | #include <linux/pm.h> |
593f4a78 MR |
7 | |
8 | #include <asm/alternative.h> | |
e2780a68 | 9 | #include <asm/cpufeature.h> |
67c5fc5c | 10 | #include <asm/processor.h> |
e2780a68 IM |
11 | #include <asm/apicdef.h> |
12 | #include <asm/atomic.h> | |
13 | #include <asm/fixmap.h> | |
14 | #include <asm/mpspec.h> | |
67c5fc5c | 15 | #include <asm/system.h> |
13c88fb5 | 16 | #include <asm/msr.h> |
67c5fc5c TG |
17 | |
18 | #define ARCH_APICTIMER_STOPS_ON_C3 1 | |
19 | ||
67c5fc5c TG |
20 | /* |
21 | * Debugging macros | |
22 | */ | |
23 | #define APIC_QUIET 0 | |
24 | #define APIC_VERBOSE 1 | |
25 | #define APIC_DEBUG 2 | |
26 | ||
27 | /* | |
28 | * Define the default level of output to be very little | |
29 | * This can be turned up by using apic=verbose for more | |
30 | * information and apic=debug for _lots_ of information. | |
31 | * apic_verbosity is defined in apic.c | |
32 | */ | |
33 | #define apic_printk(v, s, a...) do { \ | |
34 | if ((v) <= apic_verbosity) \ | |
35 | printk(s, ##a); \ | |
36 | } while (0) | |
37 | ||
38 | ||
160d8dac | 39 | #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32) |
67c5fc5c | 40 | extern void generic_apic_probe(void); |
160d8dac IM |
41 | #else |
42 | static inline void generic_apic_probe(void) | |
43 | { | |
44 | } | |
45 | #endif | |
67c5fc5c TG |
46 | |
47 | #ifdef CONFIG_X86_LOCAL_APIC | |
48 | ||
baa13188 | 49 | extern unsigned int apic_verbosity; |
67c5fc5c | 50 | extern int local_apic_timer_c2_ok; |
67c5fc5c | 51 | |
3c999f14 | 52 | extern int disable_apic; |
0939e4fd IM |
53 | |
54 | #ifdef CONFIG_SMP | |
55 | extern void __inquire_remote_apic(int apicid); | |
56 | #else /* CONFIG_SMP */ | |
57 | static inline void __inquire_remote_apic(int apicid) | |
58 | { | |
59 | } | |
60 | #endif /* CONFIG_SMP */ | |
61 | ||
62 | static inline void default_inquire_remote_apic(int apicid) | |
63 | { | |
64 | if (apic_verbosity >= APIC_DEBUG) | |
65 | __inquire_remote_apic(apicid); | |
66 | } | |
67 | ||
67c5fc5c TG |
68 | /* |
69 | * Basic functions accessing APICs. | |
70 | */ | |
71 | #ifdef CONFIG_PARAVIRT | |
72 | #include <asm/paravirt.h> | |
96a388de | 73 | #else |
67c5fc5c TG |
74 | #define setup_boot_clock setup_boot_APIC_clock |
75 | #define setup_secondary_clock setup_secondary_APIC_clock | |
96a388de | 76 | #endif |
67c5fc5c | 77 | |
aa7d8e25 | 78 | extern int is_vsmp_box(void); |
2b97df06 JS |
79 | extern void xapic_wait_icr_idle(void); |
80 | extern u32 safe_xapic_wait_icr_idle(void); | |
2b97df06 JS |
81 | extern void xapic_icr_write(u32, u32); |
82 | extern int setup_profiling_timer(unsigned int); | |
aa7d8e25 | 83 | |
1b374e4d | 84 | static inline void native_apic_mem_write(u32 reg, u32 v) |
67c5fc5c | 85 | { |
593f4a78 | 86 | volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg); |
67c5fc5c | 87 | |
593f4a78 MR |
88 | alternative_io("movl %0, %1", "xchgl %0, %1", X86_FEATURE_11AP, |
89 | ASM_OUTPUT2("=r" (v), "=m" (*addr)), | |
90 | ASM_OUTPUT2("0" (v), "m" (*addr))); | |
67c5fc5c TG |
91 | } |
92 | ||
1b374e4d | 93 | static inline u32 native_apic_mem_read(u32 reg) |
67c5fc5c TG |
94 | { |
95 | return *((volatile u32 *)(APIC_BASE + reg)); | |
96 | } | |
97 | ||
c1eeb2de YL |
98 | extern void native_apic_wait_icr_idle(void); |
99 | extern u32 native_safe_apic_wait_icr_idle(void); | |
100 | extern void native_apic_icr_write(u32 low, u32 id); | |
101 | extern u64 native_apic_icr_read(void); | |
102 | ||
103 | #ifdef CONFIG_X86_X2APIC | |
13c88fb5 SS |
104 | static inline void native_apic_msr_write(u32 reg, u32 v) |
105 | { | |
106 | if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR || | |
107 | reg == APIC_LVR) | |
108 | return; | |
109 | ||
110 | wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0); | |
111 | } | |
112 | ||
113 | static inline u32 native_apic_msr_read(u32 reg) | |
114 | { | |
115 | u32 low, high; | |
116 | ||
117 | if (reg == APIC_DFR) | |
118 | return -1; | |
119 | ||
120 | rdmsr(APIC_BASE_MSR + (reg >> 4), low, high); | |
121 | return low; | |
122 | } | |
123 | ||
c1eeb2de YL |
124 | static inline void native_x2apic_wait_icr_idle(void) |
125 | { | |
126 | /* no need to wait for icr idle in x2apic */ | |
127 | return; | |
128 | } | |
129 | ||
130 | static inline u32 native_safe_x2apic_wait_icr_idle(void) | |
131 | { | |
132 | /* no need to wait for icr idle in x2apic */ | |
133 | return 0; | |
134 | } | |
135 | ||
136 | static inline void native_x2apic_icr_write(u32 low, u32 id) | |
137 | { | |
138 | wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low); | |
139 | } | |
140 | ||
141 | static inline u64 native_x2apic_icr_read(void) | |
142 | { | |
143 | unsigned long val; | |
144 | ||
145 | rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val); | |
146 | return val; | |
147 | } | |
148 | ||
ef1f87aa | 149 | extern int x2apic, x2apic_phys; |
6e1cb38a SS |
150 | extern void check_x2apic(void); |
151 | extern void enable_x2apic(void); | |
152 | extern void enable_IR_x2apic(void); | |
153 | extern void x2apic_icr_write(u32 low, u32 id); | |
a11b5abe YL |
154 | static inline int x2apic_enabled(void) |
155 | { | |
156 | int msr, msr2; | |
157 | ||
158 | if (!cpu_has_x2apic) | |
159 | return 0; | |
160 | ||
161 | rdmsr(MSR_IA32_APICBASE, msr, msr2); | |
162 | if (msr & X2APIC_ENABLE) | |
163 | return 1; | |
164 | return 0; | |
165 | } | |
166 | #else | |
06cd9a7d YL |
167 | static inline void check_x2apic(void) |
168 | { | |
169 | } | |
170 | static inline void enable_x2apic(void) | |
171 | { | |
172 | } | |
173 | static inline void enable_IR_x2apic(void) | |
174 | { | |
175 | } | |
176 | static inline int x2apic_enabled(void) | |
177 | { | |
178 | return 0; | |
179 | } | |
c535b6a1 | 180 | #endif |
1b374e4d | 181 | |
67c5fc5c TG |
182 | extern int get_physical_broadcast(void); |
183 | ||
06cd9a7d | 184 | #ifdef CONFIG_X86_X2APIC |
89027d35 SS |
185 | static inline void ack_x2APIC_irq(void) |
186 | { | |
187 | /* Docs say use 0 for future compatibility */ | |
188 | native_apic_msr_write(APIC_EOI, 0); | |
189 | } | |
190 | #endif | |
191 | ||
67c5fc5c TG |
192 | extern int lapic_get_maxlvt(void); |
193 | extern void clear_local_APIC(void); | |
194 | extern void connect_bsp_APIC(void); | |
195 | extern void disconnect_bsp_APIC(int virt_wire_setup); | |
196 | extern void disable_local_APIC(void); | |
197 | extern void lapic_shutdown(void); | |
198 | extern int verify_local_APIC(void); | |
199 | extern void cache_APIC_registers(void); | |
200 | extern void sync_Arb_IDs(void); | |
201 | extern void init_bsp_APIC(void); | |
202 | extern void setup_local_APIC(void); | |
739f33b3 | 203 | extern void end_local_APIC_setup(void); |
67c5fc5c | 204 | extern void init_apic_mappings(void); |
67c5fc5c TG |
205 | extern void setup_boot_APIC_clock(void); |
206 | extern void setup_secondary_APIC_clock(void); | |
207 | extern int APIC_init_uniprocessor(void); | |
e9427101 | 208 | extern void enable_NMI_through_LVT0(void); |
67c5fc5c TG |
209 | |
210 | /* | |
211 | * On 32bit this is mach-xxx local | |
212 | */ | |
213 | #ifdef CONFIG_X86_64 | |
8643f9d0 | 214 | extern void early_init_lapic_mapping(void); |
8fbbc4b4 AK |
215 | extern int apic_is_clustered_box(void); |
216 | #else | |
217 | static inline int apic_is_clustered_box(void) | |
218 | { | |
219 | return 0; | |
220 | } | |
67c5fc5c TG |
221 | #endif |
222 | ||
7b83dae7 RR |
223 | extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); |
224 | extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); | |
67c5fc5c | 225 | |
67c5fc5c TG |
226 | |
227 | #else /* !CONFIG_X86_LOCAL_APIC */ | |
228 | static inline void lapic_shutdown(void) { } | |
229 | #define local_apic_timer_c2_ok 1 | |
f3294a33 | 230 | static inline void init_apic_mappings(void) { } |
d3ec5cae | 231 | static inline void disable_local_APIC(void) { } |
67c5fc5c TG |
232 | |
233 | #endif /* !CONFIG_X86_LOCAL_APIC */ | |
234 | ||
1f75ed0c IM |
235 | #ifdef CONFIG_X86_64 |
236 | #define SET_APIC_ID(x) (apic->set_apic_id(x)) | |
237 | #else | |
238 | ||
1f75ed0c IM |
239 | #endif |
240 | ||
e2780a68 IM |
241 | /* |
242 | * Copyright 2004 James Cleverdon, IBM. | |
243 | * Subject to the GNU Public License, v.2 | |
244 | * | |
245 | * Generic APIC sub-arch data struct. | |
246 | * | |
247 | * Hacked for x86-64 by James Cleverdon from i386 architecture code by | |
248 | * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and | |
249 | * James Cleverdon. | |
250 | */ | |
be163a15 | 251 | struct apic { |
e2780a68 IM |
252 | char *name; |
253 | ||
254 | int (*probe)(void); | |
255 | int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id); | |
256 | int (*apic_id_registered)(void); | |
257 | ||
258 | u32 irq_delivery_mode; | |
259 | u32 irq_dest_mode; | |
260 | ||
261 | const struct cpumask *(*target_cpus)(void); | |
262 | ||
263 | int disable_esr; | |
264 | ||
265 | int dest_logical; | |
266 | unsigned long (*check_apicid_used)(physid_mask_t bitmap, int apicid); | |
267 | unsigned long (*check_apicid_present)(int apicid); | |
268 | ||
269 | void (*vector_allocation_domain)(int cpu, struct cpumask *retmask); | |
270 | void (*init_apic_ldr)(void); | |
271 | ||
272 | physid_mask_t (*ioapic_phys_id_map)(physid_mask_t map); | |
273 | ||
274 | void (*setup_apic_routing)(void); | |
275 | int (*multi_timer_check)(int apic, int irq); | |
276 | int (*apicid_to_node)(int logical_apicid); | |
277 | int (*cpu_to_logical_apicid)(int cpu); | |
278 | int (*cpu_present_to_apicid)(int mps_cpu); | |
279 | physid_mask_t (*apicid_to_cpu_present)(int phys_apicid); | |
280 | void (*setup_portio_remap)(void); | |
281 | int (*check_phys_apicid_present)(int boot_cpu_physical_apicid); | |
282 | void (*enable_apic_mode)(void); | |
283 | int (*phys_pkg_id)(int cpuid_apic, int index_msb); | |
284 | ||
285 | /* | |
be163a15 | 286 | * When one of the next two hooks returns 1 the apic |
e2780a68 IM |
287 | * is switched to this. Essentially they are additional |
288 | * probe functions: | |
289 | */ | |
290 | int (*mps_oem_check)(struct mpc_table *mpc, char *oem, char *productid); | |
291 | ||
292 | unsigned int (*get_apic_id)(unsigned long x); | |
293 | unsigned long (*set_apic_id)(unsigned int id); | |
294 | unsigned long apic_id_mask; | |
295 | ||
296 | unsigned int (*cpu_mask_to_apicid)(const struct cpumask *cpumask); | |
297 | unsigned int (*cpu_mask_to_apicid_and)(const struct cpumask *cpumask, | |
298 | const struct cpumask *andmask); | |
299 | ||
300 | /* ipi */ | |
301 | void (*send_IPI_mask)(const struct cpumask *mask, int vector); | |
302 | void (*send_IPI_mask_allbutself)(const struct cpumask *mask, | |
303 | int vector); | |
304 | void (*send_IPI_allbutself)(int vector); | |
305 | void (*send_IPI_all)(int vector); | |
306 | void (*send_IPI_self)(int vector); | |
307 | ||
308 | /* wakeup_secondary_cpu */ | |
309 | int (*wakeup_cpu)(int apicid, unsigned long start_eip); | |
310 | ||
311 | int trampoline_phys_low; | |
312 | int trampoline_phys_high; | |
313 | ||
314 | void (*wait_for_init_deassert)(atomic_t *deassert); | |
315 | void (*smp_callin_clear_local_apic)(void); | |
e2780a68 IM |
316 | void (*inquire_remote_apic)(int apicid); |
317 | ||
318 | /* apic ops */ | |
319 | u32 (*read)(u32 reg); | |
320 | void (*write)(u32 reg, u32 v); | |
321 | u64 (*icr_read)(void); | |
322 | void (*icr_write)(u32 low, u32 high); | |
323 | void (*wait_icr_idle)(void); | |
324 | u32 (*safe_wait_icr_idle)(void); | |
325 | }; | |
326 | ||
be163a15 | 327 | extern struct apic *apic; |
e2780a68 IM |
328 | |
329 | static inline u32 apic_read(u32 reg) | |
330 | { | |
331 | return apic->read(reg); | |
332 | } | |
333 | ||
334 | static inline void apic_write(u32 reg, u32 val) | |
335 | { | |
336 | apic->write(reg, val); | |
337 | } | |
338 | ||
339 | static inline u64 apic_icr_read(void) | |
340 | { | |
341 | return apic->icr_read(); | |
342 | } | |
343 | ||
344 | static inline void apic_icr_write(u32 low, u32 high) | |
345 | { | |
346 | apic->icr_write(low, high); | |
347 | } | |
348 | ||
349 | static inline void apic_wait_icr_idle(void) | |
350 | { | |
351 | apic->wait_icr_idle(); | |
352 | } | |
353 | ||
354 | static inline u32 safe_apic_wait_icr_idle(void) | |
355 | { | |
356 | return apic->safe_wait_icr_idle(); | |
357 | } | |
358 | ||
359 | ||
360 | static inline void ack_APIC_irq(void) | |
361 | { | |
362 | /* | |
363 | * ack_APIC_irq() actually gets compiled as a single instruction | |
364 | * ... yummie. | |
365 | */ | |
366 | ||
367 | /* Docs say use 0 for future compatibility */ | |
368 | apic_write(APIC_EOI, 0); | |
369 | } | |
370 | ||
371 | static inline unsigned default_get_apic_id(unsigned long x) | |
372 | { | |
373 | unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR)); | |
374 | ||
375 | if (APIC_XAPIC(ver)) | |
376 | return (x >> 24) & 0xFF; | |
377 | else | |
378 | return (x >> 24) & 0x0F; | |
379 | } | |
380 | ||
381 | /* | |
382 | * Warm reset vector default position: | |
383 | */ | |
384 | #define DEFAULT_TRAMPOLINE_PHYS_LOW 0x467 | |
385 | #define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469 | |
386 | ||
387 | #ifdef CONFIG_X86_32 | |
be163a15 | 388 | extern void es7000_update_apic_to_cluster(void); |
e2780a68 | 389 | #else |
be163a15 IM |
390 | extern struct apic apic_flat; |
391 | extern struct apic apic_physflat; | |
392 | extern struct apic apic_x2apic_cluster; | |
393 | extern struct apic apic_x2apic_phys; | |
e2780a68 IM |
394 | extern int default_acpi_madt_oem_check(char *, char *); |
395 | ||
396 | extern void apic_send_IPI_self(int vector); | |
397 | ||
be163a15 | 398 | extern struct apic apic_x2apic_uv_x; |
e2780a68 IM |
399 | DECLARE_PER_CPU(int, x2apic_extra_bits); |
400 | ||
401 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
402 | extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); | |
403 | #endif | |
404 | ||
405 | static inline void default_wait_for_init_deassert(atomic_t *deassert) | |
406 | { | |
407 | while (!atomic_read(deassert)) | |
408 | cpu_relax(); | |
409 | return; | |
410 | } | |
411 | ||
412 | extern void generic_bigsmp_probe(void); | |
413 | ||
414 | ||
415 | #ifdef CONFIG_X86_LOCAL_APIC | |
416 | ||
417 | #include <asm/smp.h> | |
418 | ||
419 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | |
420 | ||
421 | static inline const struct cpumask *default_target_cpus(void) | |
422 | { | |
423 | #ifdef CONFIG_SMP | |
424 | return cpu_online_mask; | |
425 | #else | |
426 | return cpumask_of(0); | |
427 | #endif | |
428 | } | |
429 | ||
430 | DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid); | |
431 | ||
432 | ||
433 | static inline unsigned int read_apic_id(void) | |
434 | { | |
435 | unsigned int reg; | |
436 | ||
437 | reg = apic_read(APIC_ID); | |
438 | ||
439 | return apic->get_apic_id(reg); | |
440 | } | |
441 | ||
442 | extern void default_setup_apic_routing(void); | |
443 | ||
444 | #ifdef CONFIG_X86_32 | |
445 | /* | |
446 | * Set up the logical destination ID. | |
447 | * | |
448 | * Intel recommends to set DFR, LDR and TPR before enabling | |
449 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel | |
450 | * document number 292116). So here it goes... | |
451 | */ | |
452 | extern void default_init_apic_ldr(void); | |
453 | ||
454 | static inline int default_apic_id_registered(void) | |
455 | { | |
456 | return physid_isset(read_apic_id(), phys_cpu_present_map); | |
457 | } | |
458 | ||
459 | static inline unsigned int | |
460 | default_cpu_mask_to_apicid(const struct cpumask *cpumask) | |
461 | { | |
462 | return cpumask_bits(cpumask)[0]; | |
463 | } | |
464 | ||
465 | static inline unsigned int | |
466 | default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, | |
467 | const struct cpumask *andmask) | |
468 | { | |
469 | unsigned long mask1 = cpumask_bits(cpumask)[0]; | |
470 | unsigned long mask2 = cpumask_bits(andmask)[0]; | |
471 | unsigned long mask3 = cpumask_bits(cpu_online_mask)[0]; | |
472 | ||
473 | return (unsigned int)(mask1 & mask2 & mask3); | |
474 | } | |
475 | ||
476 | static inline int default_phys_pkg_id(int cpuid_apic, int index_msb) | |
477 | { | |
478 | return cpuid_apic >> index_msb; | |
479 | } | |
480 | ||
481 | extern int default_apicid_to_node(int logical_apicid); | |
482 | ||
483 | #endif | |
484 | ||
485 | static inline unsigned long default_check_apicid_used(physid_mask_t bitmap, int apicid) | |
486 | { | |
487 | return physid_isset(apicid, bitmap); | |
488 | } | |
489 | ||
490 | static inline unsigned long default_check_apicid_present(int bit) | |
491 | { | |
492 | return physid_isset(bit, phys_cpu_present_map); | |
493 | } | |
494 | ||
495 | static inline physid_mask_t default_ioapic_phys_id_map(physid_mask_t phys_map) | |
496 | { | |
497 | return phys_map; | |
498 | } | |
499 | ||
500 | /* Mapping from cpu number to logical apicid */ | |
501 | static inline int default_cpu_to_logical_apicid(int cpu) | |
502 | { | |
503 | return 1 << cpu; | |
504 | } | |
505 | ||
506 | static inline int __default_cpu_present_to_apicid(int mps_cpu) | |
507 | { | |
508 | if (mps_cpu < nr_cpu_ids && cpu_present(mps_cpu)) | |
509 | return (int)per_cpu(x86_bios_cpu_apicid, mps_cpu); | |
510 | else | |
511 | return BAD_APICID; | |
512 | } | |
513 | ||
514 | static inline int | |
515 | __default_check_phys_apicid_present(int boot_cpu_physical_apicid) | |
516 | { | |
517 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); | |
518 | } | |
519 | ||
520 | #ifdef CONFIG_X86_32 | |
521 | static inline int default_cpu_present_to_apicid(int mps_cpu) | |
522 | { | |
523 | return __default_cpu_present_to_apicid(mps_cpu); | |
524 | } | |
525 | ||
526 | static inline int | |
527 | default_check_phys_apicid_present(int boot_cpu_physical_apicid) | |
528 | { | |
529 | return __default_check_phys_apicid_present(boot_cpu_physical_apicid); | |
530 | } | |
531 | #else | |
532 | extern int default_cpu_present_to_apicid(int mps_cpu); | |
533 | extern int default_check_phys_apicid_present(int boot_cpu_physical_apicid); | |
534 | #endif | |
535 | ||
536 | static inline physid_mask_t default_apicid_to_cpu_present(int phys_apicid) | |
537 | { | |
538 | return physid_mask_of_physid(phys_apicid); | |
539 | } | |
540 | ||
541 | #endif /* CONFIG_X86_LOCAL_APIC */ | |
542 | ||
2f205bc4 IM |
543 | #ifdef CONFIG_X86_32 |
544 | extern u8 cpu_2_logical_apicid[NR_CPUS]; | |
545 | #endif | |
546 | ||
1965aae3 | 547 | #endif /* _ASM_X86_APIC_H */ |