[linux-2.6-block.git] / arch / x86 / hyperv / hv_apic.c

// SPDX-License-Identifier: GPL-2.0

/*
 * Hyper-V specific APIC code.
 *
 * Copyright (C) 2018, Microsoft, Inc.
 *
 * Author : K. Y. Srinivasan <kys@microsoft.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 * NON INFRINGEMENT.  See the GNU General Public License for more
 * details.
 *
 */

#include <linux/types.h>
#include <linux/version.h>
#include <linux/vmalloc.h>
#include <linux/mm.h>
#include <linux/clockchips.h>
#include <linux/hyperv.h>
#include <linux/slab.h>
#include <linux/cpuhotplug.h>
#include <asm/hypervisor.h>
#include <asm/mshyperv.h>

#ifdef CONFIG_X86_64
#if IS_ENABLED(CONFIG_HYPERV)

static struct apic orig_apic;

static u64 hv_apic_icr_read(void)
{
	u64 reg_val;

	rdmsrl(HV_X64_MSR_ICR, reg_val);
	return reg_val;
}

static void hv_apic_icr_write(u32 low, u32 id)
{
	u64 reg_val;

	reg_val = SET_APIC_DEST_FIELD(id);
	reg_val = reg_val << 32;
	reg_val |= low;

	wrmsrl(HV_X64_MSR_ICR, reg_val);
}

static u32 hv_apic_read(u32 reg)
{
	u32 reg_val, hi;

	switch (reg) {
	case APIC_EOI:
		rdmsr(HV_X64_MSR_EOI, reg_val, hi);
		return reg_val;
	case APIC_TASKPRI:
		rdmsr(HV_X64_MSR_TPR, reg_val, hi);
		return reg_val;

	default:
		return native_apic_mem_read(reg);
	}
}

static void hv_apic_write(u32 reg, u32 val)
{
	switch (reg) {
	case APIC_EOI:
		wrmsr(HV_X64_MSR_EOI, val, 0);
		break;
	case APIC_TASKPRI:
		wrmsr(HV_X64_MSR_TPR, val, 0);
		break;
	default:
		native_apic_mem_write(reg, val);
	}
}

static void hv_apic_eoi_write(u32 reg, u32 val)
{
	wrmsr(HV_X64_MSR_EOI, val, 0);
}

/*
 * IPI implementation on Hyper-V.
 */
static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector)
{
	struct ipi_arg_ex **arg;
	struct ipi_arg_ex *ipi_arg;
	unsigned long flags;
	int nr_bank = 0;
	int ret = 1;

	local_irq_save(flags);
	arg = (struct ipi_arg_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);

	ipi_arg = *arg;
	if (unlikely(!ipi_arg))
		goto ipi_mask_ex_done;

	ipi_arg->vector = vector;
	ipi_arg->reserved = 0;
	ipi_arg->vp_set.valid_bank_mask = 0;

	if (!cpumask_equal(mask, cpu_present_mask)) {
		ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
		nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
	}
	if (!nr_bank)
		ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;

	ret = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
			      ipi_arg, NULL);

ipi_mask_ex_done:
	local_irq_restore(flags);
	return ((ret == 0) ? true : false);
}

static bool __send_ipi_mask(const struct cpumask *mask, int vector)
{
	int cur_cpu, vcpu;
	struct ipi_arg_non_ex **arg;
	struct ipi_arg_non_ex *ipi_arg;
	int ret = 1;
	unsigned long flags;

	if (cpumask_empty(mask))
		return true;

	if (!hv_hypercall_pg)
		return false;

	if ((vector < HV_IPI_LOW_VECTOR) || (vector > HV_IPI_HIGH_VECTOR))
		return false;

	if ((ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
		return __send_ipi_mask_ex(mask, vector);

	local_irq_save(flags);
	arg = (struct ipi_arg_non_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);

	ipi_arg = *arg;
	if (unlikely(!ipi_arg))
		goto ipi_mask_done;

	ipi_arg->vector = vector;
	ipi_arg->reserved = 0;
	ipi_arg->cpu_mask = 0;

	for_each_cpu(cur_cpu, mask) {
		vcpu = hv_cpu_number_to_vp_number(cur_cpu);
		/*
		 * This particular version of the IPI hypercall can
		 * only target upto 64 CPUs.
		 */
		if (vcpu >= 64)
			goto ipi_mask_done;

		__set_bit(vcpu, (unsigned long *)&ipi_arg->cpu_mask);
	}

	ret = hv_do_hypercall(HVCALL_SEND_IPI, ipi_arg, NULL);

ipi_mask_done:
	local_irq_restore(flags);
	return ((ret == 0) ? true : false);
}

static bool __send_ipi_one(int cpu, int vector)
{
	struct cpumask mask = CPU_MASK_NONE;

	cpumask_set_cpu(cpu, &mask);
	return __send_ipi_mask(&mask, vector);
}

static void hv_send_ipi(int cpu, int vector)
{
	if (!__send_ipi_one(cpu, vector))
		orig_apic.send_IPI(cpu, vector);
}

static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
{
	if (!__send_ipi_mask(mask, vector))
		orig_apic.send_IPI_mask(mask, vector);
}

static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
{
	unsigned int this_cpu = smp_processor_id();
	struct cpumask new_mask;
	const struct cpumask *local_mask;

	cpumask_copy(&new_mask, mask);
	cpumask_clear_cpu(this_cpu, &new_mask);
	local_mask = &new_mask;
	if (!__send_ipi_mask(local_mask, vector))
		orig_apic.send_IPI_mask_allbutself(mask, vector);
}

static void hv_send_ipi_allbutself(int vector)
{
	hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
}

static void hv_send_ipi_all(int vector)
{
	if (!__send_ipi_mask(cpu_online_mask, vector))
		orig_apic.send_IPI_all(vector);
}

static void hv_send_ipi_self(int vector)
{
	if (!__send_ipi_one(smp_processor_id(), vector))
		orig_apic.send_IPI_self(vector);
}

void __init hv_apic_init(void)
{
	if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
		if ((ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
			pr_info("Hyper-V: Using ext hypercalls for IPI\n");
		else
			pr_info("Hyper-V: Using IPI hypercalls\n");
		/*
		 * Set the IPI entry points.
		 */
		orig_apic = *apic;

		apic->send_IPI = hv_send_ipi;
		apic->send_IPI_mask = hv_send_ipi_mask;
		apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
		apic->send_IPI_allbutself = hv_send_ipi_allbutself;
		apic->send_IPI_all = hv_send_ipi_all;
		apic->send_IPI_self = hv_send_ipi_self;
	}

	if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
		pr_info("Hyper-V: Using MSR based APIC access\n");
		apic_set_eoi_write(hv_apic_eoi_write);
		apic->read      = hv_apic_read;
		apic->write     = hv_apic_write;
		apic->icr_write = hv_apic_icr_write;
		apic->icr_read  = hv_apic_icr_read;
	}
}

#endif /* CONFIG_HYPERV */
#endif /* CONFIG_X86_64 */
Commit	Line	Data
6b48cb5f S	1	// SPDX-License-Identifier: GPL-2.0
	2
	3	/*
	4	* Hyper-V specific APIC code.
	5	*
	6	* Copyright (C) 2018, Microsoft, Inc.
	7	*
	8	* Author : K. Y. Srinivasan <kys@microsoft.com>
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License version 2 as published
	12	* by the Free Software Foundation.
	13	*
	14	* This program is distributed in the hope that it will be useful, but
	15	* WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	17	* NON INFRINGEMENT. See the GNU General Public License for more
	18	* details.
	19	*
	20	*/
	21
	22	#include <linux/types.h>
	23	#include <linux/version.h>
	24	#include <linux/vmalloc.h>
	25	#include <linux/mm.h>
	26	#include <linux/clockchips.h>
	27	#include <linux/hyperv.h>
	28	#include <linux/slab.h>
	29	#include <linux/cpuhotplug.h>
	30	#include <asm/hypervisor.h>
	31	#include <asm/mshyperv.h>
	32
	33	#ifdef CONFIG_X86_64
	34	#if IS_ENABLED(CONFIG_HYPERV)
	35
68bb7bfb S	36	static struct apic orig_apic;
68bb7bfb S	37
6b48cb5f S	38	static u64 hv_apic_icr_read(void)
	39	{
	40	u64 reg_val;
	41
	42	rdmsrl(HV_X64_MSR_ICR, reg_val);
	43	return reg_val;
	44	}
	45
	46	static void hv_apic_icr_write(u32 low, u32 id)
	47	{
	48	u64 reg_val;
	49
	50	reg_val = SET_APIC_DEST_FIELD(id);
	51	reg_val = reg_val << 32;
	52	reg_val \|= low;
	53
	54	wrmsrl(HV_X64_MSR_ICR, reg_val);
	55	}
	56
	57	static u32 hv_apic_read(u32 reg)
	58	{
	59	u32 reg_val, hi;
	60
	61	switch (reg) {
	62	case APIC_EOI:
	63	rdmsr(HV_X64_MSR_EOI, reg_val, hi);
	64	return reg_val;
	65	case APIC_TASKPRI:
	66	rdmsr(HV_X64_MSR_TPR, reg_val, hi);
	67	return reg_val;
	68
	69	default:
	70	return native_apic_mem_read(reg);
	71	}
	72	}
	73
	74	static void hv_apic_write(u32 reg, u32 val)
	75	{
	76	switch (reg) {
	77	case APIC_EOI:
	78	wrmsr(HV_X64_MSR_EOI, val, 0);
	79	break;
	80	case APIC_TASKPRI:
	81	wrmsr(HV_X64_MSR_TPR, val, 0);
	82	break;
	83	default:
	84	native_apic_mem_write(reg, val);
	85	}
	86	}
	87
	88	static void hv_apic_eoi_write(u32 reg, u32 val)
	89	{
	90	wrmsr(HV_X64_MSR_EOI, val, 0);
	91	}
	92
68bb7bfb S	93	/*
	94	* IPI implementation on Hyper-V.
	95	*/
366f03b0 S	96	static bool __send_ipi_mask_ex(const struct cpumask *mask, int vector)
	97	{
	98	struct ipi_arg_ex **arg;
	99	struct ipi_arg_ex *ipi_arg;
	100	unsigned long flags;
	101	int nr_bank = 0;
	102	int ret = 1;
	103
	104	local_irq_save(flags);
	105	arg = (struct ipi_arg_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
	106
	107	ipi_arg = *arg;
	108	if (unlikely(!ipi_arg))
	109	goto ipi_mask_ex_done;
	110
	111	ipi_arg->vector = vector;
	112	ipi_arg->reserved = 0;
	113	ipi_arg->vp_set.valid_bank_mask = 0;
	114
	115	if (!cpumask_equal(mask, cpu_present_mask)) {
	116	ipi_arg->vp_set.format = HV_GENERIC_SET_SPARSE_4K;
	117	nr_bank = cpumask_to_vpset(&(ipi_arg->vp_set), mask);
	118	}
	119	if (!nr_bank)
	120	ipi_arg->vp_set.format = HV_GENERIC_SET_ALL;
	121
	122	ret = hv_do_rep_hypercall(HVCALL_SEND_IPI_EX, 0, nr_bank,
	123	ipi_arg, NULL);
	124
	125	ipi_mask_ex_done:
	126	local_irq_restore(flags);
	127	return ((ret == 0) ? true : false);
	128	}
	129
68bb7bfb S	130	static bool __send_ipi_mask(const struct cpumask *mask, int vector)
	131	{
	132	int cur_cpu, vcpu;
	133	struct ipi_arg_non_ex **arg;
	134	struct ipi_arg_non_ex *ipi_arg;
	135	int ret = 1;
	136	unsigned long flags;
	137
	138	if (cpumask_empty(mask))
	139	return true;
	140
	141	if (!hv_hypercall_pg)
	142	return false;
	143
	144	if ((vector < HV_IPI_LOW_VECTOR) \|\| (vector > HV_IPI_HIGH_VECTOR))
	145	return false;
	146
366f03b0 S	147	if ((ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
	148	return __send_ipi_mask_ex(mask, vector);
	149
68bb7bfb S	150	local_irq_save(flags);
	151	arg = (struct ipi_arg_non_ex **)this_cpu_ptr(hyperv_pcpu_input_arg);
	152
	153	ipi_arg = *arg;
	154	if (unlikely(!ipi_arg))
	155	goto ipi_mask_done;
	156
	157	ipi_arg->vector = vector;
	158	ipi_arg->reserved = 0;
	159	ipi_arg->cpu_mask = 0;
	160
	161	for_each_cpu(cur_cpu, mask) {
	162	vcpu = hv_cpu_number_to_vp_number(cur_cpu);
	163	/*
	164	* This particular version of the IPI hypercall can
	165	* only target upto 64 CPUs.
	166	*/
	167	if (vcpu >= 64)
	168	goto ipi_mask_done;
	169
	170	__set_bit(vcpu, (unsigned long *)&ipi_arg->cpu_mask);
	171	}
	172
	173	ret = hv_do_hypercall(HVCALL_SEND_IPI, ipi_arg, NULL);
	174
	175	ipi_mask_done:
	176	local_irq_restore(flags);
	177	return ((ret == 0) ? true : false);
	178	}
	179
	180	static bool __send_ipi_one(int cpu, int vector)
	181	{
	182	struct cpumask mask = CPU_MASK_NONE;
	183
	184	cpumask_set_cpu(cpu, &mask);
	185	return __send_ipi_mask(&mask, vector);
	186	}
	187
	188	static void hv_send_ipi(int cpu, int vector)
	189	{
	190	if (!__send_ipi_one(cpu, vector))
	191	orig_apic.send_IPI(cpu, vector);
	192	}
	193
	194	static void hv_send_ipi_mask(const struct cpumask *mask, int vector)
	195	{
	196	if (!__send_ipi_mask(mask, vector))
	197	orig_apic.send_IPI_mask(mask, vector);
	198	}
	199
	200	static void hv_send_ipi_mask_allbutself(const struct cpumask *mask, int vector)
	201	{
	202	unsigned int this_cpu = smp_processor_id();
	203	struct cpumask new_mask;
	204	const struct cpumask *local_mask;
	205
	206	cpumask_copy(&new_mask, mask);
	207	cpumask_clear_cpu(this_cpu, &new_mask);
	208	local_mask = &new_mask;
	209	if (!__send_ipi_mask(local_mask, vector))
	210	orig_apic.send_IPI_mask_allbutself(mask, vector);
	211	}
	212
	213	static void hv_send_ipi_allbutself(int vector)
214	{
215	hv_send_ipi_mask_allbutself(cpu_online_mask, vector);
216	}
217
218	static void hv_send_ipi_all(int vector)
219	{
220	if (!__send_ipi_mask(cpu_online_mask, vector))
221	orig_apic.send_IPI_all(vector);
222	}
223
224	static void hv_send_ipi_self(int vector)
225	{
226	if (!__send_ipi_one(smp_processor_id(), vector))
227	orig_apic.send_IPI_self(vector);
228	}
229
6b48cb5f S	230	void __init hv_apic_init(void)
6b48cb5f S	231	{
68bb7bfb	232	if (ms_hyperv.hints & HV_X64_CLUSTER_IPI_RECOMMENDED) {
366f03b0 S	233	if ((ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
	234	pr_info("Hyper-V: Using ext hypercalls for IPI\n");
	235	else
	236	pr_info("Hyper-V: Using IPI hypercalls\n");
68bb7bfb S	237	/*
	238	* Set the IPI entry points.
	239	*/
	240	orig_apic = *apic;
	241
	242	apic->send_IPI = hv_send_ipi;
	243	apic->send_IPI_mask = hv_send_ipi_mask;
	244	apic->send_IPI_mask_allbutself = hv_send_ipi_mask_allbutself;
	245	apic->send_IPI_allbutself = hv_send_ipi_allbutself;
	246	apic->send_IPI_all = hv_send_ipi_all;
	247	apic->send_IPI_self = hv_send_ipi_self;
	248	}
	249
6b48cb5f S	250	if (ms_hyperv.hints & HV_X64_APIC_ACCESS_RECOMMENDED) {
	251	pr_info("Hyper-V: Using MSR based APIC access\n");
	252	apic_set_eoi_write(hv_apic_eoi_write);
	253	apic->read = hv_apic_read;
	254	apic->write = hv_apic_write;
	255	apic->icr_write = hv_apic_icr_write;
	256	apic->icr_read = hv_apic_icr_read;
	257	}
	258	}
	259
	260	#endif /* CONFIG_HYPERV */
	261	#endif /* CONFIG_X86_64 */