Commit | Line | Data |
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4788e5b4 SE |
1 | /* |
2 | * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters | |
3 | * Copyright (C) 2013 Google, Inc., Stephane Eranian | |
4 | * | |
5 | * Intel RAPL interface is specified in the IA-32 Manual Vol3b | |
6 | * section 14.7.1 (September 2013) | |
7 | * | |
8 | * RAPL provides more controls than just reporting energy consumption | |
9 | * however here we only expose the 3 energy consumption free running | |
10 | * counters (pp0, pkg, dram). | |
11 | * | |
12 | * Each of those counters increments in a power unit defined by the | |
13 | * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules | |
14 | * but it can vary. | |
15 | * | |
16 | * Counter to rapl events mappings: | |
17 | * | |
18 | * pp0 counter: consumption of all physical cores (power plane 0) | |
19 | * event: rapl_energy_cores | |
20 | * perf code: 0x1 | |
21 | * | |
22 | * pkg counter: consumption of the whole processor package | |
23 | * event: rapl_energy_pkg | |
24 | * perf code: 0x2 | |
25 | * | |
26 | * dram counter: consumption of the dram domain (servers only) | |
27 | * event: rapl_energy_dram | |
28 | * perf code: 0x3 | |
29 | * | |
dcee75b3 | 30 | * gpu counter: consumption of the builtin-gpu domain (client only) |
f228c5b8 SE |
31 | * event: rapl_energy_gpu |
32 | * perf code: 0x4 | |
33 | * | |
dcee75b3 SP |
34 | * psys counter: consumption of the builtin-psys domain (client only) |
35 | * event: rapl_energy_psys | |
36 | * perf code: 0x5 | |
37 | * | |
4788e5b4 SE |
38 | * We manage those counters as free running (read-only). They may be |
39 | * use simultaneously by other tools, such as turbostat. | |
40 | * | |
41 | * The events only support system-wide mode counting. There is no | |
42 | * sampling support because it does not make sense and is not | |
43 | * supported by the RAPL hardware. | |
44 | * | |
45 | * Because we want to avoid floating-point operations in the kernel, | |
46 | * the events are all reported in fixed point arithmetic (32.32). | |
47 | * Tools must adjust the counts to convert them to Watts using | |
48 | * the duration of the measurement. Tools may use a function such as | |
49 | * ldexp(raw_count, -32); | |
50 | */ | |
512089d9 TG |
51 | |
52 | #define pr_fmt(fmt) "RAPL PMU: " fmt | |
53 | ||
4788e5b4 SE |
54 | #include <linux/module.h> |
55 | #include <linux/slab.h> | |
56 | #include <linux/perf_event.h> | |
57 | #include <asm/cpu_device_id.h> | |
7f2236d0 | 58 | #include <asm/intel-family.h> |
27f6d22b | 59 | #include "../perf_event.h" |
4788e5b4 | 60 | |
4b6e2571 KL |
61 | MODULE_LICENSE("GPL"); |
62 | ||
4788e5b4 SE |
63 | /* |
64 | * RAPL energy status counters | |
65 | */ | |
66 | #define RAPL_IDX_PP0_NRG_STAT 0 /* all cores */ | |
67 | #define INTEL_RAPL_PP0 0x1 /* pseudo-encoding */ | |
68 | #define RAPL_IDX_PKG_NRG_STAT 1 /* entire package */ | |
69 | #define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */ | |
70 | #define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */ | |
71 | #define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */ | |
e69af465 | 72 | #define RAPL_IDX_PP1_NRG_STAT 3 /* gpu */ |
f228c5b8 | 73 | #define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */ |
dcee75b3 SP |
74 | #define RAPL_IDX_PSYS_NRG_STAT 4 /* psys */ |
75 | #define INTEL_RAPL_PSYS 0x5 /* pseudo-encoding */ | |
4788e5b4 | 76 | |
dcee75b3 | 77 | #define NR_RAPL_DOMAINS 0x5 |
da008ee7 | 78 | static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = { |
64552396 JP |
79 | "pp0-core", |
80 | "package", | |
81 | "dram", | |
82 | "pp1-gpu", | |
dcee75b3 | 83 | "psys", |
64552396 JP |
84 | }; |
85 | ||
4788e5b4 SE |
86 | /* Clients have PP0, PKG */ |
87 | #define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
f228c5b8 SE |
88 | 1<<RAPL_IDX_PKG_NRG_STAT|\ |
89 | 1<<RAPL_IDX_PP1_NRG_STAT) | |
4788e5b4 SE |
90 | |
91 | /* Servers have PP0, PKG, RAM */ | |
92 | #define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
93 | 1<<RAPL_IDX_PKG_NRG_STAT|\ | |
94 | 1<<RAPL_IDX_RAM_NRG_STAT) | |
95 | ||
e69af465 VW |
96 | /* Servers have PP0, PKG, RAM, PP1 */ |
97 | #define RAPL_IDX_HSW (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
98 | 1<<RAPL_IDX_PKG_NRG_STAT|\ | |
99 | 1<<RAPL_IDX_RAM_NRG_STAT|\ | |
100 | 1<<RAPL_IDX_PP1_NRG_STAT) | |
101 | ||
dcee75b3 SP |
102 | /* SKL clients have PP0, PKG, RAM, PP1, PSYS */ |
103 | #define RAPL_IDX_SKL_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
104 | 1<<RAPL_IDX_PKG_NRG_STAT|\ | |
105 | 1<<RAPL_IDX_RAM_NRG_STAT|\ | |
106 | 1<<RAPL_IDX_PP1_NRG_STAT|\ | |
107 | 1<<RAPL_IDX_PSYS_NRG_STAT) | |
108 | ||
3a2a7797 DC |
109 | /* Knights Landing has PKG, RAM */ |
110 | #define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\ | |
111 | 1<<RAPL_IDX_RAM_NRG_STAT) | |
112 | ||
4788e5b4 SE |
113 | /* |
114 | * event code: LSB 8 bits, passed in attr->config | |
115 | * any other bit is reserved | |
116 | */ | |
117 | #define RAPL_EVENT_MASK 0xFFULL | |
118 | ||
119 | #define DEFINE_RAPL_FORMAT_ATTR(_var, _name, _format) \ | |
120 | static ssize_t __rapl_##_var##_show(struct kobject *kobj, \ | |
121 | struct kobj_attribute *attr, \ | |
122 | char *page) \ | |
123 | { \ | |
124 | BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ | |
125 | return sprintf(page, _format "\n"); \ | |
126 | } \ | |
127 | static struct kobj_attribute format_attr_##_var = \ | |
128 | __ATTR(_name, 0444, __rapl_##_var##_show, NULL) | |
129 | ||
7162b8fe | 130 | #define RAPL_CNTR_WIDTH 32 |
4788e5b4 | 131 | |
d3bcd64b HR |
132 | #define RAPL_EVENT_ATTR_STR(_name, v, str) \ |
133 | static struct perf_pmu_events_attr event_attr_##v = { \ | |
134 | .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \ | |
135 | .id = 0, \ | |
136 | .event_str = str, \ | |
433678bd SE |
137 | }; |
138 | ||
4788e5b4 | 139 | struct rapl_pmu { |
a208749c | 140 | raw_spinlock_t lock; |
7162b8fe | 141 | int n_active; |
8a6d2f8f | 142 | int cpu; |
7162b8fe TG |
143 | struct list_head active_list; |
144 | struct pmu *pmu; | |
145 | ktime_t timer_interval; | |
146 | struct hrtimer hrtimer; | |
4788e5b4 SE |
147 | }; |
148 | ||
9de8d686 TG |
149 | struct rapl_pmus { |
150 | struct pmu pmu; | |
151 | unsigned int maxpkg; | |
152 | struct rapl_pmu *pmus[]; | |
153 | }; | |
154 | ||
7162b8fe TG |
155 | /* 1/2^hw_unit Joule */ |
156 | static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly; | |
9de8d686 | 157 | static struct rapl_pmus *rapl_pmus; |
4788e5b4 | 158 | static cpumask_t rapl_cpu_mask; |
9de8d686 | 159 | static unsigned int rapl_cntr_mask; |
75c7003f | 160 | static u64 rapl_timer_ms; |
4788e5b4 | 161 | |
9de8d686 TG |
162 | static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu) |
163 | { | |
164 | return rapl_pmus->pmus[topology_logical_package_id(cpu)]; | |
165 | } | |
4788e5b4 SE |
166 | |
167 | static inline u64 rapl_read_counter(struct perf_event *event) | |
168 | { | |
169 | u64 raw; | |
170 | rdmsrl(event->hw.event_base, raw); | |
171 | return raw; | |
172 | } | |
173 | ||
64552396 | 174 | static inline u64 rapl_scale(u64 v, int cfg) |
4788e5b4 | 175 | { |
64552396 | 176 | if (cfg > NR_RAPL_DOMAINS) { |
512089d9 | 177 | pr_warn("Invalid domain %d, failed to scale data\n", cfg); |
64552396 JP |
178 | return v; |
179 | } | |
4788e5b4 SE |
180 | /* |
181 | * scale delta to smallest unit (1/2^32) | |
182 | * users must then scale back: count * 1/(1e9*2^32) to get Joules | |
183 | * or use ldexp(count, -32). | |
184 | * Watts = Joules/Time delta | |
185 | */ | |
64552396 | 186 | return v << (32 - rapl_hw_unit[cfg - 1]); |
4788e5b4 SE |
187 | } |
188 | ||
189 | static u64 rapl_event_update(struct perf_event *event) | |
190 | { | |
191 | struct hw_perf_event *hwc = &event->hw; | |
192 | u64 prev_raw_count, new_raw_count; | |
193 | s64 delta, sdelta; | |
194 | int shift = RAPL_CNTR_WIDTH; | |
195 | ||
196 | again: | |
197 | prev_raw_count = local64_read(&hwc->prev_count); | |
198 | rdmsrl(event->hw.event_base, new_raw_count); | |
199 | ||
200 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
201 | new_raw_count) != prev_raw_count) { | |
202 | cpu_relax(); | |
203 | goto again; | |
204 | } | |
205 | ||
206 | /* | |
207 | * Now we have the new raw value and have updated the prev | |
208 | * timestamp already. We can now calculate the elapsed delta | |
209 | * (event-)time and add that to the generic event. | |
210 | * | |
211 | * Careful, not all hw sign-extends above the physical width | |
212 | * of the count. | |
213 | */ | |
214 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | |
215 | delta >>= shift; | |
216 | ||
64552396 | 217 | sdelta = rapl_scale(delta, event->hw.config); |
4788e5b4 SE |
218 | |
219 | local64_add(sdelta, &event->count); | |
220 | ||
221 | return new_raw_count; | |
222 | } | |
223 | ||
65661f96 SE |
224 | static void rapl_start_hrtimer(struct rapl_pmu *pmu) |
225 | { | |
514c2304 TG |
226 | hrtimer_start(&pmu->hrtimer, pmu->timer_interval, |
227 | HRTIMER_MODE_REL_PINNED); | |
65661f96 SE |
228 | } |
229 | ||
65661f96 SE |
230 | static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer) |
231 | { | |
8a6d2f8f | 232 | struct rapl_pmu *pmu = container_of(hrtimer, struct rapl_pmu, hrtimer); |
65661f96 SE |
233 | struct perf_event *event; |
234 | unsigned long flags; | |
235 | ||
236 | if (!pmu->n_active) | |
237 | return HRTIMER_NORESTART; | |
238 | ||
a208749c | 239 | raw_spin_lock_irqsave(&pmu->lock, flags); |
65661f96 | 240 | |
7162b8fe | 241 | list_for_each_entry(event, &pmu->active_list, active_entry) |
65661f96 | 242 | rapl_event_update(event); |
65661f96 | 243 | |
a208749c | 244 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
65661f96 SE |
245 | |
246 | hrtimer_forward_now(hrtimer, pmu->timer_interval); | |
247 | ||
248 | return HRTIMER_RESTART; | |
249 | } | |
250 | ||
251 | static void rapl_hrtimer_init(struct rapl_pmu *pmu) | |
252 | { | |
253 | struct hrtimer *hr = &pmu->hrtimer; | |
254 | ||
255 | hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL); | |
256 | hr->function = rapl_hrtimer_handle; | |
257 | } | |
258 | ||
4788e5b4 SE |
259 | static void __rapl_pmu_event_start(struct rapl_pmu *pmu, |
260 | struct perf_event *event) | |
261 | { | |
262 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) | |
263 | return; | |
264 | ||
265 | event->hw.state = 0; | |
266 | ||
267 | list_add_tail(&event->active_entry, &pmu->active_list); | |
268 | ||
269 | local64_set(&event->hw.prev_count, rapl_read_counter(event)); | |
270 | ||
271 | pmu->n_active++; | |
65661f96 SE |
272 | if (pmu->n_active == 1) |
273 | rapl_start_hrtimer(pmu); | |
4788e5b4 SE |
274 | } |
275 | ||
276 | static void rapl_pmu_event_start(struct perf_event *event, int mode) | |
277 | { | |
8a6d2f8f | 278 | struct rapl_pmu *pmu = event->pmu_private; |
4788e5b4 SE |
279 | unsigned long flags; |
280 | ||
a208749c | 281 | raw_spin_lock_irqsave(&pmu->lock, flags); |
4788e5b4 | 282 | __rapl_pmu_event_start(pmu, event); |
a208749c | 283 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
4788e5b4 SE |
284 | } |
285 | ||
286 | static void rapl_pmu_event_stop(struct perf_event *event, int mode) | |
287 | { | |
8a6d2f8f | 288 | struct rapl_pmu *pmu = event->pmu_private; |
4788e5b4 SE |
289 | struct hw_perf_event *hwc = &event->hw; |
290 | unsigned long flags; | |
291 | ||
a208749c | 292 | raw_spin_lock_irqsave(&pmu->lock, flags); |
4788e5b4 SE |
293 | |
294 | /* mark event as deactivated and stopped */ | |
295 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
296 | WARN_ON_ONCE(pmu->n_active <= 0); | |
297 | pmu->n_active--; | |
65661f96 | 298 | if (pmu->n_active == 0) |
7162b8fe | 299 | hrtimer_cancel(&pmu->hrtimer); |
4788e5b4 SE |
300 | |
301 | list_del(&event->active_entry); | |
302 | ||
303 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
304 | hwc->state |= PERF_HES_STOPPED; | |
305 | } | |
306 | ||
307 | /* check if update of sw counter is necessary */ | |
308 | if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { | |
309 | /* | |
310 | * Drain the remaining delta count out of a event | |
311 | * that we are disabling: | |
312 | */ | |
313 | rapl_event_update(event); | |
314 | hwc->state |= PERF_HES_UPTODATE; | |
315 | } | |
316 | ||
a208749c | 317 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
4788e5b4 SE |
318 | } |
319 | ||
320 | static int rapl_pmu_event_add(struct perf_event *event, int mode) | |
321 | { | |
8a6d2f8f | 322 | struct rapl_pmu *pmu = event->pmu_private; |
4788e5b4 SE |
323 | struct hw_perf_event *hwc = &event->hw; |
324 | unsigned long flags; | |
325 | ||
a208749c | 326 | raw_spin_lock_irqsave(&pmu->lock, flags); |
4788e5b4 SE |
327 | |
328 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; | |
329 | ||
330 | if (mode & PERF_EF_START) | |
331 | __rapl_pmu_event_start(pmu, event); | |
332 | ||
a208749c | 333 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
4788e5b4 SE |
334 | |
335 | return 0; | |
336 | } | |
337 | ||
338 | static void rapl_pmu_event_del(struct perf_event *event, int flags) | |
339 | { | |
340 | rapl_pmu_event_stop(event, PERF_EF_UPDATE); | |
341 | } | |
342 | ||
343 | static int rapl_pmu_event_init(struct perf_event *event) | |
344 | { | |
345 | u64 cfg = event->attr.config & RAPL_EVENT_MASK; | |
346 | int bit, msr, ret = 0; | |
9de8d686 | 347 | struct rapl_pmu *pmu; |
4788e5b4 SE |
348 | |
349 | /* only look at RAPL events */ | |
9de8d686 | 350 | if (event->attr.type != rapl_pmus->pmu.type) |
4788e5b4 SE |
351 | return -ENOENT; |
352 | ||
353 | /* check only supported bits are set */ | |
354 | if (event->attr.config & ~RAPL_EVENT_MASK) | |
355 | return -EINVAL; | |
356 | ||
8a6d2f8f TG |
357 | if (event->cpu < 0) |
358 | return -EINVAL; | |
359 | ||
e64cd6f7 DCC |
360 | event->event_caps |= PERF_EV_CAP_READ_ACTIVE_PKG; |
361 | ||
4788e5b4 SE |
362 | /* |
363 | * check event is known (determines counter) | |
364 | */ | |
365 | switch (cfg) { | |
366 | case INTEL_RAPL_PP0: | |
367 | bit = RAPL_IDX_PP0_NRG_STAT; | |
368 | msr = MSR_PP0_ENERGY_STATUS; | |
369 | break; | |
370 | case INTEL_RAPL_PKG: | |
371 | bit = RAPL_IDX_PKG_NRG_STAT; | |
372 | msr = MSR_PKG_ENERGY_STATUS; | |
373 | break; | |
374 | case INTEL_RAPL_RAM: | |
375 | bit = RAPL_IDX_RAM_NRG_STAT; | |
376 | msr = MSR_DRAM_ENERGY_STATUS; | |
377 | break; | |
f228c5b8 SE |
378 | case INTEL_RAPL_PP1: |
379 | bit = RAPL_IDX_PP1_NRG_STAT; | |
380 | msr = MSR_PP1_ENERGY_STATUS; | |
381 | break; | |
dcee75b3 SP |
382 | case INTEL_RAPL_PSYS: |
383 | bit = RAPL_IDX_PSYS_NRG_STAT; | |
384 | msr = MSR_PLATFORM_ENERGY_STATUS; | |
385 | break; | |
4788e5b4 SE |
386 | default: |
387 | return -EINVAL; | |
388 | } | |
389 | /* check event supported */ | |
390 | if (!(rapl_cntr_mask & (1 << bit))) | |
391 | return -EINVAL; | |
392 | ||
393 | /* unsupported modes and filters */ | |
394 | if (event->attr.exclude_user || | |
395 | event->attr.exclude_kernel || | |
396 | event->attr.exclude_hv || | |
397 | event->attr.exclude_idle || | |
398 | event->attr.exclude_host || | |
399 | event->attr.exclude_guest || | |
400 | event->attr.sample_period) /* no sampling */ | |
401 | return -EINVAL; | |
402 | ||
403 | /* must be done before validate_group */ | |
9de8d686 | 404 | pmu = cpu_to_rapl_pmu(event->cpu); |
8a6d2f8f TG |
405 | event->cpu = pmu->cpu; |
406 | event->pmu_private = pmu; | |
4788e5b4 SE |
407 | event->hw.event_base = msr; |
408 | event->hw.config = cfg; | |
409 | event->hw.idx = bit; | |
410 | ||
411 | return ret; | |
412 | } | |
413 | ||
414 | static void rapl_pmu_event_read(struct perf_event *event) | |
415 | { | |
416 | rapl_event_update(event); | |
417 | } | |
418 | ||
419 | static ssize_t rapl_get_attr_cpumask(struct device *dev, | |
420 | struct device_attribute *attr, char *buf) | |
421 | { | |
5aaba363 | 422 | return cpumap_print_to_pagebuf(true, buf, &rapl_cpu_mask); |
4788e5b4 SE |
423 | } |
424 | ||
425 | static DEVICE_ATTR(cpumask, S_IRUGO, rapl_get_attr_cpumask, NULL); | |
426 | ||
427 | static struct attribute *rapl_pmu_attrs[] = { | |
428 | &dev_attr_cpumask.attr, | |
429 | NULL, | |
430 | }; | |
431 | ||
432 | static struct attribute_group rapl_pmu_attr_group = { | |
433 | .attrs = rapl_pmu_attrs, | |
434 | }; | |
435 | ||
433678bd SE |
436 | RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); |
437 | RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02"); | |
438 | RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03"); | |
439 | RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04"); | |
dcee75b3 | 440 | RAPL_EVENT_ATTR_STR(energy-psys, rapl_psys, "event=0x05"); |
4788e5b4 | 441 | |
433678bd SE |
442 | RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules"); |
443 | RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules"); | |
444 | RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules"); | |
445 | RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules"); | |
dcee75b3 | 446 | RAPL_EVENT_ATTR_STR(energy-psys.unit, rapl_psys_unit, "Joules"); |
4788e5b4 SE |
447 | |
448 | /* | |
449 | * we compute in 0.23 nJ increments regardless of MSR | |
450 | */ | |
433678bd SE |
451 | RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10"); |
452 | RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10"); | |
453 | RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10"); | |
454 | RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10"); | |
dcee75b3 | 455 | RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_psys_scale, "2.3283064365386962890625e-10"); |
4788e5b4 SE |
456 | |
457 | static struct attribute *rapl_events_srv_attr[] = { | |
458 | EVENT_PTR(rapl_cores), | |
459 | EVENT_PTR(rapl_pkg), | |
460 | EVENT_PTR(rapl_ram), | |
461 | ||
462 | EVENT_PTR(rapl_cores_unit), | |
463 | EVENT_PTR(rapl_pkg_unit), | |
464 | EVENT_PTR(rapl_ram_unit), | |
465 | ||
466 | EVENT_PTR(rapl_cores_scale), | |
467 | EVENT_PTR(rapl_pkg_scale), | |
468 | EVENT_PTR(rapl_ram_scale), | |
469 | NULL, | |
470 | }; | |
471 | ||
472 | static struct attribute *rapl_events_cln_attr[] = { | |
473 | EVENT_PTR(rapl_cores), | |
474 | EVENT_PTR(rapl_pkg), | |
f228c5b8 | 475 | EVENT_PTR(rapl_gpu), |
4788e5b4 SE |
476 | |
477 | EVENT_PTR(rapl_cores_unit), | |
478 | EVENT_PTR(rapl_pkg_unit), | |
f228c5b8 | 479 | EVENT_PTR(rapl_gpu_unit), |
4788e5b4 SE |
480 | |
481 | EVENT_PTR(rapl_cores_scale), | |
482 | EVENT_PTR(rapl_pkg_scale), | |
f228c5b8 | 483 | EVENT_PTR(rapl_gpu_scale), |
4788e5b4 SE |
484 | NULL, |
485 | }; | |
486 | ||
e69af465 VW |
487 | static struct attribute *rapl_events_hsw_attr[] = { |
488 | EVENT_PTR(rapl_cores), | |
489 | EVENT_PTR(rapl_pkg), | |
490 | EVENT_PTR(rapl_gpu), | |
491 | EVENT_PTR(rapl_ram), | |
492 | ||
493 | EVENT_PTR(rapl_cores_unit), | |
494 | EVENT_PTR(rapl_pkg_unit), | |
495 | EVENT_PTR(rapl_gpu_unit), | |
496 | EVENT_PTR(rapl_ram_unit), | |
497 | ||
498 | EVENT_PTR(rapl_cores_scale), | |
499 | EVENT_PTR(rapl_pkg_scale), | |
500 | EVENT_PTR(rapl_gpu_scale), | |
501 | EVENT_PTR(rapl_ram_scale), | |
502 | NULL, | |
503 | }; | |
504 | ||
dcee75b3 SP |
505 | static struct attribute *rapl_events_skl_attr[] = { |
506 | EVENT_PTR(rapl_cores), | |
507 | EVENT_PTR(rapl_pkg), | |
508 | EVENT_PTR(rapl_gpu), | |
509 | EVENT_PTR(rapl_ram), | |
510 | EVENT_PTR(rapl_psys), | |
511 | ||
512 | EVENT_PTR(rapl_cores_unit), | |
513 | EVENT_PTR(rapl_pkg_unit), | |
514 | EVENT_PTR(rapl_gpu_unit), | |
515 | EVENT_PTR(rapl_ram_unit), | |
516 | EVENT_PTR(rapl_psys_unit), | |
517 | ||
518 | EVENT_PTR(rapl_cores_scale), | |
519 | EVENT_PTR(rapl_pkg_scale), | |
520 | EVENT_PTR(rapl_gpu_scale), | |
521 | EVENT_PTR(rapl_ram_scale), | |
522 | EVENT_PTR(rapl_psys_scale), | |
523 | NULL, | |
524 | }; | |
525 | ||
3a2a7797 DC |
526 | static struct attribute *rapl_events_knl_attr[] = { |
527 | EVENT_PTR(rapl_pkg), | |
528 | EVENT_PTR(rapl_ram), | |
529 | ||
530 | EVENT_PTR(rapl_pkg_unit), | |
531 | EVENT_PTR(rapl_ram_unit), | |
532 | ||
533 | EVENT_PTR(rapl_pkg_scale), | |
534 | EVENT_PTR(rapl_ram_scale), | |
535 | NULL, | |
536 | }; | |
537 | ||
4788e5b4 SE |
538 | static struct attribute_group rapl_pmu_events_group = { |
539 | .name = "events", | |
540 | .attrs = NULL, /* patched at runtime */ | |
541 | }; | |
542 | ||
543 | DEFINE_RAPL_FORMAT_ATTR(event, event, "config:0-7"); | |
544 | static struct attribute *rapl_formats_attr[] = { | |
545 | &format_attr_event.attr, | |
546 | NULL, | |
547 | }; | |
548 | ||
549 | static struct attribute_group rapl_pmu_format_group = { | |
550 | .name = "format", | |
551 | .attrs = rapl_formats_attr, | |
552 | }; | |
553 | ||
554 | const struct attribute_group *rapl_attr_groups[] = { | |
555 | &rapl_pmu_attr_group, | |
556 | &rapl_pmu_format_group, | |
557 | &rapl_pmu_events_group, | |
558 | NULL, | |
559 | }; | |
560 | ||
8b5b773d | 561 | static int rapl_cpu_offline(unsigned int cpu) |
4788e5b4 | 562 | { |
9de8d686 TG |
563 | struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu); |
564 | int target; | |
4788e5b4 | 565 | |
9de8d686 TG |
566 | /* Check if exiting cpu is used for collecting rapl events */ |
567 | if (!cpumask_test_and_clear_cpu(cpu, &rapl_cpu_mask)) | |
8b5b773d | 568 | return 0; |
4788e5b4 | 569 | |
9de8d686 TG |
570 | pmu->cpu = -1; |
571 | /* Find a new cpu to collect rapl events */ | |
572 | target = cpumask_any_but(topology_core_cpumask(cpu), cpu); | |
65661f96 | 573 | |
9de8d686 TG |
574 | /* Migrate rapl events to the new target */ |
575 | if (target < nr_cpu_ids) { | |
576 | cpumask_set_cpu(target, &rapl_cpu_mask); | |
577 | pmu->cpu = target; | |
578 | perf_pmu_migrate_context(pmu->pmu, cpu, target); | |
579 | } | |
8b5b773d | 580 | return 0; |
4788e5b4 SE |
581 | } |
582 | ||
8b5b773d | 583 | static int rapl_cpu_online(unsigned int cpu) |
4788e5b4 | 584 | { |
9de8d686 TG |
585 | struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu); |
586 | int target; | |
587 | ||
588 | /* | |
589 | * Check if there is an online cpu in the package which collects rapl | |
590 | * events already. | |
591 | */ | |
592 | target = cpumask_any_and(&rapl_cpu_mask, topology_core_cpumask(cpu)); | |
593 | if (target < nr_cpu_ids) | |
8b5b773d | 594 | return 0; |
4788e5b4 | 595 | |
4788e5b4 | 596 | cpumask_set_cpu(cpu, &rapl_cpu_mask); |
9de8d686 | 597 | pmu->cpu = cpu; |
8b5b773d | 598 | return 0; |
4788e5b4 SE |
599 | } |
600 | ||
8b5b773d | 601 | static int rapl_cpu_prepare(unsigned int cpu) |
4788e5b4 | 602 | { |
9de8d686 | 603 | struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu); |
4788e5b4 SE |
604 | |
605 | if (pmu) | |
606 | return 0; | |
607 | ||
4788e5b4 SE |
608 | pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu)); |
609 | if (!pmu) | |
9de8d686 | 610 | return -ENOMEM; |
4788e5b4 | 611 | |
9de8d686 | 612 | raw_spin_lock_init(&pmu->lock); |
4788e5b4 | 613 | INIT_LIST_HEAD(&pmu->active_list); |
9de8d686 | 614 | pmu->pmu = &rapl_pmus->pmu; |
75c7003f | 615 | pmu->timer_interval = ms_to_ktime(rapl_timer_ms); |
9de8d686 | 616 | pmu->cpu = -1; |
65661f96 | 617 | rapl_hrtimer_init(pmu); |
9de8d686 | 618 | rapl_pmus->pmus[topology_logical_package_id(cpu)] = pmu; |
4788e5b4 SE |
619 | return 0; |
620 | } | |
621 | ||
7a869805 | 622 | static int rapl_check_hw_unit(bool apply_quirk) |
64552396 JP |
623 | { |
624 | u64 msr_rapl_power_unit_bits; | |
625 | int i; | |
626 | ||
627 | /* protect rdmsrl() to handle virtualization */ | |
628 | if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits)) | |
629 | return -1; | |
630 | for (i = 0; i < NR_RAPL_DOMAINS; i++) | |
631 | rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL; | |
632 | ||
7a869805 BP |
633 | /* |
634 | * DRAM domain on HSW server and KNL has fixed energy unit which can be | |
635 | * different than the unit from power unit MSR. See | |
636 | * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2 | |
637 | * of 2. Datasheet, September 2014, Reference Number: 330784-001 " | |
638 | */ | |
639 | if (apply_quirk) | |
640 | rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16; | |
75c7003f TG |
641 | |
642 | /* | |
643 | * Calculate the timer rate: | |
644 | * Use reference of 200W for scaling the timeout to avoid counter | |
645 | * overflows. 200W = 200 Joules/sec | |
646 | * Divide interval by 2 to avoid lockstep (2 * 100) | |
647 | * if hw unit is 32, then we use 2 ms 1/200/2 | |
648 | */ | |
649 | rapl_timer_ms = 2; | |
650 | if (rapl_hw_unit[0] < 32) { | |
651 | rapl_timer_ms = (1000 / (2 * 100)); | |
652 | rapl_timer_ms *= (1ULL << (32 - rapl_hw_unit[0] - 1)); | |
653 | } | |
64552396 JP |
654 | return 0; |
655 | } | |
656 | ||
512089d9 TG |
657 | static void __init rapl_advertise(void) |
658 | { | |
659 | int i; | |
660 | ||
661 | pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\n", | |
662 | hweight32(rapl_cntr_mask), rapl_timer_ms); | |
663 | ||
664 | for (i = 0; i < NR_RAPL_DOMAINS; i++) { | |
665 | if (rapl_cntr_mask & (1 << i)) { | |
666 | pr_info("hw unit of domain %s 2^-%d Joules\n", | |
667 | rapl_domain_names[i], rapl_hw_unit[i]); | |
668 | } | |
669 | } | |
670 | } | |
671 | ||
4b6e2571 | 672 | static void cleanup_rapl_pmus(void) |
55f2890f | 673 | { |
9de8d686 TG |
674 | int i; |
675 | ||
676 | for (i = 0; i < rapl_pmus->maxpkg; i++) | |
275ae411 | 677 | kfree(rapl_pmus->pmus[i]); |
9de8d686 TG |
678 | kfree(rapl_pmus); |
679 | } | |
55f2890f | 680 | |
9de8d686 TG |
681 | static int __init init_rapl_pmus(void) |
682 | { | |
683 | int maxpkg = topology_max_packages(); | |
684 | size_t size; | |
685 | ||
686 | size = sizeof(*rapl_pmus) + maxpkg * sizeof(struct rapl_pmu *); | |
687 | rapl_pmus = kzalloc(size, GFP_KERNEL); | |
688 | if (!rapl_pmus) | |
689 | return -ENOMEM; | |
690 | ||
691 | rapl_pmus->maxpkg = maxpkg; | |
692 | rapl_pmus->pmu.attr_groups = rapl_attr_groups; | |
693 | rapl_pmus->pmu.task_ctx_nr = perf_invalid_context; | |
694 | rapl_pmus->pmu.event_init = rapl_pmu_event_init; | |
695 | rapl_pmus->pmu.add = rapl_pmu_event_add; | |
696 | rapl_pmus->pmu.del = rapl_pmu_event_del; | |
697 | rapl_pmus->pmu.start = rapl_pmu_event_start; | |
698 | rapl_pmus->pmu.stop = rapl_pmu_event_stop; | |
699 | rapl_pmus->pmu.read = rapl_pmu_event_read; | |
700 | return 0; | |
55f2890f TG |
701 | } |
702 | ||
4b6e2571 KL |
703 | #define X86_RAPL_MODEL_MATCH(model, init) \ |
704 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&init } | |
705 | ||
706 | struct intel_rapl_init_fun { | |
707 | bool apply_quirk; | |
708 | int cntr_mask; | |
709 | struct attribute **attrs; | |
710 | }; | |
711 | ||
712 | static const struct intel_rapl_init_fun snb_rapl_init __initconst = { | |
713 | .apply_quirk = false, | |
714 | .cntr_mask = RAPL_IDX_CLN, | |
715 | .attrs = rapl_events_cln_attr, | |
716 | }; | |
717 | ||
718 | static const struct intel_rapl_init_fun hsx_rapl_init __initconst = { | |
719 | .apply_quirk = true, | |
720 | .cntr_mask = RAPL_IDX_SRV, | |
721 | .attrs = rapl_events_srv_attr, | |
722 | }; | |
723 | ||
724 | static const struct intel_rapl_init_fun hsw_rapl_init __initconst = { | |
725 | .apply_quirk = false, | |
726 | .cntr_mask = RAPL_IDX_HSW, | |
727 | .attrs = rapl_events_hsw_attr, | |
728 | }; | |
729 | ||
730 | static const struct intel_rapl_init_fun snbep_rapl_init __initconst = { | |
731 | .apply_quirk = false, | |
732 | .cntr_mask = RAPL_IDX_SRV, | |
733 | .attrs = rapl_events_srv_attr, | |
734 | }; | |
735 | ||
736 | static const struct intel_rapl_init_fun knl_rapl_init __initconst = { | |
737 | .apply_quirk = true, | |
738 | .cntr_mask = RAPL_IDX_KNL, | |
739 | .attrs = rapl_events_knl_attr, | |
740 | }; | |
741 | ||
dcee75b3 SP |
742 | static const struct intel_rapl_init_fun skl_rapl_init __initconst = { |
743 | .apply_quirk = false, | |
744 | .cntr_mask = RAPL_IDX_SKL_CLN, | |
745 | .attrs = rapl_events_skl_attr, | |
746 | }; | |
747 | ||
7162b8fe | 748 | static const struct x86_cpu_id rapl_cpu_match[] __initconst = { |
7f2236d0 DH |
749 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE, snb_rapl_init), |
750 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X, snbep_rapl_init), | |
c416e5aa | 751 | |
7f2236d0 DH |
752 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE, snb_rapl_init), |
753 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_IVYBRIDGE_X, snbep_rapl_init), | |
c416e5aa | 754 | |
7f2236d0 DH |
755 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_CORE, hsw_rapl_init), |
756 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_X, hsw_rapl_init), | |
757 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_ULT, hsw_rapl_init), | |
758 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_HASWELL_GT3E, hsw_rapl_init), | |
c416e5aa | 759 | |
7f2236d0 DH |
760 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_CORE, hsw_rapl_init), |
761 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_GT3E, hsw_rapl_init), | |
762 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_X, hsw_rapl_init), | |
763 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_BROADWELL_XEON_D, hsw_rapl_init), | |
c416e5aa | 764 | |
7f2236d0 | 765 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_XEON_PHI_KNL, knl_rapl_init), |
c416e5aa | 766 | |
7f2236d0 DH |
767 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_rapl_init), |
768 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init), | |
348c5ac6 | 769 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, hsx_rapl_init), |
2668c619 HP |
770 | |
771 | X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), | |
4b6e2571 | 772 | {}, |
4788e5b4 SE |
773 | }; |
774 | ||
4b6e2571 KL |
775 | MODULE_DEVICE_TABLE(x86cpu, rapl_cpu_match); |
776 | ||
4788e5b4 SE |
777 | static int __init rapl_pmu_init(void) |
778 | { | |
4b6e2571 KL |
779 | const struct x86_cpu_id *id; |
780 | struct intel_rapl_init_fun *rapl_init; | |
781 | bool apply_quirk; | |
7162b8fe | 782 | int ret; |
4788e5b4 | 783 | |
4b6e2571 KL |
784 | id = x86_match_cpu(rapl_cpu_match); |
785 | if (!id) | |
55f2890f | 786 | return -ENODEV; |
4788e5b4 | 787 | |
4b6e2571 KL |
788 | rapl_init = (struct intel_rapl_init_fun *)id->driver_data; |
789 | apply_quirk = rapl_init->apply_quirk; | |
790 | rapl_cntr_mask = rapl_init->cntr_mask; | |
791 | rapl_pmu_events_group.attrs = rapl_init->attrs; | |
55f2890f | 792 | |
7a869805 | 793 | ret = rapl_check_hw_unit(apply_quirk); |
64552396 JP |
794 | if (ret) |
795 | return ret; | |
fd537e56 | 796 | |
9de8d686 TG |
797 | ret = init_rapl_pmus(); |
798 | if (ret) | |
799 | return ret; | |
800 | ||
8b5b773d RC |
801 | /* |
802 | * Install callbacks. Core will call them for each online cpu. | |
803 | */ | |
4788e5b4 | 804 | |
8b5b773d RC |
805 | ret = cpuhp_setup_state(CPUHP_PERF_X86_RAPL_PREP, "PERF_X86_RAPL_PREP", |
806 | rapl_cpu_prepare, NULL); | |
7162b8fe TG |
807 | if (ret) |
808 | goto out; | |
4788e5b4 | 809 | |
8b5b773d RC |
810 | ret = cpuhp_setup_state(CPUHP_AP_PERF_X86_RAPL_ONLINE, |
811 | "AP_PERF_X86_RAPL_ONLINE", | |
812 | rapl_cpu_online, rapl_cpu_offline); | |
813 | if (ret) | |
814 | goto out1; | |
815 | ||
9de8d686 | 816 | ret = perf_pmu_register(&rapl_pmus->pmu, "power", -1); |
512089d9 | 817 | if (ret) |
8b5b773d | 818 | goto out2; |
4788e5b4 | 819 | |
512089d9 | 820 | rapl_advertise(); |
4788e5b4 | 821 | return 0; |
55f2890f | 822 | |
8b5b773d RC |
823 | out2: |
824 | cpuhp_remove_state(CPUHP_AP_PERF_X86_RAPL_ONLINE); | |
825 | out1: | |
826 | cpuhp_remove_state(CPUHP_PERF_X86_RAPL_PREP); | |
55f2890f | 827 | out: |
512089d9 | 828 | pr_warn("Initialization failed (%d), disabled\n", ret); |
55f2890f | 829 | cleanup_rapl_pmus(); |
55f2890f | 830 | return ret; |
4788e5b4 | 831 | } |
4b6e2571 KL |
832 | module_init(rapl_pmu_init); |
833 | ||
834 | static void __exit intel_rapl_exit(void) | |
835 | { | |
8b5b773d RC |
836 | cpuhp_remove_state_nocalls(CPUHP_AP_PERF_X86_RAPL_ONLINE); |
837 | cpuhp_remove_state_nocalls(CPUHP_PERF_X86_RAPL_PREP); | |
4b6e2571 KL |
838 | perf_pmu_unregister(&rapl_pmus->pmu); |
839 | cleanup_rapl_pmus(); | |
4b6e2571 KL |
840 | } |
841 | module_exit(intel_rapl_exit); |