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4788e5b4 SE |
1 | /* |
2 | * perf_event_intel_rapl.c: support Intel RAPL energy consumption counters | |
3 | * Copyright (C) 2013 Google, Inc., Stephane Eranian | |
4 | * | |
5 | * Intel RAPL interface is specified in the IA-32 Manual Vol3b | |
6 | * section 14.7.1 (September 2013) | |
7 | * | |
8 | * RAPL provides more controls than just reporting energy consumption | |
9 | * however here we only expose the 3 energy consumption free running | |
10 | * counters (pp0, pkg, dram). | |
11 | * | |
12 | * Each of those counters increments in a power unit defined by the | |
13 | * RAPL_POWER_UNIT MSR. On SandyBridge, this unit is 1/(2^16) Joules | |
14 | * but it can vary. | |
15 | * | |
16 | * Counter to rapl events mappings: | |
17 | * | |
18 | * pp0 counter: consumption of all physical cores (power plane 0) | |
19 | * event: rapl_energy_cores | |
20 | * perf code: 0x1 | |
21 | * | |
22 | * pkg counter: consumption of the whole processor package | |
23 | * event: rapl_energy_pkg | |
24 | * perf code: 0x2 | |
25 | * | |
26 | * dram counter: consumption of the dram domain (servers only) | |
27 | * event: rapl_energy_dram | |
28 | * perf code: 0x3 | |
29 | * | |
f228c5b8 SE |
30 | * dram counter: consumption of the builtin-gpu domain (client only) |
31 | * event: rapl_energy_gpu | |
32 | * perf code: 0x4 | |
33 | * | |
4788e5b4 SE |
34 | * We manage those counters as free running (read-only). They may be |
35 | * use simultaneously by other tools, such as turbostat. | |
36 | * | |
37 | * The events only support system-wide mode counting. There is no | |
38 | * sampling support because it does not make sense and is not | |
39 | * supported by the RAPL hardware. | |
40 | * | |
41 | * Because we want to avoid floating-point operations in the kernel, | |
42 | * the events are all reported in fixed point arithmetic (32.32). | |
43 | * Tools must adjust the counts to convert them to Watts using | |
44 | * the duration of the measurement. Tools may use a function such as | |
45 | * ldexp(raw_count, -32); | |
46 | */ | |
512089d9 TG |
47 | |
48 | #define pr_fmt(fmt) "RAPL PMU: " fmt | |
49 | ||
4788e5b4 SE |
50 | #include <linux/module.h> |
51 | #include <linux/slab.h> | |
52 | #include <linux/perf_event.h> | |
53 | #include <asm/cpu_device_id.h> | |
27f6d22b | 54 | #include "../perf_event.h" |
4788e5b4 SE |
55 | |
56 | /* | |
57 | * RAPL energy status counters | |
58 | */ | |
59 | #define RAPL_IDX_PP0_NRG_STAT 0 /* all cores */ | |
60 | #define INTEL_RAPL_PP0 0x1 /* pseudo-encoding */ | |
61 | #define RAPL_IDX_PKG_NRG_STAT 1 /* entire package */ | |
62 | #define INTEL_RAPL_PKG 0x2 /* pseudo-encoding */ | |
63 | #define RAPL_IDX_RAM_NRG_STAT 2 /* DRAM */ | |
64 | #define INTEL_RAPL_RAM 0x3 /* pseudo-encoding */ | |
e69af465 | 65 | #define RAPL_IDX_PP1_NRG_STAT 3 /* gpu */ |
f228c5b8 | 66 | #define INTEL_RAPL_PP1 0x4 /* pseudo-encoding */ |
4788e5b4 | 67 | |
64552396 | 68 | #define NR_RAPL_DOMAINS 0x4 |
da008ee7 | 69 | static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = { |
64552396 JP |
70 | "pp0-core", |
71 | "package", | |
72 | "dram", | |
73 | "pp1-gpu", | |
74 | }; | |
75 | ||
4788e5b4 SE |
76 | /* Clients have PP0, PKG */ |
77 | #define RAPL_IDX_CLN (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
f228c5b8 SE |
78 | 1<<RAPL_IDX_PKG_NRG_STAT|\ |
79 | 1<<RAPL_IDX_PP1_NRG_STAT) | |
4788e5b4 SE |
80 | |
81 | /* Servers have PP0, PKG, RAM */ | |
82 | #define RAPL_IDX_SRV (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
83 | 1<<RAPL_IDX_PKG_NRG_STAT|\ | |
84 | 1<<RAPL_IDX_RAM_NRG_STAT) | |
85 | ||
e69af465 VW |
86 | /* Servers have PP0, PKG, RAM, PP1 */ |
87 | #define RAPL_IDX_HSW (1<<RAPL_IDX_PP0_NRG_STAT|\ | |
88 | 1<<RAPL_IDX_PKG_NRG_STAT|\ | |
89 | 1<<RAPL_IDX_RAM_NRG_STAT|\ | |
90 | 1<<RAPL_IDX_PP1_NRG_STAT) | |
91 | ||
3a2a7797 DC |
92 | /* Knights Landing has PKG, RAM */ |
93 | #define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\ | |
94 | 1<<RAPL_IDX_RAM_NRG_STAT) | |
95 | ||
4788e5b4 SE |
96 | /* |
97 | * event code: LSB 8 bits, passed in attr->config | |
98 | * any other bit is reserved | |
99 | */ | |
100 | #define RAPL_EVENT_MASK 0xFFULL | |
101 | ||
102 | #define DEFINE_RAPL_FORMAT_ATTR(_var, _name, _format) \ | |
103 | static ssize_t __rapl_##_var##_show(struct kobject *kobj, \ | |
104 | struct kobj_attribute *attr, \ | |
105 | char *page) \ | |
106 | { \ | |
107 | BUILD_BUG_ON(sizeof(_format) >= PAGE_SIZE); \ | |
108 | return sprintf(page, _format "\n"); \ | |
109 | } \ | |
110 | static struct kobj_attribute format_attr_##_var = \ | |
111 | __ATTR(_name, 0444, __rapl_##_var##_show, NULL) | |
112 | ||
7162b8fe | 113 | #define RAPL_CNTR_WIDTH 32 |
4788e5b4 | 114 | |
d3bcd64b HR |
115 | #define RAPL_EVENT_ATTR_STR(_name, v, str) \ |
116 | static struct perf_pmu_events_attr event_attr_##v = { \ | |
117 | .attr = __ATTR(_name, 0444, perf_event_sysfs_show, NULL), \ | |
118 | .id = 0, \ | |
119 | .event_str = str, \ | |
433678bd SE |
120 | }; |
121 | ||
4788e5b4 | 122 | struct rapl_pmu { |
a208749c | 123 | raw_spinlock_t lock; |
7162b8fe | 124 | int n_active; |
8a6d2f8f | 125 | int cpu; |
7162b8fe TG |
126 | struct list_head active_list; |
127 | struct pmu *pmu; | |
128 | ktime_t timer_interval; | |
129 | struct hrtimer hrtimer; | |
4788e5b4 SE |
130 | }; |
131 | ||
9de8d686 TG |
132 | struct rapl_pmus { |
133 | struct pmu pmu; | |
134 | unsigned int maxpkg; | |
135 | struct rapl_pmu *pmus[]; | |
136 | }; | |
137 | ||
7162b8fe TG |
138 | /* 1/2^hw_unit Joule */ |
139 | static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly; | |
9de8d686 | 140 | static struct rapl_pmus *rapl_pmus; |
4788e5b4 | 141 | static cpumask_t rapl_cpu_mask; |
9de8d686 | 142 | static unsigned int rapl_cntr_mask; |
75c7003f | 143 | static u64 rapl_timer_ms; |
4788e5b4 | 144 | |
9de8d686 TG |
145 | static inline struct rapl_pmu *cpu_to_rapl_pmu(unsigned int cpu) |
146 | { | |
147 | return rapl_pmus->pmus[topology_logical_package_id(cpu)]; | |
148 | } | |
4788e5b4 SE |
149 | |
150 | static inline u64 rapl_read_counter(struct perf_event *event) | |
151 | { | |
152 | u64 raw; | |
153 | rdmsrl(event->hw.event_base, raw); | |
154 | return raw; | |
155 | } | |
156 | ||
64552396 | 157 | static inline u64 rapl_scale(u64 v, int cfg) |
4788e5b4 | 158 | { |
64552396 | 159 | if (cfg > NR_RAPL_DOMAINS) { |
512089d9 | 160 | pr_warn("Invalid domain %d, failed to scale data\n", cfg); |
64552396 JP |
161 | return v; |
162 | } | |
4788e5b4 SE |
163 | /* |
164 | * scale delta to smallest unit (1/2^32) | |
165 | * users must then scale back: count * 1/(1e9*2^32) to get Joules | |
166 | * or use ldexp(count, -32). | |
167 | * Watts = Joules/Time delta | |
168 | */ | |
64552396 | 169 | return v << (32 - rapl_hw_unit[cfg - 1]); |
4788e5b4 SE |
170 | } |
171 | ||
172 | static u64 rapl_event_update(struct perf_event *event) | |
173 | { | |
174 | struct hw_perf_event *hwc = &event->hw; | |
175 | u64 prev_raw_count, new_raw_count; | |
176 | s64 delta, sdelta; | |
177 | int shift = RAPL_CNTR_WIDTH; | |
178 | ||
179 | again: | |
180 | prev_raw_count = local64_read(&hwc->prev_count); | |
181 | rdmsrl(event->hw.event_base, new_raw_count); | |
182 | ||
183 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, | |
184 | new_raw_count) != prev_raw_count) { | |
185 | cpu_relax(); | |
186 | goto again; | |
187 | } | |
188 | ||
189 | /* | |
190 | * Now we have the new raw value and have updated the prev | |
191 | * timestamp already. We can now calculate the elapsed delta | |
192 | * (event-)time and add that to the generic event. | |
193 | * | |
194 | * Careful, not all hw sign-extends above the physical width | |
195 | * of the count. | |
196 | */ | |
197 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | |
198 | delta >>= shift; | |
199 | ||
64552396 | 200 | sdelta = rapl_scale(delta, event->hw.config); |
4788e5b4 SE |
201 | |
202 | local64_add(sdelta, &event->count); | |
203 | ||
204 | return new_raw_count; | |
205 | } | |
206 | ||
65661f96 SE |
207 | static void rapl_start_hrtimer(struct rapl_pmu *pmu) |
208 | { | |
514c2304 TG |
209 | hrtimer_start(&pmu->hrtimer, pmu->timer_interval, |
210 | HRTIMER_MODE_REL_PINNED); | |
65661f96 SE |
211 | } |
212 | ||
65661f96 SE |
213 | static enum hrtimer_restart rapl_hrtimer_handle(struct hrtimer *hrtimer) |
214 | { | |
8a6d2f8f | 215 | struct rapl_pmu *pmu = container_of(hrtimer, struct rapl_pmu, hrtimer); |
65661f96 SE |
216 | struct perf_event *event; |
217 | unsigned long flags; | |
218 | ||
219 | if (!pmu->n_active) | |
220 | return HRTIMER_NORESTART; | |
221 | ||
a208749c | 222 | raw_spin_lock_irqsave(&pmu->lock, flags); |
65661f96 | 223 | |
7162b8fe | 224 | list_for_each_entry(event, &pmu->active_list, active_entry) |
65661f96 | 225 | rapl_event_update(event); |
65661f96 | 226 | |
a208749c | 227 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
65661f96 SE |
228 | |
229 | hrtimer_forward_now(hrtimer, pmu->timer_interval); | |
230 | ||
231 | return HRTIMER_RESTART; | |
232 | } | |
233 | ||
234 | static void rapl_hrtimer_init(struct rapl_pmu *pmu) | |
235 | { | |
236 | struct hrtimer *hr = &pmu->hrtimer; | |
237 | ||
238 | hrtimer_init(hr, CLOCK_MONOTONIC, HRTIMER_MODE_REL); | |
239 | hr->function = rapl_hrtimer_handle; | |
240 | } | |
241 | ||
4788e5b4 SE |
242 | static void __rapl_pmu_event_start(struct rapl_pmu *pmu, |
243 | struct perf_event *event) | |
244 | { | |
245 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) | |
246 | return; | |
247 | ||
248 | event->hw.state = 0; | |
249 | ||
250 | list_add_tail(&event->active_entry, &pmu->active_list); | |
251 | ||
252 | local64_set(&event->hw.prev_count, rapl_read_counter(event)); | |
253 | ||
254 | pmu->n_active++; | |
65661f96 SE |
255 | if (pmu->n_active == 1) |
256 | rapl_start_hrtimer(pmu); | |
4788e5b4 SE |
257 | } |
258 | ||
259 | static void rapl_pmu_event_start(struct perf_event *event, int mode) | |
260 | { | |
8a6d2f8f | 261 | struct rapl_pmu *pmu = event->pmu_private; |
4788e5b4 SE |
262 | unsigned long flags; |
263 | ||
a208749c | 264 | raw_spin_lock_irqsave(&pmu->lock, flags); |
4788e5b4 | 265 | __rapl_pmu_event_start(pmu, event); |
a208749c | 266 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
4788e5b4 SE |
267 | } |
268 | ||
269 | static void rapl_pmu_event_stop(struct perf_event *event, int mode) | |
270 | { | |
8a6d2f8f | 271 | struct rapl_pmu *pmu = event->pmu_private; |
4788e5b4 SE |
272 | struct hw_perf_event *hwc = &event->hw; |
273 | unsigned long flags; | |
274 | ||
a208749c | 275 | raw_spin_lock_irqsave(&pmu->lock, flags); |
4788e5b4 SE |
276 | |
277 | /* mark event as deactivated and stopped */ | |
278 | if (!(hwc->state & PERF_HES_STOPPED)) { | |
279 | WARN_ON_ONCE(pmu->n_active <= 0); | |
280 | pmu->n_active--; | |
65661f96 | 281 | if (pmu->n_active == 0) |
7162b8fe | 282 | hrtimer_cancel(&pmu->hrtimer); |
4788e5b4 SE |
283 | |
284 | list_del(&event->active_entry); | |
285 | ||
286 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
287 | hwc->state |= PERF_HES_STOPPED; | |
288 | } | |
289 | ||
290 | /* check if update of sw counter is necessary */ | |
291 | if ((mode & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { | |
292 | /* | |
293 | * Drain the remaining delta count out of a event | |
294 | * that we are disabling: | |
295 | */ | |
296 | rapl_event_update(event); | |
297 | hwc->state |= PERF_HES_UPTODATE; | |
298 | } | |
299 | ||
a208749c | 300 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
4788e5b4 SE |
301 | } |
302 | ||
303 | static int rapl_pmu_event_add(struct perf_event *event, int mode) | |
304 | { | |
8a6d2f8f | 305 | struct rapl_pmu *pmu = event->pmu_private; |
4788e5b4 SE |
306 | struct hw_perf_event *hwc = &event->hw; |
307 | unsigned long flags; | |
308 | ||
a208749c | 309 | raw_spin_lock_irqsave(&pmu->lock, flags); |
4788e5b4 SE |
310 | |
311 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; | |
312 | ||
313 | if (mode & PERF_EF_START) | |
314 | __rapl_pmu_event_start(pmu, event); | |
315 | ||
a208749c | 316 | raw_spin_unlock_irqrestore(&pmu->lock, flags); |
4788e5b4 SE |
317 | |
318 | return 0; | |
319 | } | |
320 | ||
321 | static void rapl_pmu_event_del(struct perf_event *event, int flags) | |
322 | { | |
323 | rapl_pmu_event_stop(event, PERF_EF_UPDATE); | |
324 | } | |
325 | ||
326 | static int rapl_pmu_event_init(struct perf_event *event) | |
327 | { | |
328 | u64 cfg = event->attr.config & RAPL_EVENT_MASK; | |
329 | int bit, msr, ret = 0; | |
9de8d686 | 330 | struct rapl_pmu *pmu; |
4788e5b4 SE |
331 | |
332 | /* only look at RAPL events */ | |
9de8d686 | 333 | if (event->attr.type != rapl_pmus->pmu.type) |
4788e5b4 SE |
334 | return -ENOENT; |
335 | ||
336 | /* check only supported bits are set */ | |
337 | if (event->attr.config & ~RAPL_EVENT_MASK) | |
338 | return -EINVAL; | |
339 | ||
8a6d2f8f TG |
340 | if (event->cpu < 0) |
341 | return -EINVAL; | |
342 | ||
4788e5b4 SE |
343 | /* |
344 | * check event is known (determines counter) | |
345 | */ | |
346 | switch (cfg) { | |
347 | case INTEL_RAPL_PP0: | |
348 | bit = RAPL_IDX_PP0_NRG_STAT; | |
349 | msr = MSR_PP0_ENERGY_STATUS; | |
350 | break; | |
351 | case INTEL_RAPL_PKG: | |
352 | bit = RAPL_IDX_PKG_NRG_STAT; | |
353 | msr = MSR_PKG_ENERGY_STATUS; | |
354 | break; | |
355 | case INTEL_RAPL_RAM: | |
356 | bit = RAPL_IDX_RAM_NRG_STAT; | |
357 | msr = MSR_DRAM_ENERGY_STATUS; | |
358 | break; | |
f228c5b8 SE |
359 | case INTEL_RAPL_PP1: |
360 | bit = RAPL_IDX_PP1_NRG_STAT; | |
361 | msr = MSR_PP1_ENERGY_STATUS; | |
362 | break; | |
4788e5b4 SE |
363 | default: |
364 | return -EINVAL; | |
365 | } | |
366 | /* check event supported */ | |
367 | if (!(rapl_cntr_mask & (1 << bit))) | |
368 | return -EINVAL; | |
369 | ||
370 | /* unsupported modes and filters */ | |
371 | if (event->attr.exclude_user || | |
372 | event->attr.exclude_kernel || | |
373 | event->attr.exclude_hv || | |
374 | event->attr.exclude_idle || | |
375 | event->attr.exclude_host || | |
376 | event->attr.exclude_guest || | |
377 | event->attr.sample_period) /* no sampling */ | |
378 | return -EINVAL; | |
379 | ||
380 | /* must be done before validate_group */ | |
9de8d686 | 381 | pmu = cpu_to_rapl_pmu(event->cpu); |
8a6d2f8f TG |
382 | event->cpu = pmu->cpu; |
383 | event->pmu_private = pmu; | |
4788e5b4 SE |
384 | event->hw.event_base = msr; |
385 | event->hw.config = cfg; | |
386 | event->hw.idx = bit; | |
387 | ||
388 | return ret; | |
389 | } | |
390 | ||
391 | static void rapl_pmu_event_read(struct perf_event *event) | |
392 | { | |
393 | rapl_event_update(event); | |
394 | } | |
395 | ||
396 | static ssize_t rapl_get_attr_cpumask(struct device *dev, | |
397 | struct device_attribute *attr, char *buf) | |
398 | { | |
5aaba363 | 399 | return cpumap_print_to_pagebuf(true, buf, &rapl_cpu_mask); |
4788e5b4 SE |
400 | } |
401 | ||
402 | static DEVICE_ATTR(cpumask, S_IRUGO, rapl_get_attr_cpumask, NULL); | |
403 | ||
404 | static struct attribute *rapl_pmu_attrs[] = { | |
405 | &dev_attr_cpumask.attr, | |
406 | NULL, | |
407 | }; | |
408 | ||
409 | static struct attribute_group rapl_pmu_attr_group = { | |
410 | .attrs = rapl_pmu_attrs, | |
411 | }; | |
412 | ||
433678bd SE |
413 | RAPL_EVENT_ATTR_STR(energy-cores, rapl_cores, "event=0x01"); |
414 | RAPL_EVENT_ATTR_STR(energy-pkg , rapl_pkg, "event=0x02"); | |
415 | RAPL_EVENT_ATTR_STR(energy-ram , rapl_ram, "event=0x03"); | |
416 | RAPL_EVENT_ATTR_STR(energy-gpu , rapl_gpu, "event=0x04"); | |
4788e5b4 | 417 | |
433678bd SE |
418 | RAPL_EVENT_ATTR_STR(energy-cores.unit, rapl_cores_unit, "Joules"); |
419 | RAPL_EVENT_ATTR_STR(energy-pkg.unit , rapl_pkg_unit, "Joules"); | |
420 | RAPL_EVENT_ATTR_STR(energy-ram.unit , rapl_ram_unit, "Joules"); | |
421 | RAPL_EVENT_ATTR_STR(energy-gpu.unit , rapl_gpu_unit, "Joules"); | |
4788e5b4 SE |
422 | |
423 | /* | |
424 | * we compute in 0.23 nJ increments regardless of MSR | |
425 | */ | |
433678bd SE |
426 | RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_cores_scale, "2.3283064365386962890625e-10"); |
427 | RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_pkg_scale, "2.3283064365386962890625e-10"); | |
428 | RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890625e-10"); | |
429 | RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10"); | |
4788e5b4 SE |
430 | |
431 | static struct attribute *rapl_events_srv_attr[] = { | |
432 | EVENT_PTR(rapl_cores), | |
433 | EVENT_PTR(rapl_pkg), | |
434 | EVENT_PTR(rapl_ram), | |
435 | ||
436 | EVENT_PTR(rapl_cores_unit), | |
437 | EVENT_PTR(rapl_pkg_unit), | |
438 | EVENT_PTR(rapl_ram_unit), | |
439 | ||
440 | EVENT_PTR(rapl_cores_scale), | |
441 | EVENT_PTR(rapl_pkg_scale), | |
442 | EVENT_PTR(rapl_ram_scale), | |
443 | NULL, | |
444 | }; | |
445 | ||
446 | static struct attribute *rapl_events_cln_attr[] = { | |
447 | EVENT_PTR(rapl_cores), | |
448 | EVENT_PTR(rapl_pkg), | |
f228c5b8 | 449 | EVENT_PTR(rapl_gpu), |
4788e5b4 SE |
450 | |
451 | EVENT_PTR(rapl_cores_unit), | |
452 | EVENT_PTR(rapl_pkg_unit), | |
f228c5b8 | 453 | EVENT_PTR(rapl_gpu_unit), |
4788e5b4 SE |
454 | |
455 | EVENT_PTR(rapl_cores_scale), | |
456 | EVENT_PTR(rapl_pkg_scale), | |
f228c5b8 | 457 | EVENT_PTR(rapl_gpu_scale), |
4788e5b4 SE |
458 | NULL, |
459 | }; | |
460 | ||
e69af465 VW |
461 | static struct attribute *rapl_events_hsw_attr[] = { |
462 | EVENT_PTR(rapl_cores), | |
463 | EVENT_PTR(rapl_pkg), | |
464 | EVENT_PTR(rapl_gpu), | |
465 | EVENT_PTR(rapl_ram), | |
466 | ||
467 | EVENT_PTR(rapl_cores_unit), | |
468 | EVENT_PTR(rapl_pkg_unit), | |
469 | EVENT_PTR(rapl_gpu_unit), | |
470 | EVENT_PTR(rapl_ram_unit), | |
471 | ||
472 | EVENT_PTR(rapl_cores_scale), | |
473 | EVENT_PTR(rapl_pkg_scale), | |
474 | EVENT_PTR(rapl_gpu_scale), | |
475 | EVENT_PTR(rapl_ram_scale), | |
476 | NULL, | |
477 | }; | |
478 | ||
3a2a7797 DC |
479 | static struct attribute *rapl_events_knl_attr[] = { |
480 | EVENT_PTR(rapl_pkg), | |
481 | EVENT_PTR(rapl_ram), | |
482 | ||
483 | EVENT_PTR(rapl_pkg_unit), | |
484 | EVENT_PTR(rapl_ram_unit), | |
485 | ||
486 | EVENT_PTR(rapl_pkg_scale), | |
487 | EVENT_PTR(rapl_ram_scale), | |
488 | NULL, | |
489 | }; | |
490 | ||
4788e5b4 SE |
491 | static struct attribute_group rapl_pmu_events_group = { |
492 | .name = "events", | |
493 | .attrs = NULL, /* patched at runtime */ | |
494 | }; | |
495 | ||
496 | DEFINE_RAPL_FORMAT_ATTR(event, event, "config:0-7"); | |
497 | static struct attribute *rapl_formats_attr[] = { | |
498 | &format_attr_event.attr, | |
499 | NULL, | |
500 | }; | |
501 | ||
502 | static struct attribute_group rapl_pmu_format_group = { | |
503 | .name = "format", | |
504 | .attrs = rapl_formats_attr, | |
505 | }; | |
506 | ||
507 | const struct attribute_group *rapl_attr_groups[] = { | |
508 | &rapl_pmu_attr_group, | |
509 | &rapl_pmu_format_group, | |
510 | &rapl_pmu_events_group, | |
511 | NULL, | |
512 | }; | |
513 | ||
4788e5b4 SE |
514 | static void rapl_cpu_exit(int cpu) |
515 | { | |
9de8d686 TG |
516 | struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu); |
517 | int target; | |
4788e5b4 | 518 | |
9de8d686 TG |
519 | /* Check if exiting cpu is used for collecting rapl events */ |
520 | if (!cpumask_test_and_clear_cpu(cpu, &rapl_cpu_mask)) | |
521 | return; | |
4788e5b4 | 522 | |
9de8d686 TG |
523 | pmu->cpu = -1; |
524 | /* Find a new cpu to collect rapl events */ | |
525 | target = cpumask_any_but(topology_core_cpumask(cpu), cpu); | |
65661f96 | 526 | |
9de8d686 TG |
527 | /* Migrate rapl events to the new target */ |
528 | if (target < nr_cpu_ids) { | |
529 | cpumask_set_cpu(target, &rapl_cpu_mask); | |
530 | pmu->cpu = target; | |
531 | perf_pmu_migrate_context(pmu->pmu, cpu, target); | |
532 | } | |
4788e5b4 SE |
533 | } |
534 | ||
535 | static void rapl_cpu_init(int cpu) | |
536 | { | |
9de8d686 TG |
537 | struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu); |
538 | int target; | |
539 | ||
540 | /* | |
541 | * Check if there is an online cpu in the package which collects rapl | |
542 | * events already. | |
543 | */ | |
544 | target = cpumask_any_and(&rapl_cpu_mask, topology_core_cpumask(cpu)); | |
545 | if (target < nr_cpu_ids) | |
546 | return; | |
4788e5b4 | 547 | |
4788e5b4 | 548 | cpumask_set_cpu(cpu, &rapl_cpu_mask); |
9de8d686 | 549 | pmu->cpu = cpu; |
4788e5b4 SE |
550 | } |
551 | ||
552 | static int rapl_cpu_prepare(int cpu) | |
553 | { | |
9de8d686 | 554 | struct rapl_pmu *pmu = cpu_to_rapl_pmu(cpu); |
4788e5b4 SE |
555 | |
556 | if (pmu) | |
557 | return 0; | |
558 | ||
4788e5b4 SE |
559 | pmu = kzalloc_node(sizeof(*pmu), GFP_KERNEL, cpu_to_node(cpu)); |
560 | if (!pmu) | |
9de8d686 | 561 | return -ENOMEM; |
4788e5b4 | 562 | |
9de8d686 | 563 | raw_spin_lock_init(&pmu->lock); |
4788e5b4 | 564 | INIT_LIST_HEAD(&pmu->active_list); |
9de8d686 | 565 | pmu->pmu = &rapl_pmus->pmu; |
75c7003f | 566 | pmu->timer_interval = ms_to_ktime(rapl_timer_ms); |
9de8d686 | 567 | pmu->cpu = -1; |
65661f96 | 568 | rapl_hrtimer_init(pmu); |
9de8d686 | 569 | rapl_pmus->pmus[topology_logical_package_id(cpu)] = pmu; |
4788e5b4 SE |
570 | return 0; |
571 | } | |
572 | ||
573 | static int rapl_cpu_notifier(struct notifier_block *self, | |
574 | unsigned long action, void *hcpu) | |
575 | { | |
576 | unsigned int cpu = (long)hcpu; | |
577 | ||
578 | switch (action & ~CPU_TASKS_FROZEN) { | |
579 | case CPU_UP_PREPARE: | |
580 | rapl_cpu_prepare(cpu); | |
581 | break; | |
9de8d686 TG |
582 | |
583 | case CPU_DOWN_FAILED: | |
4788e5b4 | 584 | case CPU_ONLINE: |
9de8d686 | 585 | rapl_cpu_init(cpu); |
4788e5b4 | 586 | break; |
9de8d686 | 587 | |
4788e5b4 SE |
588 | case CPU_DOWN_PREPARE: |
589 | rapl_cpu_exit(cpu); | |
590 | break; | |
4788e5b4 | 591 | } |
4788e5b4 SE |
592 | return NOTIFY_OK; |
593 | } | |
594 | ||
7a869805 | 595 | static int rapl_check_hw_unit(bool apply_quirk) |
64552396 JP |
596 | { |
597 | u64 msr_rapl_power_unit_bits; | |
598 | int i; | |
599 | ||
600 | /* protect rdmsrl() to handle virtualization */ | |
601 | if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits)) | |
602 | return -1; | |
603 | for (i = 0; i < NR_RAPL_DOMAINS; i++) | |
604 | rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL; | |
605 | ||
7a869805 BP |
606 | /* |
607 | * DRAM domain on HSW server and KNL has fixed energy unit which can be | |
608 | * different than the unit from power unit MSR. See | |
609 | * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2 | |
610 | * of 2. Datasheet, September 2014, Reference Number: 330784-001 " | |
611 | */ | |
612 | if (apply_quirk) | |
613 | rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16; | |
75c7003f TG |
614 | |
615 | /* | |
616 | * Calculate the timer rate: | |
617 | * Use reference of 200W for scaling the timeout to avoid counter | |
618 | * overflows. 200W = 200 Joules/sec | |
619 | * Divide interval by 2 to avoid lockstep (2 * 100) | |
620 | * if hw unit is 32, then we use 2 ms 1/200/2 | |
621 | */ | |
622 | rapl_timer_ms = 2; | |
623 | if (rapl_hw_unit[0] < 32) { | |
624 | rapl_timer_ms = (1000 / (2 * 100)); | |
625 | rapl_timer_ms *= (1ULL << (32 - rapl_hw_unit[0] - 1)); | |
626 | } | |
64552396 JP |
627 | return 0; |
628 | } | |
629 | ||
512089d9 TG |
630 | static void __init rapl_advertise(void) |
631 | { | |
632 | int i; | |
633 | ||
634 | pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\n", | |
635 | hweight32(rapl_cntr_mask), rapl_timer_ms); | |
636 | ||
637 | for (i = 0; i < NR_RAPL_DOMAINS; i++) { | |
638 | if (rapl_cntr_mask & (1 << i)) { | |
639 | pr_info("hw unit of domain %s 2^-%d Joules\n", | |
640 | rapl_domain_names[i], rapl_hw_unit[i]); | |
641 | } | |
642 | } | |
643 | } | |
644 | ||
7162b8fe TG |
645 | static int __init rapl_prepare_cpus(void) |
646 | { | |
9de8d686 | 647 | unsigned int cpu, pkg; |
7162b8fe TG |
648 | int ret; |
649 | ||
650 | for_each_online_cpu(cpu) { | |
9de8d686 TG |
651 | pkg = topology_logical_package_id(cpu); |
652 | if (rapl_pmus->pmus[pkg]) | |
653 | continue; | |
654 | ||
7162b8fe TG |
655 | ret = rapl_cpu_prepare(cpu); |
656 | if (ret) | |
657 | return ret; | |
658 | rapl_cpu_init(cpu); | |
659 | } | |
660 | return 0; | |
661 | } | |
662 | ||
55f2890f TG |
663 | static void __init cleanup_rapl_pmus(void) |
664 | { | |
9de8d686 TG |
665 | int i; |
666 | ||
667 | for (i = 0; i < rapl_pmus->maxpkg; i++) | |
668 | kfree(rapl_pmus->pmus + i); | |
669 | kfree(rapl_pmus); | |
670 | } | |
55f2890f | 671 | |
9de8d686 TG |
672 | static int __init init_rapl_pmus(void) |
673 | { | |
674 | int maxpkg = topology_max_packages(); | |
675 | size_t size; | |
676 | ||
677 | size = sizeof(*rapl_pmus) + maxpkg * sizeof(struct rapl_pmu *); | |
678 | rapl_pmus = kzalloc(size, GFP_KERNEL); | |
679 | if (!rapl_pmus) | |
680 | return -ENOMEM; | |
681 | ||
682 | rapl_pmus->maxpkg = maxpkg; | |
683 | rapl_pmus->pmu.attr_groups = rapl_attr_groups; | |
684 | rapl_pmus->pmu.task_ctx_nr = perf_invalid_context; | |
685 | rapl_pmus->pmu.event_init = rapl_pmu_event_init; | |
686 | rapl_pmus->pmu.add = rapl_pmu_event_add; | |
687 | rapl_pmus->pmu.del = rapl_pmu_event_del; | |
688 | rapl_pmus->pmu.start = rapl_pmu_event_start; | |
689 | rapl_pmus->pmu.stop = rapl_pmu_event_stop; | |
690 | rapl_pmus->pmu.read = rapl_pmu_event_read; | |
691 | return 0; | |
55f2890f TG |
692 | } |
693 | ||
7162b8fe | 694 | static const struct x86_cpu_id rapl_cpu_match[] __initconst = { |
4788e5b4 SE |
695 | [0] = { .vendor = X86_VENDOR_INTEL, .family = 6 }, |
696 | [1] = {}, | |
697 | }; | |
698 | ||
699 | static int __init rapl_pmu_init(void) | |
700 | { | |
7a869805 | 701 | bool apply_quirk = false; |
7162b8fe | 702 | int ret; |
4788e5b4 | 703 | |
4788e5b4 | 704 | if (!x86_match_cpu(rapl_cpu_match)) |
55f2890f | 705 | return -ENODEV; |
4788e5b4 | 706 | |
4788e5b4 SE |
707 | switch (boot_cpu_data.x86_model) { |
708 | case 42: /* Sandy Bridge */ | |
709 | case 58: /* Ivy Bridge */ | |
4788e5b4 SE |
710 | rapl_cntr_mask = RAPL_IDX_CLN; |
711 | rapl_pmu_events_group.attrs = rapl_events_cln_attr; | |
712 | break; | |
64552396 | 713 | case 63: /* Haswell-Server */ |
7b0fd569 | 714 | case 79: /* Broadwell-Server */ |
7a869805 | 715 | apply_quirk = true; |
64552396 JP |
716 | rapl_cntr_mask = RAPL_IDX_SRV; |
717 | rapl_pmu_events_group.attrs = rapl_events_srv_attr; | |
718 | break; | |
e69af465 VW |
719 | case 60: /* Haswell */ |
720 | case 69: /* Haswell-Celeron */ | |
e1089602 | 721 | case 70: /* Haswell GT3e */ |
44b11fee | 722 | case 61: /* Broadwell */ |
7b0fd569 | 723 | case 71: /* Broadwell-H */ |
e69af465 VW |
724 | rapl_cntr_mask = RAPL_IDX_HSW; |
725 | rapl_pmu_events_group.attrs = rapl_events_hsw_attr; | |
726 | break; | |
4788e5b4 SE |
727 | case 45: /* Sandy Bridge-EP */ |
728 | case 62: /* IvyTown */ | |
729 | rapl_cntr_mask = RAPL_IDX_SRV; | |
730 | rapl_pmu_events_group.attrs = rapl_events_srv_attr; | |
731 | break; | |
3a2a7797 | 732 | case 87: /* Knights Landing */ |
7a869805 | 733 | apply_quirk = true; |
3a2a7797 DC |
734 | rapl_cntr_mask = RAPL_IDX_KNL; |
735 | rapl_pmu_events_group.attrs = rapl_events_knl_attr; | |
4d120c53 | 736 | break; |
4788e5b4 | 737 | default: |
55f2890f | 738 | return -ENODEV; |
4788e5b4 | 739 | } |
55f2890f | 740 | |
7a869805 | 741 | ret = rapl_check_hw_unit(apply_quirk); |
64552396 JP |
742 | if (ret) |
743 | return ret; | |
fd537e56 | 744 | |
9de8d686 TG |
745 | ret = init_rapl_pmus(); |
746 | if (ret) | |
747 | return ret; | |
748 | ||
fd537e56 | 749 | cpu_notifier_register_begin(); |
4788e5b4 | 750 | |
7162b8fe TG |
751 | ret = rapl_prepare_cpus(); |
752 | if (ret) | |
753 | goto out; | |
4788e5b4 | 754 | |
9de8d686 | 755 | ret = perf_pmu_register(&rapl_pmus->pmu, "power", -1); |
512089d9 | 756 | if (ret) |
55f2890f | 757 | goto out; |
4788e5b4 | 758 | |
55f2890f | 759 | __perf_cpu_notifier(rapl_cpu_notifier); |
75c7003f | 760 | cpu_notifier_register_done(); |
512089d9 | 761 | rapl_advertise(); |
4788e5b4 | 762 | return 0; |
55f2890f TG |
763 | |
764 | out: | |
512089d9 | 765 | pr_warn("Initialization failed (%d), disabled\n", ret); |
55f2890f TG |
766 | cleanup_rapl_pmus(); |
767 | cpu_notifier_register_done(); | |
768 | return ret; | |
4788e5b4 SE |
769 | } |
770 | device_initcall(rapl_pmu_init); |