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perf/core: Add perf_sample_save_brstack() helper
[linux-block.git] / arch / x86 / events / intel / ds.c
CommitLineData
b2441318 1// SPDX-License-Identifier: GPL-2.0
de0428a7
KW		 2#include <linux/bitops.h>
3#include <linux/types.h>
4#include <linux/slab.h>
ca037701 5
c1961a46 6#include <asm/cpu_entry_area.h>
de0428a7 7#include <asm/perf_event.h>
42f3bdc5 8#include <asm/tlbflush.h>
3e702ff6 9#include <asm/insn.h>
59e9f587 10#include <asm/io.h>
de0428a7 11
27f6d22b 12#include "../perf_event.h"
ca037701 13
10043e02
TG		 14/* Waste a full page so it can be mapped into the cpu_entry_area */
15DEFINE_PER_CPU_PAGE_ALIGNED(struct debug_store, cpu_debug_store);
16
ca037701
PZ		 17/* The size of a BTS record in bytes: */
18#define BTS_RECORD_SIZE 24
19
9536c8d2 20#define PEBS_FIXUP_SIZE PAGE_SIZE
ca037701
PZ		 21
22/*
23 * pebs_record_32 for p4 and core not supported
24
25struct pebs_record_32 {
26 u32 flags, ip;
27 u32 ax, bc, cx, dx;
28 u32 si, di, bp, sp;
29};
30
31 */
32
f20093ee
SE		 33union intel_x86_pebs_dse {
34 u64 val;
35 struct {
36 unsigned int ld_dse:4;
37 unsigned int ld_stlb_miss:1;
38 unsigned int ld_locked:1;
61b985e3
KL		 39 unsigned int ld_data_blk:1;
40 unsigned int ld_addr_blk:1;
41 unsigned int ld_reserved:24;
f20093ee
SE		 42 };
43 struct {
44 unsigned int st_l1d_hit:1;
45 unsigned int st_reserved1:3;
46 unsigned int st_stlb_miss:1;
47 unsigned int st_locked:1;
48 unsigned int st_reserved2:26;
49 };
61b985e3
KL		 50 struct {
51 unsigned int st_lat_dse:4;
52 unsigned int st_lat_stlb_miss:1;
53 unsigned int st_lat_locked:1;
54 unsigned int ld_reserved3:26;
55 };
38aaf921
KL		 56 struct {
57 unsigned int mtl_dse:5;
58 unsigned int mtl_locked:1;
59 unsigned int mtl_stlb_miss:1;
60 unsigned int mtl_fwd_blk:1;
61 unsigned int ld_reserved4:24;
62 };
f20093ee
SE		 63};
64
65
66/*
67 * Map PEBS Load Latency Data Source encodings to generic
68 * memory data source information
69 */
70#define P(a, b) PERF_MEM_S(a, b)
71#define OP_LH (P(OP, LOAD) | P(LVL, HIT))
6ae5fa61
AK		 72#define LEVEL(x) P(LVLNUM, x)
73#define REM P(REMOTE, REMOTE)
f20093ee
SE		 74#define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
75
e17dc653
AK		 76/* Version for Sandy Bridge and later */
77static u64 pebs_data_source[] = {
6ae5fa61
AK		 78 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
79 OP_LH | P(LVL, L1) | LEVEL(L1) | P(SNOOP, NONE), /* 0x01: L1 local */
80 OP_LH | P(LVL, LFB) | LEVEL(LFB) | P(SNOOP, NONE), /* 0x02: LFB hit */
81 OP_LH | P(LVL, L2) | LEVEL(L2) | P(SNOOP, NONE), /* 0x03: L2 hit */
82 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
83 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
84 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
85 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
86 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
87 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
88 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, HIT), /* 0x0a: L3 miss, shared */
89 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
90 OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | SNOOP_NONE_MISS, /* 0x0c: L3 miss, excl */
91 OP_LH | P(LVL, REM_RAM1) | LEVEL(RAM) | REM | SNOOP_NONE_MISS, /* 0x0d: L3 miss, excl */
92 OP_LH | P(LVL, IO) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0e: I/O */
93 OP_LH | P(LVL, UNC) | LEVEL(NA) | P(SNOOP, NONE), /* 0x0f: uncached */
f20093ee
SE		 94};
95
e17dc653
AK		 96/* Patch up minor differences in the bits */
97void __init intel_pmu_pebs_data_source_nhm(void)
98{
6ae5fa61
AK		 99 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
100 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
101 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
102}
103
ccf170e9 104static void __init __intel_pmu_pebs_data_source_skl(bool pmem, u64 *data_source)
6ae5fa61
AK		 105{
106 u64 pmem_or_l4 = pmem ? LEVEL(PMEM) : LEVEL(L4);
107
ccf170e9
KL		 108 data_source[0x08] = OP_LH | pmem_or_l4 | P(SNOOP, HIT);
109 data_source[0x09] = OP_LH | pmem_or_l4 | REM | P(SNOOP, HIT);
110 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
111 data_source[0x0c] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOPX, FWD);
112 data_source[0x0d] = OP_LH | LEVEL(ANY_CACHE) | REM | P(SNOOP, HITM);
113}
114
115void __init intel_pmu_pebs_data_source_skl(bool pmem)
116{
117 __intel_pmu_pebs_data_source_skl(pmem, pebs_data_source);
118}
119
24919fde 120static void __init __intel_pmu_pebs_data_source_grt(u64 *data_source)
ccf170e9
KL		 121{
122 data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT);
123 data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
124 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
125}
126
24919fde
KL		 127void __init intel_pmu_pebs_data_source_grt(void)
128{
129 __intel_pmu_pebs_data_source_grt(pebs_data_source);
130}
131
ccf170e9
KL		 132void __init intel_pmu_pebs_data_source_adl(void)
133{
134 u64 *data_source;
135
136 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
137 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
138 __intel_pmu_pebs_data_source_skl(false, data_source);
139
140 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
141 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
24919fde 142 __intel_pmu_pebs_data_source_grt(data_source);
e17dc653
AK		 143}
144
38aaf921
KL		 145static void __init intel_pmu_pebs_data_source_cmt(u64 *data_source)
146{
147 data_source[0x07] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOPX, FWD);
148 data_source[0x08] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM);
149 data_source[0x0a] = OP_LH | P(LVL, LOC_RAM) | LEVEL(RAM) | P(SNOOP, NONE);
150 data_source[0x0b] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, NONE);
151 data_source[0x0c] = OP_LH | LEVEL(RAM) | REM | P(SNOOPX, FWD);
152 data_source[0x0d] = OP_LH | LEVEL(RAM) | REM | P(SNOOP, HITM);
153}
154
155void __init intel_pmu_pebs_data_source_mtl(void)
156{
157 u64 *data_source;
158
159 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_CORE_IDX].pebs_data_source;
160 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
161 __intel_pmu_pebs_data_source_skl(false, data_source);
162
163 data_source = x86_pmu.hybrid_pmu[X86_HYBRID_PMU_ATOM_IDX].pebs_data_source;
164 memcpy(data_source, pebs_data_source, sizeof(pebs_data_source));
165 intel_pmu_pebs_data_source_cmt(data_source);
166}
167
9ad64c0f
SE		 168static u64 precise_store_data(u64 status)
169{
170 union intel_x86_pebs_dse dse;
171 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
172
173 dse.val = status;
174
175 /*
176 * bit 4: TLB access
177 * 1 = stored missed 2nd level TLB
178 *
179 * so it either hit the walker or the OS
180 * otherwise hit 2nd level TLB
181 */
182 if (dse.st_stlb_miss)
183 val |= P(TLB, MISS);
184 else
185 val |= P(TLB, HIT);
186
187 /*
188 * bit 0: hit L1 data cache
189 * if not set, then all we know is that
190 * it missed L1D
191 */
192 if (dse.st_l1d_hit)
193 val |= P(LVL, HIT);
194 else
195 val |= P(LVL, MISS);
196
197 /*
198 * bit 5: Locked prefix
199 */
200 if (dse.st_locked)
201 val |= P(LOCK, LOCKED);
202
203 return val;
204}
205
c8aab2e0 206static u64 precise_datala_hsw(struct perf_event *event, u64 status)
f9134f36
AK		 207{
208 union perf_mem_data_src dse;
209
770eee1f
SE		 210 dse.val = PERF_MEM_NA;
211
212 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
213 dse.mem_op = PERF_MEM_OP_STORE;
214 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
215 dse.mem_op = PERF_MEM_OP_LOAD;
722e76e6
SE		 216
217 /*
218 * L1 info only valid for following events:
219 *
220 * MEM_UOPS_RETIRED.STLB_MISS_STORES
221 * MEM_UOPS_RETIRED.LOCK_STORES
222 * MEM_UOPS_RETIRED.SPLIT_STORES
223 * MEM_UOPS_RETIRED.ALL_STORES
224 */
c8aab2e0
SE		 225 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
226 if (status & 1)
227 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
228 else
229 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
230 }
f9134f36
AK		 231 return dse.val;
232}
233
39a41278
KL		 234static inline void pebs_set_tlb_lock(u64 *val, bool tlb, bool lock)
235{
236 /*
237 * TLB access
238 * 0 = did not miss 2nd level TLB
239 * 1 = missed 2nd level TLB
240 */
241 if (tlb)
242 *val |= P(TLB, MISS) | P(TLB, L2);
243 else
244 *val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
245
246 /* locked prefix */
247 if (lock)
248 *val |= P(LOCK, LOCKED);
249}
250
251/* Retrieve the latency data for e-core of ADL */
38aaf921
KL		 252static u64 __adl_latency_data_small(struct perf_event *event, u64 status,
253 u8 dse, bool tlb, bool lock, bool blk)
39a41278 254{
39a41278
KL		 255 u64 val;
256
257 WARN_ON_ONCE(hybrid_pmu(event->pmu)->cpu_type == hybrid_big);
258
38aaf921
KL		 259 dse &= PERF_PEBS_DATA_SOURCE_MASK;
260 val = hybrid_var(event->pmu, pebs_data_source)[dse];
39a41278 261
38aaf921 262 pebs_set_tlb_lock(&val, tlb, lock);
39a41278 263
38aaf921 264 if (blk)
39a41278
KL		 265 val |= P(BLK, DATA);
266 else
267 val |= P(BLK, NA);
268
269 return val;
270}
271
38aaf921
KL		 272u64 adl_latency_data_small(struct perf_event *event, u64 status)
273{
274 union intel_x86_pebs_dse dse;
275
276 dse.val = status;
277
278 return __adl_latency_data_small(event, status, dse.ld_dse,
279 dse.ld_locked, dse.ld_stlb_miss,
280 dse.ld_data_blk);
281}
282
283/* Retrieve the latency data for e-core of MTL */
284u64 mtl_latency_data_small(struct perf_event *event, u64 status)
285{
286 union intel_x86_pebs_dse dse;
287
288 dse.val = status;
289
290 return __adl_latency_data_small(event, status, dse.mtl_dse,
291 dse.mtl_stlb_miss, dse.mtl_locked,
292 dse.mtl_fwd_blk);
293}
294
ccf170e9 295static u64 load_latency_data(struct perf_event *event, u64 status)
f20093ee
SE		 296{
297 union intel_x86_pebs_dse dse;
298 u64 val;
f20093ee
SE		 299
300 dse.val = status;
301
302 /*
303 * use the mapping table for bit 0-3
304 */
ccf170e9 305 val = hybrid_var(event->pmu, pebs_data_source)[dse.ld_dse];
f20093ee
SE		 306
307 /*
308 * Nehalem models do not support TLB, Lock infos
309 */
95298355 310 if (x86_pmu.pebs_no_tlb) {
f20093ee
SE		 311 val |= P(TLB, NA) | P(LOCK, NA);
312 return val;
313 }
f20093ee 314
39a41278 315 pebs_set_tlb_lock(&val, dse.ld_stlb_miss, dse.ld_locked);
f20093ee 316
61b985e3
KL		 317 /*
318 * Ice Lake and earlier models do not support block infos.
319 */
320 if (!x86_pmu.pebs_block) {
321 val |= P(BLK, NA);
322 return val;
323 }
324 /*
325 * bit 6: load was blocked since its data could not be forwarded
326 * from a preceding store
327 */
328 if (dse.ld_data_blk)
329 val |= P(BLK, DATA);
330
331 /*
332 * bit 7: load was blocked due to potential address conflict with
333 * a preceding store
334 */
335 if (dse.ld_addr_blk)
336 val |= P(BLK, ADDR);
337
338 if (!dse.ld_data_blk && !dse.ld_addr_blk)
339 val |= P(BLK, NA);
340
341 return val;
342}
343
ccf170e9 344static u64 store_latency_data(struct perf_event *event, u64 status)
61b985e3
KL		 345{
346 union intel_x86_pebs_dse dse;
d4bdb0be 347 union perf_mem_data_src src;
61b985e3
KL		 348 u64 val;
349
350 dse.val = status;
351
352 /*
353 * use the mapping table for bit 0-3
354 */
ccf170e9 355 val = hybrid_var(event->pmu, pebs_data_source)[dse.st_lat_dse];
61b985e3 356
39a41278 357 pebs_set_tlb_lock(&val, dse.st_lat_stlb_miss, dse.st_lat_locked);
61b985e3
KL		 358
359 val |= P(BLK, NA);
360
d4bdb0be
SE		 361 /*
362 * the pebs_data_source table is only for loads
363 * so override the mem_op to say STORE instead
364 */
365 src.val = val;
366 src.mem_op = P(OP,STORE);
367
368 return src.val;
f20093ee
SE		 369}
370
ca037701
PZ		 371struct pebs_record_core {
372 u64 flags, ip;
373 u64 ax, bx, cx, dx;
374 u64 si, di, bp, sp;
375 u64 r8, r9, r10, r11;
376 u64 r12, r13, r14, r15;
377};
378
379struct pebs_record_nhm {
380 u64 flags, ip;
381 u64 ax, bx, cx, dx;
382 u64 si, di, bp, sp;
383 u64 r8, r9, r10, r11;
384 u64 r12, r13, r14, r15;
385 u64 status, dla, dse, lat;
386};
387
130768b8
AK		 388/*
389 * Same as pebs_record_nhm, with two additional fields.
390 */
391struct pebs_record_hsw {
748e86aa
AK		 392 u64 flags, ip;
393 u64 ax, bx, cx, dx;
394 u64 si, di, bp, sp;
395 u64 r8, r9, r10, r11;
396 u64 r12, r13, r14, r15;
397 u64 status, dla, dse, lat;
d2beea4a 398 u64 real_ip, tsx_tuning;
748e86aa
AK		 399};
400
401union hsw_tsx_tuning {
402 struct {
403 u32 cycles_last_block : 32,
404 hle_abort : 1,
405 rtm_abort : 1,
406 instruction_abort : 1,
407 non_instruction_abort : 1,
408 retry : 1,
409 data_conflict : 1,
410 capacity_writes : 1,
411 capacity_reads : 1;
412 };
413 u64 value;
130768b8
AK		 414};
415
a405bad5
AK		 416#define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
417
2f7ebf2e
AK		 418/* Same as HSW, plus TSC */
419
420struct pebs_record_skl {
421 u64 flags, ip;
422 u64 ax, bx, cx, dx;
423 u64 si, di, bp, sp;
424 u64 r8, r9, r10, r11;
425 u64 r12, r13, r14, r15;
426 u64 status, dla, dse, lat;
427 u64 real_ip, tsx_tuning;
428 u64 tsc;
429};
430
de0428a7 431void init_debug_store_on_cpu(int cpu)
ca037701
PZ		 432{
433 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
434
435 if (!ds)
436 return;
437
438 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
439 (u32)((u64)(unsigned long)ds),
440 (u32)((u64)(unsigned long)ds >> 32));
441}
442
de0428a7 443void fini_debug_store_on_cpu(int cpu)
ca037701
PZ		 444{
445 if (!per_cpu(cpu_hw_events, cpu).ds)
446 return;
447
448 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
449}
450
9536c8d2
PZ		 451static DEFINE_PER_CPU(void *, insn_buffer);
452
c1961a46 453static void ds_update_cea(void *cea, void *addr, size_t size, pgprot_t prot)
5ee25c87 454{
42f3bdc5 455 unsigned long start = (unsigned long)cea;
c1961a46
HD		 456 phys_addr_t pa;
457 size_t msz = 0;
458
459 pa = virt_to_phys(addr);
42f3bdc5
PZ		 460
461 preempt_disable();
c1961a46
HD		 462 for (; msz < size; msz += PAGE_SIZE, pa += PAGE_SIZE, cea += PAGE_SIZE)
463 cea_set_pte(cea, pa, prot);
42f3bdc5
PZ		 464
465 /*
466 * This is a cross-CPU update of the cpu_entry_area, we must shoot down
467 * all TLB entries for it.
468 */
469 flush_tlb_kernel_range(start, start + size);
470 preempt_enable();
c1961a46
HD		 471}
472
473static void ds_clear_cea(void *cea, size_t size)
474{
42f3bdc5 475 unsigned long start = (unsigned long)cea;
c1961a46
HD		 476 size_t msz = 0;
477
42f3bdc5 478 preempt_disable();
c1961a46
HD		 479 for (; msz < size; msz += PAGE_SIZE, cea += PAGE_SIZE)
480 cea_set_pte(cea, 0, PAGE_NONE);
42f3bdc5
PZ		 481
482 flush_tlb_kernel_range(start, start + size);
483 preempt_enable();
c1961a46
HD		 484}
485
486static void *dsalloc_pages(size_t size, gfp_t flags, int cpu)
487{
488 unsigned int order = get_order(size);
96681fc3 489 int node = cpu_to_node(cpu);
c1961a46
HD		 490 struct page *page;
491
492 page = __alloc_pages_node(node, flags | __GFP_ZERO, order);
493 return page ? page_address(page) : NULL;
494}
495
496static void dsfree_pages(const void *buffer, size_t size)
497{
498 if (buffer)
499 free_pages((unsigned long)buffer, get_order(size));
500}
501
502static int alloc_pebs_buffer(int cpu)
503{
504 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
505 struct debug_store *ds = hwev->ds;
506 size_t bsiz = x86_pmu.pebs_buffer_size;
507 int max, node = cpu_to_node(cpu);
1fc654cf 508 void *buffer, *insn_buff, *cea;
5ee25c87
PZ		 509
510 if (!x86_pmu.pebs)
511 return 0;
512
c1961a46 513 buffer = dsalloc_pages(bsiz, GFP_KERNEL, cpu);
5ee25c87
PZ		 514 if (unlikely(!buffer))
515 return -ENOMEM;
516
9536c8d2
PZ		 517 /*
518 * HSW+ already provides us the eventing ip; no need to allocate this
519 * buffer then.
520 */
521 if (x86_pmu.intel_cap.pebs_format < 2) {
1fc654cf
IM		 522 insn_buff = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
523 if (!insn_buff) {
c1961a46 524 dsfree_pages(buffer, bsiz);
9536c8d2
PZ		 525 return -ENOMEM;
526 }
1fc654cf 527 per_cpu(insn_buffer, cpu) = insn_buff;
9536c8d2 528 }
c1961a46
HD		 529 hwev->ds_pebs_vaddr = buffer;
530 /* Update the cpu entry area mapping */
531 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
532 ds->pebs_buffer_base = (unsigned long) cea;
533 ds_update_cea(cea, buffer, bsiz, PAGE_KERNEL);
5ee25c87 534 ds->pebs_index = ds->pebs_buffer_base;
c1961a46
HD		 535 max = x86_pmu.pebs_record_size * (bsiz / x86_pmu.pebs_record_size);
536 ds->pebs_absolute_maximum = ds->pebs_buffer_base + max;
5ee25c87
PZ		 537 return 0;
538}
539
b39f88ac
PZ		 540static void release_pebs_buffer(int cpu)
541{
c1961a46 542 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
c1961a46 543 void *cea;
b39f88ac 544
efe951d3 545 if (!x86_pmu.pebs)
b39f88ac
PZ		 546 return;
547
9536c8d2
PZ		 548 kfree(per_cpu(insn_buffer, cpu));
549 per_cpu(insn_buffer, cpu) = NULL;
550
c1961a46
HD		 551 /* Clear the fixmap */
552 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.pebs_buffer;
553 ds_clear_cea(cea, x86_pmu.pebs_buffer_size);
c1961a46
HD		 554 dsfree_pages(hwev->ds_pebs_vaddr, x86_pmu.pebs_buffer_size);
555 hwev->ds_pebs_vaddr = NULL;
b39f88ac
PZ		 556}
557
5ee25c87
PZ		 558static int alloc_bts_buffer(int cpu)
559{
c1961a46
HD		 560 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
561 struct debug_store *ds = hwev->ds;
562 void *buffer, *cea;
563 int max;
5ee25c87
PZ		 564
565 if (!x86_pmu.bts)
566 return 0;
567
c1961a46 568 buffer = dsalloc_pages(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, cpu);
44851541
DR		 569 if (unlikely(!buffer)) {
570 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
5ee25c87 571 return -ENOMEM;
44851541 572 }
c1961a46
HD		 573 hwev->ds_bts_vaddr = buffer;
574 /* Update the fixmap */
575 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
576 ds->bts_buffer_base = (unsigned long) cea;
577 ds_update_cea(cea, buffer, BTS_BUFFER_SIZE, PAGE_KERNEL);
5ee25c87 578 ds->bts_index = ds->bts_buffer_base;
2c991e40
HD		 579 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
580 ds->bts_absolute_maximum = ds->bts_buffer_base +
581 max * BTS_RECORD_SIZE;
582 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
583 (max / 16) * BTS_RECORD_SIZE;
5ee25c87
PZ		 584 return 0;
585}
586
b39f88ac
PZ		 587static void release_bts_buffer(int cpu)
588{
c1961a46 589 struct cpu_hw_events *hwev = per_cpu_ptr(&cpu_hw_events, cpu);
c1961a46 590 void *cea;
b39f88ac 591
efe951d3 592 if (!x86_pmu.bts)
b39f88ac
PZ		 593 return;
594
c1961a46
HD		 595 /* Clear the fixmap */
596 cea = &get_cpu_entry_area(cpu)->cpu_debug_buffers.bts_buffer;
597 ds_clear_cea(cea, BTS_BUFFER_SIZE);
c1961a46
HD		 598 dsfree_pages(hwev->ds_bts_vaddr, BTS_BUFFER_SIZE);
599 hwev->ds_bts_vaddr = NULL;
b39f88ac
PZ		 600}
601
65af94ba
PZ		 602static int alloc_ds_buffer(int cpu)
603{
c1961a46 604 struct debug_store *ds = &get_cpu_entry_area(cpu)->cpu_debug_store;
65af94ba 605
c1961a46 606 memset(ds, 0, sizeof(*ds));
65af94ba 607 per_cpu(cpu_hw_events, cpu).ds = ds;
65af94ba
PZ		 608 return 0;
609}
610
611static void release_ds_buffer(int cpu)
612{
65af94ba 613 per_cpu(cpu_hw_events, cpu).ds = NULL;
65af94ba
PZ		 614}
615
de0428a7 616void release_ds_buffers(void)
ca037701
PZ		 617{
618 int cpu;
619
620 if (!x86_pmu.bts && !x86_pmu.pebs)
621 return;
622
efe951d3
PZ		 623 for_each_possible_cpu(cpu)
624 release_ds_buffer(cpu);
625
626 for_each_possible_cpu(cpu) {
627 /*
628 * Again, ignore errors from offline CPUs, they will no longer
629 * observe cpu_hw_events.ds and not program the DS_AREA when
630 * they come up.
631 */
ca037701 632 fini_debug_store_on_cpu(cpu);
efe951d3 633 }
ca037701
PZ		 634
635 for_each_possible_cpu(cpu) {
b39f88ac
PZ		 636 release_pebs_buffer(cpu);
637 release_bts_buffer(cpu);
ca037701 638 }
ca037701
PZ		 639}
640
de0428a7 641void reserve_ds_buffers(void)
ca037701 642{
6809b6ea
PZ		 643 int bts_err = 0, pebs_err = 0;
644 int cpu;
645
646 x86_pmu.bts_active = 0;
647 x86_pmu.pebs_active = 0;
ca037701
PZ		 648
649 if (!x86_pmu.bts && !x86_pmu.pebs)
f80c9e30 650 return;
ca037701 651
6809b6ea
PZ		 652 if (!x86_pmu.bts)
653 bts_err = 1;
654
655 if (!x86_pmu.pebs)
656 pebs_err = 1;
657
ca037701 658 for_each_possible_cpu(cpu) {
6809b6ea
PZ		 659 if (alloc_ds_buffer(cpu)) {
660 bts_err = 1;
661 pebs_err = 1;
662 }
ca037701 663
6809b6ea
PZ		 664 if (!bts_err && alloc_bts_buffer(cpu))
665 bts_err = 1;
666
667 if (!pebs_err && alloc_pebs_buffer(cpu))
668 pebs_err = 1;
5ee25c87 669
6809b6ea 670 if (bts_err && pebs_err)
5ee25c87 671 break;
6809b6ea
PZ		 672 }
673
674 if (bts_err) {
675 for_each_possible_cpu(cpu)
676 release_bts_buffer(cpu);
677 }
ca037701 678
6809b6ea
PZ		 679 if (pebs_err) {
680 for_each_possible_cpu(cpu)
681 release_pebs_buffer(cpu);
ca037701
PZ		 682 }
683
6809b6ea
PZ		 684 if (bts_err && pebs_err) {
685 for_each_possible_cpu(cpu)
686 release_ds_buffer(cpu);
687 } else {
688 if (x86_pmu.bts && !bts_err)
689 x86_pmu.bts_active = 1;
690
691 if (x86_pmu.pebs && !pebs_err)
692 x86_pmu.pebs_active = 1;
693
efe951d3
PZ		 694 for_each_possible_cpu(cpu) {
695 /*
696 * Ignores wrmsr_on_cpu() errors for offline CPUs they
697 * will get this call through intel_pmu_cpu_starting().
698 */
ca037701 699 init_debug_store_on_cpu(cpu);
efe951d3 700 }
ca037701 701 }
ca037701
PZ		 702}
703
704/*
705 * BTS
706 */
707
de0428a7 708struct event_constraint bts_constraint =
15c7ad51 709 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
ca037701 710
de0428a7 711void intel_pmu_enable_bts(u64 config)
ca037701
PZ		 712{
713 unsigned long debugctlmsr;
714
715 debugctlmsr = get_debugctlmsr();
716
7c5ecaf7
PZ		 717 debugctlmsr |= DEBUGCTLMSR_TR;
718 debugctlmsr |= DEBUGCTLMSR_BTS;
8062382c
AS		 719 if (config & ARCH_PERFMON_EVENTSEL_INT)
720 debugctlmsr |= DEBUGCTLMSR_BTINT;
ca037701
PZ		 721
722 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
7c5ecaf7 723 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
ca037701
PZ		 724
725 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
7c5ecaf7 726 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
ca037701
PZ		 727
728 update_debugctlmsr(debugctlmsr);
729}
730
de0428a7 731void intel_pmu_disable_bts(void)
ca037701 732{
89cbc767 733 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
ca037701
PZ		 734 unsigned long debugctlmsr;
735
736 if (!cpuc->ds)
737 return;
738
739 debugctlmsr = get_debugctlmsr();
740
741 debugctlmsr &=
7c5ecaf7
PZ		 742 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
743 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
ca037701
PZ		 744
745 update_debugctlmsr(debugctlmsr);
746}
747
de0428a7 748int intel_pmu_drain_bts_buffer(void)
ca037701 749{
89cbc767 750 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
ca037701
PZ		 751 struct debug_store *ds = cpuc->ds;
752 struct bts_record {
753 u64 from;
754 u64 to;
755 u64 flags;
756 };
15c7ad51 757 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
a09d31f4 758 struct bts_record *at, *base, *top;
ca037701
PZ		 759 struct perf_output_handle handle;
760 struct perf_event_header header;
761 struct perf_sample_data data;
a09d31f4 762 unsigned long skip = 0;
ca037701
PZ		 763 struct pt_regs regs;
764
765 if (!event)
b0b2072d 766 return 0;
ca037701 767
6809b6ea 768 if (!x86_pmu.bts_active)
b0b2072d 769 return 0;
ca037701 770
a09d31f4
AS		 771 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
772 top = (struct bts_record *)(unsigned long)ds->bts_index;
ca037701 773
a09d31f4 774 if (top <= base)
b0b2072d 775 return 0;
ca037701 776
0e48026a
SE		 777 memset(&regs, 0, sizeof(regs));
778
ca037701
PZ		 779 ds->bts_index = ds->bts_buffer_base;
780
fd0d000b 781 perf_sample_data_init(&data, 0, event->hw.last_period);
ca037701 782
a09d31f4
AS		 783 /*
784 * BTS leaks kernel addresses in branches across the cpl boundary,
785 * such as traps or system calls, so unless the user is asking for
786 * kernel tracing (and right now it's not possible), we'd need to
787 * filter them out. But first we need to count how many of those we
788 * have in the current batch. This is an extra O(n) pass, however,
789 * it's much faster than the other one especially considering that
790 * n <= 2560 (BTS_BUFFER_SIZE / BTS_RECORD_SIZE * 15/16; see the
791 * alloc_bts_buffer()).
792 */
793 for (at = base; at < top; at++) {
794 /*
795 * Note that right now *this* BTS code only works if
796 * attr::exclude_kernel is set, but let's keep this extra
797 * check here in case that changes.
798 */
799 if (event->attr.exclude_kernel &&
800 (kernel_ip(at->from) || kernel_ip(at->to)))
801 skip++;
802 }
803
ca037701
PZ		 804 /*
805 * Prepare a generic sample, i.e. fill in the invariant fields.
806 * We will overwrite the from and to address before we output
807 * the sample.
808 */
e8d8a90f 809 rcu_read_lock();
ca037701
PZ		 810 perf_prepare_sample(&header, &data, event, &regs);
811
267fb273
PZ		 812 if (perf_output_begin(&handle, &data, event,
813 header.size * (top - base - skip)))
e8d8a90f 814 goto unlock;
ca037701 815
a09d31f4
AS		 816 for (at = base; at < top; at++) {
817 /* Filter out any records that contain kernel addresses. */
818 if (event->attr.exclude_kernel &&
819 (kernel_ip(at->from) || kernel_ip(at->to)))
820 continue;
821
ca037701
PZ		 822 data.ip = at->from;
823 data.addr = at->to;
824
825 perf_output_sample(&handle, &header, &data, event);
826 }
827
828 perf_output_end(&handle);
829
830 /* There's new data available. */
831 event->hw.interrupts++;
832 event->pending_kill = POLL_IN;
e8d8a90f
PZ		 833unlock:
834 rcu_read_unlock();
b0b2072d 835 return 1;
ca037701
PZ		 836}
837
9c964efa
YZ		 838static inline void intel_pmu_drain_pebs_buffer(void)
839{
9dfa9a5c
PZ		 840 struct perf_sample_data data;
841
842 x86_pmu.drain_pebs(NULL, &data);
9c964efa
YZ		 843}
844
ca037701
PZ		 845/*
846 * PEBS
847 */
de0428a7 848struct event_constraint intel_core2_pebs_event_constraints[] = {
af4bdcf6
AK		 849 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
850 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1), /* X87_OPS_RETIRED.ANY */
851 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* BR_INST_RETIRED.MISPRED */
852 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1), /* SIMD_INST_RETURED.ANY */
853 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
517e6341 854 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
23e3983a 855 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
ca037701
PZ		 856 EVENT_CONSTRAINT_END
857};
858
de0428a7 859struct event_constraint intel_atom_pebs_event_constraints[] = {
af4bdcf6
AK		 860 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1), /* INST_RETIRED.ANY */
861 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1), /* MISPREDICTED_BRANCH_RETIRED */
862 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED.* */
517e6341 863 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
23e3983a 864 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x01),
673d188b
SE		 865 /* Allow all events as PEBS with no flags */
866 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
17e31629
SE		 867 EVENT_CONSTRAINT_END
868};
869
1fa64180 870struct event_constraint intel_slm_pebs_event_constraints[] = {
33636732 871 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
23e3983a 872 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x1),
86a04461
AK		 873 /* Allow all events as PEBS with no flags */
874 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
1fa64180
YZ		 875 EVENT_CONSTRAINT_END
876};
877
8b92c3a7
KL		 878struct event_constraint intel_glm_pebs_event_constraints[] = {
879 /* Allow all events as PEBS with no flags */
880 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
881 EVENT_CONSTRAINT_END
882};
883
f83d2f91
KL		 884struct event_constraint intel_grt_pebs_event_constraints[] = {
885 /* Allow all events as PEBS with no flags */
cde643ff 886 INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
39a41278 887 INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
f83d2f91
KL		 888 EVENT_CONSTRAINT_END
889};
890
de0428a7 891struct event_constraint intel_nehalem_pebs_event_constraints[] = {
f20093ee 892 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
af4bdcf6
AK		 893 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
894 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
895 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INST_RETIRED.ANY */
7d5d02da 896 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
af4bdcf6
AK		 897 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
898 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf), /* BR_MISP_RETIRED.NEAR_CALL */
899 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
900 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
901 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
902 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
517e6341 903 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
23e3983a 904 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
17e31629
SE		 905 EVENT_CONSTRAINT_END
906};
907
de0428a7 908struct event_constraint intel_westmere_pebs_event_constraints[] = {
f20093ee 909 INTEL_PLD_CONSTRAINT(0x100b, 0xf), /* MEM_INST_RETIRED.* */
af4bdcf6
AK		 910 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf), /* MEM_UNCORE_RETIRED.* */
911 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf), /* MEM_STORE_RETIRED.DTLB_MISS */
912 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf), /* INSTR_RETIRED.* */
7d5d02da 913 INTEL_EVENT_CONSTRAINT(0xc2, 0xf), /* UOPS_RETIRED.* */
af4bdcf6
AK		 914 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf), /* BR_INST_RETIRED.* */
915 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf), /* BR_MISP_RETIRED.* */
916 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf), /* SSEX_UOPS_RETIRED.* */
917 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf), /* ITLB_MISS_RETIRED */
918 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf), /* MEM_LOAD_RETIRED.* */
919 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf), /* FP_ASSIST.* */
517e6341 920 /* INST_RETIRED.ANY_P, inv=1, cmask=16 (cycles:p). */
23e3983a 921 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
ca037701
PZ		 922 EVENT_CONSTRAINT_END
923};
924
de0428a7 925struct event_constraint intel_snb_pebs_event_constraints[] = {
0dbc9479 926 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
f20093ee 927 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
9ad64c0f 928 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
86a04461 929 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
23e3983a 930 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
b63b4b45
MD		 931 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
932 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
933 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
934 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
86a04461
AK		 935 /* Allow all events as PEBS with no flags */
936 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
b06b3d49
LM		 937 EVENT_CONSTRAINT_END
938};
939
20a36e39 940struct event_constraint intel_ivb_pebs_event_constraints[] = {
0dbc9479 941 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
f20093ee 942 INTEL_PLD_CONSTRAINT(0x01cd, 0x8), /* MEM_TRANS_RETIRED.LAT_ABOVE_THR */
9ad64c0f 943 INTEL_PST_CONSTRAINT(0x02cd, 0x8), /* MEM_TRANS_RETIRED.PRECISE_STORES */
86a04461 944 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
23e3983a 945 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
72469764 946 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
23e3983a 947 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
b63b4b45
MD		 948 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOP_RETIRED.* */
949 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
950 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
951 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
86a04461
AK		 952 /* Allow all events as PEBS with no flags */
953 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
20a36e39
SE		 954 EVENT_CONSTRAINT_END
955};
956
3044318f 957struct event_constraint intel_hsw_pebs_event_constraints[] = {
0dbc9479 958 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
86a04461
AK		 959 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
960 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
23e3983a 961 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
72469764 962 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
23e3983a 963 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
86a04461 964 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
b63b4b45
MD		 965 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
966 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
967 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
968 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
969 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
970 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
971 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
972 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
973 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
974 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
9a92e16f
AK		 975 /* Allow all events as PEBS with no flags */
976 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
977 EVENT_CONSTRAINT_END
978};
979
b3e62463
SE		 980struct event_constraint intel_bdw_pebs_event_constraints[] = {
981 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PRECDIST */
982 INTEL_PLD_CONSTRAINT(0x01cd, 0xf), /* MEM_TRANS_RETIRED.* */
983 /* UOPS_RETIRED.ALL, inv=1, cmask=16 (cycles:p). */
23e3983a 984 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c2, 0xf),
b3e62463 985 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
23e3983a 986 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
b3e62463
SE		 987 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf), /* UOPS_RETIRED.ALL */
988 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_LOADS */
989 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_UOPS_RETIRED.LOCK_LOADS */
990 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_LOADS */
991 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_UOPS_RETIRED.ALL_LOADS */
992 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_UOPS_RETIRED.STLB_MISS_STORES */
993 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_UOPS_RETIRED.SPLIT_STORES */
994 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_UOPS_RETIRED.ALL_STORES */
995 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
996 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_UOPS_L3_HIT_RETIRED.* */
997 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_UOPS_L3_MISS_RETIRED.* */
998 /* Allow all events as PEBS with no flags */
999 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
1000 EVENT_CONSTRAINT_END
1001};
1002
1003
9a92e16f
AK		 1004struct event_constraint intel_skl_pebs_event_constraints[] = {
1005 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
72469764 1006 /* INST_RETIRED.PREC_DIST, inv=1, cmask=16 (cycles:ppp). */
23e3983a 1007 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108001c0, 0x2),
442f5c74 1008 /* INST_RETIRED.TOTAL_CYCLES_PS (inv=1, cmask=16) (cycles:p). */
23e3983a 1009 INTEL_FLAGS_UEVENT_CONSTRAINT(0x108000c0, 0x0f),
9a92e16f
AK		 1010 INTEL_PLD_CONSTRAINT(0x1cd, 0xf), /* MEM_TRANS_RETIRED.* */
1011 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1012 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1013 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1014 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf), /* MEM_INST_RETIRED.LOCK_STORES */
1015 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1016 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1017 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1018 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
1019 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
1020 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
1021 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf), /* MEM_LOAD_L3_MISS_RETIRED.* */
86a04461
AK		 1022 /* Allow all events as PEBS with no flags */
1023 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
3044318f
AK		 1024 EVENT_CONSTRAINT_END
1025};
1026
60176089 1027struct event_constraint intel_icl_pebs_event_constraints[] = {
2de71ee1
SE		 1028 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x100000000ULL), /* old INST_RETIRED.PREC_DIST */
1029 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
3d0c3953 1030 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL), /* SLOTS */
60176089
KL		 1031
1032 INTEL_PLD_CONSTRAINT(0x1cd, 0xff), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
acc5568b
KL		 1033 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1034 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1035 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1036 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1037 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1038 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1039 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
60176089
KL		 1040
1041 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf), /* MEM_LOAD_*_RETIRED.* */
1042
1043 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
1044
1045 /*
1046 * Everything else is handled by PMU_FL_PEBS_ALL, because we
1047 * need the full constraints from the main table.
1048 */
1049
1050 EVENT_CONSTRAINT_END
1051};
1052
61b985e3 1053struct event_constraint intel_spr_pebs_event_constraints[] = {
2de71ee1 1054 INTEL_FLAGS_UEVENT_CONSTRAINT(0x100, 0x100000000ULL), /* INST_RETIRED.PREC_DIST */
61b985e3
KL		 1055 INTEL_FLAGS_UEVENT_CONSTRAINT(0x0400, 0x800000000ULL),
1056
1057 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xfe),
1058 INTEL_PLD_CONSTRAINT(0x1cd, 0xfe),
1059 INTEL_PSD_CONSTRAINT(0x2cd, 0x1),
0916886b
KL		 1060 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_LOADS */
1061 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf), /* MEM_INST_RETIRED.STLB_MISS_STORES */
1062 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf), /* MEM_INST_RETIRED.LOCK_LOADS */
1063 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf), /* MEM_INST_RETIRED.SPLIT_LOADS */
1064 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf), /* MEM_INST_RETIRED.SPLIT_STORES */
1065 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf), /* MEM_INST_RETIRED.ALL_LOADS */
1066 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf), /* MEM_INST_RETIRED.ALL_STORES */
61b985e3
KL		 1067
1068 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(0xd1, 0xd4, 0xf),
1069
1070 INTEL_FLAGS_EVENT_CONSTRAINT(0xd0, 0xf),
1071
1072 /*
1073 * Everything else is handled by PMU_FL_PEBS_ALL, because we
1074 * need the full constraints from the main table.
1075 */
1076
1077 EVENT_CONSTRAINT_END
1078};
1079
de0428a7 1080struct event_constraint *intel_pebs_constraints(struct perf_event *event)
ca037701 1081{
24ee38ff 1082 struct event_constraint *pebs_constraints = hybrid(event->pmu, pebs_constraints);
ca037701
PZ		 1083 struct event_constraint *c;
1084
ab608344 1085 if (!event->attr.precise_ip)
ca037701
PZ		 1086 return NULL;
1087
24ee38ff
KL		 1088 if (pebs_constraints) {
1089 for_each_event_constraint(c, pebs_constraints) {
63b79f6e 1090 if (constraint_match(c, event->hw.config)) {
9fac2cf3 1091 event->hw.flags |= c->flags;
ca037701 1092 return c;
9fac2cf3 1093 }
ca037701
PZ		 1094 }
1095 }
1096
31962340
KL		 1097 /*
1098 * Extended PEBS support
1099 * Makes the PEBS code search the normal constraints.
1100 */
1101 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
1102 return NULL;
1103
ca037701
PZ		 1104 return &emptyconstraint;
1105}
1106
09e61b4f
PZ		 1107/*
1108 * We need the sched_task callback even for per-cpu events when we use
1109 * the large interrupt threshold, such that we can provide PID and TID
1110 * to PEBS samples.
1111 */
1112static inline bool pebs_needs_sched_cb(struct cpu_hw_events *cpuc)
1113{
42880f72
AS		 1114 if (cpuc->n_pebs == cpuc->n_pebs_via_pt)
1115 return false;
1116
09e61b4f
PZ		 1117 return cpuc->n_pebs && (cpuc->n_pebs == cpuc->n_large_pebs);
1118}
1119
bd275681 1120void intel_pmu_pebs_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in)
df6c3db8
JO		 1121{
1122 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1123
1124 if (!sched_in && pebs_needs_sched_cb(cpuc))
1125 intel_pmu_drain_pebs_buffer();
1126}
1127
09e61b4f
PZ		 1128static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
1129{
1130 struct debug_store *ds = cpuc->ds;
d4b294bf
KL		 1131 int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
1132 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
09e61b4f 1133 u64 threshold;
ec71a398
KL		 1134 int reserved;
1135
42880f72
AS		 1136 if (cpuc->n_pebs_via_pt)
1137 return;
1138
ec71a398 1139 if (x86_pmu.flags & PMU_FL_PEBS_ALL)
d4b294bf 1140 reserved = max_pebs_events + num_counters_fixed;
ec71a398 1141 else
d4b294bf 1142 reserved = max_pebs_events;
09e61b4f
PZ		 1143
1144 if (cpuc->n_pebs == cpuc->n_large_pebs) {
1145 threshold = ds->pebs_absolute_maximum -
c22497f5 1146 reserved * cpuc->pebs_record_size;
09e61b4f 1147 } else {
c22497f5 1148 threshold = ds->pebs_buffer_base + cpuc->pebs_record_size;
09e61b4f
PZ		 1149 }
1150
1151 ds->pebs_interrupt_threshold = threshold;
1152}
1153
c22497f5
KL		 1154static void adaptive_pebs_record_size_update(void)
1155{
1156 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1157 u64 pebs_data_cfg = cpuc->pebs_data_cfg;
1158 int sz = sizeof(struct pebs_basic);
1159
1160 if (pebs_data_cfg & PEBS_DATACFG_MEMINFO)
1161 sz += sizeof(struct pebs_meminfo);
1162 if (pebs_data_cfg & PEBS_DATACFG_GP)
1163 sz += sizeof(struct pebs_gprs);
1164 if (pebs_data_cfg & PEBS_DATACFG_XMMS)
1165 sz += sizeof(struct pebs_xmm);
1166 if (pebs_data_cfg & PEBS_DATACFG_LBRS)
5624986d 1167 sz += x86_pmu.lbr_nr * sizeof(struct lbr_entry);
c22497f5
KL		 1168
1169 cpuc->pebs_record_size = sz;
1170}
1171
1172#define PERF_PEBS_MEMINFO_TYPE (PERF_SAMPLE_ADDR | PERF_SAMPLE_DATA_SRC | \
2a6c6b7d
KL		 1173 PERF_SAMPLE_PHYS_ADDR | \
1174 PERF_SAMPLE_WEIGHT_TYPE | \
76a5433f
KL		 1175 PERF_SAMPLE_TRANSACTION | \
1176 PERF_SAMPLE_DATA_PAGE_SIZE)
c22497f5
KL		 1177
1178static u64 pebs_update_adaptive_cfg(struct perf_event *event)
1179{
1180 struct perf_event_attr *attr = &event->attr;
1181 u64 sample_type = attr->sample_type;
1182 u64 pebs_data_cfg = 0;
1183 bool gprs, tsx_weight;
1184
1185 if (!(sample_type & ~(PERF_SAMPLE_IP|PERF_SAMPLE_TIME)) &&
1186 attr->precise_ip > 1)
1187 return pebs_data_cfg;
1188
1189 if (sample_type & PERF_PEBS_MEMINFO_TYPE)
1190 pebs_data_cfg |= PEBS_DATACFG_MEMINFO;
1191
1192 /*
1193 * We need GPRs when:
1194 * + user requested them
1195 * + precise_ip < 2 for the non event IP
1196 * + For RTM TSX weight we need GPRs for the abort code.
1197 */
1198 gprs = (sample_type & PERF_SAMPLE_REGS_INTR) &&
1199 (attr->sample_regs_intr & PEBS_GP_REGS);
1200
2a6c6b7d 1201 tsx_weight = (sample_type & PERF_SAMPLE_WEIGHT_TYPE) &&
c22497f5
KL		 1202 ((attr->config & INTEL_ARCH_EVENT_MASK) ==
1203 x86_pmu.rtm_abort_event);
1204
1205 if (gprs || (attr->precise_ip < 2) || tsx_weight)
1206 pebs_data_cfg |= PEBS_DATACFG_GP;
1207
1208 if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
dce86ac7 1209 (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
c22497f5
KL		 1210 pebs_data_cfg |= PEBS_DATACFG_XMMS;
1211
1212 if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
1213 /*
1214 * For now always log all LBRs. Could configure this
1215 * later.
1216 */
1217 pebs_data_cfg |= PEBS_DATACFG_LBRS |
1218 ((x86_pmu.lbr_nr-1) << PEBS_DATACFG_LBR_SHIFT);
1219 }
1220
1221 return pebs_data_cfg;
1222}
1223
09e61b4f 1224static void
c22497f5
KL		 1225pebs_update_state(bool needed_cb, struct cpu_hw_events *cpuc,
1226 struct perf_event *event, bool add)
09e61b4f 1227{
bd275681 1228 struct pmu *pmu = event->pmu;
b6a32f02
JO		 1229 /*
1230 * Make sure we get updated with the first PEBS
1231 * event. It will trigger also during removal, but
1232 * that does not hurt:
1233 */
1234 bool update = cpuc->n_pebs == 1;
1235
09e61b4f
PZ		 1236 if (needed_cb != pebs_needs_sched_cb(cpuc)) {
1237 if (!needed_cb)
1238 perf_sched_cb_inc(pmu);
1239 else
1240 perf_sched_cb_dec(pmu);
1241
b6a32f02 1242 update = true;
09e61b4f 1243 }
b6a32f02 1244
c22497f5
KL		 1245 /*
1246 * The PEBS record doesn't shrink on pmu::del(). Doing so would require
1247 * iterating all remaining PEBS events to reconstruct the config.
1248 */
1249 if (x86_pmu.intel_cap.pebs_baseline && add) {
1250 u64 pebs_data_cfg;
1251
1252 /* Clear pebs_data_cfg and pebs_record_size for first PEBS. */
1253 if (cpuc->n_pebs == 1) {
1254 cpuc->pebs_data_cfg = 0;
1255 cpuc->pebs_record_size = sizeof(struct pebs_basic);
1256 }
1257
1258 pebs_data_cfg = pebs_update_adaptive_cfg(event);
1259
1260 /* Update pebs_record_size if new event requires more data. */
1261 if (pebs_data_cfg & ~cpuc->pebs_data_cfg) {
1262 cpuc->pebs_data_cfg |= pebs_data_cfg;
1263 adaptive_pebs_record_size_update();
1264 update = true;
1265 }
1266 }
1267
b6a32f02
JO		 1268 if (update)
1269 pebs_update_threshold(cpuc);
09e61b4f
PZ		 1270}
1271
68f7082f 1272void intel_pmu_pebs_add(struct perf_event *event)
3569c0d7 1273{
09e61b4f
PZ		 1274 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1275 struct hw_perf_event *hwc = &event->hw;
1276 bool needed_cb = pebs_needs_sched_cb(cpuc);
1277
1278 cpuc->n_pebs++;
174afc3e 1279 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
09e61b4f 1280 cpuc->n_large_pebs++;
42880f72
AS		 1281 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1282 cpuc->n_pebs_via_pt++;
09e61b4f 1283
c22497f5 1284 pebs_update_state(needed_cb, cpuc, event, true);
3569c0d7
YZ		 1285}
1286
42880f72
AS		 1287static void intel_pmu_pebs_via_pt_disable(struct perf_event *event)
1288{
1289 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1290
1291 if (!is_pebs_pt(event))
1292 return;
1293
1294 if (!(cpuc->pebs_enabled & ~PEBS_VIA_PT_MASK))
1295 cpuc->pebs_enabled &= ~PEBS_VIA_PT_MASK;
1296}
1297
1298static void intel_pmu_pebs_via_pt_enable(struct perf_event *event)
1299{
1300 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1301 struct hw_perf_event *hwc = &event->hw;
1302 struct debug_store *ds = cpuc->ds;
4c58d922
LX		 1303 u64 value = ds->pebs_event_reset[hwc->idx];
1304 u32 base = MSR_RELOAD_PMC0;
1305 unsigned int idx = hwc->idx;
42880f72
AS		 1306
1307 if (!is_pebs_pt(event))
1308 return;
1309
1310 if (!(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS))
1311 cpuc->pebs_enabled |= PEBS_PMI_AFTER_EACH_RECORD;
1312
1313 cpuc->pebs_enabled |= PEBS_OUTPUT_PT;
1314
4c58d922
LX		 1315 if (hwc->idx >= INTEL_PMC_IDX_FIXED) {
1316 base = MSR_RELOAD_FIXED_CTR0;
1317 idx = hwc->idx - INTEL_PMC_IDX_FIXED;
2145e77f
KL		 1318 if (x86_pmu.intel_cap.pebs_format < 5)
1319 value = ds->pebs_event_reset[MAX_PEBS_EVENTS_FMT4 + idx];
1320 else
1321 value = ds->pebs_event_reset[MAX_PEBS_EVENTS + idx];
4c58d922
LX		 1322 }
1323 wrmsrl(base + idx, value);
42880f72
AS		 1324}
1325
de0428a7 1326void intel_pmu_pebs_enable(struct perf_event *event)
ca037701 1327{
89cbc767 1328 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
ef21f683 1329 struct hw_perf_event *hwc = &event->hw;
851559e3 1330 struct debug_store *ds = cpuc->ds;
4c58d922 1331 unsigned int idx = hwc->idx;
09e61b4f 1332
ca037701
PZ		 1333 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
1334
ad0e6cfe 1335 cpuc->pebs_enabled |= 1ULL << hwc->idx;
f20093ee 1336
60176089 1337 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) && (x86_pmu.version < 5))
f20093ee 1338 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
9ad64c0f
SE		 1339 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
1340 cpuc->pebs_enabled |= 1ULL << 63;
851559e3 1341
c22497f5
KL		 1342 if (x86_pmu.intel_cap.pebs_baseline) {
1343 hwc->config |= ICL_EVENTSEL_ADAPTIVE;
1344 if (cpuc->pebs_data_cfg != cpuc->active_pebs_data_cfg) {
1345 wrmsrl(MSR_PEBS_DATA_CFG, cpuc->pebs_data_cfg);
1346 cpuc->active_pebs_data_cfg = cpuc->pebs_data_cfg;
1347 }
1348 }
1349
2145e77f
KL		 1350 if (idx >= INTEL_PMC_IDX_FIXED) {
1351 if (x86_pmu.intel_cap.pebs_format < 5)
1352 idx = MAX_PEBS_EVENTS_FMT4 + (idx - INTEL_PMC_IDX_FIXED);
1353 else
1354 idx = MAX_PEBS_EVENTS + (idx - INTEL_PMC_IDX_FIXED);
1355 }
4c58d922 1356
3569c0d7 1357 /*
09e61b4f
PZ		 1358 * Use auto-reload if possible to save a MSR write in the PMI.
1359 * This must be done in pmu::start(), because PERF_EVENT_IOC_PERIOD.
3569c0d7 1360 */
851559e3 1361 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
ec71a398 1362 ds->pebs_event_reset[idx] =
851559e3 1363 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
dc853e26 1364 } else {
4c58d922 1365 ds->pebs_event_reset[idx] = 0;
851559e3 1366 }
42880f72
AS		 1367
1368 intel_pmu_pebs_via_pt_enable(event);
09e61b4f
PZ		 1369}
1370
68f7082f 1371void intel_pmu_pebs_del(struct perf_event *event)
09e61b4f
PZ		 1372{
1373 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1374 struct hw_perf_event *hwc = &event->hw;
1375 bool needed_cb = pebs_needs_sched_cb(cpuc);
1376
1377 cpuc->n_pebs--;
174afc3e 1378 if (hwc->flags & PERF_X86_EVENT_LARGE_PEBS)
09e61b4f 1379 cpuc->n_large_pebs--;
42880f72
AS		 1380 if (hwc->flags & PERF_X86_EVENT_PEBS_VIA_PT)
1381 cpuc->n_pebs_via_pt--;
3569c0d7 1382
c22497f5 1383 pebs_update_state(needed_cb, cpuc, event, false);
ca037701
PZ		 1384}
1385
de0428a7 1386void intel_pmu_pebs_disable(struct perf_event *event)
ca037701 1387{
89cbc767 1388 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
ef21f683 1389 struct hw_perf_event *hwc = &event->hw;
2a853e11 1390
42880f72
AS		 1391 if (cpuc->n_pebs == cpuc->n_large_pebs &&
1392 cpuc->n_pebs != cpuc->n_pebs_via_pt)
2a853e11 1393 intel_pmu_drain_pebs_buffer();
ca037701 1394
ad0e6cfe 1395 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
983433b5 1396
60176089
KL		 1397 if ((event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT) &&
1398 (x86_pmu.version < 5))
983433b5 1399 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
b371b594 1400 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
983433b5
SE		 1401 cpuc->pebs_enabled &= ~(1ULL << 63);
1402
42880f72
AS		 1403 intel_pmu_pebs_via_pt_disable(event);
1404
4807e3d5 1405 if (cpuc->enabled)
ad0e6cfe 1406 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
ca037701
PZ		 1407
1408 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
1409}
1410
de0428a7 1411void intel_pmu_pebs_enable_all(void)
ca037701 1412{
89cbc767 1413 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
ca037701
PZ		 1414
1415 if (cpuc->pebs_enabled)
1416 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
1417}
1418
de0428a7 1419void intel_pmu_pebs_disable_all(void)
ca037701 1420{
89cbc767 1421 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
ca037701
PZ		 1422
1423 if (cpuc->pebs_enabled)
c22ac2a3 1424 __intel_pmu_pebs_disable_all();
ca037701
PZ		 1425}
1426
ef21f683
PZ		 1427static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
1428{
89cbc767 1429 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
ef21f683
PZ		 1430 unsigned long from = cpuc->lbr_entries[0].from;
1431 unsigned long old_to, to = cpuc->lbr_entries[0].to;
1432 unsigned long ip = regs->ip;
57d1c0c0 1433 int is_64bit = 0;
9536c8d2 1434 void *kaddr;
6ba48ff4 1435 int size;
ef21f683 1436
8db909a7
PZ		 1437 /*
1438 * We don't need to fixup if the PEBS assist is fault like
1439 */
1440 if (!x86_pmu.intel_cap.pebs_trap)
1441 return 1;
1442
a562b187
PZ		 1443 /*
1444 * No LBR entry, no basic block, no rewinding
1445 */
ef21f683
PZ		 1446 if (!cpuc->lbr_stack.nr || !from || !to)
1447 return 0;
1448
a562b187
PZ		 1449 /*
1450 * Basic blocks should never cross user/kernel boundaries
1451 */
1452 if (kernel_ip(ip) != kernel_ip(to))
1453 return 0;
1454
1455 /*
1456 * unsigned math, either ip is before the start (impossible) or
1457 * the basic block is larger than 1 page (sanity)
1458 */
9536c8d2 1459 if ((ip - to) > PEBS_FIXUP_SIZE)
ef21f683
PZ		 1460 return 0;
1461
1462 /*
1463 * We sampled a branch insn, rewind using the LBR stack
1464 */
1465 if (ip == to) {
d07bdfd3 1466 set_linear_ip(regs, from);
ef21f683
PZ		 1467 return 1;
1468 }
1469
6ba48ff4 1470 size = ip - to;
9536c8d2 1471 if (!kernel_ip(ip)) {
6ba48ff4 1472 int bytes;
9536c8d2
PZ		 1473 u8 *buf = this_cpu_read(insn_buffer);
1474
6ba48ff4 1475 /* 'size' must fit our buffer, see above */
9536c8d2 1476 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
0a196848 1477 if (bytes != 0)
9536c8d2
PZ		 1478 return 0;
1479
1480 kaddr = buf;
1481 } else {
1482 kaddr = (void *)to;
1483 }
1484
ef21f683
PZ		 1485 do {
1486 struct insn insn;
ef21f683
PZ		 1487
1488 old_to = to;
ef21f683 1489
57d1c0c0 1490#ifdef CONFIG_X86_64
375d4bfd 1491 is_64bit = kernel_ip(to) || any_64bit_mode(regs);
57d1c0c0 1492#endif
6ba48ff4 1493 insn_init(&insn, kaddr, size, is_64bit);
2ff49881 1494
6ba48ff4 1495 /*
2ff49881
BP		 1496 * Make sure there was not a problem decoding the instruction.
1497 * This is doubly important because we have an infinite loop if
1498 * insn.length=0.
6ba48ff4 1499 */
2ff49881 1500 if (insn_get_length(&insn))
6ba48ff4 1501 break;
9536c8d2 1502
ef21f683 1503 to += insn.length;
9536c8d2 1504 kaddr += insn.length;
6ba48ff4 1505 size -= insn.length;
ef21f683
PZ		 1506 } while (to < ip);
1507
1508 if (to == ip) {
d07bdfd3 1509 set_linear_ip(regs, old_to);
ef21f683
PZ		 1510 return 1;
1511 }
1512
a562b187
PZ		 1513 /*
1514 * Even though we decoded the basic block, the instruction stream
1515 * never matched the given IP, either the TO or the IP got corrupted.
1516 */
ef21f683
PZ		 1517 return 0;
1518}
1519
48f38aa4 1520static inline u64 intel_get_tsx_weight(u64 tsx_tuning)
748e86aa 1521{
48f38aa4
AK		 1522 if (tsx_tuning) {
1523 union hsw_tsx_tuning tsx = { .value = tsx_tuning };
748e86aa
AK		 1524 return tsx.cycles_last_block;
1525 }
1526 return 0;
1527}
1528
48f38aa4 1529static inline u64 intel_get_tsx_transaction(u64 tsx_tuning, u64 ax)
a405bad5 1530{
48f38aa4 1531 u64 txn = (tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
a405bad5
AK		 1532
1533 /* For RTM XABORTs also log the abort code from AX */
48f38aa4
AK		 1534 if ((txn & PERF_TXN_TRANSACTION) && (ax & 1))
1535 txn |= ((ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
a405bad5
AK		 1536 return txn;
1537}
1538
c22497f5
KL		 1539static inline u64 get_pebs_status(void *n)
1540{
1541 if (x86_pmu.intel_cap.pebs_format < 4)
1542 return ((struct pebs_record_nhm *)n)->status;
1543 return ((struct pebs_basic *)n)->applicable_counters;
1544}
1545
48f38aa4
AK		 1546#define PERF_X86_EVENT_PEBS_HSW_PREC \
1547 (PERF_X86_EVENT_PEBS_ST_HSW | \
1548 PERF_X86_EVENT_PEBS_LD_HSW | \
1549 PERF_X86_EVENT_PEBS_NA_HSW)
1550
1551static u64 get_data_src(struct perf_event *event, u64 aux)
1552{
1553 u64 val = PERF_MEM_NA;
1554 int fl = event->hw.flags;
1555 bool fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1556
1557 if (fl & PERF_X86_EVENT_PEBS_LDLAT)
ccf170e9 1558 val = load_latency_data(event, aux);
61b985e3 1559 else if (fl & PERF_X86_EVENT_PEBS_STLAT)
ccf170e9 1560 val = store_latency_data(event, aux);
39a41278
KL		 1561 else if (fl & PERF_X86_EVENT_PEBS_LAT_HYBRID)
1562 val = x86_pmu.pebs_latency_data(event, aux);
48f38aa4
AK		 1563 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1564 val = precise_datala_hsw(event, aux);
1565 else if (fst)
1566 val = precise_store_data(aux);
1567 return val;
1568}
1569
76a5433f
KL		 1570#define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \
1571 PERF_SAMPLE_PHYS_ADDR | \
1572 PERF_SAMPLE_DATA_PAGE_SIZE)
1573
c22497f5 1574static void setup_pebs_fixed_sample_data(struct perf_event *event,
43cf7631
YZ		 1575 struct pt_regs *iregs, void *__pebs,
1576 struct perf_sample_data *data,
1577 struct pt_regs *regs)
2b0b5c6f
PZ		 1578{
1579 /*
d2beea4a
PZ		 1580 * We cast to the biggest pebs_record but are careful not to
1581 * unconditionally access the 'extra' entries.
2b0b5c6f 1582 */
89cbc767 1583 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
2f7ebf2e 1584 struct pebs_record_skl *pebs = __pebs;
f20093ee 1585 u64 sample_type;
48f38aa4 1586 int fll;
2b0b5c6f 1587
21509084
YZ		 1588 if (pebs == NULL)
1589 return;
1590
c8aab2e0 1591 sample_type = event->attr.sample_type;
48f38aa4 1592 fll = event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT;
f20093ee 1593
43cf7631 1594 perf_sample_data_init(data, 0, event->hw.last_period);
2b0b5c6f 1595
43cf7631 1596 data->period = event->hw.last_period;
f20093ee
SE		 1597
1598 /*
c8aab2e0 1599 * Use latency for weight (only avail with PEBS-LL)
f20093ee 1600 */
2abe681d 1601 if (fll && (sample_type & PERF_SAMPLE_WEIGHT_TYPE)) {
2a6c6b7d 1602 data->weight.full = pebs->lat;
2abe681d
KL		 1603 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
1604 }
c8aab2e0
SE		 1605
1606 /*
1607 * data.data_src encodes the data source
1608 */
e16fd7f2 1609 if (sample_type & PERF_SAMPLE_DATA_SRC) {
48f38aa4 1610 data->data_src.val = get_data_src(event, pebs->dse);
e16fd7f2
KL		 1611 data->sample_flags |= PERF_SAMPLE_DATA_SRC;
1612 }
f20093ee 1613
6cbc304f
PZ		 1614 /*
1615 * We must however always use iregs for the unwinder to stay sane; the
1616 * record BP,SP,IP can point into thin air when the record is from a
a97673a1 1617 * previous PMI context or an (I)RET happened between the record and
6cbc304f
PZ		 1618 * PMI.
1619 */
31046500
NK		 1620 if (sample_type & PERF_SAMPLE_CALLCHAIN)
1621 perf_sample_save_callchain(data, event, iregs);
6cbc304f 1622
2b0b5c6f 1623 /*
b8000586
PZ		 1624 * We use the interrupt regs as a base because the PEBS record does not
1625 * contain a full regs set, specifically it seems to lack segment
1626 * descriptors, which get used by things like user_mode().
2b0b5c6f 1627 *
b8000586 1628 * In the simple case fix up only the IP for PERF_SAMPLE_IP.
2b0b5c6f 1629 */
43cf7631 1630 *regs = *iregs;
d1e7e602
SE		 1631
1632 /*
1633 * Initialize regs_>flags from PEBS,
1634 * Clear exact bit (which uses x86 EFLAGS Reserved bit 3),
1635 * i.e., do not rely on it being zero:
1636 */
1637 regs->flags = pebs->flags & ~PERF_EFLAGS_EXACT;
2b0b5c6f 1638
aea48559 1639 if (sample_type & PERF_SAMPLE_REGS_INTR) {
43cf7631
YZ		 1640 regs->ax = pebs->ax;
1641 regs->bx = pebs->bx;
1642 regs->cx = pebs->cx;
1643 regs->dx = pebs->dx;
1644 regs->si = pebs->si;
1645 regs->di = pebs->di;
43cf7631 1646
6cbc304f
PZ		 1647 regs->bp = pebs->bp;
1648 regs->sp = pebs->sp;
b8000586 1649
aea48559 1650#ifndef CONFIG_X86_32
43cf7631
YZ		 1651 regs->r8 = pebs->r8;
1652 regs->r9 = pebs->r9;
1653 regs->r10 = pebs->r10;
1654 regs->r11 = pebs->r11;
1655 regs->r12 = pebs->r12;
1656 regs->r13 = pebs->r13;
1657 regs->r14 = pebs->r14;
1658 regs->r15 = pebs->r15;
aea48559
SE		 1659#endif
1660 }
1661
71eb9ee9 1662 if (event->attr.precise_ip > 1) {
d1e7e602
SE		 1663 /*
1664 * Haswell and later processors have an 'eventing IP'
1665 * (real IP) which fixes the off-by-1 skid in hardware.
1666 * Use it when precise_ip >= 2 :
1667 */
71eb9ee9
SE		 1668 if (x86_pmu.intel_cap.pebs_format >= 2) {
1669 set_linear_ip(regs, pebs->real_ip);
1670 regs->flags |= PERF_EFLAGS_EXACT;
1671 } else {
d1e7e602 1672 /* Otherwise, use PEBS off-by-1 IP: */
71eb9ee9
SE		 1673 set_linear_ip(regs, pebs->ip);
1674
d1e7e602
SE		 1675 /*
1676 * With precise_ip >= 2, try to fix up the off-by-1 IP
1677 * using the LBR. If successful, the fixup function
1678 * corrects regs->ip and calls set_linear_ip() on regs:
1679 */
71eb9ee9
SE		 1680 if (intel_pmu_pebs_fixup_ip(regs))
1681 regs->flags |= PERF_EFLAGS_EXACT;
1682 }
d1e7e602
SE		 1683 } else {
1684 /*
1685 * When precise_ip == 1, return the PEBS off-by-1 IP,
1686 * no fixup attempted:
1687 */
71eb9ee9 1688 set_linear_ip(regs, pebs->ip);
d1e7e602 1689 }
71eb9ee9 1690
2b0b5c6f 1691
76a5433f 1692 if ((sample_type & PERF_SAMPLE_ADDR_TYPE) &&
7b084630 1693 x86_pmu.intel_cap.pebs_format >= 1) {
43cf7631 1694 data->addr = pebs->dla;
7b084630
NK		 1695 data->sample_flags |= PERF_SAMPLE_ADDR;
1696 }
f9134f36 1697
a405bad5
AK		 1698 if (x86_pmu.intel_cap.pebs_format >= 2) {
1699 /* Only set the TSX weight when no memory weight. */
2abe681d 1700 if ((sample_type & PERF_SAMPLE_WEIGHT_TYPE) && !fll) {
2a6c6b7d 1701 data->weight.full = intel_get_tsx_weight(pebs->tsx_tuning);
2abe681d
KL		 1702 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
1703 }
ee9db0e1 1704 if (sample_type & PERF_SAMPLE_TRANSACTION) {
48f38aa4
AK		 1705 data->txn = intel_get_tsx_transaction(pebs->tsx_tuning,
1706 pebs->ax);
ee9db0e1
KL		 1707 data->sample_flags |= PERF_SAMPLE_TRANSACTION;
1708 }
a405bad5 1709 }
748e86aa 1710
2f7ebf2e
AK		 1711 /*
1712 * v3 supplies an accurate time stamp, so we use that
1713 * for the time stamp.
1714 *
1715 * We can only do this for the default trace clock.
1716 */
1717 if (x86_pmu.intel_cap.pebs_format >= 3 &&
47a3aeb3 1718 event->attr.use_clockid == 0) {
2f7ebf2e 1719 data->time = native_sched_clock_from_tsc(pebs->tsc);
47a3aeb3
KL		 1720 data->sample_flags |= PERF_SAMPLE_TIME;
1721 }
2f7ebf2e 1722
eb55b455
NK		 1723 if (has_branch_stack(event))
1724 perf_sample_save_brstack(data, event, &cpuc->lbr_stack);
43cf7631
YZ		 1725}
1726
c22497f5
KL		 1727static void adaptive_pebs_save_regs(struct pt_regs *regs,
1728 struct pebs_gprs *gprs)
1729{
1730 regs->ax = gprs->ax;
1731 regs->bx = gprs->bx;
1732 regs->cx = gprs->cx;
1733 regs->dx = gprs->dx;
1734 regs->si = gprs->si;
1735 regs->di = gprs->di;
1736 regs->bp = gprs->bp;
1737 regs->sp = gprs->sp;
1738#ifndef CONFIG_X86_32
1739 regs->r8 = gprs->r8;
1740 regs->r9 = gprs->r9;
1741 regs->r10 = gprs->r10;
1742 regs->r11 = gprs->r11;
1743 regs->r12 = gprs->r12;
1744 regs->r13 = gprs->r13;
1745 regs->r14 = gprs->r14;
1746 regs->r15 = gprs->r15;
1747#endif
1748}
1749
61b985e3
KL		 1750#define PEBS_LATENCY_MASK 0xffff
1751#define PEBS_CACHE_LATENCY_OFFSET 32
c87a3109 1752#define PEBS_RETIRE_LATENCY_OFFSET 32
61b985e3 1753
c22497f5
KL		 1754/*
1755 * With adaptive PEBS the layout depends on what fields are configured.
1756 */
1757
1758static void setup_pebs_adaptive_sample_data(struct perf_event *event,
1759 struct pt_regs *iregs, void *__pebs,
1760 struct perf_sample_data *data,
1761 struct pt_regs *regs)
1762{
1763 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1764 struct pebs_basic *basic = __pebs;
1765 void *next_record = basic + 1;
1766 u64 sample_type;
1767 u64 format_size;
1768 struct pebs_meminfo *meminfo = NULL;
1769 struct pebs_gprs *gprs = NULL;
1770 struct x86_perf_regs *perf_regs;
1771
1772 if (basic == NULL)
1773 return;
1774
1775 perf_regs = container_of(regs, struct x86_perf_regs, regs);
1776 perf_regs->xmm_regs = NULL;
1777
1778 sample_type = event->attr.sample_type;
1779 format_size = basic->format_size;
1780 perf_sample_data_init(data, 0, event->hw.last_period);
1781 data->period = event->hw.last_period;
1782
47a3aeb3 1783 if (event->attr.use_clockid == 0) {
c22497f5 1784 data->time = native_sched_clock_from_tsc(basic->tsc);
47a3aeb3
KL		 1785 data->sample_flags |= PERF_SAMPLE_TIME;
1786 }
c22497f5
KL		 1787
1788 /*
1789 * We must however always use iregs for the unwinder to stay sane; the
1790 * record BP,SP,IP can point into thin air when the record is from a
1791 * previous PMI context or an (I)RET happened between the record and
1792 * PMI.
1793 */
31046500
NK		 1794 if (sample_type & PERF_SAMPLE_CALLCHAIN)
1795 perf_sample_save_callchain(data, event, iregs);
c22497f5
KL		 1796
1797 *regs = *iregs;
1798 /* The ip in basic is EventingIP */
1799 set_linear_ip(regs, basic->ip);
1800 regs->flags = PERF_EFLAGS_EXACT;
1801
c87a3109
KL		 1802 if ((sample_type & PERF_SAMPLE_WEIGHT_STRUCT) && (x86_pmu.flags & PMU_FL_RETIRE_LATENCY))
1803 data->weight.var3_w = format_size >> PEBS_RETIRE_LATENCY_OFFSET & PEBS_LATENCY_MASK;
1804
c22497f5
KL		 1805 /*
1806 * The record for MEMINFO is in front of GP
1807 * But PERF_SAMPLE_TRANSACTION needs gprs->ax.
1808 * Save the pointer here but process later.
1809 */
1810 if (format_size & PEBS_DATACFG_MEMINFO) {
1811 meminfo = next_record;
1812 next_record = meminfo + 1;
1813 }
1814
1815 if (format_size & PEBS_DATACFG_GP) {
1816 gprs = next_record;
1817 next_record = gprs + 1;
1818
1819 if (event->attr.precise_ip < 2) {
1820 set_linear_ip(regs, gprs->ip);
1821 regs->flags &= ~PERF_EFLAGS_EXACT;
1822 }
1823
1824 if (sample_type & PERF_SAMPLE_REGS_INTR)
1825 adaptive_pebs_save_regs(regs, gprs);
1826 }
1827
1828 if (format_size & PEBS_DATACFG_MEMINFO) {
61b985e3
KL		 1829 if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) {
1830 u64 weight = meminfo->latency;
1831
1832 if (x86_pmu.flags & PMU_FL_INSTR_LATENCY) {
1833 data->weight.var2_w = weight & PEBS_LATENCY_MASK;
1834 weight >>= PEBS_CACHE_LATENCY_OFFSET;
1835 }
1836
1837 /*
1838 * Although meminfo::latency is defined as a u64,
1839 * only the lower 32 bits include the valid data
1840 * in practice on Ice Lake and earlier platforms.
1841 */
1842 if (sample_type & PERF_SAMPLE_WEIGHT) {
1843 data->weight.full = weight ?:
1844 intel_get_tsx_weight(meminfo->tsx_tuning);
1845 } else {
1846 data->weight.var1_dw = (u32)(weight & PEBS_LATENCY_MASK) ?:
1847 intel_get_tsx_weight(meminfo->tsx_tuning);
1848 }
2abe681d 1849 data->sample_flags |= PERF_SAMPLE_WEIGHT_TYPE;
61b985e3 1850 }
c22497f5 1851
e16fd7f2 1852 if (sample_type & PERF_SAMPLE_DATA_SRC) {
c22497f5 1853 data->data_src.val = get_data_src(event, meminfo->aux);
e16fd7f2
KL		 1854 data->sample_flags |= PERF_SAMPLE_DATA_SRC;
1855 }
c22497f5 1856
7b084630 1857 if (sample_type & PERF_SAMPLE_ADDR_TYPE) {
c22497f5 1858 data->addr = meminfo->address;
7b084630
NK		 1859 data->sample_flags |= PERF_SAMPLE_ADDR;
1860 }
c22497f5 1861
ee9db0e1 1862 if (sample_type & PERF_SAMPLE_TRANSACTION) {
c22497f5
KL		 1863 data->txn = intel_get_tsx_transaction(meminfo->tsx_tuning,
1864 gprs ? gprs->ax : 0);
ee9db0e1
KL		 1865 data->sample_flags |= PERF_SAMPLE_TRANSACTION;
1866 }
c22497f5
KL		 1867 }
1868
1869 if (format_size & PEBS_DATACFG_XMMS) {
1870 struct pebs_xmm *xmm = next_record;
1871
1872 next_record = xmm + 1;
1873 perf_regs->xmm_regs = xmm->xmm;
1874 }
1875
1876 if (format_size & PEBS_DATACFG_LBRS) {
5624986d 1877 struct lbr_entry *lbr = next_record;
c22497f5
KL		 1878 int num_lbr = ((format_size >> PEBS_DATACFG_LBR_SHIFT)
1879 & 0xff) + 1;
5624986d 1880 next_record = next_record + num_lbr * sizeof(struct lbr_entry);
c22497f5
KL		 1881
1882 if (has_branch_stack(event)) {
1883 intel_pmu_store_pebs_lbrs(lbr);
eb55b455 1884 perf_sample_save_brstack(data, event, &cpuc->lbr_stack);
c22497f5
KL		 1885 }
1886 }
1887
1888 WARN_ONCE(next_record != __pebs + (format_size >> 48),
1889 "PEBS record size %llu, expected %llu, config %llx\n",
1890 format_size >> 48,
1891 (u64)(next_record - __pebs),
1892 basic->format_size);
1893}
1894
21509084
YZ		 1895static inline void *
1896get_next_pebs_record_by_bit(void *base, void *top, int bit)
1897{
1898 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1899 void *at;
1900 u64 pebs_status;
1901
1424a09a
SE		 1902 /*
1903 * fmt0 does not have a status bitfield (does not use
1904 * perf_record_nhm format)
1905 */
1906 if (x86_pmu.intel_cap.pebs_format < 1)
1907 return base;
1908
21509084
YZ		 1909 if (base == NULL)
1910 return NULL;
1911
c22497f5
KL		 1912 for (at = base; at < top; at += cpuc->pebs_record_size) {
1913 unsigned long status = get_pebs_status(at);
21509084 1914
c22497f5 1915 if (test_bit(bit, (unsigned long *)&status)) {
a3d86542
PZ		 1916 /* PEBS v3 has accurate status bits */
1917 if (x86_pmu.intel_cap.pebs_format >= 3)
1918 return at;
21509084 1919
c22497f5 1920 if (status == (1 << bit))
21509084
YZ		 1921 return at;
1922
1923 /* clear non-PEBS bit and re-check */
c22497f5 1924 pebs_status = status & cpuc->pebs_enabled;
fd583ad1 1925 pebs_status &= PEBS_COUNTER_MASK;
21509084
YZ		 1926 if (pebs_status == (1 << bit))
1927 return at;
1928 }
1929 }
1930 return NULL;
1931}
1932
5bee2cc6
KL		 1933void intel_pmu_auto_reload_read(struct perf_event *event)
1934{
1935 WARN_ON(!(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD));
1936
1937 perf_pmu_disable(event->pmu);
1938 intel_pmu_drain_pebs_buffer();
1939 perf_pmu_enable(event->pmu);
1940}
1941
d31fc13f
KL		 1942/*
1943 * Special variant of intel_pmu_save_and_restart() for auto-reload.
1944 */
1945static int
1946intel_pmu_save_and_restart_reload(struct perf_event *event, int count)
1947{
1948 struct hw_perf_event *hwc = &event->hw;
1949 int shift = 64 - x86_pmu.cntval_bits;
1950 u64 period = hwc->sample_period;
1951 u64 prev_raw_count, new_raw_count;
1952 s64 new, old;
1953
1954 WARN_ON(!period);
1955
1956 /*
1957 * drain_pebs() only happens when the PMU is disabled.
1958 */
1959 WARN_ON(this_cpu_read(cpu_hw_events.enabled));
1960
1961 prev_raw_count = local64_read(&hwc->prev_count);
1962 rdpmcl(hwc->event_base_rdpmc, new_raw_count);
1963 local64_set(&hwc->prev_count, new_raw_count);
1964
1965 /*
1966 * Since the counter increments a negative counter value and
1967 * overflows on the sign switch, giving the interval:
1968 *
1969 * [-period, 0]
1970 *
d9f6e12f 1971 * the difference between two consecutive reads is:
d31fc13f
KL		 1972 *
1973 * A) value2 - value1;
1974 * when no overflows have happened in between,
1975 *
1976 * B) (0 - value1) + (value2 - (-period));
1977 * when one overflow happened in between,
1978 *
1979 * C) (0 - value1) + (n - 1) * (period) + (value2 - (-period));
1980 * when @n overflows happened in between.
1981 *
1982 * Here A) is the obvious difference, B) is the extension to the
1983 * discrete interval, where the first term is to the top of the
1984 * interval and the second term is from the bottom of the next
1985 * interval and C) the extension to multiple intervals, where the
1986 * middle term is the whole intervals covered.
1987 *
1988 * An equivalent of C, by reduction, is:
1989 *
1990 * value2 - value1 + n * period
1991 */
1992 new = ((s64)(new_raw_count << shift) >> shift);
1993 old = ((s64)(prev_raw_count << shift) >> shift);
1994 local64_add(new - old + count * period, &event->count);
1995
f861854e
KL		 1996 local64_set(&hwc->period_left, -new);
1997
d31fc13f
KL		 1998 perf_event_update_userpage(event);
1999
2000 return 0;
2001}
2002
9dfa9a5c
PZ		 2003static __always_inline void
2004__intel_pmu_pebs_event(struct perf_event *event,
2005 struct pt_regs *iregs,
2006 struct perf_sample_data *data,
2007 void *base, void *top,
2008 int bit, int count,
2009 void (*setup_sample)(struct perf_event *,
2010 struct pt_regs *,
2011 void *,
2012 struct perf_sample_data *,
2013 struct pt_regs *))
43cf7631 2014{
c22497f5 2015 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
d31fc13f 2016 struct hw_perf_event *hwc = &event->hw;
c22497f5
KL		 2017 struct x86_perf_regs perf_regs;
2018 struct pt_regs *regs = &perf_regs.regs;
21509084 2019 void *at = get_next_pebs_record_by_bit(base, top, bit);
e506d1da 2020 static struct pt_regs dummy_iregs;
43cf7631 2021
d31fc13f
KL		 2022 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
2023 /*
2024 * Now, auto-reload is only enabled in fixed period mode.
2025 * The reload value is always hwc->sample_period.
2026 * May need to change it, if auto-reload is enabled in
2027 * freq mode later.
2028 */
2029 intel_pmu_save_and_restart_reload(event, count);
2030 } else if (!intel_pmu_save_and_restart(event))
43cf7631
YZ		 2031 return;
2032
35d1ce6b
KL		 2033 if (!iregs)
2034 iregs = &dummy_iregs;
2035
a3d86542 2036 while (count > 1) {
9dfa9a5c
PZ		 2037 setup_sample(event, iregs, at, data, regs);
2038 perf_event_output(event, data, regs);
c22497f5 2039 at += cpuc->pebs_record_size;
a3d86542
PZ		 2040 at = get_next_pebs_record_by_bit(at, top, bit);
2041 count--;
21509084
YZ		 2042 }
2043
9dfa9a5c 2044 setup_sample(event, iregs, at, data, regs);
35d1ce6b
KL		 2045 if (iregs == &dummy_iregs) {
2046 /*
2047 * The PEBS records may be drained in the non-overflow context,
2048 * e.g., large PEBS + context switch. Perf should treat the
2049 * last record the same as other PEBS records, and doesn't
2050 * invoke the generic overflow handler.
2051 */
9dfa9a5c 2052 perf_event_output(event, data, regs);
35d1ce6b
KL		 2053 } else {
2054 /*
2055 * All but the last records are processed.
2056 * The last one is left to be able to call the overflow handler.
2057 */
9dfa9a5c 2058 if (perf_event_overflow(event, data, regs))
35d1ce6b 2059 x86_pmu_stop(event, 0);
21509084 2060 }
2b0b5c6f
PZ		 2061}
2062
9dfa9a5c 2063static void intel_pmu_drain_pebs_core(struct pt_regs *iregs, struct perf_sample_data *data)
ca037701 2064{
89cbc767 2065 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
ca037701
PZ		 2066 struct debug_store *ds = cpuc->ds;
2067 struct perf_event *event = cpuc->events[0]; /* PMC0 only */
2068 struct pebs_record_core *at, *top;
ca037701
PZ		 2069 int n;
2070
6809b6ea 2071 if (!x86_pmu.pebs_active)
ca037701
PZ		 2072 return;
2073
ca037701
PZ		 2074 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
2075 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
2076
d80c7502
PZ		 2077 /*
2078 * Whatever else happens, drain the thing
2079 */
2080 ds->pebs_index = ds->pebs_buffer_base;
2081
2082 if (!test_bit(0, cpuc->active_mask))
8f4aebd2 2083 return;
ca037701 2084
d80c7502
PZ		 2085 WARN_ON_ONCE(!event);
2086
ab608344 2087 if (!event->attr.precise_ip)
d80c7502
PZ		 2088 return;
2089
1424a09a 2090 n = top - at;
d31fc13f
KL		 2091 if (n <= 0) {
2092 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2093 intel_pmu_save_and_restart_reload(event, 0);
d80c7502 2094 return;
d31fc13f 2095 }
ca037701 2096
9dfa9a5c 2097 __intel_pmu_pebs_event(event, iregs, data, at, top, 0, n,
c22497f5 2098 setup_pebs_fixed_sample_data);
ca037701
PZ		 2099}
2100
477f00f9
KL		 2101static void intel_pmu_pebs_event_update_no_drain(struct cpu_hw_events *cpuc, int size)
2102{
2103 struct perf_event *event;
2104 int bit;
2105
2106 /*
2107 * The drain_pebs() could be called twice in a short period
2108 * for auto-reload event in pmu::read(). There are no
2109 * overflows have happened in between.
2110 * It needs to call intel_pmu_save_and_restart_reload() to
2111 * update the event->count for this case.
2112 */
2113 for_each_set_bit(bit, (unsigned long *)&cpuc->pebs_enabled, size) {
2114 event = cpuc->events[bit];
2115 if (event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD)
2116 intel_pmu_save_and_restart_reload(event, 0);
2117 }
2118}
2119
9dfa9a5c 2120static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_data *data)
ca037701 2121{
89cbc767 2122 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
ca037701 2123 struct debug_store *ds = cpuc->ds;
21509084
YZ		 2124 struct perf_event *event;
2125 void *base, *at, *top;
ec71a398
KL		 2126 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2127 short error[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2128 int bit, i, size;
2129 u64 mask;
d2beea4a
PZ		 2130
2131 if (!x86_pmu.pebs_active)
2132 return;
2133
21509084 2134 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
d2beea4a 2135 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
ca037701 2136
ca037701
PZ		 2137 ds->pebs_index = ds->pebs_buffer_base;
2138
ec71a398
KL		 2139 mask = (1ULL << x86_pmu.max_pebs_events) - 1;
2140 size = x86_pmu.max_pebs_events;
2141 if (x86_pmu.flags & PMU_FL_PEBS_ALL) {
2142 mask |= ((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED;
2143 size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
2144 }
2145
d31fc13f 2146 if (unlikely(base >= top)) {
477f00f9 2147 intel_pmu_pebs_event_update_no_drain(cpuc, size);
d2beea4a 2148 return;
d31fc13f 2149 }
d2beea4a 2150
21509084 2151 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
130768b8 2152 struct pebs_record_nhm *p = at;
75f80859 2153 u64 pebs_status;
ca037701 2154
8ef9b845 2155 pebs_status = p->status & cpuc->pebs_enabled;
ec71a398 2156 pebs_status &= mask;
8ef9b845
PZ		 2157
2158 /* PEBS v3 has more accurate status bits */
a3d86542 2159 if (x86_pmu.intel_cap.pebs_format >= 3) {
c22497f5 2160 for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
a3d86542
PZ		 2161 counts[bit]++;
2162
2163 continue;
2164 }
2165
01330d72
AK		 2166 /*
2167 * On some CPUs the PEBS status can be zero when PEBS is
2168 * racing with clearing of GLOBAL_STATUS.
2169 *
2170 * Normally we would drop that record, but in the
2171 * case when there is only a single active PEBS event
2172 * we can assume it's for that event.
2173 */
2174 if (!pebs_status && cpuc->pebs_enabled &&
2175 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
d88d05a9 2176 pebs_status = p->status = cpuc->pebs_enabled;
01330d72 2177
75f80859 2178 bit = find_first_bit((unsigned long *)&pebs_status,
21509084 2179 x86_pmu.max_pebs_events);
957ea1fd 2180 if (bit >= x86_pmu.max_pebs_events)
21509084 2181 continue;
75f80859 2182
21509084
YZ		 2183 /*
2184 * The PEBS hardware does not deal well with the situation
2185 * when events happen near to each other and multiple bits
2186 * are set. But it should happen rarely.
2187 *
2188 * If these events include one PEBS and multiple non-PEBS
2189 * events, it doesn't impact PEBS record. The record will
2190 * be handled normally. (slow path)
2191 *
2192 * If these events include two or more PEBS events, the
2193 * records for the events can be collapsed into a single
2194 * one, and it's not possible to reconstruct all events
2195 * that caused the PEBS record. It's called collision.
2196 * If collision happened, the record will be dropped.
21509084 2197 */
fc17db8a 2198 if (pebs_status != (1ULL << bit)) {
c22497f5 2199 for_each_set_bit(i, (unsigned long *)&pebs_status, size)
75f80859
PZ		 2200 error[i]++;
2201 continue;
ca037701 2202 }
75f80859 2203
21509084
YZ		 2204 counts[bit]++;
2205 }
ca037701 2206
c22497f5 2207 for_each_set_bit(bit, (unsigned long *)&mask, size) {
f38b0dbb 2208 if ((counts[bit] == 0) && (error[bit] == 0))
ca037701 2209 continue;
75f80859 2210
21509084 2211 event = cpuc->events[bit];
8ef9b845
PZ		 2212 if (WARN_ON_ONCE(!event))
2213 continue;
2214
2215 if (WARN_ON_ONCE(!event->attr.precise_ip))
2216 continue;
ca037701 2217
f38b0dbb 2218 /* log dropped samples number */
475113d9 2219 if (error[bit]) {
f38b0dbb
KL		 2220 perf_log_lost_samples(event, error[bit]);
2221
5debf021 2222 if (iregs && perf_event_account_interrupt(event))
475113d9
JO		 2223 x86_pmu_stop(event, 0);
2224 }
2225
f38b0dbb 2226 if (counts[bit]) {
9dfa9a5c 2227 __intel_pmu_pebs_event(event, iregs, data, base,
c22497f5
KL		 2228 top, bit, counts[bit],
2229 setup_pebs_fixed_sample_data);
f38b0dbb 2230 }
ca037701 2231 }
ca037701
PZ		 2232}
2233
9dfa9a5c 2234static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_data *data)
c22497f5
KL		 2235{
2236 short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
2237 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
d4b294bf
KL		 2238 int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
2239 int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
c22497f5
KL		 2240 struct debug_store *ds = cpuc->ds;
2241 struct perf_event *event;
2242 void *base, *at, *top;
2243 int bit, size;
2244 u64 mask;
2245
2246 if (!x86_pmu.pebs_active)
2247 return;
2248
2249 base = (struct pebs_basic *)(unsigned long)ds->pebs_buffer_base;
2250 top = (struct pebs_basic *)(unsigned long)ds->pebs_index;
2251
2252 ds->pebs_index = ds->pebs_buffer_base;
2253
d4b294bf
KL		 2254 mask = ((1ULL << max_pebs_events) - 1) |
2255 (((1ULL << num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED);
2256 size = INTEL_PMC_IDX_FIXED + num_counters_fixed;
c22497f5
KL		 2257
2258 if (unlikely(base >= top)) {
2259 intel_pmu_pebs_event_update_no_drain(cpuc, size);
2260 return;
2261 }
2262
2263 for (at = base; at < top; at += cpuc->pebs_record_size) {
2264 u64 pebs_status;
2265
2266 pebs_status = get_pebs_status(at) & cpuc->pebs_enabled;
2267 pebs_status &= mask;
2268
2269 for_each_set_bit(bit, (unsigned long *)&pebs_status, size)
2270 counts[bit]++;
2271 }
2272
2273 for_each_set_bit(bit, (unsigned long *)&mask, size) {
2274 if (counts[bit] == 0)
2275 continue;
2276
2277 event = cpuc->events[bit];
2278 if (WARN_ON_ONCE(!event))
2279 continue;
2280
2281 if (WARN_ON_ONCE(!event->attr.precise_ip))
2282 continue;
2283
9dfa9a5c 2284 __intel_pmu_pebs_event(event, iregs, data, base,
c22497f5
KL		 2285 top, bit, counts[bit],
2286 setup_pebs_adaptive_sample_data);
2287 }
2288}
2289
ca037701
PZ		 2290/*
2291 * BTS, PEBS probe and setup
2292 */
2293
066ce64c 2294void __init intel_ds_init(void)
ca037701
PZ		 2295{
2296 /*
2297 * No support for 32bit formats
2298 */
2299 if (!boot_cpu_has(X86_FEATURE_DTES64))
2300 return;
2301
2302 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
2303 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
e72daf3f 2304 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
cd6b984f 2305 if (x86_pmu.version <= 4)
9b545c04 2306 x86_pmu.pebs_no_isolation = 1;
cd6b984f 2307
ca037701 2308 if (x86_pmu.pebs) {
8db909a7 2309 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
c22497f5 2310 char *pebs_qual = "";
8db909a7 2311 int format = x86_pmu.intel_cap.pebs_format;
ca037701 2312
c22497f5
KL		 2313 if (format < 4)
2314 x86_pmu.intel_cap.pebs_baseline = 0;
2315
ca037701
PZ		 2316 switch (format) {
2317 case 0:
1b74dde7 2318 pr_cont("PEBS fmt0%c, ", pebs_type);
ca037701 2319 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
e72daf3f
JO		 2320 /*
2321 * Using >PAGE_SIZE buffers makes the WRMSR to
2322 * PERF_GLOBAL_CTRL in intel_pmu_enable_all()
2323 * mysteriously hang on Core2.
2324 *
2325 * As a workaround, we don't do this.
2326 */
2327 x86_pmu.pebs_buffer_size = PAGE_SIZE;
ca037701 2328 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
ca037701
PZ		 2329 break;
2330
2331 case 1:
1b74dde7 2332 pr_cont("PEBS fmt1%c, ", pebs_type);
ca037701
PZ		 2333 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
2334 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
ca037701
PZ		 2335 break;
2336
130768b8
AK		 2337 case 2:
2338 pr_cont("PEBS fmt2%c, ", pebs_type);
2339 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
d2beea4a 2340 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
130768b8
AK		 2341 break;
2342
2f7ebf2e
AK		 2343 case 3:
2344 pr_cont("PEBS fmt3%c, ", pebs_type);
2345 x86_pmu.pebs_record_size =
2346 sizeof(struct pebs_record_skl);
2347 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
174afc3e 2348 x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;
2f7ebf2e
AK		 2349 break;
2350
c22497f5 2351 case 4:
2145e77f 2352 case 5:
c22497f5
KL		 2353 x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl;
2354 x86_pmu.pebs_record_size = sizeof(struct pebs_basic);
2355 if (x86_pmu.intel_cap.pebs_baseline) {
2356 x86_pmu.large_pebs_flags |=
2357 PERF_SAMPLE_BRANCH_STACK |
2358 PERF_SAMPLE_TIME;
2359 x86_pmu.flags |= PMU_FL_PEBS_ALL;
7d359886 2360 x86_pmu.pebs_capable = ~0ULL;
c22497f5 2361 pebs_qual = "-baseline";
61e76d53 2362 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
c22497f5
KL		 2363 } else {
2364 /* Only basic record supported */
c22497f5
KL		 2365 x86_pmu.large_pebs_flags &=
2366 ~(PERF_SAMPLE_ADDR |
2367 PERF_SAMPLE_TIME |
2368 PERF_SAMPLE_DATA_SRC |
2369 PERF_SAMPLE_TRANSACTION |
2370 PERF_SAMPLE_REGS_USER |
2371 PERF_SAMPLE_REGS_INTR);
2372 }
2373 pr_cont("PEBS fmt4%c%s, ", pebs_type, pebs_qual);
42880f72 2374
d0946a88 2375 if (!is_hybrid() && x86_pmu.intel_cap.pebs_output_pt_available) {
42880f72 2376 pr_cont("PEBS-via-PT, ");
61e76d53 2377 x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_AUX_OUTPUT;
42880f72
AS		 2378 }
2379
c22497f5
KL		 2380 break;
2381
ca037701 2382 default:
1b74dde7 2383 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
ca037701 2384 x86_pmu.pebs = 0;
ca037701
PZ		 2385 }
2386 }
2387}
1d9d8639
SE		 2388
2389void perf_restore_debug_store(void)
2390{
2a6e06b2
LT		 2391 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
2392
1d9d8639
SE		 2393 if (!x86_pmu.bts && !x86_pmu.pebs)
2394 return;
2395
2a6e06b2 2396 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1d9d8639 2397}
Linux 6.x block layer and io_uring tree(s)