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perf/x86/intel: Honour the CPUID for number of fixed counters in hypervisors
[linux-2.6-block.git] / arch / x86 / events / intel / core.c
CommitLineData
a7e3ed1e 1/*
efc9f05d
SE		 2 * Per core/cpu state
3 *
4 * Used to coordinate shared registers between HT threads or
5 * among events on a single PMU.
a7e3ed1e 6 */
de0428a7 7
c767a54b
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
de0428a7
KW		 10#include <linux/stddef.h>
11#include <linux/types.h>
12#include <linux/init.h>
13#include <linux/slab.h>
69c60c88 14#include <linux/export.h>
aacfbe6a 15#include <linux/nmi.h>
de0428a7 16
3a632cb2 17#include <asm/cpufeature.h>
de0428a7 18#include <asm/hardirq.h>
ef5f9f47 19#include <asm/intel-family.h>
de0428a7
KW		 20#include <asm/apic.h>
21
27f6d22b 22#include "../perf_event.h"
a7e3ed1e 23
f22f54f4 24/*
b622d644 25 * Intel PerfMon, used on Core and later.
f22f54f4 26 */
ec75a716 27static u64 intel_perfmon_event_map[PERF_COUNT_HW_MAX] __read_mostly =
f22f54f4 28{
c3b7cdf1
PE		 29 [PERF_COUNT_HW_CPU_CYCLES] = 0x003c,
30 [PERF_COUNT_HW_INSTRUCTIONS] = 0x00c0,
31 [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4f2e,
32 [PERF_COUNT_HW_CACHE_MISSES] = 0x412e,
33 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x00c4,
34 [PERF_COUNT_HW_BRANCH_MISSES] = 0x00c5,
35 [PERF_COUNT_HW_BUS_CYCLES] = 0x013c,
36 [PERF_COUNT_HW_REF_CPU_CYCLES] = 0x0300, /* pseudo-encoding */
f22f54f4
PZ		 37};
38
5c543e3c 39static struct event_constraint intel_core_event_constraints[] __read_mostly =
f22f54f4
PZ		 40{
41 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
42 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
43 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
44 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
45 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
46 INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
47 EVENT_CONSTRAINT_END
48};
49
5c543e3c 50static struct event_constraint intel_core2_event_constraints[] __read_mostly =
f22f54f4 51{
b622d644
PZ		 52 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
53 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 54 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 55 INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
56 INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
57 INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
58 INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
59 INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
60 INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
61 INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
62 INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
b622d644 63 INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
f22f54f4
PZ		 64 INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
65 EVENT_CONSTRAINT_END
66};
67
5c543e3c 68static struct event_constraint intel_nehalem_event_constraints[] __read_mostly =
f22f54f4 69{
b622d644
PZ		 70 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
71 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 72 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 73 INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
74 INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
75 INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
76 INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
77 INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
78 INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
79 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
80 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
81 EVENT_CONSTRAINT_END
82};
83
5c543e3c 84static struct extra_reg intel_nehalem_extra_regs[] __read_mostly =
a7e3ed1e 85{
53ad0447
YZ		 86 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
87 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
f20093ee 88 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 89 EVENT_EXTRA_END
90};
91
5c543e3c 92static struct event_constraint intel_westmere_event_constraints[] __read_mostly =
f22f54f4 93{
b622d644
PZ		 94 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
95 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 96 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 97 INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
98 INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
99 INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
d1100770 100 INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
f22f54f4
PZ		 101 EVENT_CONSTRAINT_END
102};
103
5c543e3c 104static struct event_constraint intel_snb_event_constraints[] __read_mostly =
b06b3d49
LM		 105{
106 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
107 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 108 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
fd4a5aef
SE		 109 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
110 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
111 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
112 INTEL_UEVENT_CONSTRAINT(0x06a3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
b06b3d49 113 INTEL_EVENT_CONSTRAINT(0x48, 0x4), /* L1D_PEND_MISS.PENDING */
b06b3d49
LM		 114 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
115 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
f8378f52
AK		 116 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
117 INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
93fcf72c 118
9010ae4a
SE		 119 /*
120 * When HT is off these events can only run on the bottom 4 counters
121 * When HT is on, they are impacted by the HT bug and require EXCL access
122 */
93fcf72c
MD		 123 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
124 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
125 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
126 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
127
b06b3d49
LM		 128 EVENT_CONSTRAINT_END
129};
130
69943182
SE		 131static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
132{
133 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
134 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
135 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
136 INTEL_UEVENT_CONSTRAINT(0x0148, 0x4), /* L1D_PEND_MISS.PENDING */
137 INTEL_UEVENT_CONSTRAINT(0x0279, 0xf), /* IDQ.EMTPY */
138 INTEL_UEVENT_CONSTRAINT(0x019c, 0xf), /* IDQ_UOPS_NOT_DELIVERED.CORE */
6113af14 139 INTEL_UEVENT_CONSTRAINT(0x02a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_LDM_PENDING */
69943182
SE		 140 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
141 INTEL_UEVENT_CONSTRAINT(0x05a3, 0xf), /* CYCLE_ACTIVITY.STALLS_L2_PENDING */
142 INTEL_UEVENT_CONSTRAINT(0x06a3, 0xf), /* CYCLE_ACTIVITY.STALLS_LDM_PENDING */
143 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
144 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
145 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
93fcf72c 146
9010ae4a
SE		 147 /*
148 * When HT is off these events can only run on the bottom 4 counters
149 * When HT is on, they are impacted by the HT bug and require EXCL access
150 */
93fcf72c
MD		 151 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
152 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
153 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
154 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
155
69943182
SE		 156 EVENT_CONSTRAINT_END
157};
158
5c543e3c 159static struct extra_reg intel_westmere_extra_regs[] __read_mostly =
a7e3ed1e 160{
53ad0447
YZ		 161 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
162 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0xffff, RSP_0),
163 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
f20093ee 164 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x100b),
a7e3ed1e
AK		 165 EVENT_EXTRA_END
166};
167
0af3ac1f
AK		 168static struct event_constraint intel_v1_event_constraints[] __read_mostly =
169{
170 EVENT_CONSTRAINT_END
171};
172
5c543e3c 173static struct event_constraint intel_gen_event_constraints[] __read_mostly =
f22f54f4 174{
b622d644
PZ		 175 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
176 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
cd09c0c4 177 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
f22f54f4
PZ		 178 EVENT_CONSTRAINT_END
179};
180
1fa64180
YZ		 181static struct event_constraint intel_slm_event_constraints[] __read_mostly =
182{
183 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
184 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
1fa64180
YZ		 185 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
186 EVENT_CONSTRAINT_END
187};
188
20f36278 189static struct event_constraint intel_skl_event_constraints[] = {
9a92e16f
AK		 190 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
191 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
192 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
193 INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
9010ae4a
SE		 194
195 /*
196 * when HT is off, these can only run on the bottom 4 counters
197 */
198 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
199 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
200 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
201 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
202 INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
203
9a92e16f
AK		 204 EVENT_CONSTRAINT_END
205};
206
1e7b9390 207static struct extra_reg intel_knl_extra_regs[] __read_mostly = {
9c489fce
LO		 208 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x799ffbb6e7ull, RSP_0),
209 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
1e7b9390
HC		 210 EVENT_EXTRA_END
211};
212
ee89cbc2 213static struct extra_reg intel_snb_extra_regs[] __read_mostly = {
53ad0447
YZ		 214 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
215 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3f807f8fffull, RSP_0),
216 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
f20093ee 217 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
f1923820
SE		 218 EVENT_EXTRA_END
219};
220
221static struct extra_reg intel_snbep_extra_regs[] __read_mostly = {
53ad0447
YZ		 222 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
223 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
224 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
f1a52789 225 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
ee89cbc2
SE		 226 EVENT_EXTRA_END
227};
228
9a92e16f
AK		 229static struct extra_reg intel_skl_extra_regs[] __read_mostly = {
230 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff8fffull, RSP_0),
231 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
232 INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
dfe1f3cb
AK		 233 /*
234 * Note the low 8 bits eventsel code is not a continuous field, containing
235 * some #GPing bits. These are masked out.
236 */
237 INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
9a92e16f
AK		 238 EVENT_EXTRA_END
239};
240
7f2ee91f
IM		 241EVENT_ATTR_STR(mem-loads, mem_ld_nhm, "event=0x0b,umask=0x10,ldlat=3");
242EVENT_ATTR_STR(mem-loads, mem_ld_snb, "event=0xcd,umask=0x1,ldlat=3");
243EVENT_ATTR_STR(mem-stores, mem_st_snb, "event=0xcd,umask=0x2");
f20093ee 244
20f36278 245static struct attribute *nhm_events_attrs[] = {
f20093ee
SE		 246 EVENT_PTR(mem_ld_nhm),
247 NULL,
248};
249
a39fcae7
AK		 250/*
251 * topdown events for Intel Core CPUs.
252 *
253 * The events are all in slots, which is a free slot in a 4 wide
254 * pipeline. Some events are already reported in slots, for cycle
255 * events we multiply by the pipeline width (4).
256 *
257 * With Hyper Threading on, topdown metrics are either summed or averaged
258 * between the threads of a core: (count_t0 + count_t1).
259 *
260 * For the average case the metric is always scaled to pipeline width,
261 * so we use factor 2 ((count_t0 + count_t1) / 2 * 4)
262 */
263
264EVENT_ATTR_STR_HT(topdown-total-slots, td_total_slots,
265 "event=0x3c,umask=0x0", /* cpu_clk_unhalted.thread */
266 "event=0x3c,umask=0x0,any=1"); /* cpu_clk_unhalted.thread_any */
267EVENT_ATTR_STR_HT(topdown-total-slots.scale, td_total_slots_scale, "4", "2");
268EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued,
269 "event=0xe,umask=0x1"); /* uops_issued.any */
270EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired,
271 "event=0xc2,umask=0x2"); /* uops_retired.retire_slots */
272EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles,
273 "event=0x9c,umask=0x1"); /* idq_uops_not_delivered_core */
274EVENT_ATTR_STR_HT(topdown-recovery-bubbles, td_recovery_bubbles,
275 "event=0xd,umask=0x3,cmask=1", /* int_misc.recovery_cycles */
276 "event=0xd,umask=0x3,cmask=1,any=1"); /* int_misc.recovery_cycles_any */
277EVENT_ATTR_STR_HT(topdown-recovery-bubbles.scale, td_recovery_bubbles_scale,
278 "4", "2");
279
20f36278 280static struct attribute *snb_events_attrs[] = {
f20093ee 281 EVENT_PTR(mem_ld_snb),
9ad64c0f 282 EVENT_PTR(mem_st_snb),
a39fcae7
AK		 283 EVENT_PTR(td_slots_issued),
284 EVENT_PTR(td_slots_retired),
285 EVENT_PTR(td_fetch_bubbles),
286 EVENT_PTR(td_total_slots),
287 EVENT_PTR(td_total_slots_scale),
288 EVENT_PTR(td_recovery_bubbles),
289 EVENT_PTR(td_recovery_bubbles_scale),
f20093ee
SE		 290 NULL,
291};
292
3a632cb2
AK		 293static struct event_constraint intel_hsw_event_constraints[] = {
294 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
295 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
296 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
e0fbac1c 297 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
3a632cb2
AK		 298 INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
299 INTEL_EVENT_CONSTRAINT(0xcd, 0x8), /* MEM_TRANS_RETIRED.LOAD_LATENCY */
300 /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
c420f19b 301 INTEL_UEVENT_CONSTRAINT(0x08a3, 0x4),
3a632cb2 302 /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
c420f19b 303 INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4),
3a632cb2 304 /* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
c420f19b 305 INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
93fcf72c 306
9010ae4a
SE		 307 /*
308 * When HT is off these events can only run on the bottom 4 counters
309 * When HT is on, they are impacted by the HT bug and require EXCL access
310 */
93fcf72c
MD		 311 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
312 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
313 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
314 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf), /* MEM_LOAD_UOPS_LLC_MISS_RETIRED.* */
315
3a632cb2
AK		 316 EVENT_CONSTRAINT_END
317};
318
20f36278 319static struct event_constraint intel_bdw_event_constraints[] = {
91f1b705
AK		 320 FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
321 FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
322 FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
323 INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
b7883a1c 324 INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
9010ae4a
SE		 325 /*
326 * when HT is off, these can only run on the bottom 4 counters
327 */
328 INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
329 INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
330 INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
331 INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
91f1b705
AK		 332 EVENT_CONSTRAINT_END
333};
334
f22f54f4
PZ		 335static u64 intel_pmu_event_map(int hw_event)
336{
337 return intel_perfmon_event_map[hw_event];
338}
339
9a92e16f
AK		 340/*
341 * Notes on the events:
342 * - data reads do not include code reads (comparable to earlier tables)
343 * - data counts include speculative execution (except L1 write, dtlb, bpu)
344 * - remote node access includes remote memory, remote cache, remote mmio.
345 * - prefetches are not included in the counts.
346 * - icache miss does not include decoded icache
347 */
348
349#define SKL_DEMAND_DATA_RD BIT_ULL(0)
350#define SKL_DEMAND_RFO BIT_ULL(1)
351#define SKL_ANY_RESPONSE BIT_ULL(16)
352#define SKL_SUPPLIER_NONE BIT_ULL(17)
353#define SKL_L3_MISS_LOCAL_DRAM BIT_ULL(26)
354#define SKL_L3_MISS_REMOTE_HOP0_DRAM BIT_ULL(27)
355#define SKL_L3_MISS_REMOTE_HOP1_DRAM BIT_ULL(28)
356#define SKL_L3_MISS_REMOTE_HOP2P_DRAM BIT_ULL(29)
357#define SKL_L3_MISS (SKL_L3_MISS_LOCAL_DRAM| \
358 SKL_L3_MISS_REMOTE_HOP0_DRAM| \
359 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
360 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
361#define SKL_SPL_HIT BIT_ULL(30)
362#define SKL_SNOOP_NONE BIT_ULL(31)
363#define SKL_SNOOP_NOT_NEEDED BIT_ULL(32)
364#define SKL_SNOOP_MISS BIT_ULL(33)
365#define SKL_SNOOP_HIT_NO_FWD BIT_ULL(34)
366#define SKL_SNOOP_HIT_WITH_FWD BIT_ULL(35)
367#define SKL_SNOOP_HITM BIT_ULL(36)
368#define SKL_SNOOP_NON_DRAM BIT_ULL(37)
369#define SKL_ANY_SNOOP (SKL_SPL_HIT|SKL_SNOOP_NONE| \
370 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
371 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
372 SKL_SNOOP_HITM|SKL_SNOOP_NON_DRAM)
373#define SKL_DEMAND_READ SKL_DEMAND_DATA_RD
374#define SKL_SNOOP_DRAM (SKL_SNOOP_NONE| \
375 SKL_SNOOP_NOT_NEEDED|SKL_SNOOP_MISS| \
376 SKL_SNOOP_HIT_NO_FWD|SKL_SNOOP_HIT_WITH_FWD| \
377 SKL_SNOOP_HITM|SKL_SPL_HIT)
378#define SKL_DEMAND_WRITE SKL_DEMAND_RFO
379#define SKL_LLC_ACCESS SKL_ANY_RESPONSE
380#define SKL_L3_MISS_REMOTE (SKL_L3_MISS_REMOTE_HOP0_DRAM| \
381 SKL_L3_MISS_REMOTE_HOP1_DRAM| \
382 SKL_L3_MISS_REMOTE_HOP2P_DRAM)
383
384static __initconst const u64 skl_hw_cache_event_ids
385 [PERF_COUNT_HW_CACHE_MAX]
386 [PERF_COUNT_HW_CACHE_OP_MAX]
387 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
388{
389 [ C(L1D ) ] = {
390 [ C(OP_READ) ] = {
391 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
392 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
393 },
394 [ C(OP_WRITE) ] = {
395 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
396 [ C(RESULT_MISS) ] = 0x0,
397 },
398 [ C(OP_PREFETCH) ] = {
399 [ C(RESULT_ACCESS) ] = 0x0,
400 [ C(RESULT_MISS) ] = 0x0,
401 },
402 },
403 [ C(L1I ) ] = {
404 [ C(OP_READ) ] = {
405 [ C(RESULT_ACCESS) ] = 0x0,
406 [ C(RESULT_MISS) ] = 0x283, /* ICACHE_64B.MISS */
407 },
408 [ C(OP_WRITE) ] = {
409 [ C(RESULT_ACCESS) ] = -1,
410 [ C(RESULT_MISS) ] = -1,
411 },
412 [ C(OP_PREFETCH) ] = {
413 [ C(RESULT_ACCESS) ] = 0x0,
414 [ C(RESULT_MISS) ] = 0x0,
415 },
416 },
417 [ C(LL ) ] = {
418 [ C(OP_READ) ] = {
419 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
420 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
421 },
422 [ C(OP_WRITE) ] = {
423 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
424 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
425 },
426 [ C(OP_PREFETCH) ] = {
427 [ C(RESULT_ACCESS) ] = 0x0,
428 [ C(RESULT_MISS) ] = 0x0,
429 },
430 },
431 [ C(DTLB) ] = {
432 [ C(OP_READ) ] = {
433 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_INST_RETIRED.ALL_LOADS */
434 [ C(RESULT_MISS) ] = 0x608, /* DTLB_LOAD_MISSES.WALK_COMPLETED */
435 },
436 [ C(OP_WRITE) ] = {
437 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_INST_RETIRED.ALL_STORES */
438 [ C(RESULT_MISS) ] = 0x649, /* DTLB_STORE_MISSES.WALK_COMPLETED */
439 },
440 [ C(OP_PREFETCH) ] = {
441 [ C(RESULT_ACCESS) ] = 0x0,
442 [ C(RESULT_MISS) ] = 0x0,
443 },
444 },
445 [ C(ITLB) ] = {
446 [ C(OP_READ) ] = {
447 [ C(RESULT_ACCESS) ] = 0x2085, /* ITLB_MISSES.STLB_HIT */
448 [ C(RESULT_MISS) ] = 0xe85, /* ITLB_MISSES.WALK_COMPLETED */
449 },
450 [ C(OP_WRITE) ] = {
451 [ C(RESULT_ACCESS) ] = -1,
452 [ C(RESULT_MISS) ] = -1,
453 },
454 [ C(OP_PREFETCH) ] = {
455 [ C(RESULT_ACCESS) ] = -1,
456 [ C(RESULT_MISS) ] = -1,
457 },
458 },
459 [ C(BPU ) ] = {
460 [ C(OP_READ) ] = {
461 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
462 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
463 },
464 [ C(OP_WRITE) ] = {
465 [ C(RESULT_ACCESS) ] = -1,
466 [ C(RESULT_MISS) ] = -1,
467 },
468 [ C(OP_PREFETCH) ] = {
469 [ C(RESULT_ACCESS) ] = -1,
470 [ C(RESULT_MISS) ] = -1,
471 },
472 },
473 [ C(NODE) ] = {
474 [ C(OP_READ) ] = {
475 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
476 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
477 },
478 [ C(OP_WRITE) ] = {
479 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
480 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
481 },
482 [ C(OP_PREFETCH) ] = {
483 [ C(RESULT_ACCESS) ] = 0x0,
484 [ C(RESULT_MISS) ] = 0x0,
485 },
486 },
487};
488
489static __initconst const u64 skl_hw_cache_extra_regs
490 [PERF_COUNT_HW_CACHE_MAX]
491 [PERF_COUNT_HW_CACHE_OP_MAX]
492 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
493{
494 [ C(LL ) ] = {
495 [ C(OP_READ) ] = {
496 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
497 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
498 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
499 SKL_L3_MISS|SKL_ANY_SNOOP|
500 SKL_SUPPLIER_NONE,
501 },
502 [ C(OP_WRITE) ] = {
503 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
504 SKL_LLC_ACCESS|SKL_ANY_SNOOP,
505 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
506 SKL_L3_MISS|SKL_ANY_SNOOP|
507 SKL_SUPPLIER_NONE,
508 },
509 [ C(OP_PREFETCH) ] = {
510 [ C(RESULT_ACCESS) ] = 0x0,
511 [ C(RESULT_MISS) ] = 0x0,
512 },
513 },
514 [ C(NODE) ] = {
515 [ C(OP_READ) ] = {
516 [ C(RESULT_ACCESS) ] = SKL_DEMAND_READ|
517 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
518 [ C(RESULT_MISS) ] = SKL_DEMAND_READ|
519 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
520 },
521 [ C(OP_WRITE) ] = {
522 [ C(RESULT_ACCESS) ] = SKL_DEMAND_WRITE|
523 SKL_L3_MISS_LOCAL_DRAM|SKL_SNOOP_DRAM,
524 [ C(RESULT_MISS) ] = SKL_DEMAND_WRITE|
525 SKL_L3_MISS_REMOTE|SKL_SNOOP_DRAM,
526 },
527 [ C(OP_PREFETCH) ] = {
528 [ C(RESULT_ACCESS) ] = 0x0,
529 [ C(RESULT_MISS) ] = 0x0,
530 },
531 },
532};
533
74e6543f
YZ		 534#define SNB_DMND_DATA_RD (1ULL << 0)
535#define SNB_DMND_RFO (1ULL << 1)
536#define SNB_DMND_IFETCH (1ULL << 2)
537#define SNB_DMND_WB (1ULL << 3)
538#define SNB_PF_DATA_RD (1ULL << 4)
539#define SNB_PF_RFO (1ULL << 5)
540#define SNB_PF_IFETCH (1ULL << 6)
541#define SNB_LLC_DATA_RD (1ULL << 7)
542#define SNB_LLC_RFO (1ULL << 8)
543#define SNB_LLC_IFETCH (1ULL << 9)
544#define SNB_BUS_LOCKS (1ULL << 10)
545#define SNB_STRM_ST (1ULL << 11)
546#define SNB_OTHER (1ULL << 15)
547#define SNB_RESP_ANY (1ULL << 16)
548#define SNB_NO_SUPP (1ULL << 17)
549#define SNB_LLC_HITM (1ULL << 18)
550#define SNB_LLC_HITE (1ULL << 19)
551#define SNB_LLC_HITS (1ULL << 20)
552#define SNB_LLC_HITF (1ULL << 21)
553#define SNB_LOCAL (1ULL << 22)
554#define SNB_REMOTE (0xffULL << 23)
555#define SNB_SNP_NONE (1ULL << 31)
556#define SNB_SNP_NOT_NEEDED (1ULL << 32)
557#define SNB_SNP_MISS (1ULL << 33)
558#define SNB_NO_FWD (1ULL << 34)
559#define SNB_SNP_FWD (1ULL << 35)
560#define SNB_HITM (1ULL << 36)
561#define SNB_NON_DRAM (1ULL << 37)
562
563#define SNB_DMND_READ (SNB_DMND_DATA_RD|SNB_LLC_DATA_RD)
564#define SNB_DMND_WRITE (SNB_DMND_RFO|SNB_LLC_RFO)
565#define SNB_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
566
567#define SNB_SNP_ANY (SNB_SNP_NONE|SNB_SNP_NOT_NEEDED| \
568 SNB_SNP_MISS|SNB_NO_FWD|SNB_SNP_FWD| \
569 SNB_HITM)
570
571#define SNB_DRAM_ANY (SNB_LOCAL|SNB_REMOTE|SNB_SNP_ANY)
572#define SNB_DRAM_REMOTE (SNB_REMOTE|SNB_SNP_ANY)
573
574#define SNB_L3_ACCESS SNB_RESP_ANY
575#define SNB_L3_MISS (SNB_DRAM_ANY|SNB_NON_DRAM)
576
577static __initconst const u64 snb_hw_cache_extra_regs
578 [PERF_COUNT_HW_CACHE_MAX]
579 [PERF_COUNT_HW_CACHE_OP_MAX]
580 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
581{
582 [ C(LL ) ] = {
583 [ C(OP_READ) ] = {
584 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_L3_ACCESS,
585 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_L3_MISS,
586 },
587 [ C(OP_WRITE) ] = {
588 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_L3_ACCESS,
589 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_L3_MISS,
590 },
591 [ C(OP_PREFETCH) ] = {
592 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_L3_ACCESS,
593 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_L3_MISS,
594 },
595 },
596 [ C(NODE) ] = {
597 [ C(OP_READ) ] = {
598 [ C(RESULT_ACCESS) ] = SNB_DMND_READ|SNB_DRAM_ANY,
599 [ C(RESULT_MISS) ] = SNB_DMND_READ|SNB_DRAM_REMOTE,
600 },
601 [ C(OP_WRITE) ] = {
602 [ C(RESULT_ACCESS) ] = SNB_DMND_WRITE|SNB_DRAM_ANY,
603 [ C(RESULT_MISS) ] = SNB_DMND_WRITE|SNB_DRAM_REMOTE,
604 },
605 [ C(OP_PREFETCH) ] = {
606 [ C(RESULT_ACCESS) ] = SNB_DMND_PREFETCH|SNB_DRAM_ANY,
607 [ C(RESULT_MISS) ] = SNB_DMND_PREFETCH|SNB_DRAM_REMOTE,
608 },
609 },
610};
611
b06b3d49
LM		 612static __initconst const u64 snb_hw_cache_event_ids
613 [PERF_COUNT_HW_CACHE_MAX]
614 [PERF_COUNT_HW_CACHE_OP_MAX]
615 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
616{
617 [ C(L1D) ] = {
618 [ C(OP_READ) ] = {
619 [ C(RESULT_ACCESS) ] = 0xf1d0, /* MEM_UOP_RETIRED.LOADS */
620 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPLACEMENT */
621 },
622 [ C(OP_WRITE) ] = {
623 [ C(RESULT_ACCESS) ] = 0xf2d0, /* MEM_UOP_RETIRED.STORES */
624 [ C(RESULT_MISS) ] = 0x0851, /* L1D.ALL_M_REPLACEMENT */
625 },
626 [ C(OP_PREFETCH) ] = {
627 [ C(RESULT_ACCESS) ] = 0x0,
628 [ C(RESULT_MISS) ] = 0x024e, /* HW_PRE_REQ.DL1_MISS */
629 },
630 },
631 [ C(L1I ) ] = {
632 [ C(OP_READ) ] = {
633 [ C(RESULT_ACCESS) ] = 0x0,
634 [ C(RESULT_MISS) ] = 0x0280, /* ICACHE.MISSES */
635 },
636 [ C(OP_WRITE) ] = {
637 [ C(RESULT_ACCESS) ] = -1,
638 [ C(RESULT_MISS) ] = -1,
639 },
640 [ C(OP_PREFETCH) ] = {
641 [ C(RESULT_ACCESS) ] = 0x0,
642 [ C(RESULT_MISS) ] = 0x0,
643 },
644 },
645 [ C(LL ) ] = {
b06b3d49 646 [ C(OP_READ) ] = {
63b6a675 647 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
b06b3d49 648 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 649 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
650 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 651 },
652 [ C(OP_WRITE) ] = {
63b6a675 653 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
b06b3d49 654 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 655 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
656 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 657 },
658 [ C(OP_PREFETCH) ] = {
63b6a675 659 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
b06b3d49 660 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 661 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
662 [ C(RESULT_MISS) ] = 0x01b7,
b06b3d49
LM		 663 },
664 },
665 [ C(DTLB) ] = {
666 [ C(OP_READ) ] = {
667 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOP_RETIRED.ALL_LOADS */
668 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.CAUSES_A_WALK */
669 },
670 [ C(OP_WRITE) ] = {
671 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOP_RETIRED.ALL_STORES */
672 [ C(RESULT_MISS) ] = 0x0149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
673 },
674 [ C(OP_PREFETCH) ] = {
675 [ C(RESULT_ACCESS) ] = 0x0,
676 [ C(RESULT_MISS) ] = 0x0,
677 },
678 },
679 [ C(ITLB) ] = {
680 [ C(OP_READ) ] = {
681 [ C(RESULT_ACCESS) ] = 0x1085, /* ITLB_MISSES.STLB_HIT */
682 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.CAUSES_A_WALK */
683 },
684 [ C(OP_WRITE) ] = {
685 [ C(RESULT_ACCESS) ] = -1,
686 [ C(RESULT_MISS) ] = -1,
687 },
688 [ C(OP_PREFETCH) ] = {
689 [ C(RESULT_ACCESS) ] = -1,
690 [ C(RESULT_MISS) ] = -1,
691 },
692 },
693 [ C(BPU ) ] = {
694 [ C(OP_READ) ] = {
695 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
696 [ C(RESULT_MISS) ] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
697 },
698 [ C(OP_WRITE) ] = {
699 [ C(RESULT_ACCESS) ] = -1,
700 [ C(RESULT_MISS) ] = -1,
701 },
702 [ C(OP_PREFETCH) ] = {
703 [ C(RESULT_ACCESS) ] = -1,
704 [ C(RESULT_MISS) ] = -1,
705 },
706 },
89d6c0b5
PZ		 707 [ C(NODE) ] = {
708 [ C(OP_READ) ] = {
74e6543f
YZ		 709 [ C(RESULT_ACCESS) ] = 0x01b7,
710 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 711 },
712 [ C(OP_WRITE) ] = {
74e6543f
YZ		 713 [ C(RESULT_ACCESS) ] = 0x01b7,
714 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 715 },
716 [ C(OP_PREFETCH) ] = {
74e6543f
YZ		 717 [ C(RESULT_ACCESS) ] = 0x01b7,
718 [ C(RESULT_MISS) ] = 0x01b7,
89d6c0b5
PZ		 719 },
720 },
721
b06b3d49
LM		 722};
723
0f1b5ca2
AK		 724/*
725 * Notes on the events:
726 * - data reads do not include code reads (comparable to earlier tables)
727 * - data counts include speculative execution (except L1 write, dtlb, bpu)
728 * - remote node access includes remote memory, remote cache, remote mmio.
729 * - prefetches are not included in the counts because they are not
730 * reliably counted.
731 */
732
733#define HSW_DEMAND_DATA_RD BIT_ULL(0)
734#define HSW_DEMAND_RFO BIT_ULL(1)
735#define HSW_ANY_RESPONSE BIT_ULL(16)
736#define HSW_SUPPLIER_NONE BIT_ULL(17)
737#define HSW_L3_MISS_LOCAL_DRAM BIT_ULL(22)
738#define HSW_L3_MISS_REMOTE_HOP0 BIT_ULL(27)
739#define HSW_L3_MISS_REMOTE_HOP1 BIT_ULL(28)
740#define HSW_L3_MISS_REMOTE_HOP2P BIT_ULL(29)
741#define HSW_L3_MISS (HSW_L3_MISS_LOCAL_DRAM| \
742 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
743 HSW_L3_MISS_REMOTE_HOP2P)
744#define HSW_SNOOP_NONE BIT_ULL(31)
745#define HSW_SNOOP_NOT_NEEDED BIT_ULL(32)
746#define HSW_SNOOP_MISS BIT_ULL(33)
747#define HSW_SNOOP_HIT_NO_FWD BIT_ULL(34)
748#define HSW_SNOOP_HIT_WITH_FWD BIT_ULL(35)
749#define HSW_SNOOP_HITM BIT_ULL(36)
750#define HSW_SNOOP_NON_DRAM BIT_ULL(37)
751#define HSW_ANY_SNOOP (HSW_SNOOP_NONE| \
752 HSW_SNOOP_NOT_NEEDED|HSW_SNOOP_MISS| \
753 HSW_SNOOP_HIT_NO_FWD|HSW_SNOOP_HIT_WITH_FWD| \
754 HSW_SNOOP_HITM|HSW_SNOOP_NON_DRAM)
755#define HSW_SNOOP_DRAM (HSW_ANY_SNOOP & ~HSW_SNOOP_NON_DRAM)
756#define HSW_DEMAND_READ HSW_DEMAND_DATA_RD
757#define HSW_DEMAND_WRITE HSW_DEMAND_RFO
758#define HSW_L3_MISS_REMOTE (HSW_L3_MISS_REMOTE_HOP0|\
759 HSW_L3_MISS_REMOTE_HOP1|HSW_L3_MISS_REMOTE_HOP2P)
760#define HSW_LLC_ACCESS HSW_ANY_RESPONSE
761
91f1b705
AK		 762#define BDW_L3_MISS_LOCAL BIT(26)
763#define BDW_L3_MISS (BDW_L3_MISS_LOCAL| \
764 HSW_L3_MISS_REMOTE_HOP0|HSW_L3_MISS_REMOTE_HOP1| \
765 HSW_L3_MISS_REMOTE_HOP2P)
766
767
0f1b5ca2
AK		 768static __initconst const u64 hsw_hw_cache_event_ids
769 [PERF_COUNT_HW_CACHE_MAX]
770 [PERF_COUNT_HW_CACHE_OP_MAX]
771 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
772{
773 [ C(L1D ) ] = {
774 [ C(OP_READ) ] = {
775 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
776 [ C(RESULT_MISS) ] = 0x151, /* L1D.REPLACEMENT */
777 },
778 [ C(OP_WRITE) ] = {
779 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
780 [ C(RESULT_MISS) ] = 0x0,
781 },
782 [ C(OP_PREFETCH) ] = {
783 [ C(RESULT_ACCESS) ] = 0x0,
784 [ C(RESULT_MISS) ] = 0x0,
785 },
786 },
787 [ C(L1I ) ] = {
788 [ C(OP_READ) ] = {
789 [ C(RESULT_ACCESS) ] = 0x0,
790 [ C(RESULT_MISS) ] = 0x280, /* ICACHE.MISSES */
791 },
792 [ C(OP_WRITE) ] = {
793 [ C(RESULT_ACCESS) ] = -1,
794 [ C(RESULT_MISS) ] = -1,
795 },
796 [ C(OP_PREFETCH) ] = {
797 [ C(RESULT_ACCESS) ] = 0x0,
798 [ C(RESULT_MISS) ] = 0x0,
799 },
800 },
801 [ C(LL ) ] = {
802 [ C(OP_READ) ] = {
803 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
804 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
805 },
806 [ C(OP_WRITE) ] = {
807 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
808 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
809 },
810 [ C(OP_PREFETCH) ] = {
811 [ C(RESULT_ACCESS) ] = 0x0,
812 [ C(RESULT_MISS) ] = 0x0,
813 },
814 },
815 [ C(DTLB) ] = {
816 [ C(OP_READ) ] = {
817 [ C(RESULT_ACCESS) ] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
818 [ C(RESULT_MISS) ] = 0x108, /* DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK */
819 },
820 [ C(OP_WRITE) ] = {
821 [ C(RESULT_ACCESS) ] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
822 [ C(RESULT_MISS) ] = 0x149, /* DTLB_STORE_MISSES.MISS_CAUSES_A_WALK */
823 },
824 [ C(OP_PREFETCH) ] = {
825 [ C(RESULT_ACCESS) ] = 0x0,
826 [ C(RESULT_MISS) ] = 0x0,
827 },
828 },
829 [ C(ITLB) ] = {
830 [ C(OP_READ) ] = {
831 [ C(RESULT_ACCESS) ] = 0x6085, /* ITLB_MISSES.STLB_HIT */
832 [ C(RESULT_MISS) ] = 0x185, /* ITLB_MISSES.MISS_CAUSES_A_WALK */
833 },
834 [ C(OP_WRITE) ] = {
835 [ C(RESULT_ACCESS) ] = -1,
836 [ C(RESULT_MISS) ] = -1,
837 },
838 [ C(OP_PREFETCH) ] = {
839 [ C(RESULT_ACCESS) ] = -1,
840 [ C(RESULT_MISS) ] = -1,
841 },
842 },
843 [ C(BPU ) ] = {
844 [ C(OP_READ) ] = {
845 [ C(RESULT_ACCESS) ] = 0xc4, /* BR_INST_RETIRED.ALL_BRANCHES */
846 [ C(RESULT_MISS) ] = 0xc5, /* BR_MISP_RETIRED.ALL_BRANCHES */
847 },
848 [ C(OP_WRITE) ] = {
849 [ C(RESULT_ACCESS) ] = -1,
850 [ C(RESULT_MISS) ] = -1,
851 },
852 [ C(OP_PREFETCH) ] = {
853 [ C(RESULT_ACCESS) ] = -1,
854 [ C(RESULT_MISS) ] = -1,
855 },
856 },
857 [ C(NODE) ] = {
858 [ C(OP_READ) ] = {
859 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
860 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
861 },
862 [ C(OP_WRITE) ] = {
863 [ C(RESULT_ACCESS) ] = 0x1b7, /* OFFCORE_RESPONSE */
864 [ C(RESULT_MISS) ] = 0x1b7, /* OFFCORE_RESPONSE */
865 },
866 [ C(OP_PREFETCH) ] = {
867 [ C(RESULT_ACCESS) ] = 0x0,
868 [ C(RESULT_MISS) ] = 0x0,
869 },
870 },
871};
872
873static __initconst const u64 hsw_hw_cache_extra_regs
874 [PERF_COUNT_HW_CACHE_MAX]
875 [PERF_COUNT_HW_CACHE_OP_MAX]
876 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
877{
878 [ C(LL ) ] = {
879 [ C(OP_READ) ] = {
880 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
881 HSW_LLC_ACCESS,
882 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
883 HSW_L3_MISS|HSW_ANY_SNOOP,
884 },
885 [ C(OP_WRITE) ] = {
886 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
887 HSW_LLC_ACCESS,
888 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
889 HSW_L3_MISS|HSW_ANY_SNOOP,
890 },
891 [ C(OP_PREFETCH) ] = {
892 [ C(RESULT_ACCESS) ] = 0x0,
893 [ C(RESULT_MISS) ] = 0x0,
894 },
895 },
896 [ C(NODE) ] = {
897 [ C(OP_READ) ] = {
898 [ C(RESULT_ACCESS) ] = HSW_DEMAND_READ|
899 HSW_L3_MISS_LOCAL_DRAM|
900 HSW_SNOOP_DRAM,
901 [ C(RESULT_MISS) ] = HSW_DEMAND_READ|
902 HSW_L3_MISS_REMOTE|
903 HSW_SNOOP_DRAM,
904 },
905 [ C(OP_WRITE) ] = {
906 [ C(RESULT_ACCESS) ] = HSW_DEMAND_WRITE|
907 HSW_L3_MISS_LOCAL_DRAM|
908 HSW_SNOOP_DRAM,
909 [ C(RESULT_MISS) ] = HSW_DEMAND_WRITE|
910 HSW_L3_MISS_REMOTE|
911 HSW_SNOOP_DRAM,
912 },
913 [ C(OP_PREFETCH) ] = {
914 [ C(RESULT_ACCESS) ] = 0x0,
915 [ C(RESULT_MISS) ] = 0x0,
916 },
917 },
918};
919
caaa8be3 920static __initconst const u64 westmere_hw_cache_event_ids
f22f54f4
PZ		 921 [PERF_COUNT_HW_CACHE_MAX]
922 [PERF_COUNT_HW_CACHE_OP_MAX]
923 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
924{
925 [ C(L1D) ] = {
926 [ C(OP_READ) ] = {
927 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
928 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
929 },
930 [ C(OP_WRITE) ] = {
931 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
932 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
933 },
934 [ C(OP_PREFETCH) ] = {
935 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
936 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
937 },
938 },
939 [ C(L1I ) ] = {
940 [ C(OP_READ) ] = {
941 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
942 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
943 },
944 [ C(OP_WRITE) ] = {
945 [ C(RESULT_ACCESS) ] = -1,
946 [ C(RESULT_MISS) ] = -1,
947 },
948 [ C(OP_PREFETCH) ] = {
949 [ C(RESULT_ACCESS) ] = 0x0,
950 [ C(RESULT_MISS) ] = 0x0,
951 },
952 },
953 [ C(LL ) ] = {
954 [ C(OP_READ) ] = {
63b6a675 955 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
e994d7d2 956 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 957 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
958 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 959 },
e994d7d2
AK		 960 /*
961 * Use RFO, not WRITEBACK, because a write miss would typically occur
962 * on RFO.
963 */
f22f54f4 964 [ C(OP_WRITE) ] = {
63b6a675
PZ		 965 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
966 [ C(RESULT_ACCESS) ] = 0x01b7,
967 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
e994d7d2 968 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 969 },
970 [ C(OP_PREFETCH) ] = {
63b6a675 971 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
e994d7d2 972 [ C(RESULT_ACCESS) ] = 0x01b7,
63b6a675
PZ		 973 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
974 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 975 },
976 },
977 [ C(DTLB) ] = {
978 [ C(OP_READ) ] = {
979 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
980 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
981 },
982 [ C(OP_WRITE) ] = {
983 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
984 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
985 },
986 [ C(OP_PREFETCH) ] = {
987 [ C(RESULT_ACCESS) ] = 0x0,
988 [ C(RESULT_MISS) ] = 0x0,
989 },
990 },
991 [ C(ITLB) ] = {
992 [ C(OP_READ) ] = {
993 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
994 [ C(RESULT_MISS) ] = 0x0185, /* ITLB_MISSES.ANY */
995 },
996 [ C(OP_WRITE) ] = {
997 [ C(RESULT_ACCESS) ] = -1,
998 [ C(RESULT_MISS) ] = -1,
999 },
1000 [ C(OP_PREFETCH) ] = {
1001 [ C(RESULT_ACCESS) ] = -1,
1002 [ C(RESULT_MISS) ] = -1,
1003 },
1004 },
1005 [ C(BPU ) ] = {
1006 [ C(OP_READ) ] = {
1007 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1008 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1009 },
1010 [ C(OP_WRITE) ] = {
1011 [ C(RESULT_ACCESS) ] = -1,
1012 [ C(RESULT_MISS) ] = -1,
1013 },
1014 [ C(OP_PREFETCH) ] = {
1015 [ C(RESULT_ACCESS) ] = -1,
1016 [ C(RESULT_MISS) ] = -1,
1017 },
1018 },
89d6c0b5
PZ		 1019 [ C(NODE) ] = {
1020 [ C(OP_READ) ] = {
1021 [ C(RESULT_ACCESS) ] = 0x01b7,
1022 [ C(RESULT_MISS) ] = 0x01b7,
1023 },
1024 [ C(OP_WRITE) ] = {
1025 [ C(RESULT_ACCESS) ] = 0x01b7,
1026 [ C(RESULT_MISS) ] = 0x01b7,
1027 },
1028 [ C(OP_PREFETCH) ] = {
1029 [ C(RESULT_ACCESS) ] = 0x01b7,
1030 [ C(RESULT_MISS) ] = 0x01b7,
1031 },
1032 },
f22f54f4
PZ		 1033};
1034
e994d7d2 1035/*
63b6a675
PZ		 1036 * Nehalem/Westmere MSR_OFFCORE_RESPONSE bits;
1037 * See IA32 SDM Vol 3B 30.6.1.3
e994d7d2
AK		 1038 */
1039
63b6a675
PZ		 1040#define NHM_DMND_DATA_RD (1 << 0)
1041#define NHM_DMND_RFO (1 << 1)
1042#define NHM_DMND_IFETCH (1 << 2)
1043#define NHM_DMND_WB (1 << 3)
1044#define NHM_PF_DATA_RD (1 << 4)
1045#define NHM_PF_DATA_RFO (1 << 5)
1046#define NHM_PF_IFETCH (1 << 6)
1047#define NHM_OFFCORE_OTHER (1 << 7)
1048#define NHM_UNCORE_HIT (1 << 8)
1049#define NHM_OTHER_CORE_HIT_SNP (1 << 9)
1050#define NHM_OTHER_CORE_HITM (1 << 10)
1051 /* reserved */
1052#define NHM_REMOTE_CACHE_FWD (1 << 12)
1053#define NHM_REMOTE_DRAM (1 << 13)
1054#define NHM_LOCAL_DRAM (1 << 14)
1055#define NHM_NON_DRAM (1 << 15)
1056
87e24f4b
PZ		 1057#define NHM_LOCAL (NHM_LOCAL_DRAM|NHM_REMOTE_CACHE_FWD)
1058#define NHM_REMOTE (NHM_REMOTE_DRAM)
63b6a675
PZ		 1059
1060#define NHM_DMND_READ (NHM_DMND_DATA_RD)
1061#define NHM_DMND_WRITE (NHM_DMND_RFO|NHM_DMND_WB)
1062#define NHM_DMND_PREFETCH (NHM_PF_DATA_RD|NHM_PF_DATA_RFO)
1063
1064#define NHM_L3_HIT (NHM_UNCORE_HIT|NHM_OTHER_CORE_HIT_SNP|NHM_OTHER_CORE_HITM)
87e24f4b 1065#define NHM_L3_MISS (NHM_NON_DRAM|NHM_LOCAL_DRAM|NHM_REMOTE_DRAM|NHM_REMOTE_CACHE_FWD)
63b6a675 1066#define NHM_L3_ACCESS (NHM_L3_HIT|NHM_L3_MISS)
e994d7d2
AK		 1067
1068static __initconst const u64 nehalem_hw_cache_extra_regs
1069 [PERF_COUNT_HW_CACHE_MAX]
1070 [PERF_COUNT_HW_CACHE_OP_MAX]
1071 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1072{
1073 [ C(LL ) ] = {
1074 [ C(OP_READ) ] = {
63b6a675
PZ		 1075 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_L3_ACCESS,
1076 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_L3_MISS,
e994d7d2
AK		 1077 },
1078 [ C(OP_WRITE) ] = {
63b6a675
PZ		 1079 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_L3_ACCESS,
1080 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_L3_MISS,
e994d7d2
AK		 1081 },
1082 [ C(OP_PREFETCH) ] = {
63b6a675
PZ		 1083 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_L3_ACCESS,
1084 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_L3_MISS,
e994d7d2 1085 },
89d6c0b5
PZ		 1086 },
1087 [ C(NODE) ] = {
1088 [ C(OP_READ) ] = {
87e24f4b
PZ		 1089 [ C(RESULT_ACCESS) ] = NHM_DMND_READ|NHM_LOCAL|NHM_REMOTE,
1090 [ C(RESULT_MISS) ] = NHM_DMND_READ|NHM_REMOTE,
89d6c0b5
PZ		 1091 },
1092 [ C(OP_WRITE) ] = {
87e24f4b
PZ		 1093 [ C(RESULT_ACCESS) ] = NHM_DMND_WRITE|NHM_LOCAL|NHM_REMOTE,
1094 [ C(RESULT_MISS) ] = NHM_DMND_WRITE|NHM_REMOTE,
89d6c0b5
PZ		 1095 },
1096 [ C(OP_PREFETCH) ] = {
87e24f4b
PZ		 1097 [ C(RESULT_ACCESS) ] = NHM_DMND_PREFETCH|NHM_LOCAL|NHM_REMOTE,
1098 [ C(RESULT_MISS) ] = NHM_DMND_PREFETCH|NHM_REMOTE,
89d6c0b5
PZ		 1099 },
1100 },
e994d7d2
AK		 1101};
1102
caaa8be3 1103static __initconst const u64 nehalem_hw_cache_event_ids
f22f54f4
PZ		 1104 [PERF_COUNT_HW_CACHE_MAX]
1105 [PERF_COUNT_HW_CACHE_OP_MAX]
1106 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1107{
1108 [ C(L1D) ] = {
1109 [ C(OP_READ) ] = {
f4929bd3
PZ		 1110 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS */
1111 [ C(RESULT_MISS) ] = 0x0151, /* L1D.REPL */
f22f54f4
PZ		 1112 },
1113 [ C(OP_WRITE) ] = {
f4929bd3
PZ		 1114 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES */
1115 [ C(RESULT_MISS) ] = 0x0251, /* L1D.M_REPL */
f22f54f4
PZ		 1116 },
1117 [ C(OP_PREFETCH) ] = {
1118 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS */
1119 [ C(RESULT_MISS) ] = 0x024e, /* L1D_PREFETCH.MISS */
1120 },
1121 },
1122 [ C(L1I ) ] = {
1123 [ C(OP_READ) ] = {
1124 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1125 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1126 },
1127 [ C(OP_WRITE) ] = {
1128 [ C(RESULT_ACCESS) ] = -1,
1129 [ C(RESULT_MISS) ] = -1,
1130 },
1131 [ C(OP_PREFETCH) ] = {
1132 [ C(RESULT_ACCESS) ] = 0x0,
1133 [ C(RESULT_MISS) ] = 0x0,
1134 },
1135 },
1136 [ C(LL ) ] = {
1137 [ C(OP_READ) ] = {
e994d7d2
AK		 1138 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1139 [ C(RESULT_ACCESS) ] = 0x01b7,
1140 /* OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS */
1141 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4 1142 },
e994d7d2
AK		 1143 /*
1144 * Use RFO, not WRITEBACK, because a write miss would typically occur
1145 * on RFO.
1146 */
f22f54f4 1147 [ C(OP_WRITE) ] = {
e994d7d2
AK		 1148 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1149 [ C(RESULT_ACCESS) ] = 0x01b7,
1150 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1151 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1152 },
1153 [ C(OP_PREFETCH) ] = {
e994d7d2
AK		 1154 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1155 [ C(RESULT_ACCESS) ] = 0x01b7,
1156 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1157 [ C(RESULT_MISS) ] = 0x01b7,
f22f54f4
PZ		 1158 },
1159 },
1160 [ C(DTLB) ] = {
1161 [ C(OP_READ) ] = {
1162 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1163 [ C(RESULT_MISS) ] = 0x0108, /* DTLB_LOAD_MISSES.ANY */
1164 },
1165 [ C(OP_WRITE) ] = {
1166 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1167 [ C(RESULT_MISS) ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS */
1168 },
1169 [ C(OP_PREFETCH) ] = {
1170 [ C(RESULT_ACCESS) ] = 0x0,
1171 [ C(RESULT_MISS) ] = 0x0,
1172 },
1173 },
1174 [ C(ITLB) ] = {
1175 [ C(OP_READ) ] = {
1176 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P */
1177 [ C(RESULT_MISS) ] = 0x20c8, /* ITLB_MISS_RETIRED */
1178 },
1179 [ C(OP_WRITE) ] = {
1180 [ C(RESULT_ACCESS) ] = -1,
1181 [ C(RESULT_MISS) ] = -1,
1182 },
1183 [ C(OP_PREFETCH) ] = {
1184 [ C(RESULT_ACCESS) ] = -1,
1185 [ C(RESULT_MISS) ] = -1,
1186 },
1187 },
1188 [ C(BPU ) ] = {
1189 [ C(OP_READ) ] = {
1190 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1191 [ C(RESULT_MISS) ] = 0x03e8, /* BPU_CLEARS.ANY */
1192 },
1193 [ C(OP_WRITE) ] = {
1194 [ C(RESULT_ACCESS) ] = -1,
1195 [ C(RESULT_MISS) ] = -1,
1196 },
1197 [ C(OP_PREFETCH) ] = {
1198 [ C(RESULT_ACCESS) ] = -1,
1199 [ C(RESULT_MISS) ] = -1,
1200 },
1201 },
89d6c0b5
PZ		 1202 [ C(NODE) ] = {
1203 [ C(OP_READ) ] = {
1204 [ C(RESULT_ACCESS) ] = 0x01b7,
1205 [ C(RESULT_MISS) ] = 0x01b7,
1206 },
1207 [ C(OP_WRITE) ] = {
1208 [ C(RESULT_ACCESS) ] = 0x01b7,
1209 [ C(RESULT_MISS) ] = 0x01b7,
1210 },
1211 [ C(OP_PREFETCH) ] = {
1212 [ C(RESULT_ACCESS) ] = 0x01b7,
1213 [ C(RESULT_MISS) ] = 0x01b7,
1214 },
1215 },
f22f54f4
PZ		 1216};
1217
caaa8be3 1218static __initconst const u64 core2_hw_cache_event_ids
f22f54f4
PZ		 1219 [PERF_COUNT_HW_CACHE_MAX]
1220 [PERF_COUNT_HW_CACHE_OP_MAX]
1221 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1222{
1223 [ C(L1D) ] = {
1224 [ C(OP_READ) ] = {
1225 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI */
1226 [ C(RESULT_MISS) ] = 0x0140, /* L1D_CACHE_LD.I_STATE */
1227 },
1228 [ C(OP_WRITE) ] = {
1229 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI */
1230 [ C(RESULT_MISS) ] = 0x0141, /* L1D_CACHE_ST.I_STATE */
1231 },
1232 [ C(OP_PREFETCH) ] = {
1233 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS */
1234 [ C(RESULT_MISS) ] = 0,
1235 },
1236 },
1237 [ C(L1I ) ] = {
1238 [ C(OP_READ) ] = {
1239 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS */
1240 [ C(RESULT_MISS) ] = 0x0081, /* L1I.MISSES */
1241 },
1242 [ C(OP_WRITE) ] = {
1243 [ C(RESULT_ACCESS) ] = -1,
1244 [ C(RESULT_MISS) ] = -1,
1245 },
1246 [ C(OP_PREFETCH) ] = {
1247 [ C(RESULT_ACCESS) ] = 0,
1248 [ C(RESULT_MISS) ] = 0,
1249 },
1250 },
1251 [ C(LL ) ] = {
1252 [ C(OP_READ) ] = {
1253 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1254 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1255 },
1256 [ C(OP_WRITE) ] = {
1257 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1258 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1259 },
1260 [ C(OP_PREFETCH) ] = {
1261 [ C(RESULT_ACCESS) ] = 0,
1262 [ C(RESULT_MISS) ] = 0,
1263 },
1264 },
1265 [ C(DTLB) ] = {
1266 [ C(OP_READ) ] = {
1267 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI (alias) */
1268 [ C(RESULT_MISS) ] = 0x0208, /* DTLB_MISSES.MISS_LD */
1269 },
1270 [ C(OP_WRITE) ] = {
1271 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI (alias) */
1272 [ C(RESULT_MISS) ] = 0x0808, /* DTLB_MISSES.MISS_ST */
1273 },
1274 [ C(OP_PREFETCH) ] = {
1275 [ C(RESULT_ACCESS) ] = 0,
1276 [ C(RESULT_MISS) ] = 0,
1277 },
1278 },
1279 [ C(ITLB) ] = {
1280 [ C(OP_READ) ] = {
1281 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1282 [ C(RESULT_MISS) ] = 0x1282, /* ITLBMISSES */
1283 },
1284 [ C(OP_WRITE) ] = {
1285 [ C(RESULT_ACCESS) ] = -1,
1286 [ C(RESULT_MISS) ] = -1,
1287 },
1288 [ C(OP_PREFETCH) ] = {
1289 [ C(RESULT_ACCESS) ] = -1,
1290 [ C(RESULT_MISS) ] = -1,
1291 },
1292 },
1293 [ C(BPU ) ] = {
1294 [ C(OP_READ) ] = {
1295 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1296 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1297 },
1298 [ C(OP_WRITE) ] = {
1299 [ C(RESULT_ACCESS) ] = -1,
1300 [ C(RESULT_MISS) ] = -1,
1301 },
1302 [ C(OP_PREFETCH) ] = {
1303 [ C(RESULT_ACCESS) ] = -1,
1304 [ C(RESULT_MISS) ] = -1,
1305 },
1306 },
1307};
1308
caaa8be3 1309static __initconst const u64 atom_hw_cache_event_ids
f22f54f4
PZ		 1310 [PERF_COUNT_HW_CACHE_MAX]
1311 [PERF_COUNT_HW_CACHE_OP_MAX]
1312 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1313{
1314 [ C(L1D) ] = {
1315 [ C(OP_READ) ] = {
1316 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD */
1317 [ C(RESULT_MISS) ] = 0,
1318 },
1319 [ C(OP_WRITE) ] = {
1320 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST */
1321 [ C(RESULT_MISS) ] = 0,
1322 },
1323 [ C(OP_PREFETCH) ] = {
1324 [ C(RESULT_ACCESS) ] = 0x0,
1325 [ C(RESULT_MISS) ] = 0,
1326 },
1327 },
1328 [ C(L1I ) ] = {
1329 [ C(OP_READ) ] = {
1330 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS */
1331 [ C(RESULT_MISS) ] = 0x0280, /* L1I.MISSES */
1332 },
1333 [ C(OP_WRITE) ] = {
1334 [ C(RESULT_ACCESS) ] = -1,
1335 [ C(RESULT_MISS) ] = -1,
1336 },
1337 [ C(OP_PREFETCH) ] = {
1338 [ C(RESULT_ACCESS) ] = 0,
1339 [ C(RESULT_MISS) ] = 0,
1340 },
1341 },
1342 [ C(LL ) ] = {
1343 [ C(OP_READ) ] = {
1344 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI */
1345 [ C(RESULT_MISS) ] = 0x4129, /* L2_LD.ISTATE */
1346 },
1347 [ C(OP_WRITE) ] = {
1348 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI */
1349 [ C(RESULT_MISS) ] = 0x412A, /* L2_ST.ISTATE */
1350 },
1351 [ C(OP_PREFETCH) ] = {
1352 [ C(RESULT_ACCESS) ] = 0,
1353 [ C(RESULT_MISS) ] = 0,
1354 },
1355 },
1356 [ C(DTLB) ] = {
1357 [ C(OP_READ) ] = {
1358 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI (alias) */
1359 [ C(RESULT_MISS) ] = 0x0508, /* DTLB_MISSES.MISS_LD */
1360 },
1361 [ C(OP_WRITE) ] = {
1362 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI (alias) */
1363 [ C(RESULT_MISS) ] = 0x0608, /* DTLB_MISSES.MISS_ST */
1364 },
1365 [ C(OP_PREFETCH) ] = {
1366 [ C(RESULT_ACCESS) ] = 0,
1367 [ C(RESULT_MISS) ] = 0,
1368 },
1369 },
1370 [ C(ITLB) ] = {
1371 [ C(OP_READ) ] = {
1372 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
1373 [ C(RESULT_MISS) ] = 0x0282, /* ITLB.MISSES */
1374 },
1375 [ C(OP_WRITE) ] = {
1376 [ C(RESULT_ACCESS) ] = -1,
1377 [ C(RESULT_MISS) ] = -1,
1378 },
1379 [ C(OP_PREFETCH) ] = {
1380 [ C(RESULT_ACCESS) ] = -1,
1381 [ C(RESULT_MISS) ] = -1,
1382 },
1383 },
1384 [ C(BPU ) ] = {
1385 [ C(OP_READ) ] = {
1386 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1387 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1388 },
1389 [ C(OP_WRITE) ] = {
1390 [ C(RESULT_ACCESS) ] = -1,
1391 [ C(RESULT_MISS) ] = -1,
1392 },
1393 [ C(OP_PREFETCH) ] = {
1394 [ C(RESULT_ACCESS) ] = -1,
1395 [ C(RESULT_MISS) ] = -1,
1396 },
1397 },
1398};
1399
eb12b8ec
AK		 1400EVENT_ATTR_STR(topdown-total-slots, td_total_slots_slm, "event=0x3c");
1401EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_slm, "2");
1402/* no_alloc_cycles.not_delivered */
1403EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_slm,
1404 "event=0xca,umask=0x50");
1405EVENT_ATTR_STR(topdown-fetch-bubbles.scale, td_fetch_bubbles_scale_slm, "2");
1406/* uops_retired.all */
1407EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_slm,
1408 "event=0xc2,umask=0x10");
1409/* uops_retired.all */
1410EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_slm,
1411 "event=0xc2,umask=0x10");
1412
1413static struct attribute *slm_events_attrs[] = {
1414 EVENT_PTR(td_total_slots_slm),
1415 EVENT_PTR(td_total_slots_scale_slm),
1416 EVENT_PTR(td_fetch_bubbles_slm),
1417 EVENT_PTR(td_fetch_bubbles_scale_slm),
1418 EVENT_PTR(td_slots_issued_slm),
1419 EVENT_PTR(td_slots_retired_slm),
1420 NULL
1421};
1422
1fa64180
YZ		 1423static struct extra_reg intel_slm_extra_regs[] __read_mostly =
1424{
1425 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
06c939c1 1426 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x768005ffffull, RSP_0),
ae3f011f 1427 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1fa64180
YZ		 1428 EVENT_EXTRA_END
1429};
1430
1431#define SLM_DMND_READ SNB_DMND_DATA_RD
1432#define SLM_DMND_WRITE SNB_DMND_RFO
1433#define SLM_DMND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1434
1435#define SLM_SNP_ANY (SNB_SNP_NONE|SNB_SNP_MISS|SNB_NO_FWD|SNB_HITM)
1436#define SLM_LLC_ACCESS SNB_RESP_ANY
1437#define SLM_LLC_MISS (SLM_SNP_ANY|SNB_NON_DRAM)
1438
1439static __initconst const u64 slm_hw_cache_extra_regs
1440 [PERF_COUNT_HW_CACHE_MAX]
1441 [PERF_COUNT_HW_CACHE_OP_MAX]
1442 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1443{
1444 [ C(LL ) ] = {
1445 [ C(OP_READ) ] = {
1446 [ C(RESULT_ACCESS) ] = SLM_DMND_READ|SLM_LLC_ACCESS,
6d374056 1447 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1448 },
1449 [ C(OP_WRITE) ] = {
1450 [ C(RESULT_ACCESS) ] = SLM_DMND_WRITE|SLM_LLC_ACCESS,
1451 [ C(RESULT_MISS) ] = SLM_DMND_WRITE|SLM_LLC_MISS,
1452 },
1453 [ C(OP_PREFETCH) ] = {
1454 [ C(RESULT_ACCESS) ] = SLM_DMND_PREFETCH|SLM_LLC_ACCESS,
1455 [ C(RESULT_MISS) ] = SLM_DMND_PREFETCH|SLM_LLC_MISS,
1456 },
1457 },
1458};
1459
1460static __initconst const u64 slm_hw_cache_event_ids
1461 [PERF_COUNT_HW_CACHE_MAX]
1462 [PERF_COUNT_HW_CACHE_OP_MAX]
1463 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
1464{
1465 [ C(L1D) ] = {
1466 [ C(OP_READ) ] = {
1467 [ C(RESULT_ACCESS) ] = 0,
1468 [ C(RESULT_MISS) ] = 0x0104, /* LD_DCU_MISS */
1469 },
1470 [ C(OP_WRITE) ] = {
1471 [ C(RESULT_ACCESS) ] = 0,
1472 [ C(RESULT_MISS) ] = 0,
1473 },
1474 [ C(OP_PREFETCH) ] = {
1475 [ C(RESULT_ACCESS) ] = 0,
1476 [ C(RESULT_MISS) ] = 0,
1477 },
1478 },
1479 [ C(L1I ) ] = {
1480 [ C(OP_READ) ] = {
1481 [ C(RESULT_ACCESS) ] = 0x0380, /* ICACHE.ACCESSES */
1482 [ C(RESULT_MISS) ] = 0x0280, /* ICACGE.MISSES */
1483 },
1484 [ C(OP_WRITE) ] = {
1485 [ C(RESULT_ACCESS) ] = -1,
1486 [ C(RESULT_MISS) ] = -1,
1487 },
1488 [ C(OP_PREFETCH) ] = {
1489 [ C(RESULT_ACCESS) ] = 0,
1490 [ C(RESULT_MISS) ] = 0,
1491 },
1492 },
1493 [ C(LL ) ] = {
1494 [ C(OP_READ) ] = {
1495 /* OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE */
1496 [ C(RESULT_ACCESS) ] = 0x01b7,
6d374056 1497 [ C(RESULT_MISS) ] = 0,
1fa64180
YZ		 1498 },
1499 [ C(OP_WRITE) ] = {
1500 /* OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE */
1501 [ C(RESULT_ACCESS) ] = 0x01b7,
1502 /* OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS */
1503 [ C(RESULT_MISS) ] = 0x01b7,
1504 },
1505 [ C(OP_PREFETCH) ] = {
1506 /* OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE */
1507 [ C(RESULT_ACCESS) ] = 0x01b7,
1508 /* OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS */
1509 [ C(RESULT_MISS) ] = 0x01b7,
1510 },
1511 },
1512 [ C(DTLB) ] = {
1513 [ C(OP_READ) ] = {
1514 [ C(RESULT_ACCESS) ] = 0,
1515 [ C(RESULT_MISS) ] = 0x0804, /* LD_DTLB_MISS */
1516 },
1517 [ C(OP_WRITE) ] = {
1518 [ C(RESULT_ACCESS) ] = 0,
1519 [ C(RESULT_MISS) ] = 0,
1520 },
1521 [ C(OP_PREFETCH) ] = {
1522 [ C(RESULT_ACCESS) ] = 0,
1523 [ C(RESULT_MISS) ] = 0,
1524 },
1525 },
1526 [ C(ITLB) ] = {
1527 [ C(OP_READ) ] = {
1528 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P */
6d374056 1529 [ C(RESULT_MISS) ] = 0x40205, /* PAGE_WALKS.I_SIDE_WALKS */
1fa64180
YZ		 1530 },
1531 [ C(OP_WRITE) ] = {
1532 [ C(RESULT_ACCESS) ] = -1,
1533 [ C(RESULT_MISS) ] = -1,
1534 },
1535 [ C(OP_PREFETCH) ] = {
1536 [ C(RESULT_ACCESS) ] = -1,
1537 [ C(RESULT_MISS) ] = -1,
1538 },
1539 },
1540 [ C(BPU ) ] = {
1541 [ C(OP_READ) ] = {
1542 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY */
1543 [ C(RESULT_MISS) ] = 0x00c5, /* BP_INST_RETIRED.MISPRED */
1544 },
1545 [ C(OP_WRITE) ] = {
1546 [ C(RESULT_ACCESS) ] = -1,
1547 [ C(RESULT_MISS) ] = -1,
1548 },
1549 [ C(OP_PREFETCH) ] = {
1550 [ C(RESULT_ACCESS) ] = -1,
1551 [ C(RESULT_MISS) ] = -1,
1552 },
1553 },
1554};
1555
8b92c3a7
KL		 1556static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
1557 /* must define OFFCORE_RSP_X first, see intel_fixup_er() */
1558 INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x760005ffbfull, RSP_0),
1559 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1560 EVENT_EXTRA_END
1561};
1562
1563#define GLM_DEMAND_DATA_RD BIT_ULL(0)
1564#define GLM_DEMAND_RFO BIT_ULL(1)
1565#define GLM_ANY_RESPONSE BIT_ULL(16)
1566#define GLM_SNP_NONE_OR_MISS BIT_ULL(33)
1567#define GLM_DEMAND_READ GLM_DEMAND_DATA_RD
1568#define GLM_DEMAND_WRITE GLM_DEMAND_RFO
1569#define GLM_DEMAND_PREFETCH (SNB_PF_DATA_RD|SNB_PF_RFO)
1570#define GLM_LLC_ACCESS GLM_ANY_RESPONSE
1571#define GLM_SNP_ANY (GLM_SNP_NONE_OR_MISS|SNB_NO_FWD|SNB_HITM)
1572#define GLM_LLC_MISS (GLM_SNP_ANY|SNB_NON_DRAM)
1573
1574static __initconst const u64 glm_hw_cache_event_ids
1575 [PERF_COUNT_HW_CACHE_MAX]
1576 [PERF_COUNT_HW_CACHE_OP_MAX]
1577 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1578 [C(L1D)] = {
1579 [C(OP_READ)] = {
1580 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1581 [C(RESULT_MISS)] = 0x0,
1582 },
1583 [C(OP_WRITE)] = {
1584 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1585 [C(RESULT_MISS)] = 0x0,
1586 },
1587 [C(OP_PREFETCH)] = {
1588 [C(RESULT_ACCESS)] = 0x0,
1589 [C(RESULT_MISS)] = 0x0,
1590 },
1591 },
1592 [C(L1I)] = {
1593 [C(OP_READ)] = {
1594 [C(RESULT_ACCESS)] = 0x0380, /* ICACHE.ACCESSES */
1595 [C(RESULT_MISS)] = 0x0280, /* ICACHE.MISSES */
1596 },
1597 [C(OP_WRITE)] = {
1598 [C(RESULT_ACCESS)] = -1,
1599 [C(RESULT_MISS)] = -1,
1600 },
1601 [C(OP_PREFETCH)] = {
1602 [C(RESULT_ACCESS)] = 0x0,
1603 [C(RESULT_MISS)] = 0x0,
1604 },
1605 },
1606 [C(LL)] = {
1607 [C(OP_READ)] = {
1608 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1609 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1610 },
1611 [C(OP_WRITE)] = {
1612 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1613 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1614 },
1615 [C(OP_PREFETCH)] = {
1616 [C(RESULT_ACCESS)] = 0x1b7, /* OFFCORE_RESPONSE */
1617 [C(RESULT_MISS)] = 0x1b7, /* OFFCORE_RESPONSE */
1618 },
1619 },
1620 [C(DTLB)] = {
1621 [C(OP_READ)] = {
1622 [C(RESULT_ACCESS)] = 0x81d0, /* MEM_UOPS_RETIRED.ALL_LOADS */
1623 [C(RESULT_MISS)] = 0x0,
1624 },
1625 [C(OP_WRITE)] = {
1626 [C(RESULT_ACCESS)] = 0x82d0, /* MEM_UOPS_RETIRED.ALL_STORES */
1627 [C(RESULT_MISS)] = 0x0,
1628 },
1629 [C(OP_PREFETCH)] = {
1630 [C(RESULT_ACCESS)] = 0x0,
1631 [C(RESULT_MISS)] = 0x0,
1632 },
1633 },
1634 [C(ITLB)] = {
1635 [C(OP_READ)] = {
1636 [C(RESULT_ACCESS)] = 0x00c0, /* INST_RETIRED.ANY_P */
1637 [C(RESULT_MISS)] = 0x0481, /* ITLB.MISS */
1638 },
1639 [C(OP_WRITE)] = {
1640 [C(RESULT_ACCESS)] = -1,
1641 [C(RESULT_MISS)] = -1,
1642 },
1643 [C(OP_PREFETCH)] = {
1644 [C(RESULT_ACCESS)] = -1,
1645 [C(RESULT_MISS)] = -1,
1646 },
1647 },
1648 [C(BPU)] = {
1649 [C(OP_READ)] = {
1650 [C(RESULT_ACCESS)] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
1651 [C(RESULT_MISS)] = 0x00c5, /* BR_MISP_RETIRED.ALL_BRANCHES */
1652 },
1653 [C(OP_WRITE)] = {
1654 [C(RESULT_ACCESS)] = -1,
1655 [C(RESULT_MISS)] = -1,
1656 },
1657 [C(OP_PREFETCH)] = {
1658 [C(RESULT_ACCESS)] = -1,
1659 [C(RESULT_MISS)] = -1,
1660 },
1661 },
1662};
1663
1664static __initconst const u64 glm_hw_cache_extra_regs
1665 [PERF_COUNT_HW_CACHE_MAX]
1666 [PERF_COUNT_HW_CACHE_OP_MAX]
1667 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1668 [C(LL)] = {
1669 [C(OP_READ)] = {
1670 [C(RESULT_ACCESS)] = GLM_DEMAND_READ|
1671 GLM_LLC_ACCESS,
1672 [C(RESULT_MISS)] = GLM_DEMAND_READ|
1673 GLM_LLC_MISS,
1674 },
1675 [C(OP_WRITE)] = {
1676 [C(RESULT_ACCESS)] = GLM_DEMAND_WRITE|
1677 GLM_LLC_ACCESS,
1678 [C(RESULT_MISS)] = GLM_DEMAND_WRITE|
1679 GLM_LLC_MISS,
1680 },
1681 [C(OP_PREFETCH)] = {
1682 [C(RESULT_ACCESS)] = GLM_DEMAND_PREFETCH|
1683 GLM_LLC_ACCESS,
1684 [C(RESULT_MISS)] = GLM_DEMAND_PREFETCH|
1685 GLM_LLC_MISS,
1686 },
1687 },
1688};
1689
1e7b9390
HC		 1690#define KNL_OT_L2_HITE BIT_ULL(19) /* Other Tile L2 Hit */
1691#define KNL_OT_L2_HITF BIT_ULL(20) /* Other Tile L2 Hit */
1692#define KNL_MCDRAM_LOCAL BIT_ULL(21)
1693#define KNL_MCDRAM_FAR BIT_ULL(22)
1694#define KNL_DDR_LOCAL BIT_ULL(23)
1695#define KNL_DDR_FAR BIT_ULL(24)
1696#define KNL_DRAM_ANY (KNL_MCDRAM_LOCAL | KNL_MCDRAM_FAR | \
1697 KNL_DDR_LOCAL | KNL_DDR_FAR)
1698#define KNL_L2_READ SLM_DMND_READ
1699#define KNL_L2_WRITE SLM_DMND_WRITE
1700#define KNL_L2_PREFETCH SLM_DMND_PREFETCH
1701#define KNL_L2_ACCESS SLM_LLC_ACCESS
1702#define KNL_L2_MISS (KNL_OT_L2_HITE | KNL_OT_L2_HITF | \
1703 KNL_DRAM_ANY | SNB_SNP_ANY | \
1704 SNB_NON_DRAM)
1705
1706static __initconst const u64 knl_hw_cache_extra_regs
1707 [PERF_COUNT_HW_CACHE_MAX]
1708 [PERF_COUNT_HW_CACHE_OP_MAX]
1709 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1710 [C(LL)] = {
1711 [C(OP_READ)] = {
1712 [C(RESULT_ACCESS)] = KNL_L2_READ | KNL_L2_ACCESS,
1713 [C(RESULT_MISS)] = 0,
1714 },
1715 [C(OP_WRITE)] = {
1716 [C(RESULT_ACCESS)] = KNL_L2_WRITE | KNL_L2_ACCESS,
1717 [C(RESULT_MISS)] = KNL_L2_WRITE | KNL_L2_MISS,
1718 },
1719 [C(OP_PREFETCH)] = {
1720 [C(RESULT_ACCESS)] = KNL_L2_PREFETCH | KNL_L2_ACCESS,
1721 [C(RESULT_MISS)] = KNL_L2_PREFETCH | KNL_L2_MISS,
1722 },
1723 },
1724};
1725
1a78d937 1726/*
c3d266c8
KL		 1727 * Used from PMIs where the LBRs are already disabled.
1728 *
1729 * This function could be called consecutively. It is required to remain in
1730 * disabled state if called consecutively.
1731 *
1732 * During consecutive calls, the same disable value will be written to related
cecf6235
AS		 1733 * registers, so the PMU state remains unchanged.
1734 *
1735 * intel_bts events don't coexist with intel PMU's BTS events because of
1736 * x86_add_exclusive(x86_lbr_exclusive_lbr); there's no need to keep them
1737 * disabled around intel PMU's event batching etc, only inside the PMI handler.
1a78d937
AK		 1738 */
1739static void __intel_pmu_disable_all(void)
f22f54f4 1740{
89cbc767 1741 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4
PZ		 1742
1743 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
1744
15c7ad51 1745 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask))
f22f54f4 1746 intel_pmu_disable_bts();
ca037701
PZ		 1747
1748 intel_pmu_pebs_disable_all();
1a78d937
AK		 1749}
1750
1751static void intel_pmu_disable_all(void)
1752{
1753 __intel_pmu_disable_all();
caff2bef 1754 intel_pmu_lbr_disable_all();
f22f54f4
PZ		 1755}
1756
1a78d937 1757static void __intel_pmu_enable_all(int added, bool pmi)
f22f54f4 1758{
89cbc767 1759 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 1760
d329527e 1761 intel_pmu_pebs_enable_all();
1a78d937 1762 intel_pmu_lbr_enable_all(pmi);
144d31e6
GN		 1763 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL,
1764 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask);
f22f54f4 1765
15c7ad51 1766 if (test_bit(INTEL_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
f22f54f4 1767 struct perf_event *event =
15c7ad51 1768 cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
f22f54f4
PZ		 1769
1770 if (WARN_ON_ONCE(!event))
1771 return;
1772
1773 intel_pmu_enable_bts(event->hw.config);
cecf6235 1774 }
f22f54f4
PZ		 1775}
1776
1a78d937
AK		 1777static void intel_pmu_enable_all(int added)
1778{
1779 __intel_pmu_enable_all(added, false);
1780}
1781
11164cd4
PZ		 1782/*
1783 * Workaround for:
1784 * Intel Errata AAK100 (model 26)
1785 * Intel Errata AAP53 (model 30)
40b91cd1 1786 * Intel Errata BD53 (model 44)
11164cd4 1787 *
351af072
ZY		 1788 * The official story:
1789 * These chips need to be 'reset' when adding counters by programming the
1790 * magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
1791 * in sequence on the same PMC or on different PMCs.
1792 *
1793 * In practise it appears some of these events do in fact count, and
1794 * we need to programm all 4 events.
11164cd4 1795 */
351af072 1796static void intel_pmu_nhm_workaround(void)
11164cd4 1797{
89cbc767 1798 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
351af072
ZY		 1799 static const unsigned long nhm_magic[4] = {
1800 0x4300B5,
1801 0x4300D2,
1802 0x4300B1,
1803 0x4300B1
1804 };
1805 struct perf_event *event;
1806 int i;
11164cd4 1807
351af072
ZY		 1808 /*
1809 * The Errata requires below steps:
1810 * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
1811 * 2) Configure 4 PERFEVTSELx with the magic events and clear
1812 * the corresponding PMCx;
1813 * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
1814 * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
1815 * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
1816 */
11164cd4 1817
351af072
ZY		 1818 /*
1819 * The real steps we choose are a little different from above.
1820 * A) To reduce MSR operations, we don't run step 1) as they
1821 * are already cleared before this function is called;
1822 * B) Call x86_perf_event_update to save PMCx before configuring
1823 * PERFEVTSELx with magic number;
1824 * C) With step 5), we do clear only when the PERFEVTSELx is
1825 * not used currently.
1826 * D) Call x86_perf_event_set_period to restore PMCx;
1827 */
11164cd4 1828
351af072
ZY		 1829 /* We always operate 4 pairs of PERF Counters */
1830 for (i = 0; i < 4; i++) {
1831 event = cpuc->events[i];
1832 if (event)
1833 x86_perf_event_update(event);
1834 }
11164cd4 1835
351af072
ZY		 1836 for (i = 0; i < 4; i++) {
1837 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
1838 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
1839 }
1840
1841 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
1842 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
11164cd4 1843
351af072
ZY		 1844 for (i = 0; i < 4; i++) {
1845 event = cpuc->events[i];
1846
1847 if (event) {
1848 x86_perf_event_set_period(event);
31fa58af 1849 __x86_pmu_enable_event(&event->hw,
351af072
ZY		 1850 ARCH_PERFMON_EVENTSEL_ENABLE);
1851 } else
1852 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
11164cd4 1853 }
351af072
ZY		 1854}
1855
1856static void intel_pmu_nhm_enable_all(int added)
1857{
1858 if (added)
1859 intel_pmu_nhm_workaround();
11164cd4
PZ		 1860 intel_pmu_enable_all(added);
1861}
1862
f22f54f4
PZ		 1863static inline u64 intel_pmu_get_status(void)
1864{
1865 u64 status;
1866
1867 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
1868
1869 return status;
1870}
1871
1872static inline void intel_pmu_ack_status(u64 ack)
1873{
1874 wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
1875}
1876
ca037701 1877static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
f22f54f4 1878{
15c7ad51 1879 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4
PZ		 1880 u64 ctrl_val, mask;
1881
1882 mask = 0xfULL << (idx * 4);
1883
1884 rdmsrl(hwc->config_base, ctrl_val);
1885 ctrl_val &= ~mask;
7645a24c 1886 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1887}
1888
2b9e344d
PZ		 1889static inline bool event_is_checkpointed(struct perf_event *event)
1890{
1891 return (event->hw.config & HSW_IN_TX_CHECKPOINTED) != 0;
1892}
1893
ca037701 1894static void intel_pmu_disable_event(struct perf_event *event)
f22f54f4 1895{
aff3d91a 1896 struct hw_perf_event *hwc = &event->hw;
89cbc767 1897 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1898
15c7ad51 1899 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
f22f54f4
PZ		 1900 intel_pmu_disable_bts();
1901 intel_pmu_drain_bts_buffer();
1902 return;
1903 }
1904
144d31e6
GN		 1905 cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
1906 cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
2b9e344d 1907 cpuc->intel_cp_status &= ~(1ull << hwc->idx);
144d31e6 1908
f22f54f4 1909 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1910 intel_pmu_disable_fixed(hwc);
f22f54f4
PZ		 1911 return;
1912 }
1913
aff3d91a 1914 x86_pmu_disable_event(event);
ca037701 1915
ab608344 1916 if (unlikely(event->attr.precise_ip))
ef21f683 1917 intel_pmu_pebs_disable(event);
f22f54f4
PZ		 1918}
1919
68f7082f
PZ		 1920static void intel_pmu_del_event(struct perf_event *event)
1921{
1922 if (needs_branch_stack(event))
1923 intel_pmu_lbr_del(event);
1924 if (event->attr.precise_ip)
1925 intel_pmu_pebs_del(event);
1926}
1927
ca037701 1928static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
f22f54f4 1929{
15c7ad51 1930 int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
f22f54f4 1931 u64 ctrl_val, bits, mask;
f22f54f4
PZ		 1932
1933 /*
1934 * Enable IRQ generation (0x8),
1935 * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
1936 * if requested:
1937 */
1938 bits = 0x8ULL;
1939 if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
1940 bits |= 0x2;
1941 if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
1942 bits |= 0x1;
1943
1944 /*
1945 * ANY bit is supported in v3 and up
1946 */
1947 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
1948 bits |= 0x4;
1949
1950 bits <<= (idx * 4);
1951 mask = 0xfULL << (idx * 4);
1952
1953 rdmsrl(hwc->config_base, ctrl_val);
1954 ctrl_val &= ~mask;
1955 ctrl_val |= bits;
7645a24c 1956 wrmsrl(hwc->config_base, ctrl_val);
f22f54f4
PZ		 1957}
1958
aff3d91a 1959static void intel_pmu_enable_event(struct perf_event *event)
f22f54f4 1960{
aff3d91a 1961 struct hw_perf_event *hwc = &event->hw;
89cbc767 1962 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
aff3d91a 1963
15c7ad51 1964 if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
0a3aee0d 1965 if (!__this_cpu_read(cpu_hw_events.enabled))
f22f54f4
PZ		 1966 return;
1967
1968 intel_pmu_enable_bts(hwc->config);
1969 return;
1970 }
1971
144d31e6
GN		 1972 if (event->attr.exclude_host)
1973 cpuc->intel_ctrl_guest_mask |= (1ull << hwc->idx);
1974 if (event->attr.exclude_guest)
1975 cpuc->intel_ctrl_host_mask |= (1ull << hwc->idx);
1976
2b9e344d
PZ		 1977 if (unlikely(event_is_checkpointed(event)))
1978 cpuc->intel_cp_status |= (1ull << hwc->idx);
1979
f22f54f4 1980 if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
aff3d91a 1981 intel_pmu_enable_fixed(hwc);
f22f54f4
PZ		 1982 return;
1983 }
1984
ab608344 1985 if (unlikely(event->attr.precise_ip))
ef21f683 1986 intel_pmu_pebs_enable(event);
ca037701 1987
31fa58af 1988 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
f22f54f4
PZ		 1989}
1990
68f7082f
PZ		 1991static void intel_pmu_add_event(struct perf_event *event)
1992{
1993 if (event->attr.precise_ip)
1994 intel_pmu_pebs_add(event);
1995 if (needs_branch_stack(event))
1996 intel_pmu_lbr_add(event);
1997}
1998
f22f54f4
PZ		 1999/*
2000 * Save and restart an expired event. Called by NMI contexts,
2001 * so it has to be careful about preempting normal event ops:
2002 */
de0428a7 2003int intel_pmu_save_and_restart(struct perf_event *event)
f22f54f4 2004{
cc2ad4ba 2005 x86_perf_event_update(event);
2dbf0116
AK		 2006 /*
2007 * For a checkpointed counter always reset back to 0. This
2008 * avoids a situation where the counter overflows, aborts the
2009 * transaction and is then set back to shortly before the
2010 * overflow, and overflows and aborts again.
2011 */
2012 if (unlikely(event_is_checkpointed(event))) {
2013 /* No race with NMIs because the counter should not be armed */
2014 wrmsrl(event->hw.event_base, 0);
2015 local64_set(&event->hw.prev_count, 0);
2016 }
cc2ad4ba 2017 return x86_perf_event_set_period(event);
f22f54f4
PZ		 2018}
2019
2020static void intel_pmu_reset(void)
2021{
0a3aee0d 2022 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
f22f54f4
PZ		 2023 unsigned long flags;
2024 int idx;
2025
948b1bb8 2026 if (!x86_pmu.num_counters)
f22f54f4
PZ		 2027 return;
2028
2029 local_irq_save(flags);
2030
c767a54b 2031 pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
f22f54f4 2032
948b1bb8 2033 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
715c85b1
PA		 2034 wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
2035 wrmsrl_safe(x86_pmu_event_addr(idx), 0ull);
f22f54f4 2036 }
948b1bb8 2037 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
715c85b1 2038 wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
948b1bb8 2039
f22f54f4
PZ		 2040 if (ds)
2041 ds->bts_index = ds->bts_buffer_base;
2042
8882edf7
AK		 2043 /* Ack all overflows and disable fixed counters */
2044 if (x86_pmu.version >= 2) {
2045 intel_pmu_ack_status(intel_pmu_get_status());
2046 wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
2047 }
2048
2049 /* Reset LBRs and LBR freezing */
2050 if (x86_pmu.lbr_nr) {
2051 update_debugctlmsr(get_debugctlmsr() &
2052 ~(DEBUGCTLMSR_FREEZE_LBRS_ON_PMI|DEBUGCTLMSR_LBR));
2053 }
2054
f22f54f4
PZ		 2055 local_irq_restore(flags);
2056}
2057
2058/*
2059 * This handler is triggered by the local APIC, so the APIC IRQ handling
2060 * rules apply:
2061 */
2062static int intel_pmu_handle_irq(struct pt_regs *regs)
2063{
2064 struct perf_sample_data data;
2065 struct cpu_hw_events *cpuc;
2066 int bit, loops;
2e556b5b 2067 u64 status;
b0b2072d 2068 int handled;
f22f54f4 2069
89cbc767 2070 cpuc = this_cpu_ptr(&cpu_hw_events);
f22f54f4 2071
2bce5dac 2072 /*
72db5596
AK		 2073 * No known reason to not always do late ACK,
2074 * but just in case do it opt-in.
2bce5dac 2075 */
72db5596
AK		 2076 if (!x86_pmu.late_ack)
2077 apic_write(APIC_LVTPC, APIC_DM_NMI);
cecf6235 2078 intel_bts_disable_local();
1a78d937 2079 __intel_pmu_disable_all();
b0b2072d 2080 handled = intel_pmu_drain_bts_buffer();
8062382c 2081 handled += intel_bts_interrupt();
f22f54f4 2082 status = intel_pmu_get_status();
a3ef2229
MM		 2083 if (!status)
2084 goto done;
f22f54f4
PZ		 2085
2086 loops = 0;
2087again:
0f29e573 2088 intel_pmu_lbr_read();
2e556b5b 2089 intel_pmu_ack_status(status);
f22f54f4 2090 if (++loops > 100) {
ae0def05
DH		 2091 static bool warned = false;
2092 if (!warned) {
2093 WARN(1, "perfevents: irq loop stuck!\n");
2094 perf_event_print_debug();
2095 warned = true;
2096 }
f22f54f4 2097 intel_pmu_reset();
3fb2b8dd 2098 goto done;
f22f54f4
PZ		 2099 }
2100
2101 inc_irq_stat(apic_perf_irqs);
ca037701 2102
caff2bef 2103
b292d7a1 2104 /*
d8020bee
AK		 2105 * Ignore a range of extra bits in status that do not indicate
2106 * overflow by themselves.
b292d7a1 2107 */
d8020bee
AK		 2108 status &= ~(GLOBAL_STATUS_COND_CHG |
2109 GLOBAL_STATUS_ASIF |
2110 GLOBAL_STATUS_LBRS_FROZEN);
2111 if (!status)
2112 goto done;
b292d7a1 2113
ca037701
PZ		 2114 /*
2115 * PEBS overflow sets bit 62 in the global status register
2116 */
de725dec
PZ		 2117 if (__test_and_clear_bit(62, (unsigned long *)&status)) {
2118 handled++;
ca037701 2119 x86_pmu.drain_pebs(regs);
8077eca0
SE		 2120 /*
2121 * There are cases where, even though, the PEBS ovfl bit is set
2122 * in GLOBAL_OVF_STATUS, the PEBS events may also have their
2123 * overflow bits set for their counters. We must clear them
2124 * here because they have been processed as exact samples in
2125 * the drain_pebs() routine. They must not be processed again
2126 * in the for_each_bit_set() loop for regular samples below.
2127 */
2128 status &= ~cpuc->pebs_enabled;
2129 status &= x86_pmu.intel_ctrl | GLOBAL_STATUS_TRACE_TOPAPMI;
de725dec 2130 }
ca037701 2131
52ca9ced
AS		 2132 /*
2133 * Intel PT
2134 */
2135 if (__test_and_clear_bit(55, (unsigned long *)&status)) {
2136 handled++;
2137 intel_pt_interrupt();
2138 }
2139
2dbf0116 2140 /*
2b9e344d
PZ		 2141 * Checkpointed counters can lead to 'spurious' PMIs because the
2142 * rollback caused by the PMI will have cleared the overflow status
2143 * bit. Therefore always force probe these counters.
2dbf0116 2144 */
2b9e344d 2145 status |= cpuc->intel_cp_status;
2dbf0116 2146
984b3f57 2147 for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
f22f54f4
PZ		 2148 struct perf_event *event = cpuc->events[bit];
2149
de725dec
PZ		 2150 handled++;
2151
f22f54f4
PZ		 2152 if (!test_bit(bit, cpuc->active_mask))
2153 continue;
2154
2155 if (!intel_pmu_save_and_restart(event))
2156 continue;
2157
fd0d000b 2158 perf_sample_data_init(&data, 0, event->hw.last_period);
f22f54f4 2159
60ce0fbd
SE		 2160 if (has_branch_stack(event))
2161 data.br_stack = &cpuc->lbr_stack;
2162
a8b0ca17 2163 if (perf_event_overflow(event, &data, regs))
a4eaf7f1 2164 x86_pmu_stop(event, 0);
f22f54f4
PZ		 2165 }
2166
f22f54f4
PZ		 2167 /*
2168 * Repeat if there is more work to be done:
2169 */
2170 status = intel_pmu_get_status();
2171 if (status)
2172 goto again;
2173
3fb2b8dd 2174done:
c3d266c8
KL		 2175 /* Only restore PMU state when it's active. See x86_pmu_disable(). */
2176 if (cpuc->enabled)
2177 __intel_pmu_enable_all(0, true);
cecf6235 2178 intel_bts_enable_local();
c3d266c8 2179
72db5596
AK		 2180 /*
2181 * Only unmask the NMI after the overflow counters
2182 * have been reset. This avoids spurious NMIs on
2183 * Haswell CPUs.
2184 */
2185 if (x86_pmu.late_ack)
2186 apic_write(APIC_LVTPC, APIC_DM_NMI);
de725dec 2187 return handled;
f22f54f4
PZ		 2188}
2189
f22f54f4 2190static struct event_constraint *
ca037701 2191intel_bts_constraints(struct perf_event *event)
f22f54f4 2192{
ca037701
PZ		 2193 struct hw_perf_event *hwc = &event->hw;
2194 unsigned int hw_event, bts_event;
f22f54f4 2195
18a073a3
PZ		 2196 if (event->attr.freq)
2197 return NULL;
2198
ca037701
PZ		 2199 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
2200 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
f22f54f4 2201
ca037701 2202 if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
f22f54f4 2203 return &bts_constraint;
ca037701 2204
f22f54f4
PZ		 2205 return NULL;
2206}
2207
ae3f011f 2208static int intel_alt_er(int idx, u64 config)
b79e8941 2209{
e01d8718
PZ		 2210 int alt_idx = idx;
2211
9a5e3fb5 2212 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1))
5a425294 2213 return idx;
b79e8941 2214
5a425294 2215 if (idx == EXTRA_REG_RSP_0)
ae3f011f 2216 alt_idx = EXTRA_REG_RSP_1;
5a425294
PZ		 2217
2218 if (idx == EXTRA_REG_RSP_1)
ae3f011f 2219 alt_idx = EXTRA_REG_RSP_0;
5a425294 2220
ae3f011f
KL		 2221 if (config & ~x86_pmu.extra_regs[alt_idx].valid_mask)
2222 return idx;
2223
2224 return alt_idx;
5a425294
PZ		 2225}
2226
2227static void intel_fixup_er(struct perf_event *event, int idx)
2228{
2229 event->hw.extra_reg.idx = idx;
2230
2231 if (idx == EXTRA_REG_RSP_0) {
b79e8941 2232 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 2233 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event;
b79e8941 2234 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_0;
5a425294
PZ		 2235 } else if (idx == EXTRA_REG_RSP_1) {
2236 event->hw.config &= ~INTEL_ARCH_EVENT_MASK;
53ad0447 2237 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event;
5a425294 2238 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1;
b79e8941 2239 }
b79e8941
PZ		 2240}
2241
efc9f05d
SE		 2242/*
2243 * manage allocation of shared extra msr for certain events
2244 *
2245 * sharing can be:
2246 * per-cpu: to be shared between the various events on a single PMU
2247 * per-core: per-cpu + shared by HT threads
2248 */
a7e3ed1e 2249static struct event_constraint *
efc9f05d 2250__intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
b36817e8
SE		 2251 struct perf_event *event,
2252 struct hw_perf_event_extra *reg)
a7e3ed1e 2253{
efc9f05d 2254 struct event_constraint *c = &emptyconstraint;
a7e3ed1e 2255 struct er_account *era;
cd8a38d3 2256 unsigned long flags;
5a425294 2257 int idx = reg->idx;
a7e3ed1e 2258
5a425294
PZ		 2259 /*
2260 * reg->alloc can be set due to existing state, so for fake cpuc we
2261 * need to ignore this, otherwise we might fail to allocate proper fake
2262 * state for this extra reg constraint. Also see the comment below.
2263 */
2264 if (reg->alloc && !cpuc->is_fake)
b36817e8 2265 return NULL; /* call x86_get_event_constraint() */
a7e3ed1e 2266
b79e8941 2267again:
5a425294 2268 era = &cpuc->shared_regs->regs[idx];
cd8a38d3
SE		 2269 /*
2270 * we use spin_lock_irqsave() to avoid lockdep issues when
2271 * passing a fake cpuc
2272 */
2273 raw_spin_lock_irqsave(&era->lock, flags);
efc9f05d
SE		 2274
2275 if (!atomic_read(&era->ref) || era->config == reg->config) {
2276
5a425294
PZ		 2277 /*
2278 * If its a fake cpuc -- as per validate_{group,event}() we
2279 * shouldn't touch event state and we can avoid doing so
2280 * since both will only call get_event_constraints() once
2281 * on each event, this avoids the need for reg->alloc.
2282 *
2283 * Not doing the ER fixup will only result in era->reg being
2284 * wrong, but since we won't actually try and program hardware
2285 * this isn't a problem either.
2286 */
2287 if (!cpuc->is_fake) {
2288 if (idx != reg->idx)
2289 intel_fixup_er(event, idx);
2290
2291 /*
2292 * x86_schedule_events() can call get_event_constraints()
2293 * multiple times on events in the case of incremental
2294 * scheduling(). reg->alloc ensures we only do the ER
2295 * allocation once.
2296 */
2297 reg->alloc = 1;
2298 }
2299
efc9f05d
SE		 2300 /* lock in msr value */
2301 era->config = reg->config;
2302 era->reg = reg->reg;
2303
2304 /* one more user */
2305 atomic_inc(&era->ref);
2306
a7e3ed1e 2307 /*
b36817e8
SE		 2308 * need to call x86_get_event_constraint()
2309 * to check if associated event has constraints
a7e3ed1e 2310 */
b36817e8 2311 c = NULL;
5a425294 2312 } else {
ae3f011f 2313 idx = intel_alt_er(idx, reg->config);
5a425294
PZ		 2314 if (idx != reg->idx) {
2315 raw_spin_unlock_irqrestore(&era->lock, flags);
2316 goto again;
2317 }
a7e3ed1e 2318 }
cd8a38d3 2319 raw_spin_unlock_irqrestore(&era->lock, flags);
a7e3ed1e 2320
efc9f05d
SE		 2321 return c;
2322}
2323
2324static void
2325__intel_shared_reg_put_constraints(struct cpu_hw_events *cpuc,
2326 struct hw_perf_event_extra *reg)
2327{
2328 struct er_account *era;
2329
2330 /*
5a425294
PZ		 2331 * Only put constraint if extra reg was actually allocated. Also takes
2332 * care of event which do not use an extra shared reg.
2333 *
2334 * Also, if this is a fake cpuc we shouldn't touch any event state
2335 * (reg->alloc) and we don't care about leaving inconsistent cpuc state
2336 * either since it'll be thrown out.
efc9f05d 2337 */
5a425294 2338 if (!reg->alloc || cpuc->is_fake)
efc9f05d
SE		 2339 return;
2340
2341 era = &cpuc->shared_regs->regs[reg->idx];
2342
2343 /* one fewer user */
2344 atomic_dec(&era->ref);
2345
2346 /* allocate again next time */
2347 reg->alloc = 0;
2348}
2349
2350static struct event_constraint *
2351intel_shared_regs_constraints(struct cpu_hw_events *cpuc,
2352 struct perf_event *event)
2353{
b36817e8
SE		 2354 struct event_constraint *c = NULL, *d;
2355 struct hw_perf_event_extra *xreg, *breg;
2356
2357 xreg = &event->hw.extra_reg;
2358 if (xreg->idx != EXTRA_REG_NONE) {
2359 c = __intel_shared_reg_get_constraints(cpuc, event, xreg);
2360 if (c == &emptyconstraint)
2361 return c;
2362 }
2363 breg = &event->hw.branch_reg;
2364 if (breg->idx != EXTRA_REG_NONE) {
2365 d = __intel_shared_reg_get_constraints(cpuc, event, breg);
2366 if (d == &emptyconstraint) {
2367 __intel_shared_reg_put_constraints(cpuc, xreg);
2368 c = d;
2369 }
2370 }
efc9f05d 2371 return c;
a7e3ed1e
AK		 2372}
2373
de0428a7 2374struct event_constraint *
79cba822
SE		 2375x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2376 struct perf_event *event)
de0428a7
KW		 2377{
2378 struct event_constraint *c;
2379
2380 if (x86_pmu.event_constraints) {
2381 for_each_event_constraint(c, x86_pmu.event_constraints) {
9fac2cf3 2382 if ((event->hw.config & c->cmask) == c->code) {
9fac2cf3 2383 event->hw.flags |= c->flags;
de0428a7 2384 return c;
9fac2cf3 2385 }
de0428a7
KW		 2386 }
2387 }
2388
2389 return &unconstrained;
2390}
2391
f22f54f4 2392static struct event_constraint *
e979121b 2393__intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
79cba822 2394 struct perf_event *event)
f22f54f4
PZ		 2395{
2396 struct event_constraint *c;
2397
ca037701
PZ		 2398 c = intel_bts_constraints(event);
2399 if (c)
2400 return c;
2401
687805e4 2402 c = intel_shared_regs_constraints(cpuc, event);
f22f54f4
PZ		 2403 if (c)
2404 return c;
2405
687805e4 2406 c = intel_pebs_constraints(event);
a7e3ed1e
AK		 2407 if (c)
2408 return c;
2409
79cba822 2410 return x86_get_event_constraints(cpuc, idx, event);
f22f54f4
PZ		 2411}
2412
e979121b
MD		 2413static void
2414intel_start_scheduling(struct cpu_hw_events *cpuc)
2415{
2416 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2417 struct intel_excl_states *xl;
e979121b 2418 int tid = cpuc->excl_thread_id;
e979121b
MD		 2419
2420 /*
2421 * nothing needed if in group validation mode
2422 */
b37609c3 2423 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b 2424 return;
b37609c3 2425
e979121b
MD		 2426 /*
2427 * no exclusion needed
2428 */
17186ccd 2429 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2430 return;
2431
e979121b
MD		 2432 xl = &excl_cntrs->states[tid];
2433
2434 xl->sched_started = true;
e979121b
MD		 2435 /*
2436 * lock shared state until we are done scheduling
2437 * in stop_event_scheduling()
2438 * makes scheduling appear as a transaction
2439 */
e979121b 2440 raw_spin_lock(&excl_cntrs->lock);
e979121b
MD		 2441}
2442
0c41e756
PZ		 2443static void intel_commit_scheduling(struct cpu_hw_events *cpuc, int idx, int cntr)
2444{
2445 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
2446 struct event_constraint *c = cpuc->event_constraint[idx];
2447 struct intel_excl_states *xl;
2448 int tid = cpuc->excl_thread_id;
2449
2450 if (cpuc->is_fake || !is_ht_workaround_enabled())
2451 return;
2452
2453 if (WARN_ON_ONCE(!excl_cntrs))
2454 return;
2455
2456 if (!(c->flags & PERF_X86_EVENT_DYNAMIC))
2457 return;
2458
2459 xl = &excl_cntrs->states[tid];
2460
2461 lockdep_assert_held(&excl_cntrs->lock);
2462
1fe684e3 2463 if (c->flags & PERF_X86_EVENT_EXCL)
43ef205b 2464 xl->state[cntr] = INTEL_EXCL_EXCLUSIVE;
1fe684e3 2465 else
43ef205b 2466 xl->state[cntr] = INTEL_EXCL_SHARED;
0c41e756
PZ		 2467}
2468
e979121b
MD		 2469static void
2470intel_stop_scheduling(struct cpu_hw_events *cpuc)
2471{
2472 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2473 struct intel_excl_states *xl;
e979121b 2474 int tid = cpuc->excl_thread_id;
e979121b
MD		 2475
2476 /*
2477 * nothing needed if in group validation mode
2478 */
b37609c3 2479 if (cpuc->is_fake || !is_ht_workaround_enabled())
e979121b
MD		 2480 return;
2481 /*
2482 * no exclusion needed
2483 */
17186ccd 2484 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2485 return;
2486
e979121b
MD		 2487 xl = &excl_cntrs->states[tid];
2488
e979121b
MD		 2489 xl->sched_started = false;
2490 /*
2491 * release shared state lock (acquired in intel_start_scheduling())
2492 */
2493 raw_spin_unlock(&excl_cntrs->lock);
2494}
2495
2496static struct event_constraint *
2497intel_get_excl_constraints(struct cpu_hw_events *cpuc, struct perf_event *event,
2498 int idx, struct event_constraint *c)
2499{
e979121b 2500 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
1c565833 2501 struct intel_excl_states *xlo;
e979121b 2502 int tid = cpuc->excl_thread_id;
1c565833 2503 int is_excl, i;
e979121b
MD		 2504
2505 /*
2506 * validating a group does not require
2507 * enforcing cross-thread exclusion
2508 */
b37609c3
SE		 2509 if (cpuc->is_fake || !is_ht_workaround_enabled())
2510 return c;
2511
2512 /*
2513 * no exclusion needed
2514 */
17186ccd 2515 if (WARN_ON_ONCE(!excl_cntrs))
e979121b 2516 return c;
e979121b 2517
e979121b
MD		 2518 /*
2519 * because we modify the constraint, we need
2520 * to make a copy. Static constraints come
2521 * from static const tables.
2522 *
2523 * only needed when constraint has not yet
2524 * been cloned (marked dynamic)
2525 */
2526 if (!(c->flags & PERF_X86_EVENT_DYNAMIC)) {
aaf932e8 2527 struct event_constraint *cx;
e979121b 2528
e979121b
MD		 2529 /*
2530 * grab pre-allocated constraint entry
2531 */
2532 cx = &cpuc->constraint_list[idx];
2533
2534 /*
2535 * initialize dynamic constraint
2536 * with static constraint
2537 */
aaf932e8 2538 *cx = *c;
e979121b
MD		 2539
2540 /*
2541 * mark constraint as dynamic, so we
2542 * can free it later on
2543 */
2544 cx->flags |= PERF_X86_EVENT_DYNAMIC;
aaf932e8 2545 c = cx;
e979121b
MD		 2546 }
2547
2548 /*
2549 * From here on, the constraint is dynamic.
2550 * Either it was just allocated above, or it
2551 * was allocated during a earlier invocation
2552 * of this function
2553 */
2554
1c565833
PZ		 2555 /*
2556 * state of sibling HT
2557 */
2558 xlo = &excl_cntrs->states[tid ^ 1];
2559
2560 /*
2561 * event requires exclusive counter access
2562 * across HT threads
2563 */
2564 is_excl = c->flags & PERF_X86_EVENT_EXCL;
2565 if (is_excl && !(event->hw.flags & PERF_X86_EVENT_EXCL_ACCT)) {
2566 event->hw.flags |= PERF_X86_EVENT_EXCL_ACCT;
2567 if (!cpuc->n_excl++)
2568 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 1);
2569 }
2570
e979121b
MD		 2571 /*
2572 * Modify static constraint with current dynamic
2573 * state of thread
2574 *
2575 * EXCLUSIVE: sibling counter measuring exclusive event
2576 * SHARED : sibling counter measuring non-exclusive event
2577 * UNUSED : sibling counter unused
2578 */
aaf932e8 2579 for_each_set_bit(i, c->idxmsk, X86_PMC_IDX_MAX) {
e979121b
MD		 2580 /*
2581 * exclusive event in sibling counter
2582 * our corresponding counter cannot be used
2583 * regardless of our event
2584 */
1c565833 2585 if (xlo->state[i] == INTEL_EXCL_EXCLUSIVE)
aaf932e8 2586 __clear_bit(i, c->idxmsk);
e979121b
MD		 2587 /*
2588 * if measuring an exclusive event, sibling
2589 * measuring non-exclusive, then counter cannot
2590 * be used
2591 */
1c565833 2592 if (is_excl && xlo->state[i] == INTEL_EXCL_SHARED)
aaf932e8 2593 __clear_bit(i, c->idxmsk);
e979121b
MD		 2594 }
2595
2596 /*
2597 * recompute actual bit weight for scheduling algorithm
2598 */
aaf932e8 2599 c->weight = hweight64(c->idxmsk64);
e979121b
MD		 2600
2601 /*
2602 * if we return an empty mask, then switch
2603 * back to static empty constraint to avoid
2604 * the cost of freeing later on
2605 */
aaf932e8
PZ		 2606 if (c->weight == 0)
2607 c = &emptyconstraint;
e979121b 2608
aaf932e8 2609 return c;
e979121b
MD		 2610}
2611
2612static struct event_constraint *
2613intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2614 struct perf_event *event)
2615{
ebfb4988 2616 struct event_constraint *c1 = NULL;
a90738c2 2617 struct event_constraint *c2;
e979121b 2618
ebfb4988
PZ		 2619 if (idx >= 0) /* fake does < 0 */
2620 c1 = cpuc->event_constraint[idx];
2621
e979121b
MD		 2622 /*
2623 * first time only
2624 * - static constraint: no change across incremental scheduling calls
2625 * - dynamic constraint: handled by intel_get_excl_constraints()
2626 */
a90738c2
SE		 2627 c2 = __intel_get_event_constraints(cpuc, idx, event);
2628 if (c1 && (c1->flags & PERF_X86_EVENT_DYNAMIC)) {
2629 bitmap_copy(c1->idxmsk, c2->idxmsk, X86_PMC_IDX_MAX);
2630 c1->weight = c2->weight;
2631 c2 = c1;
2632 }
e979121b
MD		 2633
2634 if (cpuc->excl_cntrs)
a90738c2 2635 return intel_get_excl_constraints(cpuc, event, idx, c2);
e979121b 2636
a90738c2 2637 return c2;
e979121b
MD		 2638}
2639
2640static void intel_put_excl_constraints(struct cpu_hw_events *cpuc,
2641 struct perf_event *event)
2642{
2643 struct hw_perf_event *hwc = &event->hw;
2644 struct intel_excl_cntrs *excl_cntrs = cpuc->excl_cntrs;
e979121b 2645 int tid = cpuc->excl_thread_id;
1c565833 2646 struct intel_excl_states *xl;
e979121b
MD		 2647
2648 /*
2649 * nothing needed if in group validation mode
2650 */
2651 if (cpuc->is_fake)
2652 return;
2653
17186ccd 2654 if (WARN_ON_ONCE(!excl_cntrs))
e979121b
MD		 2655 return;
2656
cc1790cf
PZ		 2657 if (hwc->flags & PERF_X86_EVENT_EXCL_ACCT) {
2658 hwc->flags &= ~PERF_X86_EVENT_EXCL_ACCT;
2659 if (!--cpuc->n_excl)
2660 WRITE_ONCE(excl_cntrs->has_exclusive[tid], 0);
2661 }
e979121b
MD		 2662
2663 /*
ba040653
PZ		 2664 * If event was actually assigned, then mark the counter state as
2665 * unused now.
e979121b 2666 */
ba040653
PZ		 2667 if (hwc->idx >= 0) {
2668 xl = &excl_cntrs->states[tid];
2669
2670 /*
2671 * put_constraint may be called from x86_schedule_events()
2672 * which already has the lock held so here make locking
2673 * conditional.
2674 */
2675 if (!xl->sched_started)
2676 raw_spin_lock(&excl_cntrs->lock);
e979121b 2677
1c565833 2678 xl->state[hwc->idx] = INTEL_EXCL_UNUSED;
e979121b 2679
ba040653
PZ		 2680 if (!xl->sched_started)
2681 raw_spin_unlock(&excl_cntrs->lock);
2682 }
e979121b
MD		 2683}
2684
efc9f05d
SE		 2685static void
2686intel_put_shared_regs_event_constraints(struct cpu_hw_events *cpuc,
a7e3ed1e
AK		 2687 struct perf_event *event)
2688{
efc9f05d 2689 struct hw_perf_event_extra *reg;
a7e3ed1e 2690
efc9f05d
SE		 2691 reg = &event->hw.extra_reg;
2692 if (reg->idx != EXTRA_REG_NONE)
2693 __intel_shared_reg_put_constraints(cpuc, reg);
b36817e8
SE		 2694
2695 reg = &event->hw.branch_reg;
2696 if (reg->idx != EXTRA_REG_NONE)
2697 __intel_shared_reg_put_constraints(cpuc, reg);
efc9f05d 2698}
a7e3ed1e 2699
efc9f05d
SE		 2700static void intel_put_event_constraints(struct cpu_hw_events *cpuc,
2701 struct perf_event *event)
2702{
2703 intel_put_shared_regs_event_constraints(cpuc, event);
e979121b
MD		 2704
2705 /*
2706 * is PMU has exclusive counter restrictions, then
2707 * all events are subject to and must call the
2708 * put_excl_constraints() routine
2709 */
b371b594 2710 if (cpuc->excl_cntrs)
e979121b 2711 intel_put_excl_constraints(cpuc, event);
e979121b
MD		 2712}
2713
0780c927 2714static void intel_pebs_aliases_core2(struct perf_event *event)
b4cdc5c2 2715{
0780c927 2716 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
7639dae0
PZ		 2717 /*
2718 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2719 * (0x003c) so that we can use it with PEBS.
2720 *
2721 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2722 * PEBS capable. However we can use INST_RETIRED.ANY_P
2723 * (0x00c0), which is a PEBS capable event, to get the same
2724 * count.
2725 *
2726 * INST_RETIRED.ANY_P counts the number of cycles that retires
2727 * CNTMASK instructions. By setting CNTMASK to a value (16)
2728 * larger than the maximum number of instructions that can be
2729 * retired per cycle (4) and then inverting the condition, we
2730 * count all cycles that retire 16 or less instructions, which
2731 * is every cycle.
2732 *
2733 * Thereby we gain a PEBS capable cycle counter.
2734 */
f9b4eeb8
PZ		 2735 u64 alt_config = X86_CONFIG(.event=0xc0, .inv=1, .cmask=16);
2736
0780c927
PZ		 2737 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2738 event->hw.config = alt_config;
2739 }
2740}
2741
2742static void intel_pebs_aliases_snb(struct perf_event *event)
2743{
2744 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2745 /*
2746 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2747 * (0x003c) so that we can use it with PEBS.
2748 *
2749 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2750 * PEBS capable. However we can use UOPS_RETIRED.ALL
2751 * (0x01c2), which is a PEBS capable event, to get the same
2752 * count.
2753 *
2754 * UOPS_RETIRED.ALL counts the number of cycles that retires
2755 * CNTMASK micro-ops. By setting CNTMASK to a value (16)
2756 * larger than the maximum number of micro-ops that can be
2757 * retired per cycle (4) and then inverting the condition, we
2758 * count all cycles that retire 16 or less micro-ops, which
2759 * is every cycle.
2760 *
2761 * Thereby we gain a PEBS capable cycle counter.
2762 */
2763 u64 alt_config = X86_CONFIG(.event=0xc2, .umask=0x01, .inv=1, .cmask=16);
7639dae0
PZ		 2764
2765 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2766 event->hw.config = alt_config;
2767 }
0780c927
PZ		 2768}
2769
72469764
AK		 2770static void intel_pebs_aliases_precdist(struct perf_event *event)
2771{
2772 if ((event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
2773 /*
2774 * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
2775 * (0x003c) so that we can use it with PEBS.
2776 *
2777 * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
2778 * PEBS capable. However we can use INST_RETIRED.PREC_DIST
2779 * (0x01c0), which is a PEBS capable event, to get the same
2780 * count.
2781 *
2782 * The PREC_DIST event has special support to minimize sample
2783 * shadowing effects. One drawback is that it can be
2784 * only programmed on counter 1, but that seems like an
2785 * acceptable trade off.
2786 */
2787 u64 alt_config = X86_CONFIG(.event=0xc0, .umask=0x01, .inv=1, .cmask=16);
2788
2789 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
2790 event->hw.config = alt_config;
2791 }
2792}
2793
2794static void intel_pebs_aliases_ivb(struct perf_event *event)
2795{
2796 if (event->attr.precise_ip < 3)
2797 return intel_pebs_aliases_snb(event);
2798 return intel_pebs_aliases_precdist(event);
2799}
2800
2801static void intel_pebs_aliases_skl(struct perf_event *event)
2802{
2803 if (event->attr.precise_ip < 3)
2804 return intel_pebs_aliases_core2(event);
2805 return intel_pebs_aliases_precdist(event);
2806}
2807
a7b58d21
AK		 2808static unsigned long intel_pmu_free_running_flags(struct perf_event *event)
2809{
2810 unsigned long flags = x86_pmu.free_running_flags;
2811
2812 if (event->attr.use_clockid)
2813 flags &= ~PERF_SAMPLE_TIME;
2814 return flags;
2815}
2816
0780c927
PZ		 2817static int intel_pmu_hw_config(struct perf_event *event)
2818{
2819 int ret = x86_pmu_hw_config(event);
2820
2821 if (ret)
2822 return ret;
2823
851559e3 2824 if (event->attr.precise_ip) {
3569c0d7 2825 if (!event->attr.freq) {
851559e3 2826 event->hw.flags |= PERF_X86_EVENT_AUTO_RELOAD;
a7b58d21
AK		 2827 if (!(event->attr.sample_type &
2828 ~intel_pmu_free_running_flags(event)))
3569c0d7
YZ		 2829 event->hw.flags |= PERF_X86_EVENT_FREERUNNING;
2830 }
851559e3
YZ		 2831 if (x86_pmu.pebs_aliases)
2832 x86_pmu.pebs_aliases(event);
2833 }
7639dae0 2834
a46a2300 2835 if (needs_branch_stack(event)) {
60ce0fbd
SE		 2836 ret = intel_pmu_setup_lbr_filter(event);
2837 if (ret)
2838 return ret;
48070342
AS		 2839
2840 /*
2841 * BTS is set up earlier in this path, so don't account twice
2842 */
2843 if (!intel_pmu_has_bts(event)) {
2844 /* disallow lbr if conflicting events are present */
2845 if (x86_add_exclusive(x86_lbr_exclusive_lbr))
2846 return -EBUSY;
2847
2848 event->destroy = hw_perf_lbr_event_destroy;
2849 }
60ce0fbd
SE		 2850 }
2851
b4cdc5c2
PZ		 2852 if (event->attr.type != PERF_TYPE_RAW)
2853 return 0;
2854
2855 if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
2856 return 0;
2857
2858 if (x86_pmu.version < 3)
2859 return -EINVAL;
2860
2861 if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
2862 return -EACCES;
2863
2864 event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
2865
2866 return 0;
2867}
2868
144d31e6
GN		 2869struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr)
2870{
2871 if (x86_pmu.guest_get_msrs)
2872 return x86_pmu.guest_get_msrs(nr);
2873 *nr = 0;
2874 return NULL;
2875}
2876EXPORT_SYMBOL_GPL(perf_guest_get_msrs);
2877
2878static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr)
2879{
89cbc767 2880 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2881 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2882
2883 arr[0].msr = MSR_CORE_PERF_GLOBAL_CTRL;
2884 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask;
2885 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask;
26a4f3c0
GN		 2886 /*
2887 * If PMU counter has PEBS enabled it is not enough to disable counter
2888 * on a guest entry since PEBS memory write can overshoot guest entry
2889 * and corrupt guest memory. Disabling PEBS solves the problem.
2890 */
2891 arr[1].msr = MSR_IA32_PEBS_ENABLE;
2892 arr[1].host = cpuc->pebs_enabled;
2893 arr[1].guest = 0;
144d31e6 2894
26a4f3c0 2895 *nr = 2;
144d31e6
GN		 2896 return arr;
2897}
2898
2899static struct perf_guest_switch_msr *core_guest_get_msrs(int *nr)
2900{
89cbc767 2901 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2902 struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
2903 int idx;
2904
2905 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2906 struct perf_event *event = cpuc->events[idx];
2907
2908 arr[idx].msr = x86_pmu_config_addr(idx);
2909 arr[idx].host = arr[idx].guest = 0;
2910
2911 if (!test_bit(idx, cpuc->active_mask))
2912 continue;
2913
2914 arr[idx].host = arr[idx].guest =
2915 event->hw.config | ARCH_PERFMON_EVENTSEL_ENABLE;
2916
2917 if (event->attr.exclude_host)
2918 arr[idx].host &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2919 else if (event->attr.exclude_guest)
2920 arr[idx].guest &= ~ARCH_PERFMON_EVENTSEL_ENABLE;
2921 }
2922
2923 *nr = x86_pmu.num_counters;
2924 return arr;
2925}
2926
2927static void core_pmu_enable_event(struct perf_event *event)
2928{
2929 if (!event->attr.exclude_host)
2930 x86_pmu_enable_event(event);
2931}
2932
2933static void core_pmu_enable_all(int added)
2934{
89cbc767 2935 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
144d31e6
GN		 2936 int idx;
2937
2938 for (idx = 0; idx < x86_pmu.num_counters; idx++) {
2939 struct hw_perf_event *hwc = &cpuc->events[idx]->hw;
2940
2941 if (!test_bit(idx, cpuc->active_mask) ||
2942 cpuc->events[idx]->attr.exclude_host)
2943 continue;
2944
2945 __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
2946 }
2947}
2948
3a632cb2
AK		 2949static int hsw_hw_config(struct perf_event *event)
2950{
2951 int ret = intel_pmu_hw_config(event);
2952
2953 if (ret)
2954 return ret;
2955 if (!boot_cpu_has(X86_FEATURE_RTM) && !boot_cpu_has(X86_FEATURE_HLE))
2956 return 0;
2957 event->hw.config |= event->attr.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED);
2958
2959 /*
2960 * IN_TX/IN_TX-CP filters are not supported by the Haswell PMU with
2961 * PEBS or in ANY thread mode. Since the results are non-sensical forbid
2962 * this combination.
2963 */
2964 if ((event->hw.config & (HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)) &&
2965 ((event->hw.config & ARCH_PERFMON_EVENTSEL_ANY) ||
2966 event->attr.precise_ip > 0))
2967 return -EOPNOTSUPP;
2968
2dbf0116
AK		 2969 if (event_is_checkpointed(event)) {
2970 /*
2971 * Sampling of checkpointed events can cause situations where
2972 * the CPU constantly aborts because of a overflow, which is
2973 * then checkpointed back and ignored. Forbid checkpointing
2974 * for sampling.
2975 *
2976 * But still allow a long sampling period, so that perf stat
2977 * from KVM works.
2978 */
2979 if (event->attr.sample_period > 0 &&
2980 event->attr.sample_period < 0x7fffffff)
2981 return -EOPNOTSUPP;
2982 }
3a632cb2
AK		 2983 return 0;
2984}
2985
2986static struct event_constraint counter2_constraint =
2987 EVENT_CONSTRAINT(0, 0x4, 0);
2988
2989static struct event_constraint *
79cba822
SE		 2990hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
2991 struct perf_event *event)
3a632cb2 2992{
79cba822
SE		 2993 struct event_constraint *c;
2994
2995 c = intel_get_event_constraints(cpuc, idx, event);
3a632cb2
AK		 2996
2997 /* Handle special quirk on in_tx_checkpointed only in counter 2 */
2998 if (event->hw.config & HSW_IN_TX_CHECKPOINTED) {
2999 if (c->idxmsk64 & (1U << 2))
3000 return &counter2_constraint;
3001 return &emptyconstraint;
3002 }
3003
3004 return c;
3005}
3006
294fe0f5
AK		 3007/*
3008 * Broadwell:
3009 *
3010 * The INST_RETIRED.ALL period always needs to have lowest 6 bits cleared
3011 * (BDM55) and it must not use a period smaller than 100 (BDM11). We combine
3012 * the two to enforce a minimum period of 128 (the smallest value that has bits
3013 * 0-5 cleared and >= 100).
3014 *
3015 * Because of how the code in x86_perf_event_set_period() works, the truncation
3016 * of the lower 6 bits is 'harmless' as we'll occasionally add a longer period
3017 * to make up for the 'lost' events due to carrying the 'error' in period_left.
3018 *
3019 * Therefore the effective (average) period matches the requested period,
3020 * despite coarser hardware granularity.
3021 */
3022static unsigned bdw_limit_period(struct perf_event *event, unsigned left)
3023{
3024 if ((event->hw.config & INTEL_ARCH_EVENT_MASK) ==
3025 X86_CONFIG(.event=0xc0, .umask=0x01)) {
3026 if (left < 128)
3027 left = 128;
3028 left &= ~0x3fu;
3029 }
3030 return left;
3031}
3032
641cc938
JO		 3033PMU_FORMAT_ATTR(event, "config:0-7" );
3034PMU_FORMAT_ATTR(umask, "config:8-15" );
3035PMU_FORMAT_ATTR(edge, "config:18" );
3036PMU_FORMAT_ATTR(pc, "config:19" );
3037PMU_FORMAT_ATTR(any, "config:21" ); /* v3 + */
3038PMU_FORMAT_ATTR(inv, "config:23" );
3039PMU_FORMAT_ATTR(cmask, "config:24-31" );
3a632cb2
AK		 3040PMU_FORMAT_ATTR(in_tx, "config:32");
3041PMU_FORMAT_ATTR(in_tx_cp, "config:33");
641cc938
JO		 3042
3043static struct attribute *intel_arch_formats_attr[] = {
3044 &format_attr_event.attr,
3045 &format_attr_umask.attr,
3046 &format_attr_edge.attr,
3047 &format_attr_pc.attr,
3048 &format_attr_inv.attr,
3049 &format_attr_cmask.attr,
3050 NULL,
3051};
3052
0bf79d44
JO		 3053ssize_t intel_event_sysfs_show(char *page, u64 config)
3054{
3055 u64 event = (config & ARCH_PERFMON_EVENTSEL_EVENT);
3056
3057 return x86_event_sysfs_show(page, config, event);
3058}
3059
de0428a7 3060struct intel_shared_regs *allocate_shared_regs(int cpu)
efc9f05d
SE		 3061{
3062 struct intel_shared_regs *regs;
3063 int i;
3064
3065 regs = kzalloc_node(sizeof(struct intel_shared_regs),
3066 GFP_KERNEL, cpu_to_node(cpu));
3067 if (regs) {
3068 /*
3069 * initialize the locks to keep lockdep happy
3070 */
3071 for (i = 0; i < EXTRA_REG_MAX; i++)
3072 raw_spin_lock_init(&regs->regs[i].lock);
3073
3074 regs->core_id = -1;
3075 }
3076 return regs;
3077}
3078
6f6539ca
MD		 3079static struct intel_excl_cntrs *allocate_excl_cntrs(int cpu)
3080{
3081 struct intel_excl_cntrs *c;
6f6539ca
MD		 3082
3083 c = kzalloc_node(sizeof(struct intel_excl_cntrs),
3084 GFP_KERNEL, cpu_to_node(cpu));
3085 if (c) {
3086 raw_spin_lock_init(&c->lock);
6f6539ca
MD		 3087 c->core_id = -1;
3088 }
3089 return c;
3090}
3091
a7e3ed1e
AK		 3092static int intel_pmu_cpu_prepare(int cpu)
3093{
3094 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3095
6f6539ca
MD		 3096 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) {
3097 cpuc->shared_regs = allocate_shared_regs(cpu);
3098 if (!cpuc->shared_regs)
dbc72b7a 3099 goto err;
6f6539ca 3100 }
69092624 3101
6f6539ca
MD		 3102 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
3103 size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint);
3104
3105 cpuc->constraint_list = kzalloc(sz, GFP_KERNEL);
3106 if (!cpuc->constraint_list)
dbc72b7a 3107 goto err_shared_regs;
6f6539ca
MD		 3108
3109 cpuc->excl_cntrs = allocate_excl_cntrs(cpu);
dbc72b7a
PZ		 3110 if (!cpuc->excl_cntrs)
3111 goto err_constraint_list;
3112
6f6539ca
MD		 3113 cpuc->excl_thread_id = 0;
3114 }
a7e3ed1e 3115
95ca792c 3116 return 0;
dbc72b7a
PZ		 3117
3118err_constraint_list:
3119 kfree(cpuc->constraint_list);
3120 cpuc->constraint_list = NULL;
3121
3122err_shared_regs:
3123 kfree(cpuc->shared_regs);
3124 cpuc->shared_regs = NULL;
3125
3126err:
95ca792c 3127 return -ENOMEM;
a7e3ed1e
AK		 3128}
3129
74846d35
PZ		 3130static void intel_pmu_cpu_starting(int cpu)
3131{
a7e3ed1e
AK		 3132 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3133 int core_id = topology_core_id(cpu);
3134 int i;
3135
69092624
LM		 3136 init_debug_store_on_cpu(cpu);
3137 /*
3138 * Deal with CPUs that don't clear their LBRs on power-up.
3139 */
3140 intel_pmu_lbr_reset();
3141
b36817e8
SE		 3142 cpuc->lbr_sel = NULL;
3143
3144 if (!cpuc->shared_regs)
69092624
LM		 3145 return;
3146
9a5e3fb5 3147 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) {
06931e62 3148 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
b36817e8 3149 struct intel_shared_regs *pc;
a7e3ed1e 3150
b36817e8
SE		 3151 pc = per_cpu(cpu_hw_events, i).shared_regs;
3152 if (pc && pc->core_id == core_id) {
8f04b853 3153 cpuc->kfree_on_online[0] = cpuc->shared_regs;
b36817e8
SE		 3154 cpuc->shared_regs = pc;
3155 break;
3156 }
a7e3ed1e 3157 }
b36817e8
SE		 3158 cpuc->shared_regs->core_id = core_id;
3159 cpuc->shared_regs->refcnt++;
a7e3ed1e
AK		 3160 }
3161
b36817e8
SE		 3162 if (x86_pmu.lbr_sel_map)
3163 cpuc->lbr_sel = &cpuc->shared_regs->regs[EXTRA_REG_LBR];
6f6539ca
MD		 3164
3165 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) {
06931e62 3166 for_each_cpu(i, topology_sibling_cpumask(cpu)) {
6f6539ca
MD		 3167 struct intel_excl_cntrs *c;
3168
3169 c = per_cpu(cpu_hw_events, i).excl_cntrs;
3170 if (c && c->core_id == core_id) {
3171 cpuc->kfree_on_online[1] = cpuc->excl_cntrs;
3172 cpuc->excl_cntrs = c;
3173 cpuc->excl_thread_id = 1;
3174 break;
3175 }
3176 }
3177 cpuc->excl_cntrs->core_id = core_id;
3178 cpuc->excl_cntrs->refcnt++;
3179 }
74846d35
PZ		 3180}
3181
b37609c3 3182static void free_excl_cntrs(int cpu)
74846d35 3183{
a7e3ed1e 3184 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
6f6539ca 3185 struct intel_excl_cntrs *c;
a7e3ed1e 3186
6f6539ca
MD		 3187 c = cpuc->excl_cntrs;
3188 if (c) {
3189 if (c->core_id == -1 || --c->refcnt == 0)
3190 kfree(c);
3191 cpuc->excl_cntrs = NULL;
3192 kfree(cpuc->constraint_list);
3193 cpuc->constraint_list = NULL;
3194 }
b37609c3 3195}
a7e3ed1e 3196
b37609c3
SE		 3197static void intel_pmu_cpu_dying(int cpu)
3198{
3199 struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
3200 struct intel_shared_regs *pc;
3201
3202 pc = cpuc->shared_regs;
3203 if (pc) {
3204 if (pc->core_id == -1 || --pc->refcnt == 0)
3205 kfree(pc);
3206 cpuc->shared_regs = NULL;
e979121b
MD		 3207 }
3208
b37609c3
SE		 3209 free_excl_cntrs(cpu);
3210
74846d35
PZ		 3211 fini_debug_store_on_cpu(cpu);
3212}
3213
9c964efa
YZ		 3214static void intel_pmu_sched_task(struct perf_event_context *ctx,
3215 bool sched_in)
3216{
3217 if (x86_pmu.pebs_active)
3218 intel_pmu_pebs_sched_task(ctx, sched_in);
3219 if (x86_pmu.lbr_nr)
3220 intel_pmu_lbr_sched_task(ctx, sched_in);
3221}
3222
641cc938
JO		 3223PMU_FORMAT_ATTR(offcore_rsp, "config1:0-63");
3224
a63fcab4
SE		 3225PMU_FORMAT_ATTR(ldlat, "config1:0-15");
3226
d0dc8494
AK		 3227PMU_FORMAT_ATTR(frontend, "config1:0-23");
3228
641cc938
JO		 3229static struct attribute *intel_arch3_formats_attr[] = {
3230 &format_attr_event.attr,
3231 &format_attr_umask.attr,
3232 &format_attr_edge.attr,
3233 &format_attr_pc.attr,
3234 &format_attr_any.attr,
3235 &format_attr_inv.attr,
3236 &format_attr_cmask.attr,
3a632cb2
AK		 3237 &format_attr_in_tx.attr,
3238 &format_attr_in_tx_cp.attr,
641cc938
JO		 3239
3240 &format_attr_offcore_rsp.attr, /* XXX do NHM/WSM + SNB breakout */
a63fcab4 3241 &format_attr_ldlat.attr, /* PEBS load latency */
641cc938
JO		 3242 NULL,
3243};
3244
d0dc8494
AK		 3245static struct attribute *skl_format_attr[] = {
3246 &format_attr_frontend.attr,
3247 NULL,
3248};
3249
3b6e0421
JO		 3250static __initconst const struct x86_pmu core_pmu = {
3251 .name = "core",
3252 .handle_irq = x86_pmu_handle_irq,
3253 .disable_all = x86_pmu_disable_all,
3254 .enable_all = core_pmu_enable_all,
3255 .enable = core_pmu_enable_event,
3256 .disable = x86_pmu_disable_event,
3257 .hw_config = x86_pmu_hw_config,
3258 .schedule_events = x86_schedule_events,
3259 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3260 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3261 .event_map = intel_pmu_event_map,
3262 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3263 .apic = 1,
a7b58d21
AK		 3264 .free_running_flags = PEBS_FREERUNNING_FLAGS,
3265
3b6e0421
JO		 3266 /*
3267 * Intel PMCs cannot be accessed sanely above 32-bit width,
3268 * so we install an artificial 1<<31 period regardless of
3269 * the generic event period:
3270 */
3271 .max_period = (1ULL<<31) - 1,
3272 .get_event_constraints = intel_get_event_constraints,
3273 .put_event_constraints = intel_put_event_constraints,
3274 .event_constraints = intel_core_event_constraints,
3275 .guest_get_msrs = core_guest_get_msrs,
3276 .format_attrs = intel_arch_formats_attr,
3277 .events_sysfs_show = intel_event_sysfs_show,
3278
3279 /*
3280 * Virtual (or funny metal) CPU can define x86_pmu.extra_regs
3281 * together with PMU version 1 and thus be using core_pmu with
3282 * shared_regs. We need following callbacks here to allocate
3283 * it properly.
3284 */
3285 .cpu_prepare = intel_pmu_cpu_prepare,
3286 .cpu_starting = intel_pmu_cpu_starting,
3287 .cpu_dying = intel_pmu_cpu_dying,
3288};
3289
caaa8be3 3290static __initconst const struct x86_pmu intel_pmu = {
f22f54f4
PZ		 3291 .name = "Intel",
3292 .handle_irq = intel_pmu_handle_irq,
3293 .disable_all = intel_pmu_disable_all,
3294 .enable_all = intel_pmu_enable_all,
3295 .enable = intel_pmu_enable_event,
3296 .disable = intel_pmu_disable_event,
68f7082f
PZ		 3297 .add = intel_pmu_add_event,
3298 .del = intel_pmu_del_event,
b4cdc5c2 3299 .hw_config = intel_pmu_hw_config,
a072738e 3300 .schedule_events = x86_schedule_events,
f22f54f4
PZ		 3301 .eventsel = MSR_ARCH_PERFMON_EVENTSEL0,
3302 .perfctr = MSR_ARCH_PERFMON_PERFCTR0,
3303 .event_map = intel_pmu_event_map,
f22f54f4
PZ		 3304 .max_events = ARRAY_SIZE(intel_perfmon_event_map),
3305 .apic = 1,
a7b58d21 3306 .free_running_flags = PEBS_FREERUNNING_FLAGS,
f22f54f4
PZ		 3307 /*
3308 * Intel PMCs cannot be accessed sanely above 32 bit width,
3309 * so we install an artificial 1<<31 period regardless of
3310 * the generic event period:
3311 */
3312 .max_period = (1ULL << 31) - 1,
3f6da390 3313 .get_event_constraints = intel_get_event_constraints,
a7e3ed1e 3314 .put_event_constraints = intel_put_event_constraints,
0780c927 3315 .pebs_aliases = intel_pebs_aliases_core2,
3f6da390 3316
641cc938 3317 .format_attrs = intel_arch3_formats_attr,
0bf79d44 3318 .events_sysfs_show = intel_event_sysfs_show,
641cc938 3319
a7e3ed1e 3320 .cpu_prepare = intel_pmu_cpu_prepare,
74846d35
PZ		 3321 .cpu_starting = intel_pmu_cpu_starting,
3322 .cpu_dying = intel_pmu_cpu_dying,
144d31e6 3323 .guest_get_msrs = intel_guest_get_msrs,
9c964efa 3324 .sched_task = intel_pmu_sched_task,
f22f54f4
PZ		 3325};
3326
c1d6f42f 3327static __init void intel_clovertown_quirk(void)
3c44780b
PZ		 3328{
3329 /*
3330 * PEBS is unreliable due to:
3331 *
3332 * AJ67 - PEBS may experience CPL leaks
3333 * AJ68 - PEBS PMI may be delayed by one event
3334 * AJ69 - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
3335 * AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
3336 *
3337 * AJ67 could be worked around by restricting the OS/USR flags.
3338 * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
3339 *
3340 * AJ106 could possibly be worked around by not allowing LBR
3341 * usage from PEBS, including the fixup.
3342 * AJ68 could possibly be worked around by always programming
ec75a716 3343 * a pebs_event_reset[0] value and coping with the lost events.
3c44780b
PZ		 3344 *
3345 * But taken together it might just make sense to not enable PEBS on
3346 * these chips.
3347 */
c767a54b 3348 pr_warn("PEBS disabled due to CPU errata\n");
3c44780b
PZ		 3349 x86_pmu.pebs = 0;
3350 x86_pmu.pebs_constraints = NULL;
3351}
3352
c93dc84c
PZ		 3353static int intel_snb_pebs_broken(int cpu)
3354{
3355 u32 rev = UINT_MAX; /* default to broken for unknown models */
3356
3357 switch (cpu_data(cpu).x86_model) {
ef5f9f47 3358 case INTEL_FAM6_SANDYBRIDGE:
c93dc84c
PZ		 3359 rev = 0x28;
3360 break;
3361
ef5f9f47 3362 case INTEL_FAM6_SANDYBRIDGE_X:
c93dc84c
PZ		 3363 switch (cpu_data(cpu).x86_mask) {
3364 case 6: rev = 0x618; break;
3365 case 7: rev = 0x70c; break;
3366 }
3367 }
3368
3369 return (cpu_data(cpu).microcode < rev);
3370}
3371
3372static void intel_snb_check_microcode(void)
3373{
3374 int pebs_broken = 0;
3375 int cpu;
3376
3377 get_online_cpus();
3378 for_each_online_cpu(cpu) {
3379 if ((pebs_broken = intel_snb_pebs_broken(cpu)))
3380 break;
3381 }
3382 put_online_cpus();
3383
3384 if (pebs_broken == x86_pmu.pebs_broken)
3385 return;
3386
3387 /*
3388 * Serialized by the microcode lock..
3389 */
3390 if (x86_pmu.pebs_broken) {
3391 pr_info("PEBS enabled due to microcode update\n");
3392 x86_pmu.pebs_broken = 0;
3393 } else {
3394 pr_info("PEBS disabled due to CPU errata, please upgrade microcode\n");
3395 x86_pmu.pebs_broken = 1;
3396 }
3397}
3398
19fc9ddd
DCC		 3399static bool is_lbr_from(unsigned long msr)
3400{
3401 unsigned long lbr_from_nr = x86_pmu.lbr_from + x86_pmu.lbr_nr;
3402
3403 return x86_pmu.lbr_from <= msr && msr < lbr_from_nr;
3404}
3405
338b522c
KL		 3406/*
3407 * Under certain circumstances, access certain MSR may cause #GP.
3408 * The function tests if the input MSR can be safely accessed.
3409 */
3410static bool check_msr(unsigned long msr, u64 mask)
3411{
3412 u64 val_old, val_new, val_tmp;
3413
3414 /*
3415 * Read the current value, change it and read it back to see if it
3416 * matches, this is needed to detect certain hardware emulators
3417 * (qemu/kvm) that don't trap on the MSR access and always return 0s.
3418 */
3419 if (rdmsrl_safe(msr, &val_old))
3420 return false;
3421
3422 /*
3423 * Only change the bits which can be updated by wrmsrl.
3424 */
3425 val_tmp = val_old ^ mask;
19fc9ddd
DCC		 3426
3427 if (is_lbr_from(msr))
3428 val_tmp = lbr_from_signext_quirk_wr(val_tmp);
3429
338b522c
KL		 3430 if (wrmsrl_safe(msr, val_tmp) ||
3431 rdmsrl_safe(msr, &val_new))
3432 return false;
3433
19fc9ddd
DCC		 3434 /*
3435 * Quirk only affects validation in wrmsr(), so wrmsrl()'s value
3436 * should equal rdmsrl()'s even with the quirk.
3437 */
338b522c
KL		 3438 if (val_new != val_tmp)
3439 return false;
3440
19fc9ddd
DCC		 3441 if (is_lbr_from(msr))
3442 val_old = lbr_from_signext_quirk_wr(val_old);
3443
338b522c
KL		 3444 /* Here it's sure that the MSR can be safely accessed.
3445 * Restore the old value and return.
3446 */
3447 wrmsrl(msr, val_old);
3448
3449 return true;
3450}
3451
c1d6f42f 3452static __init void intel_sandybridge_quirk(void)
6a600a8b 3453{
c93dc84c
PZ		 3454 x86_pmu.check_microcode = intel_snb_check_microcode;
3455 intel_snb_check_microcode();
6a600a8b
PZ		 3456}
3457
c1d6f42f
PZ		 3458static const struct { int id; char *name; } intel_arch_events_map[] __initconst = {
3459 { PERF_COUNT_HW_CPU_CYCLES, "cpu cycles" },
3460 { PERF_COUNT_HW_INSTRUCTIONS, "instructions" },
3461 { PERF_COUNT_HW_BUS_CYCLES, "bus cycles" },
3462 { PERF_COUNT_HW_CACHE_REFERENCES, "cache references" },
3463 { PERF_COUNT_HW_CACHE_MISSES, "cache misses" },
3464 { PERF_COUNT_HW_BRANCH_INSTRUCTIONS, "branch instructions" },
3465 { PERF_COUNT_HW_BRANCH_MISSES, "branch misses" },
ffb871bc
GN		 3466};
3467
c1d6f42f
PZ		 3468static __init void intel_arch_events_quirk(void)
3469{
3470 int bit;
3471
3472 /* disable event that reported as not presend by cpuid */
3473 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) {
3474 intel_perfmon_event_map[intel_arch_events_map[bit].id] = 0;
c767a54b
JP		 3475 pr_warn("CPUID marked event: \'%s\' unavailable\n",
3476 intel_arch_events_map[bit].name);
c1d6f42f
PZ		 3477 }
3478}
3479
3480static __init void intel_nehalem_quirk(void)
3481{
3482 union cpuid10_ebx ebx;
3483
3484 ebx.full = x86_pmu.events_maskl;
3485 if (ebx.split.no_branch_misses_retired) {
3486 /*
3487 * Erratum AAJ80 detected, we work it around by using
3488 * the BR_MISP_EXEC.ANY event. This will over-count
3489 * branch-misses, but it's still much better than the
3490 * architectural event which is often completely bogus:
3491 */
3492 intel_perfmon_event_map[PERF_COUNT_HW_BRANCH_MISSES] = 0x7f89;
3493 ebx.split.no_branch_misses_retired = 0;
3494 x86_pmu.events_maskl = ebx.full;
c767a54b 3495 pr_info("CPU erratum AAJ80 worked around\n");
c1d6f42f
PZ		 3496 }
3497}
3498
93fcf72c
MD		 3499/*
3500 * enable software workaround for errata:
3501 * SNB: BJ122
3502 * IVB: BV98
3503 * HSW: HSD29
3504 *
3505 * Only needed when HT is enabled. However detecting
b37609c3
SE		 3506 * if HT is enabled is difficult (model specific). So instead,
3507 * we enable the workaround in the early boot, and verify if
3508 * it is needed in a later initcall phase once we have valid
3509 * topology information to check if HT is actually enabled
93fcf72c
MD		 3510 */
3511static __init void intel_ht_bug(void)
3512{
b37609c3 3513 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED;
93fcf72c 3514
93fcf72c 3515 x86_pmu.start_scheduling = intel_start_scheduling;
0c41e756 3516 x86_pmu.commit_scheduling = intel_commit_scheduling;
93fcf72c 3517 x86_pmu.stop_scheduling = intel_stop_scheduling;
93fcf72c
MD		 3518}
3519
7f2ee91f
IM		 3520EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
3521EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
f9134f36 3522
4b2c4f1f 3523/* Haswell special events */
7f2ee91f
IM		 3524EVENT_ATTR_STR(tx-start, tx_start, "event=0xc9,umask=0x1");
3525EVENT_ATTR_STR(tx-commit, tx_commit, "event=0xc9,umask=0x2");
3526EVENT_ATTR_STR(tx-abort, tx_abort, "event=0xc9,umask=0x4");
3527EVENT_ATTR_STR(tx-capacity, tx_capacity, "event=0x54,umask=0x2");
3528EVENT_ATTR_STR(tx-conflict, tx_conflict, "event=0x54,umask=0x1");
3529EVENT_ATTR_STR(el-start, el_start, "event=0xc8,umask=0x1");
3530EVENT_ATTR_STR(el-commit, el_commit, "event=0xc8,umask=0x2");
3531EVENT_ATTR_STR(el-abort, el_abort, "event=0xc8,umask=0x4");
3532EVENT_ATTR_STR(el-capacity, el_capacity, "event=0x54,umask=0x2");
3533EVENT_ATTR_STR(el-conflict, el_conflict, "event=0x54,umask=0x1");
3534EVENT_ATTR_STR(cycles-t, cycles_t, "event=0x3c,in_tx=1");
3535EVENT_ATTR_STR(cycles-ct, cycles_ct, "event=0x3c,in_tx=1,in_tx_cp=1");
4b2c4f1f 3536
f9134f36 3537static struct attribute *hsw_events_attrs[] = {
4b2c4f1f
AK		 3538 EVENT_PTR(tx_start),
3539 EVENT_PTR(tx_commit),
3540 EVENT_PTR(tx_abort),
3541 EVENT_PTR(tx_capacity),
3542 EVENT_PTR(tx_conflict),
3543 EVENT_PTR(el_start),
3544 EVENT_PTR(el_commit),
3545 EVENT_PTR(el_abort),
3546 EVENT_PTR(el_capacity),
3547 EVENT_PTR(el_conflict),
3548 EVENT_PTR(cycles_t),
3549 EVENT_PTR(cycles_ct),
f9134f36
AK		 3550 EVENT_PTR(mem_ld_hsw),
3551 EVENT_PTR(mem_st_hsw),
a39fcae7
AK		 3552 EVENT_PTR(td_slots_issued),
3553 EVENT_PTR(td_slots_retired),
3554 EVENT_PTR(td_fetch_bubbles),
3555 EVENT_PTR(td_total_slots),
3556 EVENT_PTR(td_total_slots_scale),
3557 EVENT_PTR(td_recovery_bubbles),
3558 EVENT_PTR(td_recovery_bubbles_scale),
f9134f36
AK		 3559 NULL
3560};
3561
de0428a7 3562__init int intel_pmu_init(void)
f22f54f4
PZ		 3563{
3564 union cpuid10_edx edx;
3565 union cpuid10_eax eax;
ffb871bc 3566 union cpuid10_ebx ebx;
a1eac7ac 3567 struct event_constraint *c;
f22f54f4 3568 unsigned int unused;
338b522c
KL		 3569 struct extra_reg *er;
3570 int version, i;
f22f54f4
PZ		 3571
3572 if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
a072738e
CG		 3573 switch (boot_cpu_data.x86) {
3574 case 0x6:
3575 return p6_pmu_init();
e717bf4e
VW		 3576 case 0xb:
3577 return knc_pmu_init();
a072738e
CG		 3578 case 0xf:
3579 return p4_pmu_init();
3580 }
f22f54f4 3581 return -ENODEV;
f22f54f4
PZ		 3582 }
3583
3584 /*
3585 * Check whether the Architectural PerfMon supports
3586 * Branch Misses Retired hw_event or not.
3587 */
ffb871bc
GN		 3588 cpuid(10, &eax.full, &ebx.full, &unused, &edx.full);
3589 if (eax.split.mask_length < ARCH_PERFMON_EVENTS_COUNT)
f22f54f4
PZ		 3590 return -ENODEV;
3591
3592 version = eax.split.version_id;
3593 if (version < 2)
3594 x86_pmu = core_pmu;
3595 else
3596 x86_pmu = intel_pmu;
3597
3598 x86_pmu.version = version;
948b1bb8
RR		 3599 x86_pmu.num_counters = eax.split.num_counters;
3600 x86_pmu.cntval_bits = eax.split.bit_width;
3601 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1;
f22f54f4 3602
c1d6f42f
PZ		 3603 x86_pmu.events_maskl = ebx.full;
3604 x86_pmu.events_mask_len = eax.split.mask_length;
3605
70ab7003
AK		 3606 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters);
3607
f22f54f4
PZ		 3608 /*
3609 * Quirk: v2 perfmon does not report fixed-purpose events, so
f92b7604 3610 * assume at least 3 events, when not running in a hypervisor:
f22f54f4 3611 */
f92b7604
IP		 3612 if (version > 1) {
3613 int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
3614
3615 x86_pmu.num_counters_fixed =
3616 max((int)edx.split.num_counters_fixed, assume);
3617 }
f22f54f4 3618
c9b08884 3619 if (boot_cpu_has(X86_FEATURE_PDCM)) {
8db909a7
PZ		 3620 u64 capabilities;
3621
3622 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
3623 x86_pmu.intel_cap.capabilities = capabilities;
3624 }
3625
ca037701
PZ		 3626 intel_ds_init();
3627
c1d6f42f
PZ		 3628 x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
3629
f22f54f4
PZ		 3630 /*
3631 * Install the hw-cache-events table:
3632 */
3633 switch (boot_cpu_data.x86_model) {
ef5f9f47 3634 case INTEL_FAM6_CORE_YONAH:
f22f54f4
PZ		 3635 pr_cont("Core events, ");
3636 break;
3637
ef5f9f47 3638 case INTEL_FAM6_CORE2_MEROM:
c1d6f42f 3639 x86_add_quirk(intel_clovertown_quirk);
ef5f9f47
DH		 3640 case INTEL_FAM6_CORE2_MEROM_L:
3641 case INTEL_FAM6_CORE2_PENRYN:
3642 case INTEL_FAM6_CORE2_DUNNINGTON:
f22f54f4
PZ		 3643 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
3644 sizeof(hw_cache_event_ids));
3645
caff2bef
PZ		 3646 intel_pmu_lbr_init_core();
3647
f22f54f4 3648 x86_pmu.event_constraints = intel_core2_event_constraints;
17e31629 3649 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints;
f22f54f4
PZ		 3650 pr_cont("Core2 events, ");
3651 break;
3652
ef5f9f47
DH		 3653 case INTEL_FAM6_NEHALEM:
3654 case INTEL_FAM6_NEHALEM_EP:
3655 case INTEL_FAM6_NEHALEM_EX:
f22f54f4
PZ		 3656 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
3657 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3658 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3659 sizeof(hw_cache_extra_regs));
f22f54f4 3660
caff2bef
PZ		 3661 intel_pmu_lbr_init_nhm();
3662
f22f54f4 3663 x86_pmu.event_constraints = intel_nehalem_event_constraints;
17e31629 3664 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;
11164cd4 3665 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
a7e3ed1e 3666 x86_pmu.extra_regs = intel_nehalem_extra_regs;
ec75a716 3667
f20093ee
SE		 3668 x86_pmu.cpu_events = nhm_events_attrs;
3669
91fc4cc0 3670 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3671 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3672 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
91fc4cc0 3673 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3674 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3675 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
94403f88 3676
e17dc653 3677 intel_pmu_pebs_data_source_nhm();
c1d6f42f 3678 x86_add_quirk(intel_nehalem_quirk);
ec75a716 3679
11164cd4 3680 pr_cont("Nehalem events, ");
f22f54f4 3681 break;
caff2bef 3682
ef5f9f47
DH		 3683 case INTEL_FAM6_ATOM_PINEVIEW:
3684 case INTEL_FAM6_ATOM_LINCROFT:
3685 case INTEL_FAM6_ATOM_PENWELL:
3686 case INTEL_FAM6_ATOM_CLOVERVIEW:
3687 case INTEL_FAM6_ATOM_CEDARVIEW:
f22f54f4
PZ		 3688 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
3689 sizeof(hw_cache_event_ids));
3690
caff2bef
PZ		 3691 intel_pmu_lbr_init_atom();
3692
f22f54f4 3693 x86_pmu.event_constraints = intel_gen_event_constraints;
17e31629 3694 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints;
673d188b 3695 x86_pmu.pebs_aliases = intel_pebs_aliases_core2;
f22f54f4
PZ		 3696 pr_cont("Atom events, ");
3697 break;
3698
ef5f9f47
DH		 3699 case INTEL_FAM6_ATOM_SILVERMONT1:
3700 case INTEL_FAM6_ATOM_SILVERMONT2:
3701 case INTEL_FAM6_ATOM_AIRMONT:
1fa64180
YZ		 3702 memcpy(hw_cache_event_ids, slm_hw_cache_event_ids,
3703 sizeof(hw_cache_event_ids));
3704 memcpy(hw_cache_extra_regs, slm_hw_cache_extra_regs,
3705 sizeof(hw_cache_extra_regs));
3706
f21d5adc 3707 intel_pmu_lbr_init_slm();
1fa64180
YZ		 3708
3709 x86_pmu.event_constraints = intel_slm_event_constraints;
3710 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3711 x86_pmu.extra_regs = intel_slm_extra_regs;
9a5e3fb5 3712 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
eb12b8ec 3713 x86_pmu.cpu_events = slm_events_attrs;
1fa64180
YZ		 3714 pr_cont("Silvermont events, ");
3715 break;
3716
ef5f9f47
DH		 3717 case INTEL_FAM6_ATOM_GOLDMONT:
3718 case INTEL_FAM6_ATOM_DENVERTON:
8b92c3a7
KL		 3719 memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
3720 sizeof(hw_cache_event_ids));
3721 memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
3722 sizeof(hw_cache_extra_regs));
3723
3724 intel_pmu_lbr_init_skl();
3725
3726 x86_pmu.event_constraints = intel_slm_event_constraints;
3727 x86_pmu.pebs_constraints = intel_glm_pebs_event_constraints;
3728 x86_pmu.extra_regs = intel_glm_extra_regs;
3729 /*
3730 * It's recommended to use CPU_CLK_UNHALTED.CORE_P + NPEBS
3731 * for precise cycles.
3732 * :pp is identical to :ppp
3733 */
3734 x86_pmu.pebs_aliases = NULL;
3735 x86_pmu.pebs_prec_dist = true;
ccbebba4 3736 x86_pmu.lbr_pt_coexist = true;
8b92c3a7
KL		 3737 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3738 pr_cont("Goldmont events, ");
3739 break;
3740
ef5f9f47
DH		 3741 case INTEL_FAM6_WESTMERE:
3742 case INTEL_FAM6_WESTMERE_EP:
3743 case INTEL_FAM6_WESTMERE_EX:
f22f54f4
PZ		 3744 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
3745 sizeof(hw_cache_event_ids));
e994d7d2
AK		 3746 memcpy(hw_cache_extra_regs, nehalem_hw_cache_extra_regs,
3747 sizeof(hw_cache_extra_regs));
f22f54f4 3748
caff2bef
PZ		 3749 intel_pmu_lbr_init_nhm();
3750
f22f54f4 3751 x86_pmu.event_constraints = intel_westmere_event_constraints;
40b91cd1 3752 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
17e31629 3753 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints;
a7e3ed1e 3754 x86_pmu.extra_regs = intel_westmere_extra_regs;
9a5e3fb5 3755 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
30112039 3756
f20093ee
SE		 3757 x86_pmu.cpu_events = nhm_events_attrs;
3758
30112039 3759 /* UOPS_ISSUED.STALLED_CYCLES */
f9b4eeb8
PZ		 3760 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3761 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
30112039 3762 /* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */
f9b4eeb8
PZ		 3763 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3764 X86_CONFIG(.event=0xb1, .umask=0x3f, .inv=1, .cmask=1);
30112039 3765
e17dc653 3766 intel_pmu_pebs_data_source_nhm();
f22f54f4
PZ		 3767 pr_cont("Westmere events, ");
3768 break;
b622d644 3769
ef5f9f47
DH		 3770 case INTEL_FAM6_SANDYBRIDGE:
3771 case INTEL_FAM6_SANDYBRIDGE_X:
47a8863d 3772 x86_add_quirk(intel_sandybridge_quirk);
93fcf72c 3773 x86_add_quirk(intel_ht_bug);
b06b3d49
LM		 3774 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3775 sizeof(hw_cache_event_ids));
74e6543f
YZ		 3776 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3777 sizeof(hw_cache_extra_regs));
b06b3d49 3778
c5cc2cd9 3779 intel_pmu_lbr_init_snb();
b06b3d49
LM		 3780
3781 x86_pmu.event_constraints = intel_snb_event_constraints;
de0428a7 3782 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints;
0780c927 3783 x86_pmu.pebs_aliases = intel_pebs_aliases_snb;
ef5f9f47 3784 if (boot_cpu_data.x86_model == INTEL_FAM6_SANDYBRIDGE_X)
f1923820
SE		 3785 x86_pmu.extra_regs = intel_snbep_extra_regs;
3786 else
3787 x86_pmu.extra_regs = intel_snb_extra_regs;
93fcf72c
MD		 3788
3789
ee89cbc2 3790 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3791 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3792 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
e04d1b23 3793
f20093ee
SE		 3794 x86_pmu.cpu_events = snb_events_attrs;
3795
e04d1b23 3796 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
f9b4eeb8
PZ		 3797 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3798 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3799 /* UOPS_DISPATCHED.THREAD,c=1,i=1 to count stall cycles*/
f9b4eeb8
PZ		 3800 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =
3801 X86_CONFIG(.event=0xb1, .umask=0x01, .inv=1, .cmask=1);
e04d1b23 3802
b06b3d49
LM		 3803 pr_cont("SandyBridge events, ");
3804 break;
0f7c29ce 3805
ef5f9f47
DH		 3806 case INTEL_FAM6_IVYBRIDGE:
3807 case INTEL_FAM6_IVYBRIDGE_X:
93fcf72c 3808 x86_add_quirk(intel_ht_bug);
20a36e39
SE		 3809 memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
3810 sizeof(hw_cache_event_ids));
1996388e
VW		 3811 /* dTLB-load-misses on IVB is different than SNB */
3812 hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
3813
20a36e39
SE		 3814 memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
3815 sizeof(hw_cache_extra_regs));
3816
3817 intel_pmu_lbr_init_snb();
3818
69943182 3819 x86_pmu.event_constraints = intel_ivb_event_constraints;
20a36e39 3820 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints;
72469764
AK		 3821 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3822 x86_pmu.pebs_prec_dist = true;
ef5f9f47 3823 if (boot_cpu_data.x86_model == INTEL_FAM6_IVYBRIDGE_X)
f1923820
SE		 3824 x86_pmu.extra_regs = intel_snbep_extra_regs;
3825 else
3826 x86_pmu.extra_regs = intel_snb_extra_regs;
20a36e39 3827 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3828 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3829 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
20a36e39 3830
f20093ee
SE		 3831 x86_pmu.cpu_events = snb_events_attrs;
3832
20a36e39
SE		 3833 /* UOPS_ISSUED.ANY,c=1,i=1 to count stall cycles */
3834 intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =
3835 X86_CONFIG(.event=0x0e, .umask=0x01, .inv=1, .cmask=1);
3836
3837 pr_cont("IvyBridge events, ");
3838 break;
3839
b06b3d49 3840
ef5f9f47
DH		 3841 case INTEL_FAM6_HASWELL_CORE:
3842 case INTEL_FAM6_HASWELL_X:
3843 case INTEL_FAM6_HASWELL_ULT:
3844 case INTEL_FAM6_HASWELL_GT3E:
93fcf72c 3845 x86_add_quirk(intel_ht_bug);
72db5596 3846 x86_pmu.late_ack = true;
0f1b5ca2
AK		 3847 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3848 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3a632cb2 3849
e9d7f7cd 3850 intel_pmu_lbr_init_hsw();
3a632cb2
AK		 3851
3852 x86_pmu.event_constraints = intel_hsw_event_constraints;
3044318f 3853 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;
36bbb2f2 3854 x86_pmu.extra_regs = intel_snbep_extra_regs;
72469764
AK		 3855 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3856 x86_pmu.pebs_prec_dist = true;
3a632cb2 3857 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3858 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3859 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3a632cb2
AK		 3860
3861 x86_pmu.hw_config = hsw_hw_config;
3862 x86_pmu.get_event_constraints = hsw_get_event_constraints;
f9134f36 3863 x86_pmu.cpu_events = hsw_events_attrs;
b7af41a1 3864 x86_pmu.lbr_double_abort = true;
3a632cb2
AK		 3865 pr_cont("Haswell events, ");
3866 break;
3867
ef5f9f47
DH		 3868 case INTEL_FAM6_BROADWELL_CORE:
3869 case INTEL_FAM6_BROADWELL_XEON_D:
3870 case INTEL_FAM6_BROADWELL_GT3E:
3871 case INTEL_FAM6_BROADWELL_X:
91f1b705
AK		 3872 x86_pmu.late_ack = true;
3873 memcpy(hw_cache_event_ids, hsw_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3874 memcpy(hw_cache_extra_regs, hsw_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3875
3876 /* L3_MISS_LOCAL_DRAM is BIT(26) in Broadwell */
3877 hw_cache_extra_regs[C(LL)][C(OP_READ)][C(RESULT_MISS)] = HSW_DEMAND_READ |
3878 BDW_L3_MISS|HSW_SNOOP_DRAM;
3879 hw_cache_extra_regs[C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = HSW_DEMAND_WRITE|BDW_L3_MISS|
3880 HSW_SNOOP_DRAM;
3881 hw_cache_extra_regs[C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = HSW_DEMAND_READ|
3882 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3883 hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
3884 BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
3885
78d504bc 3886 intel_pmu_lbr_init_hsw();
91f1b705
AK		 3887
3888 x86_pmu.event_constraints = intel_bdw_event_constraints;
b3e62463 3889 x86_pmu.pebs_constraints = intel_bdw_pebs_event_constraints;
91f1b705 3890 x86_pmu.extra_regs = intel_snbep_extra_regs;
72469764
AK		 3891 x86_pmu.pebs_aliases = intel_pebs_aliases_ivb;
3892 x86_pmu.pebs_prec_dist = true;
91f1b705 3893 /* all extra regs are per-cpu when HT is on */
9a5e3fb5
SE		 3894 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3895 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
91f1b705
AK		 3896
3897 x86_pmu.hw_config = hsw_hw_config;
3898 x86_pmu.get_event_constraints = hsw_get_event_constraints;
3899 x86_pmu.cpu_events = hsw_events_attrs;
294fe0f5 3900 x86_pmu.limit_period = bdw_limit_period;
91f1b705
AK		 3901 pr_cont("Broadwell events, ");
3902 break;
3903
ef5f9f47 3904 case INTEL_FAM6_XEON_PHI_KNL:
608284bf 3905 case INTEL_FAM6_XEON_PHI_KNM:
1e7b9390
HC		 3906 memcpy(hw_cache_event_ids,
3907 slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3908 memcpy(hw_cache_extra_regs,
3909 knl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3910 intel_pmu_lbr_init_knl();
3911
3912 x86_pmu.event_constraints = intel_slm_event_constraints;
3913 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints;
3914 x86_pmu.extra_regs = intel_knl_extra_regs;
3915
3916 /* all extra regs are per-cpu when HT is on */
3917 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3918 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3919
608284bf 3920 pr_cont("Knights Landing/Mill events, ");
1e7b9390
HC		 3921 break;
3922
ef5f9f47
DH		 3923 case INTEL_FAM6_SKYLAKE_MOBILE:
3924 case INTEL_FAM6_SKYLAKE_DESKTOP:
3925 case INTEL_FAM6_SKYLAKE_X:
3926 case INTEL_FAM6_KABYLAKE_MOBILE:
3927 case INTEL_FAM6_KABYLAKE_DESKTOP:
9a92e16f
AK		 3928 x86_pmu.late_ack = true;
3929 memcpy(hw_cache_event_ids, skl_hw_cache_event_ids, sizeof(hw_cache_event_ids));
3930 memcpy(hw_cache_extra_regs, skl_hw_cache_extra_regs, sizeof(hw_cache_extra_regs));
3931 intel_pmu_lbr_init_skl();
3932
a39fcae7
AK		 3933 /* INT_MISC.RECOVERY_CYCLES has umask 1 in Skylake */
3934 event_attr_td_recovery_bubbles.event_str_noht =
3935 "event=0xd,umask=0x1,cmask=1";
3936 event_attr_td_recovery_bubbles.event_str_ht =
3937 "event=0xd,umask=0x1,cmask=1,any=1";
3938
9a92e16f
AK		 3939 x86_pmu.event_constraints = intel_skl_event_constraints;
3940 x86_pmu.pebs_constraints = intel_skl_pebs_event_constraints;
3941 x86_pmu.extra_regs = intel_skl_extra_regs;
72469764
AK		 3942 x86_pmu.pebs_aliases = intel_pebs_aliases_skl;
3943 x86_pmu.pebs_prec_dist = true;
9a92e16f
AK		 3944 /* all extra regs are per-cpu when HT is on */
3945 x86_pmu.flags |= PMU_FL_HAS_RSP_1;
3946 x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
3947
3948 x86_pmu.hw_config = hsw_hw_config;
3949 x86_pmu.get_event_constraints = hsw_get_event_constraints;
d0dc8494
AK		 3950 x86_pmu.format_attrs = merge_attr(intel_arch3_formats_attr,
3951 skl_format_attr);
9a92e16f
AK		 3952 WARN_ON(!x86_pmu.format_attrs);
3953 x86_pmu.cpu_events = hsw_events_attrs;
3954 pr_cont("Skylake events, ");
3955 break;
3956
f22f54f4 3957 default:
0af3ac1f
AK		 3958 switch (x86_pmu.version) {
3959 case 1:
3960 x86_pmu.event_constraints = intel_v1_event_constraints;
3961 pr_cont("generic architected perfmon v1, ");
3962 break;
3963 default:
3964 /*
3965 * default constraints for v2 and up
3966 */
3967 x86_pmu.event_constraints = intel_gen_event_constraints;
3968 pr_cont("generic architected perfmon, ");
3969 break;
3970 }
f22f54f4 3971 }
ffb871bc 3972
a1eac7ac
RR		 3973 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) {
3974 WARN(1, KERN_ERR "hw perf events %d > max(%d), clipping!",
3975 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC);
3976 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC;
3977 }
3978 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1;
3979
3980 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) {
3981 WARN(1, KERN_ERR "hw perf events fixed %d > max(%d), clipping!",
3982 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED);
3983 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED;
3984 }
3985
3986 x86_pmu.intel_ctrl |=
3987 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED;
3988
3989 if (x86_pmu.event_constraints) {
3990 /*
3991 * event on fixed counter2 (REF_CYCLES) only works on this
3992 * counter, so do not extend mask to generic counters
3993 */
3994 for_each_event_constraint(c, x86_pmu.event_constraints) {
2c33645d
PI		 3995 if (c->cmask == FIXED_EVENT_FLAGS
3996 && c->idxmsk64 != INTEL_PMC_MSK_FIXED_REF_CYCLES) {
3997 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1;
a1eac7ac 3998 }
2c33645d 3999 c->idxmsk64 &=
6d6f2833 4000 ~(~0ULL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed));
2c33645d 4001 c->weight = hweight64(c->idxmsk64);
a1eac7ac
RR		 4002 }
4003 }
4004
338b522c
KL		 4005 /*
4006 * Access LBR MSR may cause #GP under certain circumstances.
4007 * E.g. KVM doesn't support LBR MSR
4008 * Check all LBT MSR here.
4009 * Disable LBR access if any LBR MSRs can not be accessed.
4010 */
4011 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL))
4012 x86_pmu.lbr_nr = 0;
4013 for (i = 0; i < x86_pmu.lbr_nr; i++) {
4014 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) &&
4015 check_msr(x86_pmu.lbr_to + i, 0xffffUL)))
4016 x86_pmu.lbr_nr = 0;
4017 }
4018
f09509b9
DCC		 4019 if (x86_pmu.lbr_nr)
4020 pr_cont("%d-deep LBR, ", x86_pmu.lbr_nr);
338b522c
KL		 4021 /*
4022 * Access extra MSR may cause #GP under certain circumstances.
4023 * E.g. KVM doesn't support offcore event
4024 * Check all extra_regs here.
4025 */
4026 if (x86_pmu.extra_regs) {
4027 for (er = x86_pmu.extra_regs; er->msr; er++) {
8c4fe709 4028 er->extra_msr_access = check_msr(er->msr, 0x11UL);
338b522c
KL		 4029 /* Disable LBR select mapping */
4030 if ((er->idx == EXTRA_REG_LBR) && !er->extra_msr_access)
4031 x86_pmu.lbr_sel_map = NULL;
4032 }
4033 }
4034
069e0c3c
AK		 4035 /* Support full width counters using alternative MSR range */
4036 if (x86_pmu.intel_cap.full_width_write) {
4037 x86_pmu.max_period = x86_pmu.cntval_mask;
4038 x86_pmu.perfctr = MSR_IA32_PMC0;
4039 pr_cont("full-width counters, ");
4040 }
4041
f22f54f4
PZ		 4042 return 0;
4043}
b37609c3
SE		 4044
4045/*
4046 * HT bug: phase 2 init
4047 * Called once we have valid topology information to check
4048 * whether or not HT is enabled
4049 * If HT is off, then we disable the workaround
4050 */
4051static __init int fixup_ht_bug(void)
4052{
030ba6cd 4053 int c;
b37609c3
SE		 4054 /*
4055 * problem not present on this CPU model, nothing to do
4056 */
4057 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED))
4058 return 0;
4059
030ba6cd 4060 if (topology_max_smt_threads() > 1) {
b37609c3
SE		 4061 pr_info("PMU erratum BJ122, BV98, HSD29 worked around, HT is on\n");
4062 return 0;
4063 }
4064
ec6a9066 4065 if (lockup_detector_suspend() != 0) {
999bbe49
UO		 4066 pr_debug("failed to disable PMU erratum BJ122, BV98, HSD29 workaround\n");
4067 return 0;
4068 }
b37609c3
SE		 4069
4070 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED);
4071
b37609c3 4072 x86_pmu.start_scheduling = NULL;
0c41e756 4073 x86_pmu.commit_scheduling = NULL;
b37609c3
SE		 4074 x86_pmu.stop_scheduling = NULL;
4075
ec6a9066 4076 lockup_detector_resume();
b37609c3
SE		 4077
4078 get_online_cpus();
4079
4080 for_each_online_cpu(c) {
4081 free_excl_cntrs(c);
4082 }
4083
4084 put_online_cpus();
4085 pr_info("PMU erratum BJ122, BV98, HSD29 workaround disabled, HT off\n");
4086 return 0;
4087}
4088subsys_initcall(fixup_ht_bug)
Linux 6.x block layer and io_uring tree(s)