Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
90eec103 | 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
eb008eb6 PG |
20 | #include <linux/export.h> |
21 | #include <linux/init.h> | |
241771ef | 22 | #include <linux/kdebug.h> |
589ee628 | 23 | #include <linux/sched/mm.h> |
e6017571 | 24 | #include <linux/sched/clock.h> |
d7d59fb3 | 25 | #include <linux/uaccess.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
30dd568c | 27 | #include <linux/cpu.h> |
272d30be | 28 | #include <linux/bitops.h> |
0c9d42ed | 29 | #include <linux/device.h> |
46b1b577 | 30 | #include <linux/nospec.h> |
7c9903c9 | 31 | #include <linux/static_call.h> |
241771ef | 32 | |
241771ef | 33 | #include <asm/apic.h> |
d7d59fb3 | 34 | #include <asm/stacktrace.h> |
4e935e47 | 35 | #include <asm/nmi.h> |
69092624 | 36 | #include <asm/smp.h> |
c8e5910e | 37 | #include <asm/alternative.h> |
7911d3f7 | 38 | #include <asm/mmu_context.h> |
375074cc | 39 | #include <asm/tlbflush.h> |
e3f3541c | 40 | #include <asm/timer.h> |
d07bdfd3 PZ |
41 | #include <asm/desc.h> |
42 | #include <asm/ldt.h> | |
35f4d9b3 | 43 | #include <asm/unwind.h> |
241771ef | 44 | |
27f6d22b | 45 | #include "perf_event.h" |
de0428a7 | 46 | |
de0428a7 | 47 | struct x86_pmu x86_pmu __read_mostly; |
61e76d53 | 48 | static struct pmu pmu; |
efc9f05d | 49 | |
de0428a7 | 50 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e | 51 | .enabled = 1, |
61e76d53 | 52 | .pmu = &pmu, |
b0f3f28e | 53 | }; |
241771ef | 54 | |
405b4537 | 55 | DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key); |
631fe154 | 56 | DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key); |
d0946a88 | 57 | DEFINE_STATIC_KEY_FALSE(perf_is_hybrid); |
a6673429 | 58 | |
7c9903c9 PZ |
59 | /* |
60 | * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined | |
61 | * from just a typename, as opposed to an actual function. | |
62 | */ | |
63 | DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq); | |
64 | DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all); | |
65 | DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all); | |
66 | DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable); | |
67 | DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable); | |
68 | ||
8b8ff8cc AH |
69 | DEFINE_STATIC_CALL_NULL(x86_pmu_assign, *x86_pmu.assign); |
70 | ||
7c9903c9 PZ |
71 | DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add); |
72 | DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del); | |
73 | DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read); | |
74 | ||
08b3068f PZ |
75 | DEFINE_STATIC_CALL_NULL(x86_pmu_set_period, *x86_pmu.set_period); |
76 | DEFINE_STATIC_CALL_NULL(x86_pmu_update, *x86_pmu.update); | |
77 | DEFINE_STATIC_CALL_NULL(x86_pmu_limit_period, *x86_pmu.limit_period); | |
73759c34 | 78 | |
7c9903c9 PZ |
79 | DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events); |
80 | DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints); | |
81 | DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints); | |
82 | ||
83 | DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling); | |
84 | DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling); | |
85 | DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling); | |
86 | ||
87 | DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task); | |
88 | DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx); | |
89 | ||
90 | DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs); | |
91 | DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases); | |
92 | ||
bd275681 PZ |
93 | DEFINE_STATIC_CALL_NULL(x86_pmu_filter, *x86_pmu.filter); |
94 | ||
c8e2fe13 SC |
95 | /* |
96 | * This one is magic, it will get called even when PMU init fails (because | |
97 | * there is no PMU), in which case it should simply return NULL. | |
98 | */ | |
99 | DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs); | |
abd562df | 100 | |
de0428a7 | 101 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
102 | [PERF_COUNT_HW_CACHE_MAX] |
103 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
104 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 105 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
106 | [PERF_COUNT_HW_CACHE_MAX] |
107 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
108 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 109 | |
ee06094f | 110 | /* |
cdd6c482 IM |
111 | * Propagate event elapsed time into the generic event. |
112 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
113 | * Returns the delta events processed. |
114 | */ | |
de0428a7 | 115 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 116 | { |
cc2ad4ba | 117 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 118 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 119 | u64 prev_raw_count, new_raw_count; |
7f612a7f | 120 | u64 delta; |
ee06094f | 121 | |
027440b5 | 122 | if (unlikely(!hwc->event_base)) |
30dd568c MM |
123 | return 0; |
124 | ||
ee06094f | 125 | /* |
cdd6c482 | 126 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
127 | * |
128 | * Our tactic to handle this is to first atomically read and | |
129 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 130 | * count to the generic event atomically: |
ee06094f | 131 | */ |
e7850595 | 132 | prev_raw_count = local64_read(&hwc->prev_count); |
4c1c9dea UB |
133 | do { |
134 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); | |
135 | } while (!local64_try_cmpxchg(&hwc->prev_count, | |
136 | &prev_raw_count, new_raw_count)); | |
ee06094f IM |
137 | |
138 | /* | |
139 | * Now we have the new raw value and have updated the prev | |
140 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 141 | * (event-)time and add that to the generic event. |
ee06094f IM |
142 | * |
143 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 144 | * of the count. |
ee06094f | 145 | */ |
ec3232bd PZ |
146 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
147 | delta >>= shift; | |
ee06094f | 148 | |
e7850595 PZ |
149 | local64_add(delta, &event->count); |
150 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
151 | |
152 | return new_raw_count; | |
ee06094f IM |
153 | } |
154 | ||
a7e3ed1e AK |
155 | /* |
156 | * Find and validate any extra registers to set up. | |
157 | */ | |
158 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
159 | { | |
183af736 | 160 | struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); |
efc9f05d | 161 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
162 | struct extra_reg *er; |
163 | ||
efc9f05d | 164 | reg = &event->hw.extra_reg; |
a7e3ed1e | 165 | |
183af736 | 166 | if (!extra_regs) |
a7e3ed1e AK |
167 | return 0; |
168 | ||
183af736 | 169 | for (er = extra_regs; er->msr; er++) { |
a7e3ed1e AK |
170 | if (er->event != (config & er->config_mask)) |
171 | continue; | |
172 | if (event->attr.config1 & ~er->valid_mask) | |
173 | return -EINVAL; | |
338b522c KL |
174 | /* Check if the extra msrs can be safely accessed*/ |
175 | if (!er->extra_msr_access) | |
176 | return -ENXIO; | |
efc9f05d SE |
177 | |
178 | reg->idx = er->idx; | |
179 | reg->config = event->attr.config1; | |
180 | reg->reg = er->msr; | |
a7e3ed1e AK |
181 | break; |
182 | } | |
183 | return 0; | |
184 | } | |
185 | ||
cdd6c482 | 186 | static atomic_t active_events; |
1b7b938f | 187 | static atomic_t pmc_refcount; |
4e935e47 PZ |
188 | static DEFINE_MUTEX(pmc_reserve_mutex); |
189 | ||
b27ea29c RR |
190 | #ifdef CONFIG_X86_LOCAL_APIC |
191 | ||
d4b294bf KL |
192 | static inline int get_possible_num_counters(void) |
193 | { | |
194 | int i, num_counters = x86_pmu.num_counters; | |
195 | ||
196 | if (!is_hybrid()) | |
197 | return num_counters; | |
198 | ||
199 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) | |
200 | num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters); | |
201 | ||
202 | return num_counters; | |
203 | } | |
204 | ||
4e935e47 PZ |
205 | static bool reserve_pmc_hardware(void) |
206 | { | |
d4b294bf | 207 | int i, num_counters = get_possible_num_counters(); |
4e935e47 | 208 | |
d4b294bf | 209 | for (i = 0; i < num_counters; i++) { |
41bf4989 | 210 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
211 | goto perfctr_fail; |
212 | } | |
213 | ||
d4b294bf | 214 | for (i = 0; i < num_counters; i++) { |
41bf4989 | 215 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
216 | goto eventsel_fail; |
217 | } | |
218 | ||
219 | return true; | |
220 | ||
221 | eventsel_fail: | |
222 | for (i--; i >= 0; i--) | |
41bf4989 | 223 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 224 | |
d4b294bf | 225 | i = num_counters; |
4e935e47 PZ |
226 | |
227 | perfctr_fail: | |
228 | for (i--; i >= 0; i--) | |
41bf4989 | 229 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 230 | |
4e935e47 PZ |
231 | return false; |
232 | } | |
233 | ||
234 | static void release_pmc_hardware(void) | |
235 | { | |
d4b294bf | 236 | int i, num_counters = get_possible_num_counters(); |
4e935e47 | 237 | |
d4b294bf | 238 | for (i = 0; i < num_counters; i++) { |
41bf4989 RR |
239 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
240 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 241 | } |
4e935e47 PZ |
242 | } |
243 | ||
b27ea29c RR |
244 | #else |
245 | ||
246 | static bool reserve_pmc_hardware(void) { return true; } | |
247 | static void release_pmc_hardware(void) {} | |
248 | ||
249 | #endif | |
250 | ||
fc4b8fca | 251 | bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed) |
33c6d6a7 | 252 | { |
11d8b058 AB |
253 | u64 val, val_fail = -1, val_new= ~0; |
254 | int i, reg, reg_fail = -1, ret = 0; | |
a5ebe0ba | 255 | int bios_fail = 0; |
68ab7476 | 256 | int reg_safe = -1; |
33c6d6a7 | 257 | |
4407204c PZ |
258 | /* |
259 | * Check to see if the BIOS enabled any of the counters, if so | |
260 | * complain and bail. | |
261 | */ | |
fc4b8fca | 262 | for (i = 0; i < num_counters; i++) { |
41bf4989 | 263 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
264 | ret = rdmsrl_safe(reg, &val); |
265 | if (ret) | |
266 | goto msr_fail; | |
a5ebe0ba GD |
267 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
268 | bios_fail = 1; | |
269 | val_fail = val; | |
270 | reg_fail = reg; | |
68ab7476 DZ |
271 | } else { |
272 | reg_safe = i; | |
a5ebe0ba | 273 | } |
4407204c PZ |
274 | } |
275 | ||
fc4b8fca | 276 | if (num_counters_fixed) { |
4407204c PZ |
277 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
278 | ret = rdmsrl_safe(reg, &val); | |
279 | if (ret) | |
280 | goto msr_fail; | |
fc4b8fca KL |
281 | for (i = 0; i < num_counters_fixed; i++) { |
282 | if (fixed_counter_disabled(i, pmu)) | |
32451614 | 283 | continue; |
32d35c4a | 284 | if (val & (0x03ULL << i*4)) { |
a5ebe0ba GD |
285 | bios_fail = 1; |
286 | val_fail = val; | |
287 | reg_fail = reg; | |
288 | } | |
4407204c PZ |
289 | } |
290 | } | |
291 | ||
68ab7476 DZ |
292 | /* |
293 | * If all the counters are enabled, the below test will always | |
294 | * fail. The tools will also become useless in this scenario. | |
295 | * Just fail and disable the hardware counters. | |
296 | */ | |
297 | ||
298 | if (reg_safe == -1) { | |
299 | reg = reg_safe; | |
300 | goto msr_fail; | |
301 | } | |
302 | ||
4407204c | 303 | /* |
bffd5fc2 AP |
304 | * Read the current value, change it and read it back to see if it |
305 | * matches, this is needed to detect certain hardware emulators | |
306 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 307 | */ |
68ab7476 | 308 | reg = x86_pmu_event_addr(reg_safe); |
bffd5fc2 AP |
309 | if (rdmsrl_safe(reg, &val)) |
310 | goto msr_fail; | |
311 | val ^= 0xffffUL; | |
f285f92f RR |
312 | ret = wrmsrl_safe(reg, val); |
313 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 314 | if (ret || val != val_new) |
4407204c | 315 | goto msr_fail; |
33c6d6a7 | 316 | |
45daae57 IM |
317 | /* |
318 | * We still allow the PMU driver to operate: | |
319 | */ | |
a5ebe0ba | 320 | if (bios_fail) { |
1b74dde7 CY |
321 | pr_cont("Broken BIOS detected, complain to your hardware vendor.\n"); |
322 | pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", | |
323 | reg_fail, val_fail); | |
a5ebe0ba | 324 | } |
45daae57 IM |
325 | |
326 | return true; | |
4407204c PZ |
327 | |
328 | msr_fail: | |
005bd007 JG |
329 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { |
330 | pr_cont("PMU not available due to virtualization, using software events only.\n"); | |
331 | } else { | |
332 | pr_cont("Broken PMU hardware detected, using software events only.\n"); | |
333 | pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n", | |
334 | reg, val_new); | |
335 | } | |
45daae57 | 336 | |
4407204c | 337 | return false; |
33c6d6a7 DZ |
338 | } |
339 | ||
cdd6c482 | 340 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 341 | { |
6b099d9b | 342 | x86_release_hardware(); |
1b7b938f | 343 | atomic_dec(&active_events); |
4e935e47 PZ |
344 | } |
345 | ||
48070342 AS |
346 | void hw_perf_lbr_event_destroy(struct perf_event *event) |
347 | { | |
348 | hw_perf_event_destroy(event); | |
349 | ||
350 | /* undo the lbr/bts event accounting */ | |
351 | x86_del_exclusive(x86_lbr_exclusive_lbr); | |
352 | } | |
353 | ||
85cf9dba RR |
354 | static inline int x86_pmu_initialized(void) |
355 | { | |
356 | return x86_pmu.handle_irq != NULL; | |
357 | } | |
358 | ||
8326f44d | 359 | static inline int |
e994d7d2 | 360 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 361 | { |
e994d7d2 | 362 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
363 | unsigned int cache_type, cache_op, cache_result; |
364 | u64 config, val; | |
365 | ||
366 | config = attr->config; | |
367 | ||
ef9ee4ad | 368 | cache_type = (config >> 0) & 0xff; |
8326f44d IM |
369 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
370 | return -EINVAL; | |
ef9ee4ad | 371 | cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX); |
8326f44d IM |
372 | |
373 | cache_op = (config >> 8) & 0xff; | |
374 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
375 | return -EINVAL; | |
ef9ee4ad | 376 | cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX); |
8326f44d IM |
377 | |
378 | cache_result = (config >> 16) & 0xff; | |
379 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
380 | return -EINVAL; | |
ef9ee4ad | 381 | cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX); |
8326f44d | 382 | |
0d18f2df | 383 | val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result]; |
8326f44d IM |
384 | if (val == 0) |
385 | return -ENOENT; | |
386 | ||
387 | if (val == -1) | |
388 | return -EINVAL; | |
389 | ||
390 | hwc->config |= val; | |
0d18f2df | 391 | attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result]; |
e994d7d2 | 392 | return x86_pmu_extra_regs(val, event); |
8326f44d IM |
393 | } |
394 | ||
6b099d9b AS |
395 | int x86_reserve_hardware(void) |
396 | { | |
397 | int err = 0; | |
398 | ||
1b7b938f | 399 | if (!atomic_inc_not_zero(&pmc_refcount)) { |
6b099d9b | 400 | mutex_lock(&pmc_reserve_mutex); |
1b7b938f | 401 | if (atomic_read(&pmc_refcount) == 0) { |
488e13a4 | 402 | if (!reserve_pmc_hardware()) { |
6b099d9b | 403 | err = -EBUSY; |
488e13a4 | 404 | } else { |
6b099d9b | 405 | reserve_ds_buffers(); |
488e13a4 LX |
406 | reserve_lbr_buffers(); |
407 | } | |
6b099d9b AS |
408 | } |
409 | if (!err) | |
1b7b938f | 410 | atomic_inc(&pmc_refcount); |
6b099d9b AS |
411 | mutex_unlock(&pmc_reserve_mutex); |
412 | } | |
413 | ||
414 | return err; | |
415 | } | |
416 | ||
417 | void x86_release_hardware(void) | |
418 | { | |
1b7b938f | 419 | if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { |
6b099d9b AS |
420 | release_pmc_hardware(); |
421 | release_ds_buffers(); | |
c085fb87 | 422 | release_lbr_buffers(); |
6b099d9b AS |
423 | mutex_unlock(&pmc_reserve_mutex); |
424 | } | |
425 | } | |
426 | ||
48070342 AS |
427 | /* |
428 | * Check if we can create event of a certain type (that no conflicting events | |
429 | * are present). | |
430 | */ | |
431 | int x86_add_exclusive(unsigned int what) | |
432 | { | |
93472aff | 433 | int i; |
48070342 | 434 | |
b0c1ef52 AK |
435 | /* |
436 | * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS. | |
437 | * LBR and BTS are still mutually exclusive. | |
438 | */ | |
439 | if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) | |
92ca7da4 | 440 | goto out; |
ccbebba4 | 441 | |
93472aff PZ |
442 | if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { |
443 | mutex_lock(&pmc_reserve_mutex); | |
444 | for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { | |
445 | if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) | |
446 | goto fail_unlock; | |
447 | } | |
448 | atomic_inc(&x86_pmu.lbr_exclusive[what]); | |
449 | mutex_unlock(&pmc_reserve_mutex); | |
6b099d9b | 450 | } |
48070342 | 451 | |
92ca7da4 | 452 | out: |
93472aff PZ |
453 | atomic_inc(&active_events); |
454 | return 0; | |
48070342 | 455 | |
93472aff | 456 | fail_unlock: |
48070342 | 457 | mutex_unlock(&pmc_reserve_mutex); |
93472aff | 458 | return -EBUSY; |
48070342 AS |
459 | } |
460 | ||
461 | void x86_del_exclusive(unsigned int what) | |
462 | { | |
92ca7da4 AS |
463 | atomic_dec(&active_events); |
464 | ||
465 | /* | |
466 | * See the comment in x86_add_exclusive(). | |
467 | */ | |
b0c1ef52 | 468 | if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) |
ccbebba4 AS |
469 | return; |
470 | ||
48070342 AS |
471 | atomic_dec(&x86_pmu.lbr_exclusive[what]); |
472 | } | |
473 | ||
de0428a7 | 474 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
475 | { |
476 | struct perf_event_attr *attr = &event->attr; | |
477 | struct hw_perf_event *hwc = &event->hw; | |
478 | u64 config; | |
479 | ||
6c7e550f | 480 | if (!is_sampling_event(event)) { |
c1726f34 RR |
481 | hwc->sample_period = x86_pmu.max_period; |
482 | hwc->last_period = hwc->sample_period; | |
e7850595 | 483 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
484 | } |
485 | ||
d9977c43 | 486 | if (attr->type == event->pmu->type) |
ed13ec58 | 487 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
488 | |
489 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 490 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
491 | |
492 | if (attr->config >= x86_pmu.max_events) | |
493 | return -EINVAL; | |
494 | ||
46b1b577 PZ |
495 | attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events); |
496 | ||
c1726f34 RR |
497 | /* |
498 | * The generic map: | |
499 | */ | |
500 | config = x86_pmu.event_map(attr->config); | |
501 | ||
502 | if (config == 0) | |
503 | return -ENOENT; | |
504 | ||
505 | if (config == -1LL) | |
506 | return -EINVAL; | |
507 | ||
c1726f34 RR |
508 | hwc->config |= config; |
509 | ||
510 | return 0; | |
511 | } | |
4261e0e0 | 512 | |
ff3fb511 SE |
513 | /* |
514 | * check that branch_sample_type is compatible with | |
515 | * settings needed for precise_ip > 1 which implies | |
516 | * using the LBR to capture ALL taken branches at the | |
517 | * priv levels of the measurement | |
518 | */ | |
519 | static inline int precise_br_compat(struct perf_event *event) | |
520 | { | |
521 | u64 m = event->attr.branch_sample_type; | |
522 | u64 b = 0; | |
523 | ||
524 | /* must capture all branches */ | |
525 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
526 | return 0; | |
527 | ||
528 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
529 | ||
530 | if (!event->attr.exclude_user) | |
531 | b |= PERF_SAMPLE_BRANCH_USER; | |
532 | ||
533 | if (!event->attr.exclude_kernel) | |
534 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
535 | ||
536 | /* | |
537 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
538 | */ | |
539 | ||
540 | return m == b; | |
541 | } | |
542 | ||
b00233b5 | 543 | int x86_pmu_max_precise(void) |
a072738e | 544 | { |
b00233b5 AK |
545 | int precise = 0; |
546 | ||
547 | /* Support for constant skid */ | |
548 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { | |
549 | precise++; | |
ab608344 | 550 | |
b00233b5 AK |
551 | /* Support for IP fixup */ |
552 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) | |
ab608344 PZ |
553 | precise++; |
554 | ||
b00233b5 AK |
555 | if (x86_pmu.pebs_prec_dist) |
556 | precise++; | |
557 | } | |
558 | return precise; | |
559 | } | |
72469764 | 560 | |
b00233b5 AK |
561 | int x86_pmu_hw_config(struct perf_event *event) |
562 | { | |
563 | if (event->attr.precise_ip) { | |
564 | int precise = x86_pmu_max_precise(); | |
ab608344 PZ |
565 | |
566 | if (event->attr.precise_ip > precise) | |
567 | return -EOPNOTSUPP; | |
18e7a45a JO |
568 | |
569 | /* There's no sense in having PEBS for non sampling events: */ | |
570 | if (!is_sampling_event(event)) | |
571 | return -EINVAL; | |
4b854900 YZ |
572 | } |
573 | /* | |
574 | * check that PEBS LBR correction does not conflict with | |
575 | * whatever the user is asking with attr->branch_sample_type | |
576 | */ | |
577 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { | |
578 | u64 *br_type = &event->attr.branch_sample_type; | |
579 | ||
580 | if (has_branch_stack(event)) { | |
581 | if (!precise_br_compat(event)) | |
582 | return -EOPNOTSUPP; | |
583 | ||
584 | /* branch_sample_type is compatible */ | |
585 | ||
586 | } else { | |
587 | /* | |
588 | * user did not specify branch_sample_type | |
589 | * | |
590 | * For PEBS fixups, we capture all | |
591 | * the branches at the priv level of the | |
592 | * event. | |
593 | */ | |
594 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
595 | ||
596 | if (!event->attr.exclude_user) | |
597 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
598 | ||
599 | if (!event->attr.exclude_kernel) | |
600 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
ff3fb511 | 601 | } |
ab608344 PZ |
602 | } |
603 | ||
1f2376cd | 604 | if (branch_sample_call_stack(event)) |
e18bf526 YZ |
605 | event->attach_state |= PERF_ATTACH_TASK_DATA; |
606 | ||
a072738e CG |
607 | /* |
608 | * Generate PMC IRQs: | |
609 | * (keep 'enabled' bit clear for now) | |
610 | */ | |
b4cdc5c2 | 611 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
612 | |
613 | /* | |
614 | * Count user and OS events unless requested not to | |
615 | */ | |
b4cdc5c2 PZ |
616 | if (!event->attr.exclude_user) |
617 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
618 | if (!event->attr.exclude_kernel) | |
619 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 620 | |
d9977c43 | 621 | if (event->attr.type == event->pmu->type) |
b4cdc5c2 | 622 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; |
a072738e | 623 | |
294fe0f5 | 624 | if (event->attr.sample_period && x86_pmu.limit_period) { |
28f0f3c4 PZ |
625 | s64 left = event->attr.sample_period; |
626 | x86_pmu.limit_period(event, &left); | |
627 | if (left > event->attr.sample_period) | |
294fe0f5 AK |
628 | return -EINVAL; |
629 | } | |
630 | ||
878068ea | 631 | /* sample_regs_user never support XMM registers */ |
dce86ac7 | 632 | if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK)) |
878068ea KL |
633 | return -EINVAL; |
634 | /* | |
635 | * Besides the general purpose registers, XMM registers may | |
636 | * be collected in PEBS on some platforms, e.g. Icelake | |
637 | */ | |
dce86ac7 | 638 | if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) { |
cd6b984f | 639 | if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS)) |
878068ea KL |
640 | return -EINVAL; |
641 | ||
642 | if (!event->attr.precise_ip) | |
643 | return -EINVAL; | |
644 | } | |
645 | ||
9d0fcba6 | 646 | return x86_setup_perfctr(event); |
a098f448 RR |
647 | } |
648 | ||
241771ef | 649 | /* |
0d48696f | 650 | * Setup the hardware configuration for a given attr_type |
241771ef | 651 | */ |
b0a873eb | 652 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 653 | { |
4e935e47 | 654 | int err; |
241771ef | 655 | |
85cf9dba RR |
656 | if (!x86_pmu_initialized()) |
657 | return -ENODEV; | |
241771ef | 658 | |
6b099d9b | 659 | err = x86_reserve_hardware(); |
4e935e47 PZ |
660 | if (err) |
661 | return err; | |
662 | ||
1b7b938f | 663 | atomic_inc(&active_events); |
cdd6c482 | 664 | event->destroy = hw_perf_event_destroy; |
a1792cda | 665 | |
4261e0e0 RR |
666 | event->hw.idx = -1; |
667 | event->hw.last_cpu = -1; | |
668 | event->hw.last_tag = ~0ULL; | |
b690081d | 669 | |
efc9f05d SE |
670 | /* mark unused */ |
671 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
672 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
673 | ||
9d0fcba6 | 674 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
675 | } |
676 | ||
de0428a7 | 677 | void x86_pmu_disable_all(void) |
f87ad35d | 678 | { |
89cbc767 | 679 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
9e35ad38 PZ |
680 | int idx; |
681 | ||
948b1bb8 | 682 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
57388912 | 683 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e PZ |
684 | u64 val; |
685 | ||
43f6201a | 686 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 687 | continue; |
41bf4989 | 688 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 689 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 690 | continue; |
bb1165d6 | 691 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 692 | wrmsrl(x86_pmu_config_addr(idx), val); |
57388912 KP |
693 | if (is_counter_pair(hwc)) |
694 | wrmsrl(x86_pmu_config_addr(idx + 1), 0); | |
f87ad35d | 695 | } |
f87ad35d JSR |
696 | } |
697 | ||
39a4d779 | 698 | struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr, void *data) |
abd562df | 699 | { |
39a4d779 | 700 | return static_call(x86_pmu_guest_get_msrs)(nr, data); |
abd562df LX |
701 | } |
702 | EXPORT_SYMBOL_GPL(perf_guest_get_msrs); | |
703 | ||
c3d266c8 KL |
704 | /* |
705 | * There may be PMI landing after enabled=0. The PMI hitting could be before or | |
706 | * after disable_all. | |
707 | * | |
708 | * If PMI hits before disable_all, the PMU will be disabled in the NMI handler. | |
709 | * It will not be re-enabled in the NMI handler again, because enabled=0. After | |
710 | * handling the NMI, disable_all will be called, which will not change the | |
711 | * state either. If PMI hits after disable_all, the PMU is already disabled | |
712 | * before entering NMI handler. The NMI handler will not change the state | |
713 | * either. | |
714 | * | |
715 | * So either situation is harmless. | |
716 | */ | |
a4eaf7f1 | 717 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 718 | { |
89cbc767 | 719 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 | 720 | |
85cf9dba | 721 | if (!x86_pmu_initialized()) |
9e35ad38 | 722 | return; |
1da53e02 | 723 | |
1a6e21f7 PZ |
724 | if (!cpuc->enabled) |
725 | return; | |
726 | ||
727 | cpuc->n_added = 0; | |
728 | cpuc->enabled = 0; | |
729 | barrier(); | |
1da53e02 | 730 | |
7c9903c9 | 731 | static_call(x86_pmu_disable_all)(); |
b56a3802 | 732 | } |
241771ef | 733 | |
de0428a7 | 734 | void x86_pmu_enable_all(int added) |
f87ad35d | 735 | { |
89cbc767 | 736 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f87ad35d JSR |
737 | int idx; |
738 | ||
948b1bb8 | 739 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 740 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 741 | |
43f6201a | 742 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 743 | continue; |
984b838c | 744 | |
d45dd923 | 745 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
746 | } |
747 | } | |
748 | ||
1da53e02 SE |
749 | static inline int is_x86_event(struct perf_event *event) |
750 | { | |
d9977c43 KL |
751 | int i; |
752 | ||
753 | if (!is_hybrid()) | |
754 | return event->pmu == &pmu; | |
755 | ||
756 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { | |
757 | if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu) | |
758 | return true; | |
759 | } | |
760 | ||
761 | return false; | |
1da53e02 SE |
762 | } |
763 | ||
61e76d53 | 764 | struct pmu *x86_get_pmu(unsigned int cpu) |
f447e4eb | 765 | { |
61e76d53 KL |
766 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
767 | ||
768 | /* | |
769 | * All CPUs of the hybrid type have been offline. | |
770 | * The x86_get_pmu() should not be invoked. | |
771 | */ | |
772 | if (WARN_ON_ONCE(!cpuc->pmu)) | |
773 | return &pmu; | |
774 | ||
775 | return cpuc->pmu; | |
f447e4eb | 776 | } |
1e2ad28f RR |
777 | /* |
778 | * Event scheduler state: | |
779 | * | |
780 | * Assign events iterating over all events and counters, beginning | |
781 | * with events with least weights first. Keep the current iterator | |
782 | * state in struct sched_state. | |
783 | */ | |
784 | struct sched_state { | |
785 | int weight; | |
786 | int event; /* event index */ | |
787 | int counter; /* counter index */ | |
788 | int unassigned; /* number of events to be assigned left */ | |
cc1790cf | 789 | int nr_gp; /* number of GP counters used */ |
57388912 | 790 | u64 used; |
1e2ad28f RR |
791 | }; |
792 | ||
bc1738f6 RR |
793 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
794 | #define SCHED_STATES_MAX 2 | |
795 | ||
1e2ad28f RR |
796 | struct perf_sched { |
797 | int max_weight; | |
798 | int max_events; | |
cc1790cf PZ |
799 | int max_gp; |
800 | int saved_states; | |
b371b594 | 801 | struct event_constraint **constraints; |
1e2ad28f | 802 | struct sched_state state; |
bc1738f6 | 803 | struct sched_state saved[SCHED_STATES_MAX]; |
1e2ad28f RR |
804 | }; |
805 | ||
806 | /* | |
d9f6e12f | 807 | * Initialize iterator that runs through all events and counters. |
1e2ad28f | 808 | */ |
b371b594 | 809 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, |
cc1790cf | 810 | int num, int wmin, int wmax, int gpmax) |
1e2ad28f RR |
811 | { |
812 | int idx; | |
813 | ||
814 | memset(sched, 0, sizeof(*sched)); | |
815 | sched->max_events = num; | |
816 | sched->max_weight = wmax; | |
cc1790cf | 817 | sched->max_gp = gpmax; |
b371b594 | 818 | sched->constraints = constraints; |
1e2ad28f RR |
819 | |
820 | for (idx = 0; idx < num; idx++) { | |
b371b594 | 821 | if (constraints[idx]->weight == wmin) |
1e2ad28f RR |
822 | break; |
823 | } | |
824 | ||
825 | sched->state.event = idx; /* start with min weight */ | |
826 | sched->state.weight = wmin; | |
827 | sched->state.unassigned = num; | |
828 | } | |
829 | ||
bc1738f6 RR |
830 | static void perf_sched_save_state(struct perf_sched *sched) |
831 | { | |
832 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
833 | return; | |
834 | ||
835 | sched->saved[sched->saved_states] = sched->state; | |
836 | sched->saved_states++; | |
837 | } | |
838 | ||
839 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
840 | { | |
841 | if (!sched->saved_states) | |
842 | return false; | |
843 | ||
844 | sched->saved_states--; | |
845 | sched->state = sched->saved[sched->saved_states]; | |
846 | ||
57388912 KP |
847 | /* this assignment didn't work out */ |
848 | /* XXX broken vs EVENT_PAIR */ | |
849 | sched->state.used &= ~BIT_ULL(sched->state.counter); | |
850 | ||
851 | /* try the next one */ | |
852 | sched->state.counter++; | |
bc1738f6 RR |
853 | |
854 | return true; | |
855 | } | |
856 | ||
1e2ad28f RR |
857 | /* |
858 | * Select a counter for the current event to schedule. Return true on | |
859 | * success. | |
860 | */ | |
bc1738f6 | 861 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
862 | { |
863 | struct event_constraint *c; | |
864 | int idx; | |
865 | ||
866 | if (!sched->state.unassigned) | |
867 | return false; | |
868 | ||
869 | if (sched->state.event >= sched->max_events) | |
870 | return false; | |
871 | ||
b371b594 | 872 | c = sched->constraints[sched->state.event]; |
4defea85 | 873 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
874 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
875 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 876 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
57388912 KP |
877 | u64 mask = BIT_ULL(idx); |
878 | ||
879 | if (sched->state.used & mask) | |
880 | continue; | |
881 | ||
882 | sched->state.used |= mask; | |
883 | goto done; | |
4defea85 PZ |
884 | } |
885 | } | |
cc1790cf | 886 | |
1e2ad28f RR |
887 | /* Grab the first unused counter starting with idx */ |
888 | idx = sched->state.counter; | |
15c7ad51 | 889 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
57388912 | 890 | u64 mask = BIT_ULL(idx); |
cc1790cf | 891 | |
57388912 KP |
892 | if (c->flags & PERF_X86_EVENT_PAIR) |
893 | mask |= mask << 1; | |
894 | ||
895 | if (sched->state.used & mask) | |
896 | continue; | |
897 | ||
898 | if (sched->state.nr_gp++ >= sched->max_gp) | |
899 | return false; | |
900 | ||
901 | sched->state.used |= mask; | |
902 | goto done; | |
1e2ad28f | 903 | } |
1e2ad28f | 904 | |
4defea85 PZ |
905 | return false; |
906 | ||
907 | done: | |
908 | sched->state.counter = idx; | |
1e2ad28f | 909 | |
bc1738f6 RR |
910 | if (c->overlap) |
911 | perf_sched_save_state(sched); | |
912 | ||
913 | return true; | |
914 | } | |
915 | ||
916 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
917 | { | |
918 | while (!__perf_sched_find_counter(sched)) { | |
919 | if (!perf_sched_restore_state(sched)) | |
920 | return false; | |
921 | } | |
922 | ||
1e2ad28f RR |
923 | return true; |
924 | } | |
925 | ||
926 | /* | |
927 | * Go through all unassigned events and find the next one to schedule. | |
928 | * Take events with the least weight first. Return true on success. | |
929 | */ | |
930 | static bool perf_sched_next_event(struct perf_sched *sched) | |
931 | { | |
932 | struct event_constraint *c; | |
933 | ||
934 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
935 | return false; | |
936 | ||
937 | do { | |
938 | /* next event */ | |
939 | sched->state.event++; | |
940 | if (sched->state.event >= sched->max_events) { | |
941 | /* next weight */ | |
942 | sched->state.event = 0; | |
943 | sched->state.weight++; | |
944 | if (sched->state.weight > sched->max_weight) | |
945 | return false; | |
946 | } | |
b371b594 | 947 | c = sched->constraints[sched->state.event]; |
1e2ad28f RR |
948 | } while (c->weight != sched->state.weight); |
949 | ||
950 | sched->state.counter = 0; /* start with first counter */ | |
951 | ||
952 | return true; | |
953 | } | |
954 | ||
955 | /* | |
956 | * Assign a counter for each event. | |
957 | */ | |
b371b594 | 958 | int perf_assign_events(struct event_constraint **constraints, int n, |
cc1790cf | 959 | int wmin, int wmax, int gpmax, int *assign) |
1e2ad28f RR |
960 | { |
961 | struct perf_sched sched; | |
962 | ||
cc1790cf | 963 | perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); |
1e2ad28f RR |
964 | |
965 | do { | |
966 | if (!perf_sched_find_counter(&sched)) | |
967 | break; /* failed */ | |
968 | if (assign) | |
969 | assign[sched.state.event] = sched.state.counter; | |
970 | } while (perf_sched_next_event(&sched)); | |
971 | ||
972 | return sched.state.unassigned; | |
973 | } | |
4a3dc121 | 974 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 975 | |
de0428a7 | 976 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 977 | { |
d4b294bf | 978 | int num_counters = hybrid(cpuc->pmu, num_counters); |
43b45780 | 979 | struct event_constraint *c; |
2f7f73a5 | 980 | struct perf_event *e; |
f80deefa | 981 | int n0, i, wmin, wmax, unsched = 0; |
1da53e02 | 982 | struct hw_perf_event *hwc; |
57388912 | 983 | u64 used_mask = 0; |
1da53e02 | 984 | |
f80deefa PZ |
985 | /* |
986 | * Compute the number of events already present; see x86_pmu_add(), | |
987 | * validate_group() and x86_pmu_commit_txn(). For the former two | |
988 | * cpuc->n_events hasn't been updated yet, while for the latter | |
989 | * cpuc->n_txn contains the number of events added in the current | |
990 | * transaction. | |
991 | */ | |
992 | n0 = cpuc->n_events; | |
993 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) | |
994 | n0 -= cpuc->n_txn; | |
995 | ||
7c9903c9 | 996 | static_call_cond(x86_pmu_start_scheduling)(cpuc); |
c5362c0c | 997 | |
1e2ad28f | 998 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
109717de PZ |
999 | c = cpuc->event_constraint[i]; |
1000 | ||
f80deefa PZ |
1001 | /* |
1002 | * Previously scheduled events should have a cached constraint, | |
1003 | * while new events should not have one. | |
1004 | */ | |
1005 | WARN_ON_ONCE((c && i >= n0) || (!c && i < n0)); | |
1006 | ||
109717de PZ |
1007 | /* |
1008 | * Request constraints for new events; or for those events that | |
1009 | * have a dynamic constraint -- for those the constraint can | |
1010 | * change due to external factors (sibling state, allow_tfa). | |
1011 | */ | |
1012 | if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) { | |
7c9903c9 | 1013 | c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]); |
109717de PZ |
1014 | cpuc->event_constraint[i] = c; |
1015 | } | |
43b45780 | 1016 | |
1e2ad28f RR |
1017 | wmin = min(wmin, c->weight); |
1018 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
1019 | } |
1020 | ||
8113070d SE |
1021 | /* |
1022 | * fastpath, try to reuse previous register | |
1023 | */ | |
c933c1a6 | 1024 | for (i = 0; i < n; i++) { |
57388912 KP |
1025 | u64 mask; |
1026 | ||
8113070d | 1027 | hwc = &cpuc->event_list[i]->hw; |
b371b594 | 1028 | c = cpuc->event_constraint[i]; |
8113070d SE |
1029 | |
1030 | /* never assigned */ | |
1031 | if (hwc->idx == -1) | |
1032 | break; | |
1033 | ||
1034 | /* constraint still honored */ | |
63b14649 | 1035 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
1036 | break; |
1037 | ||
57388912 KP |
1038 | mask = BIT_ULL(hwc->idx); |
1039 | if (is_counter_pair(hwc)) | |
1040 | mask |= mask << 1; | |
1041 | ||
8113070d | 1042 | /* not already used */ |
57388912 | 1043 | if (used_mask & mask) |
8113070d SE |
1044 | break; |
1045 | ||
57388912 KP |
1046 | used_mask |= mask; |
1047 | ||
8113070d SE |
1048 | if (assign) |
1049 | assign[i] = hwc->idx; | |
1050 | } | |
8113070d | 1051 | |
1e2ad28f | 1052 | /* slow path */ |
b371b594 | 1053 | if (i != n) { |
d4b294bf | 1054 | int gpmax = num_counters; |
cc1790cf PZ |
1055 | |
1056 | /* | |
1057 | * Do not allow scheduling of more than half the available | |
1058 | * generic counters. | |
1059 | * | |
1060 | * This helps avoid counter starvation of sibling thread by | |
1061 | * ensuring at most half the counters cannot be in exclusive | |
1062 | * mode. There is no designated counters for the limits. Any | |
1063 | * N/2 counters can be used. This helps with events with | |
1064 | * specific counter constraints. | |
1065 | */ | |
1066 | if (is_ht_workaround_enabled() && !cpuc->is_fake && | |
1067 | READ_ONCE(cpuc->excl_cntrs->exclusive_present)) | |
1068 | gpmax /= 2; | |
1069 | ||
57388912 KP |
1070 | /* |
1071 | * Reduce the amount of available counters to allow fitting | |
1072 | * the extra Merge events needed by large increment events. | |
1073 | */ | |
1074 | if (x86_pmu.flags & PMU_FL_PAIR) { | |
d4b294bf | 1075 | gpmax = num_counters - cpuc->n_pair; |
57388912 KP |
1076 | WARN_ON(gpmax <= 0); |
1077 | } | |
1078 | ||
b371b594 | 1079 | unsched = perf_assign_events(cpuc->event_constraint, n, wmin, |
cc1790cf | 1080 | wmax, gpmax, assign); |
b371b594 | 1081 | } |
8113070d | 1082 | |
2f7f73a5 | 1083 | /* |
e979121b MD |
1084 | * In case of success (unsched = 0), mark events as committed, |
1085 | * so we do not put_constraint() in case new events are added | |
1086 | * and fail to be scheduled | |
1087 | * | |
1088 | * We invoke the lower level commit callback to lock the resource | |
1089 | * | |
1090 | * We do not need to do all of this in case we are called to | |
1091 | * validate an event group (assign == NULL) | |
2f7f73a5 | 1092 | */ |
e979121b | 1093 | if (!unsched && assign) { |
4f32da76 | 1094 | for (i = 0; i < n; i++) |
7c9903c9 | 1095 | static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]); |
8736e548 | 1096 | } else { |
f80deefa | 1097 | for (i = n0; i < n; i++) { |
2f7f73a5 | 1098 | e = cpuc->event_list[i]; |
2f7f73a5 | 1099 | |
e979121b MD |
1100 | /* |
1101 | * release events that failed scheduling | |
1102 | */ | |
7c9903c9 | 1103 | static_call_cond(x86_pmu_put_event_constraints)(cpuc, e); |
2c9651c3 PZ |
1104 | |
1105 | cpuc->event_constraint[i] = NULL; | |
1da53e02 SE |
1106 | } |
1107 | } | |
c5362c0c | 1108 | |
7c9903c9 | 1109 | static_call_cond(x86_pmu_stop_scheduling)(cpuc); |
c5362c0c | 1110 | |
e979121b | 1111 | return unsched ? -EINVAL : 0; |
1da53e02 SE |
1112 | } |
1113 | ||
7b2c05a1 KL |
1114 | static int add_nr_metric_event(struct cpu_hw_events *cpuc, |
1115 | struct perf_event *event) | |
1116 | { | |
1117 | if (is_metric_event(event)) { | |
1118 | if (cpuc->n_metric == INTEL_TD_METRIC_NUM) | |
1119 | return -EINVAL; | |
1120 | cpuc->n_metric++; | |
3dbde695 | 1121 | cpuc->n_txn_metric++; |
7b2c05a1 KL |
1122 | } |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
1127 | static void del_nr_metric_event(struct cpu_hw_events *cpuc, | |
1128 | struct perf_event *event) | |
1129 | { | |
1130 | if (is_metric_event(event)) | |
1131 | cpuc->n_metric--; | |
1132 | } | |
1133 | ||
1134 | static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event, | |
1135 | int max_count, int n) | |
1136 | { | |
d0946a88 | 1137 | union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap); |
7b2c05a1 | 1138 | |
d0946a88 | 1139 | if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event)) |
7b2c05a1 KL |
1140 | return -EINVAL; |
1141 | ||
1142 | if (n >= max_count + cpuc->n_metric) | |
1143 | return -EINVAL; | |
1144 | ||
1145 | cpuc->event_list[n] = event; | |
871a93b0 | 1146 | if (is_counter_pair(&event->hw)) { |
7b2c05a1 | 1147 | cpuc->n_pair++; |
871a93b0 PZ |
1148 | cpuc->n_txn_pair++; |
1149 | } | |
7b2c05a1 KL |
1150 | |
1151 | return 0; | |
1152 | } | |
1153 | ||
1da53e02 SE |
1154 | /* |
1155 | * dogrp: true if must collect siblings events (group) | |
1156 | * returns total number of events and error code | |
1157 | */ | |
1158 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
1159 | { | |
d4b294bf KL |
1160 | int num_counters = hybrid(cpuc->pmu, num_counters); |
1161 | int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); | |
1da53e02 SE |
1162 | struct perf_event *event; |
1163 | int n, max_count; | |
1164 | ||
d4b294bf | 1165 | max_count = num_counters + num_counters_fixed; |
1da53e02 SE |
1166 | |
1167 | /* current number of events already accepted */ | |
1168 | n = cpuc->n_events; | |
42880f72 AS |
1169 | if (!cpuc->n_events) |
1170 | cpuc->pebs_output = 0; | |
1171 | ||
1172 | if (!cpuc->is_fake && leader->attr.precise_ip) { | |
1173 | /* | |
1174 | * For PEBS->PT, if !aux_event, the group leader (PT) went | |
1175 | * away, the group was broken down and this singleton event | |
1176 | * can't schedule any more. | |
1177 | */ | |
1178 | if (is_pebs_pt(leader) && !leader->aux_event) | |
1179 | return -EINVAL; | |
1180 | ||
1181 | /* | |
1182 | * pebs_output: 0: no PEBS so far, 1: PT, 2: DS | |
1183 | */ | |
1184 | if (cpuc->pebs_output && | |
1185 | cpuc->pebs_output != is_pebs_pt(leader) + 1) | |
1186 | return -EINVAL; | |
1187 | ||
1188 | cpuc->pebs_output = is_pebs_pt(leader) + 1; | |
1189 | } | |
1da53e02 SE |
1190 | |
1191 | if (is_x86_event(leader)) { | |
7b2c05a1 | 1192 | if (collect_event(cpuc, leader, max_count, n)) |
aa2bc1ad | 1193 | return -EINVAL; |
1da53e02 SE |
1194 | n++; |
1195 | } | |
7b2c05a1 | 1196 | |
1da53e02 SE |
1197 | if (!dogrp) |
1198 | return n; | |
1199 | ||
edb39592 | 1200 | for_each_sibling_event(event, leader) { |
7b2c05a1 | 1201 | if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
1202 | continue; |
1203 | ||
7b2c05a1 | 1204 | if (collect_event(cpuc, event, max_count, n)) |
aa2bc1ad | 1205 | return -EINVAL; |
1da53e02 | 1206 | |
1da53e02 SE |
1207 | n++; |
1208 | } | |
1209 | return n; | |
1210 | } | |
1211 | ||
1da53e02 | 1212 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 1213 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 1214 | { |
447a194b | 1215 | struct hw_perf_event *hwc = &event->hw; |
027440b5 | 1216 | int idx; |
447a194b | 1217 | |
027440b5 | 1218 | idx = hwc->idx = cpuc->assign[i]; |
447a194b SE |
1219 | hwc->last_cpu = smp_processor_id(); |
1220 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 1221 | |
8b8ff8cc AH |
1222 | static_call_cond(x86_pmu_assign)(event, idx); |
1223 | ||
027440b5 LX |
1224 | switch (hwc->idx) { |
1225 | case INTEL_PMC_IDX_FIXED_BTS: | |
097e4311 | 1226 | case INTEL_PMC_IDX_FIXED_VLBR: |
1da53e02 SE |
1227 | hwc->config_base = 0; |
1228 | hwc->event_base = 0; | |
027440b5 LX |
1229 | break; |
1230 | ||
7b2c05a1 KL |
1231 | case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: |
1232 | /* All the metric events are mapped onto the fixed counter 3. */ | |
1233 | idx = INTEL_PMC_IDX_FIXED_SLOTS; | |
b6459575 | 1234 | fallthrough; |
027440b5 | 1235 | case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1: |
1da53e02 | 1236 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
027440b5 LX |
1237 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + |
1238 | (idx - INTEL_PMC_IDX_FIXED); | |
0e2e45e2 KL |
1239 | hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) | |
1240 | INTEL_PMC_FIXED_RDPMC_BASE; | |
027440b5 LX |
1241 | break; |
1242 | ||
1243 | default: | |
73d6e522 RR |
1244 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
1245 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 1246 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
027440b5 | 1247 | break; |
1da53e02 SE |
1248 | } |
1249 | } | |
1250 | ||
1182a495 RC |
1251 | /** |
1252 | * x86_perf_rdpmc_index - Return PMC counter used for event | |
1253 | * @event: the perf_event to which the PMC counter was assigned | |
1254 | * | |
1255 | * The counter assigned to this performance event may change if interrupts | |
1256 | * are enabled. This counter should thus never be used while interrupts are | |
1257 | * enabled. Before this function is used to obtain the assigned counter the | |
1258 | * event should be checked for validity using, for example, | |
1259 | * perf_event_read_local(), within the same interrupt disabled section in | |
1260 | * which this counter is planned to be used. | |
1261 | * | |
1262 | * Return: The index of the performance monitoring counter assigned to | |
1263 | * @perf_event. | |
1264 | */ | |
1265 | int x86_perf_rdpmc_index(struct perf_event *event) | |
1266 | { | |
1267 | lockdep_assert_irqs_disabled(); | |
1268 | ||
1269 | return event->hw.event_base_rdpmc; | |
1270 | } | |
1271 | ||
447a194b SE |
1272 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
1273 | struct cpu_hw_events *cpuc, | |
1274 | int i) | |
1275 | { | |
1276 | return hwc->idx == cpuc->assign[i] && | |
1277 | hwc->last_cpu == smp_processor_id() && | |
1278 | hwc->last_tag == cpuc->tags[i]; | |
1279 | } | |
1280 | ||
a4eaf7f1 | 1281 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 1282 | |
a4eaf7f1 | 1283 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 1284 | { |
89cbc767 | 1285 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1286 | struct perf_event *event; |
1287 | struct hw_perf_event *hwc; | |
11164cd4 | 1288 | int i, added = cpuc->n_added; |
1da53e02 | 1289 | |
85cf9dba | 1290 | if (!x86_pmu_initialized()) |
2b9ff0db | 1291 | return; |
1a6e21f7 PZ |
1292 | |
1293 | if (cpuc->enabled) | |
1294 | return; | |
1295 | ||
1da53e02 | 1296 | if (cpuc->n_added) { |
19925ce7 | 1297 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
1298 | /* |
1299 | * apply assignment obtained either from | |
1300 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
1301 | * | |
1302 | * step1: save events moving to new counters | |
1da53e02 | 1303 | */ |
19925ce7 | 1304 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
1305 | event = cpuc->event_list[i]; |
1306 | hwc = &event->hw; | |
1307 | ||
447a194b SE |
1308 | /* |
1309 | * we can avoid reprogramming counter if: | |
1310 | * - assigned same counter as last time | |
1311 | * - running on same CPU as last time | |
1312 | * - no other event has used the counter since | |
1313 | */ | |
1314 | if (hwc->idx == -1 || | |
1315 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
1316 | continue; |
1317 | ||
a4eaf7f1 PZ |
1318 | /* |
1319 | * Ensure we don't accidentally enable a stopped | |
1320 | * counter simply because we rescheduled. | |
1321 | */ | |
1322 | if (hwc->state & PERF_HES_STOPPED) | |
1323 | hwc->state |= PERF_HES_ARCH; | |
1324 | ||
1325 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
1326 | } |
1327 | ||
c347a2f1 PZ |
1328 | /* |
1329 | * step2: reprogram moved events into new counters | |
1330 | */ | |
1da53e02 | 1331 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
1332 | event = cpuc->event_list[i]; |
1333 | hwc = &event->hw; | |
1334 | ||
45e16a68 | 1335 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 1336 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
1337 | else if (i < n_running) |
1338 | continue; | |
1da53e02 | 1339 | |
a4eaf7f1 PZ |
1340 | if (hwc->state & PERF_HES_ARCH) |
1341 | continue; | |
1342 | ||
ada54345 SE |
1343 | /* |
1344 | * if cpuc->enabled = 0, then no wrmsr as | |
1345 | * per x86_pmu_enable_event() | |
1346 | */ | |
a4eaf7f1 | 1347 | x86_pmu_start(event, PERF_EF_RELOAD); |
1da53e02 SE |
1348 | } |
1349 | cpuc->n_added = 0; | |
1350 | perf_events_lapic_init(); | |
1351 | } | |
1a6e21f7 PZ |
1352 | |
1353 | cpuc->enabled = 1; | |
1354 | barrier(); | |
1355 | ||
7c9903c9 | 1356 | static_call(x86_pmu_enable_all)(added); |
ee06094f | 1357 | } |
ee06094f | 1358 | |
dbf4e792 | 1359 | DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1360 | |
ee06094f IM |
1361 | /* |
1362 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1363 | * To be called with the event disabled in hw: |
ee06094f | 1364 | */ |
de0428a7 | 1365 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1366 | { |
07088edb | 1367 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1368 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1369 | s64 period = hwc->sample_period; |
7645a24c | 1370 | int ret = 0, idx = hwc->idx; |
ee06094f | 1371 | |
027440b5 | 1372 | if (unlikely(!hwc->event_base)) |
30dd568c MM |
1373 | return 0; |
1374 | ||
ee06094f | 1375 | /* |
af901ca1 | 1376 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1377 | */ |
1378 | if (unlikely(left <= -period)) { | |
1379 | left = period; | |
e7850595 | 1380 | local64_set(&hwc->period_left, left); |
9e350de3 | 1381 | hwc->last_period = period; |
e4abb5d4 | 1382 | ret = 1; |
ee06094f IM |
1383 | } |
1384 | ||
1385 | if (unlikely(left <= 0)) { | |
1386 | left += period; | |
e7850595 | 1387 | local64_set(&hwc->period_left, left); |
9e350de3 | 1388 | hwc->last_period = period; |
e4abb5d4 | 1389 | ret = 1; |
ee06094f | 1390 | } |
1c80f4b5 | 1391 | /* |
dfc65094 | 1392 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1393 | */ |
1394 | if (unlikely(left < 2)) | |
1395 | left = 2; | |
241771ef | 1396 | |
e4abb5d4 PZ |
1397 | if (left > x86_pmu.max_period) |
1398 | left = x86_pmu.max_period; | |
1399 | ||
08b3068f | 1400 | static_call_cond(x86_pmu_limit_period)(event, &left); |
294fe0f5 | 1401 | |
28f0f3c4 | 1402 | this_cpu_write(pmc_prev_left[idx], left); |
ee06094f | 1403 | |
d31fc13f KL |
1404 | /* |
1405 | * The hw event starts counting from this event offset, | |
1406 | * mark it to be able to extra future deltas: | |
1407 | */ | |
1408 | local64_set(&hwc->prev_count, (u64)-left); | |
ee06094f | 1409 | |
d31fc13f | 1410 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1411 | |
57388912 | 1412 | /* |
26e52558 | 1413 | * Sign extend the Merge event counter's upper 16 bits since |
57388912 KP |
1414 | * we currently declare a 48-bit counter width |
1415 | */ | |
1416 | if (is_counter_pair(hwc)) | |
26e52558 | 1417 | wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff); |
57388912 | 1418 | |
cdd6c482 | 1419 | perf_event_update_userpage(event); |
194002b2 | 1420 | |
e4abb5d4 | 1421 | return ret; |
2f18d1e8 IM |
1422 | } |
1423 | ||
de0428a7 | 1424 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1425 | { |
0a3aee0d | 1426 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1427 | __x86_pmu_enable_event(&event->hw, |
1428 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1429 | } |
1430 | ||
b690081d | 1431 | /* |
a4eaf7f1 | 1432 | * Add a single event to the PMU. |
1da53e02 SE |
1433 | * |
1434 | * The event is added to the group of enabled events | |
77d76032 | 1435 | * but only if it can be scheduled with existing events. |
fe9081cc | 1436 | */ |
a4eaf7f1 | 1437 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc | 1438 | { |
89cbc767 | 1439 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1440 | struct hw_perf_event *hwc; |
1441 | int assign[X86_PMC_IDX_MAX]; | |
1442 | int n, n0, ret; | |
fe9081cc | 1443 | |
1da53e02 | 1444 | hwc = &event->hw; |
fe9081cc | 1445 | |
1da53e02 | 1446 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1447 | ret = n = collect_events(cpuc, event, false); |
1448 | if (ret < 0) | |
1449 | goto out; | |
53b441a5 | 1450 | |
a4eaf7f1 PZ |
1451 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1452 | if (!(flags & PERF_EF_START)) | |
1453 | hwc->state |= PERF_HES_ARCH; | |
1454 | ||
4d1c52b0 LM |
1455 | /* |
1456 | * If group events scheduling transaction was started, | |
0d2eb44f | 1457 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1458 | * at commit time (->commit_txn) as a whole. |
68f7082f PZ |
1459 | * |
1460 | * If commit fails, we'll call ->del() on all events | |
1461 | * for which ->add() was called. | |
4d1c52b0 | 1462 | */ |
8f3e5684 | 1463 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
24cd7f54 | 1464 | goto done_collect; |
4d1c52b0 | 1465 | |
7c9903c9 | 1466 | ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign); |
1da53e02 | 1467 | if (ret) |
24cd7f54 | 1468 | goto out; |
1da53e02 SE |
1469 | /* |
1470 | * copy new assignment, now we know it is possible | |
1471 | * will be used by hw_perf_enable() | |
1472 | */ | |
1473 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1474 | |
24cd7f54 | 1475 | done_collect: |
c347a2f1 PZ |
1476 | /* |
1477 | * Commit the collect_events() state. See x86_pmu_del() and | |
1478 | * x86_pmu_*_txn(). | |
1479 | */ | |
1da53e02 | 1480 | cpuc->n_events = n; |
356e1f2e | 1481 | cpuc->n_added += n - n0; |
90151c35 | 1482 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1483 | |
7c9903c9 PZ |
1484 | /* |
1485 | * This is before x86_pmu_enable() will call x86_pmu_start(), | |
1486 | * so we enable LBRs before an event needs them etc.. | |
1487 | */ | |
1488 | static_call_cond(x86_pmu_add)(event); | |
68f7082f | 1489 | |
24cd7f54 PZ |
1490 | ret = 0; |
1491 | out: | |
24cd7f54 | 1492 | return ret; |
241771ef IM |
1493 | } |
1494 | ||
a4eaf7f1 | 1495 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1496 | { |
89cbc767 | 1497 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
c08053e6 PZ |
1498 | int idx = event->hw.idx; |
1499 | ||
a4eaf7f1 PZ |
1500 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1501 | return; | |
1502 | ||
1503 | if (WARN_ON_ONCE(idx == -1)) | |
1504 | return; | |
1505 | ||
1506 | if (flags & PERF_EF_RELOAD) { | |
1507 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
73759c34 | 1508 | static_call(x86_pmu_set_period)(event); |
a4eaf7f1 PZ |
1509 | } |
1510 | ||
1511 | event->hw.state = 0; | |
d76a0812 | 1512 | |
c08053e6 PZ |
1513 | cpuc->events[idx] = event; |
1514 | __set_bit(idx, cpuc->active_mask); | |
7c9903c9 | 1515 | static_call(x86_pmu_enable)(event); |
c08053e6 | 1516 | perf_event_update_userpage(event); |
a78ac325 PZ |
1517 | } |
1518 | ||
cdd6c482 | 1519 | void perf_event_print_debug(void) |
241771ef | 1520 | { |
2f18d1e8 | 1521 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
da3e606d | 1522 | u64 pebs, debugctl; |
d4b294bf KL |
1523 | int cpu = smp_processor_id(); |
1524 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
1525 | int num_counters = hybrid(cpuc->pmu, num_counters); | |
1526 | int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); | |
24ee38ff | 1527 | struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints); |
5bb9efe3 | 1528 | unsigned long flags; |
d4b294bf | 1529 | int idx; |
1e125676 | 1530 | |
d4b294bf | 1531 | if (!num_counters) |
1e125676 | 1532 | return; |
241771ef | 1533 | |
5bb9efe3 | 1534 | local_irq_save(flags); |
241771ef | 1535 | |
faa28ae0 | 1536 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1537 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1538 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1539 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1540 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1541 | ||
1542 | pr_info("\n"); | |
1543 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1544 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1545 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1546 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
24ee38ff | 1547 | if (pebs_constraints) { |
15fde110 AK |
1548 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
1549 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); | |
1550 | } | |
da3e606d AK |
1551 | if (x86_pmu.lbr_nr) { |
1552 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
1553 | pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); | |
1554 | } | |
f87ad35d | 1555 | } |
7645a24c | 1556 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1557 | |
d4b294bf | 1558 | for (idx = 0; idx < num_counters; idx++) { |
41bf4989 RR |
1559 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1560 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1561 | |
245b2e70 | 1562 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1563 | |
a1ef58f4 | 1564 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1565 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1566 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1567 | cpu, idx, pmc_count); |
a1ef58f4 | 1568 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1569 | cpu, idx, prev_left); |
241771ef | 1570 | } |
d4b294bf | 1571 | for (idx = 0; idx < num_counters_fixed; idx++) { |
fc4b8fca | 1572 | if (fixed_counter_disabled(idx, cpuc->pmu)) |
32451614 | 1573 | continue; |
2f18d1e8 IM |
1574 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1575 | ||
a1ef58f4 | 1576 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1577 | cpu, idx, pmc_count); |
1578 | } | |
5bb9efe3 | 1579 | local_irq_restore(flags); |
241771ef IM |
1580 | } |
1581 | ||
de0428a7 | 1582 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1583 | { |
89cbc767 | 1584 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1585 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1586 | |
3966c3fe | 1587 | if (test_bit(hwc->idx, cpuc->active_mask)) { |
7c9903c9 | 1588 | static_call(x86_pmu_disable)(event); |
3966c3fe | 1589 | __clear_bit(hwc->idx, cpuc->active_mask); |
a4eaf7f1 PZ |
1590 | cpuc->events[hwc->idx] = NULL; |
1591 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1592 | hwc->state |= PERF_HES_STOPPED; | |
1593 | } | |
30dd568c | 1594 | |
a4eaf7f1 PZ |
1595 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1596 | /* | |
1597 | * Drain the remaining delta count out of a event | |
1598 | * that we are disabling: | |
1599 | */ | |
73759c34 | 1600 | static_call(x86_pmu_update)(event); |
a4eaf7f1 PZ |
1601 | hwc->state |= PERF_HES_UPTODATE; |
1602 | } | |
2e841873 PZ |
1603 | } |
1604 | ||
a4eaf7f1 | 1605 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 | 1606 | { |
89cbc767 | 1607 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
d0946a88 | 1608 | union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap); |
2e841873 PZ |
1609 | int i; |
1610 | ||
90151c35 | 1611 | /* |
68f7082f | 1612 | * If we're called during a txn, we only need to undo x86_pmu.add. |
90151c35 SE |
1613 | * The events never got scheduled and ->cancel_txn will truncate |
1614 | * the event_list. | |
c347a2f1 PZ |
1615 | * |
1616 | * XXX assumes any ->del() called during a TXN will only be on | |
1617 | * an event added during that same TXN. | |
90151c35 | 1618 | */ |
8f3e5684 | 1619 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
68f7082f | 1620 | goto do_del; |
90151c35 | 1621 | |
5471eea5 KL |
1622 | __set_bit(event->hw.idx, cpuc->dirty); |
1623 | ||
c347a2f1 PZ |
1624 | /* |
1625 | * Not a TXN, therefore cleanup properly. | |
1626 | */ | |
a4eaf7f1 | 1627 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1628 | |
1da53e02 | 1629 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1630 | if (event == cpuc->event_list[i]) |
1631 | break; | |
1632 | } | |
1da53e02 | 1633 | |
c347a2f1 PZ |
1634 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1635 | return; | |
26e61e89 | 1636 | |
c347a2f1 PZ |
1637 | /* If we have a newly added event; make sure to decrease n_added. */ |
1638 | if (i >= cpuc->n_events - cpuc->n_added) | |
1639 | --cpuc->n_added; | |
1da53e02 | 1640 | |
7c9903c9 | 1641 | static_call_cond(x86_pmu_put_event_constraints)(cpuc, event); |
c347a2f1 PZ |
1642 | |
1643 | /* Delete the array entry. */ | |
b371b594 | 1644 | while (++i < cpuc->n_events) { |
c347a2f1 | 1645 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
b371b594 | 1646 | cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; |
dec8ced8 | 1647 | cpuc->assign[i-1] = cpuc->assign[i]; |
b371b594 | 1648 | } |
2c9651c3 | 1649 | cpuc->event_constraint[i-1] = NULL; |
c347a2f1 | 1650 | --cpuc->n_events; |
d0946a88 | 1651 | if (intel_cap.perf_metrics) |
7b2c05a1 | 1652 | del_nr_metric_event(cpuc, event); |
1da53e02 | 1653 | |
cdd6c482 | 1654 | perf_event_update_userpage(event); |
68f7082f PZ |
1655 | |
1656 | do_del: | |
7c9903c9 PZ |
1657 | |
1658 | /* | |
1659 | * This is after x86_pmu_stop(); so we disable LBRs after any | |
1660 | * event can need them etc.. | |
1661 | */ | |
1662 | static_call_cond(x86_pmu_del)(event); | |
241771ef IM |
1663 | } |
1664 | ||
de0428a7 | 1665 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1666 | { |
df1a132b | 1667 | struct perf_sample_data data; |
cdd6c482 IM |
1668 | struct cpu_hw_events *cpuc; |
1669 | struct perf_event *event; | |
11d1578f | 1670 | int idx, handled = 0; |
9029a5e3 IM |
1671 | u64 val; |
1672 | ||
89cbc767 | 1673 | cpuc = this_cpu_ptr(&cpu_hw_events); |
962bf7a6 | 1674 | |
2bce5dac DZ |
1675 | /* |
1676 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1677 | * inside the nmi handler. As a result, the unmasking was pushed | |
1678 | * into all the nmi handlers. | |
1679 | * | |
1680 | * This generic handler doesn't seem to have any issues where the | |
1681 | * unmasking occurs so it was left at the top. | |
1682 | */ | |
1683 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1684 | ||
948b1bb8 | 1685 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
3966c3fe | 1686 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1687 | continue; |
962bf7a6 | 1688 | |
cdd6c482 | 1689 | event = cpuc->events[idx]; |
a4016a79 | 1690 | |
73759c34 | 1691 | val = static_call(x86_pmu_update)(event); |
948b1bb8 | 1692 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1693 | continue; |
962bf7a6 | 1694 | |
9e350de3 | 1695 | /* |
cdd6c482 | 1696 | * event overflow |
9e350de3 | 1697 | */ |
4177c42a | 1698 | handled++; |
9e350de3 | 1699 | |
73759c34 | 1700 | if (!static_call(x86_pmu_set_period)(event)) |
e4abb5d4 PZ |
1701 | continue; |
1702 | ||
ada54345 SE |
1703 | perf_sample_data_init(&data, 0, event->hw.last_period); |
1704 | ||
90befef5 | 1705 | if (has_branch_stack(event)) |
571d91dc | 1706 | perf_sample_save_brstack(&data, event, &cpuc->lbr_stack, NULL); |
ada54345 | 1707 | |
a8b0ca17 | 1708 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1709 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1710 | } |
962bf7a6 | 1711 | |
9e350de3 PZ |
1712 | if (handled) |
1713 | inc_irq_stat(apic_perf_irqs); | |
1714 | ||
a29aa8a7 RR |
1715 | return handled; |
1716 | } | |
39d81eab | 1717 | |
cdd6c482 | 1718 | void perf_events_lapic_init(void) |
241771ef | 1719 | { |
04da8a43 | 1720 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1721 | return; |
85cf9dba | 1722 | |
241771ef | 1723 | /* |
c323d95f | 1724 | * Always use NMI for PMU |
241771ef | 1725 | */ |
c323d95f | 1726 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1727 | } |
1728 | ||
9326638c | 1729 | static int |
9c48f1c6 | 1730 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1731 | { |
14c63f17 DH |
1732 | u64 start_clock; |
1733 | u64 finish_clock; | |
e8a923cc | 1734 | int ret; |
14c63f17 | 1735 | |
1b7b938f AS |
1736 | /* |
1737 | * All PMUs/events that share this PMI handler should make sure to | |
1738 | * increment active_events for their events. | |
1739 | */ | |
cdd6c482 | 1740 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1741 | return NMI_DONE; |
4177c42a | 1742 | |
e8a923cc | 1743 | start_clock = sched_clock(); |
7c9903c9 | 1744 | ret = static_call(x86_pmu_handle_irq)(regs); |
e8a923cc | 1745 | finish_clock = sched_clock(); |
14c63f17 DH |
1746 | |
1747 | perf_sample_event_took(finish_clock - start_clock); | |
1748 | ||
1749 | return ret; | |
241771ef | 1750 | } |
9326638c | 1751 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1752 | |
de0428a7 KW |
1753 | struct event_constraint emptyconstraint; |
1754 | struct event_constraint unconstrained; | |
f87ad35d | 1755 | |
95ca792c | 1756 | static int x86_pmu_prepare_cpu(unsigned int cpu) |
3f6da390 | 1757 | { |
7fdba1ca | 1758 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
95ca792c | 1759 | int i; |
3f6da390 | 1760 | |
95ca792c TG |
1761 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) |
1762 | cpuc->kfree_on_online[i] = NULL; | |
1763 | if (x86_pmu.cpu_prepare) | |
1764 | return x86_pmu.cpu_prepare(cpu); | |
1765 | return 0; | |
1766 | } | |
7fdba1ca | 1767 | |
95ca792c TG |
1768 | static int x86_pmu_dead_cpu(unsigned int cpu) |
1769 | { | |
1770 | if (x86_pmu.cpu_dead) | |
1771 | x86_pmu.cpu_dead(cpu); | |
1772 | return 0; | |
1773 | } | |
3f6da390 | 1774 | |
95ca792c TG |
1775 | static int x86_pmu_online_cpu(unsigned int cpu) |
1776 | { | |
1777 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
1778 | int i; | |
3f6da390 | 1779 | |
95ca792c TG |
1780 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { |
1781 | kfree(cpuc->kfree_on_online[i]); | |
1782 | cpuc->kfree_on_online[i] = NULL; | |
3f6da390 | 1783 | } |
95ca792c TG |
1784 | return 0; |
1785 | } | |
3f6da390 | 1786 | |
95ca792c TG |
1787 | static int x86_pmu_starting_cpu(unsigned int cpu) |
1788 | { | |
1789 | if (x86_pmu.cpu_starting) | |
1790 | x86_pmu.cpu_starting(cpu); | |
1791 | return 0; | |
1792 | } | |
1793 | ||
1794 | static int x86_pmu_dying_cpu(unsigned int cpu) | |
1795 | { | |
1796 | if (x86_pmu.cpu_dying) | |
1797 | x86_pmu.cpu_dying(cpu); | |
1798 | return 0; | |
3f6da390 PZ |
1799 | } |
1800 | ||
12558038 CG |
1801 | static void __init pmu_check_apic(void) |
1802 | { | |
93984fbd | 1803 | if (boot_cpu_has(X86_FEATURE_APIC)) |
12558038 CG |
1804 | return; |
1805 | ||
1806 | x86_pmu.apic = 0; | |
1807 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1808 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1809 | |
1810 | /* | |
1811 | * If we have a PMU initialized but no APIC | |
1812 | * interrupts, we cannot sample hardware | |
1813 | * events (user-space has to fall back and | |
1814 | * sample via a hrtimer based software event): | |
1815 | */ | |
1816 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1817 | ||
12558038 CG |
1818 | } |
1819 | ||
2766d2ee | 1820 | static struct attribute_group x86_pmu_format_group __ro_after_init = { |
641cc938 JO |
1821 | .name = "format", |
1822 | .attrs = NULL, | |
1823 | }; | |
1824 | ||
c7ab62bf | 1825 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page) |
a4747393 | 1826 | { |
1e69a0ef | 1827 | struct perf_pmu_events_attr *pmu_attr = |
a4747393 | 1828 | container_of(attr, struct perf_pmu_events_attr, attr); |
1e69a0ef PZ |
1829 | u64 config = 0; |
1830 | ||
1831 | if (pmu_attr->id < x86_pmu.max_events) | |
1832 | config = x86_pmu.event_map(pmu_attr->id); | |
a4747393 | 1833 | |
3a54aaa0 SE |
1834 | /* string trumps id */ |
1835 | if (pmu_attr->event_str) | |
7bebfe9d | 1836 | return sprintf(page, "%s\n", pmu_attr->event_str); |
a4747393 | 1837 | |
3a54aaa0 SE |
1838 | return x86_pmu.events_sysfs_show(page, config); |
1839 | } | |
c7ab62bf | 1840 | EXPORT_SYMBOL_GPL(events_sysfs_show); |
a4747393 | 1841 | |
fc07e9f9 AK |
1842 | ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, |
1843 | char *page) | |
1844 | { | |
1845 | struct perf_pmu_events_ht_attr *pmu_attr = | |
1846 | container_of(attr, struct perf_pmu_events_ht_attr, attr); | |
1847 | ||
1848 | /* | |
1849 | * Report conditional events depending on Hyper-Threading. | |
1850 | * | |
1851 | * This is overly conservative as usually the HT special | |
1852 | * handling is not needed if the other CPU thread is idle. | |
1853 | * | |
1854 | * Note this does not (and cannot) handle the case when thread | |
1855 | * siblings are invisible, for example with virtualization | |
1856 | * if they are owned by some other guest. The user tool | |
1857 | * has to re-read when a thread sibling gets onlined later. | |
1858 | */ | |
1859 | return sprintf(page, "%s", | |
1860 | topology_max_smt_threads() > 1 ? | |
1861 | pmu_attr->event_str_ht : | |
1862 | pmu_attr->event_str_noht); | |
1863 | } | |
1864 | ||
a9c81ccd KL |
1865 | ssize_t events_hybrid_sysfs_show(struct device *dev, |
1866 | struct device_attribute *attr, | |
1867 | char *page) | |
1868 | { | |
1869 | struct perf_pmu_events_hybrid_attr *pmu_attr = | |
1870 | container_of(attr, struct perf_pmu_events_hybrid_attr, attr); | |
1871 | struct x86_hybrid_pmu *pmu; | |
1872 | const char *str, *next_str; | |
1873 | int i; | |
1874 | ||
1875 | if (hweight64(pmu_attr->pmu_type) == 1) | |
1876 | return sprintf(page, "%s", pmu_attr->event_str); | |
1877 | ||
1878 | /* | |
1879 | * Hybrid PMUs may support the same event name, but with different | |
1880 | * event encoding, e.g., the mem-loads event on an Atom PMU has | |
1881 | * different event encoding from a Core PMU. | |
1882 | * | |
1883 | * The event_str includes all event encodings. Each event encoding | |
1884 | * is divided by ";". The order of the event encodings must follow | |
1885 | * the order of the hybrid PMU index. | |
1886 | */ | |
1887 | pmu = container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); | |
1888 | ||
1889 | str = pmu_attr->event_str; | |
1890 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { | |
b0560bfd | 1891 | if (!(x86_pmu.hybrid_pmu[i].pmu_type & pmu_attr->pmu_type)) |
a9c81ccd | 1892 | continue; |
b0560bfd | 1893 | if (x86_pmu.hybrid_pmu[i].pmu_type & pmu->pmu_type) { |
a9c81ccd KL |
1894 | next_str = strchr(str, ';'); |
1895 | if (next_str) | |
1896 | return snprintf(page, next_str - str + 1, "%s", str); | |
1897 | else | |
1898 | return sprintf(page, "%s", str); | |
1899 | } | |
1900 | str = strchr(str, ';'); | |
1901 | str++; | |
1902 | } | |
1903 | ||
1904 | return 0; | |
1905 | } | |
1906 | EXPORT_SYMBOL_GPL(events_hybrid_sysfs_show); | |
1907 | ||
a4747393 JO |
1908 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); |
1909 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1910 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1911 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1912 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1913 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1914 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1915 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1916 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1917 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1918 | ||
1919 | static struct attribute *empty_attrs; | |
1920 | ||
95d18aa2 | 1921 | static struct attribute *events_attr[] = { |
a4747393 JO |
1922 | EVENT_PTR(CPU_CYCLES), |
1923 | EVENT_PTR(INSTRUCTIONS), | |
1924 | EVENT_PTR(CACHE_REFERENCES), | |
1925 | EVENT_PTR(CACHE_MISSES), | |
1926 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1927 | EVENT_PTR(BRANCH_MISSES), | |
1928 | EVENT_PTR(BUS_CYCLES), | |
1929 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1930 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1931 | EVENT_PTR(REF_CPU_CYCLES), | |
1932 | NULL, | |
1933 | }; | |
1934 | ||
3d567273 JO |
1935 | /* |
1936 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1937 | * out of events_attr attributes. | |
1938 | */ | |
1939 | static umode_t | |
1940 | is_visible(struct kobject *kobj, struct attribute *attr, int idx) | |
1941 | { | |
1942 | struct perf_pmu_events_attr *pmu_attr; | |
1943 | ||
1e69a0ef PZ |
1944 | if (idx >= x86_pmu.max_events) |
1945 | return 0; | |
1946 | ||
3d567273 JO |
1947 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); |
1948 | /* str trumps id */ | |
1949 | return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0; | |
1950 | } | |
1951 | ||
2766d2ee | 1952 | static struct attribute_group x86_pmu_events_group __ro_after_init = { |
a4747393 JO |
1953 | .name = "events", |
1954 | .attrs = events_attr, | |
3d567273 | 1955 | .is_visible = is_visible, |
a4747393 JO |
1956 | }; |
1957 | ||
0bf79d44 | 1958 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1959 | { |
43c032fe JO |
1960 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1961 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1962 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1963 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1964 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1965 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1966 | ssize_t ret; | |
1967 | ||
1968 | /* | |
1969 | * We have whole page size to spend and just little data | |
1970 | * to write, so we can safely use sprintf. | |
1971 | */ | |
1972 | ret = sprintf(page, "event=0x%02llx", event); | |
1973 | ||
1974 | if (umask) | |
1975 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1976 | ||
1977 | if (edge) | |
1978 | ret += sprintf(page + ret, ",edge"); | |
1979 | ||
1980 | if (pc) | |
1981 | ret += sprintf(page + ret, ",pc"); | |
1982 | ||
1983 | if (any) | |
1984 | ret += sprintf(page + ret, ",any"); | |
1985 | ||
1986 | if (inv) | |
1987 | ret += sprintf(page + ret, ",inv"); | |
1988 | ||
1989 | if (cmask) | |
1990 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1991 | ||
1992 | ret += sprintf(page + ret, "\n"); | |
1993 | ||
1994 | return ret; | |
1995 | } | |
1996 | ||
6089327f | 1997 | static struct attribute_group x86_pmu_attr_group; |
5da382eb | 1998 | static struct attribute_group x86_pmu_caps_group; |
6089327f | 1999 | |
7c9903c9 PZ |
2000 | static void x86_pmu_static_call_update(void) |
2001 | { | |
2002 | static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq); | |
2003 | static_call_update(x86_pmu_disable_all, x86_pmu.disable_all); | |
2004 | static_call_update(x86_pmu_enable_all, x86_pmu.enable_all); | |
2005 | static_call_update(x86_pmu_enable, x86_pmu.enable); | |
2006 | static_call_update(x86_pmu_disable, x86_pmu.disable); | |
2007 | ||
8b8ff8cc AH |
2008 | static_call_update(x86_pmu_assign, x86_pmu.assign); |
2009 | ||
7c9903c9 PZ |
2010 | static_call_update(x86_pmu_add, x86_pmu.add); |
2011 | static_call_update(x86_pmu_del, x86_pmu.del); | |
2012 | static_call_update(x86_pmu_read, x86_pmu.read); | |
2013 | ||
73759c34 PZ |
2014 | static_call_update(x86_pmu_set_period, x86_pmu.set_period); |
2015 | static_call_update(x86_pmu_update, x86_pmu.update); | |
08b3068f | 2016 | static_call_update(x86_pmu_limit_period, x86_pmu.limit_period); |
73759c34 | 2017 | |
7c9903c9 PZ |
2018 | static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events); |
2019 | static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints); | |
2020 | static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints); | |
2021 | ||
2022 | static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling); | |
2023 | static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling); | |
2024 | static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling); | |
2025 | ||
2026 | static_call_update(x86_pmu_sched_task, x86_pmu.sched_task); | |
2027 | static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx); | |
2028 | ||
2029 | static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs); | |
2030 | static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases); | |
abd562df LX |
2031 | |
2032 | static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs); | |
bd275681 | 2033 | static_call_update(x86_pmu_filter, x86_pmu.filter); |
7c9903c9 PZ |
2034 | } |
2035 | ||
2036 | static void _x86_pmu_read(struct perf_event *event) | |
2037 | { | |
73759c34 | 2038 | static_call(x86_pmu_update)(event); |
7c9903c9 PZ |
2039 | } |
2040 | ||
e11c1a7e KL |
2041 | void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed, |
2042 | u64 intel_ctrl) | |
2043 | { | |
2044 | pr_info("... version: %d\n", x86_pmu.version); | |
2045 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); | |
2046 | pr_info("... generic registers: %d\n", num_counters); | |
2047 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
2048 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); | |
2049 | pr_info("... fixed-purpose events: %lu\n", | |
2050 | hweight64((((1ULL << num_counters_fixed) - 1) | |
2051 | << INTEL_PMC_IDX_FIXED) & intel_ctrl)); | |
2052 | pr_info("... event mask: %016Lx\n", intel_ctrl); | |
2053 | } | |
2054 | ||
dda99116 | 2055 | static int __init init_hw_perf_events(void) |
b56a3802 | 2056 | { |
c1d6f42f | 2057 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
2058 | int err; |
2059 | ||
cdd6c482 | 2060 | pr_info("Performance Events: "); |
1123e3ad | 2061 | |
b56a3802 JSR |
2062 | switch (boot_cpu_data.x86_vendor) { |
2063 | case X86_VENDOR_INTEL: | |
72eae04d | 2064 | err = intel_pmu_init(); |
b56a3802 | 2065 | break; |
f87ad35d | 2066 | case X86_VENDOR_AMD: |
72eae04d | 2067 | err = amd_pmu_init(); |
f87ad35d | 2068 | break; |
6d0ef316 PW |
2069 | case X86_VENDOR_HYGON: |
2070 | err = amd_pmu_init(); | |
2071 | x86_pmu.name = "HYGON"; | |
2072 | break; | |
3a4ac121 C |
2073 | case X86_VENDOR_ZHAOXIN: |
2074 | case X86_VENDOR_CENTAUR: | |
2075 | err = zhaoxin_pmu_init(); | |
2076 | break; | |
4138960a | 2077 | default: |
8a3da6c7 | 2078 | err = -ENOTSUPP; |
b56a3802 | 2079 | } |
1123e3ad | 2080 | if (err != 0) { |
cdd6c482 | 2081 | pr_cont("no PMU driver, software events only.\n"); |
916e3a4f PB |
2082 | err = 0; |
2083 | goto out_bad_pmu; | |
1123e3ad | 2084 | } |
b56a3802 | 2085 | |
12558038 CG |
2086 | pmu_check_apic(); |
2087 | ||
33c6d6a7 | 2088 | /* sanity check that the hardware exists or is emulated */ |
fc4b8fca | 2089 | if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed)) |
916e3a4f | 2090 | goto out_bad_pmu; |
33c6d6a7 | 2091 | |
1123e3ad | 2092 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 2093 | |
e97df763 PZ |
2094 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
2095 | ||
c1d6f42f PZ |
2096 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
2097 | quirk->func(); | |
3c44780b | 2098 | |
a1eac7ac RR |
2099 | if (!x86_pmu.intel_ctrl) |
2100 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 2101 | |
cdd6c482 | 2102 | perf_events_lapic_init(); |
9c48f1c6 | 2103 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 2104 | |
63b14649 | 2105 | unconstrained = (struct event_constraint) |
948b1bb8 | 2106 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 2107 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 2108 | |
641cc938 | 2109 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 2110 | |
a4747393 JO |
2111 | if (!x86_pmu.events_sysfs_show) |
2112 | x86_pmu_events_group.attrs = &empty_attrs; | |
1a6461b1 | 2113 | |
baa0c833 | 2114 | pmu.attr_update = x86_pmu.attr_update; |
6089327f | 2115 | |
d9977c43 KL |
2116 | if (!is_hybrid()) { |
2117 | x86_pmu_show_pmu_cap(x86_pmu.num_counters, | |
2118 | x86_pmu.num_counters_fixed, | |
2119 | x86_pmu.intel_ctrl); | |
2120 | } | |
3f6da390 | 2121 | |
7c9903c9 PZ |
2122 | if (!x86_pmu.read) |
2123 | x86_pmu.read = _x86_pmu_read; | |
2124 | ||
abd562df | 2125 | if (!x86_pmu.guest_get_msrs) |
c8e2fe13 | 2126 | x86_pmu.guest_get_msrs = (void *)&__static_call_return0; |
abd562df | 2127 | |
73759c34 PZ |
2128 | if (!x86_pmu.set_period) |
2129 | x86_pmu.set_period = x86_perf_event_set_period; | |
2130 | ||
2131 | if (!x86_pmu.update) | |
2132 | x86_pmu.update = x86_perf_event_update; | |
2133 | ||
7c9903c9 PZ |
2134 | x86_pmu_static_call_update(); |
2135 | ||
95ca792c TG |
2136 | /* |
2137 | * Install callbacks. Core will call them for each online | |
2138 | * cpu. | |
2139 | */ | |
73c1b41e | 2140 | err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare", |
95ca792c TG |
2141 | x86_pmu_prepare_cpu, x86_pmu_dead_cpu); |
2142 | if (err) | |
2143 | return err; | |
2144 | ||
2145 | err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING, | |
73c1b41e | 2146 | "perf/x86:starting", x86_pmu_starting_cpu, |
95ca792c TG |
2147 | x86_pmu_dying_cpu); |
2148 | if (err) | |
2149 | goto out; | |
2150 | ||
73c1b41e | 2151 | err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online", |
95ca792c TG |
2152 | x86_pmu_online_cpu, NULL); |
2153 | if (err) | |
2154 | goto out1; | |
2155 | ||
d9977c43 KL |
2156 | if (!is_hybrid()) { |
2157 | err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); | |
2158 | if (err) | |
2159 | goto out2; | |
2160 | } else { | |
d9977c43 KL |
2161 | struct x86_hybrid_pmu *hybrid_pmu; |
2162 | int i, j; | |
2163 | ||
d9977c43 KL |
2164 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { |
2165 | hybrid_pmu = &x86_pmu.hybrid_pmu[i]; | |
2166 | ||
2167 | hybrid_pmu->pmu = pmu; | |
2168 | hybrid_pmu->pmu.type = -1; | |
2169 | hybrid_pmu->pmu.attr_update = x86_pmu.attr_update; | |
55bcf6ef | 2170 | hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE; |
d9977c43 KL |
2171 | |
2172 | err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name, | |
b0560bfd | 2173 | (hybrid_pmu->pmu_type == hybrid_big) ? PERF_TYPE_RAW : -1); |
d9977c43 KL |
2174 | if (err) |
2175 | break; | |
d9977c43 KL |
2176 | } |
2177 | ||
2178 | if (i < x86_pmu.num_hybrid_pmus) { | |
2179 | for (j = 0; j < i; j++) | |
2180 | perf_pmu_unregister(&x86_pmu.hybrid_pmu[j].pmu); | |
2181 | pr_warn("Failed to register hybrid PMUs\n"); | |
2182 | kfree(x86_pmu.hybrid_pmu); | |
2183 | x86_pmu.hybrid_pmu = NULL; | |
2184 | x86_pmu.num_hybrid_pmus = 0; | |
2185 | goto out2; | |
2186 | } | |
2187 | } | |
004417a6 PZ |
2188 | |
2189 | return 0; | |
95ca792c TG |
2190 | |
2191 | out2: | |
2192 | cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE); | |
2193 | out1: | |
2194 | cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING); | |
2195 | out: | |
2196 | cpuhp_remove_state(CPUHP_PERF_X86_PREPARE); | |
916e3a4f PB |
2197 | out_bad_pmu: |
2198 | memset(&x86_pmu, 0, sizeof(x86_pmu)); | |
95ca792c | 2199 | return err; |
241771ef | 2200 | } |
004417a6 | 2201 | early_initcall(init_hw_perf_events); |
621a01ea | 2202 | |
7c9903c9 | 2203 | static void x86_pmu_read(struct perf_event *event) |
ee06094f | 2204 | { |
7c9903c9 | 2205 | static_call(x86_pmu_read)(event); |
ee06094f IM |
2206 | } |
2207 | ||
4d1c52b0 LM |
2208 | /* |
2209 | * Start group events scheduling transaction | |
2210 | * Set the flag to make pmu::enable() not perform the | |
2211 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
2212 | * |
2213 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
2214 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
2215 | * transactions. | |
4d1c52b0 | 2216 | */ |
fbbe0701 | 2217 | static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
4d1c52b0 | 2218 | { |
fbbe0701 SB |
2219 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2220 | ||
2221 | WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ | |
2222 | ||
2223 | cpuc->txn_flags = txn_flags; | |
2224 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
2225 | return; | |
2226 | ||
33696fc0 | 2227 | perf_pmu_disable(pmu); |
0a3aee0d | 2228 | __this_cpu_write(cpu_hw_events.n_txn, 0); |
871a93b0 | 2229 | __this_cpu_write(cpu_hw_events.n_txn_pair, 0); |
3dbde695 | 2230 | __this_cpu_write(cpu_hw_events.n_txn_metric, 0); |
4d1c52b0 LM |
2231 | } |
2232 | ||
2233 | /* | |
2234 | * Stop group events scheduling transaction | |
2235 | * Clear the flag and pmu::enable() will perform the | |
2236 | * schedulability test. | |
2237 | */ | |
51b0fe39 | 2238 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 2239 | { |
fbbe0701 SB |
2240 | unsigned int txn_flags; |
2241 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2242 | ||
2243 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ | |
2244 | ||
2245 | txn_flags = cpuc->txn_flags; | |
2246 | cpuc->txn_flags = 0; | |
2247 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
2248 | return; | |
2249 | ||
90151c35 | 2250 | /* |
c347a2f1 PZ |
2251 | * Truncate collected array by the number of events added in this |
2252 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 2253 | */ |
0a3aee0d TH |
2254 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
2255 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
871a93b0 | 2256 | __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair)); |
3dbde695 | 2257 | __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric)); |
33696fc0 | 2258 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
2259 | } |
2260 | ||
2261 | /* | |
2262 | * Commit group events scheduling transaction | |
2263 | * Perform the group schedulability test as a whole | |
2264 | * Return 0 if success | |
c347a2f1 PZ |
2265 | * |
2266 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 2267 | */ |
51b0fe39 | 2268 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 | 2269 | { |
89cbc767 | 2270 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
4d1c52b0 LM |
2271 | int assign[X86_PMC_IDX_MAX]; |
2272 | int n, ret; | |
2273 | ||
fbbe0701 SB |
2274 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ |
2275 | ||
2276 | if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { | |
2277 | cpuc->txn_flags = 0; | |
2278 | return 0; | |
2279 | } | |
2280 | ||
4d1c52b0 LM |
2281 | n = cpuc->n_events; |
2282 | ||
2283 | if (!x86_pmu_initialized()) | |
2284 | return -EAGAIN; | |
2285 | ||
7c9903c9 | 2286 | ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign); |
4d1c52b0 LM |
2287 | if (ret) |
2288 | return ret; | |
2289 | ||
2290 | /* | |
2291 | * copy new assignment, now we know it is possible | |
2292 | * will be used by hw_perf_enable() | |
2293 | */ | |
2294 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
2295 | ||
fbbe0701 | 2296 | cpuc->txn_flags = 0; |
33696fc0 | 2297 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
2298 | return 0; |
2299 | } | |
cd8a38d3 SE |
2300 | /* |
2301 | * a fake_cpuc is used to validate event groups. Due to | |
2302 | * the extra reg logic, we need to also allocate a fake | |
2303 | * per_core and per_cpu structure. Otherwise, group events | |
2304 | * using extra reg may conflict without the kernel being | |
2305 | * able to catch this when the last event gets added to | |
2306 | * the group. | |
2307 | */ | |
2308 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
2309 | { | |
d01b1f96 | 2310 | intel_cpuc_finish(cpuc); |
cd8a38d3 SE |
2311 | kfree(cpuc); |
2312 | } | |
2313 | ||
d9977c43 | 2314 | static struct cpu_hw_events *allocate_fake_cpuc(struct pmu *event_pmu) |
cd8a38d3 SE |
2315 | { |
2316 | struct cpu_hw_events *cpuc; | |
d9977c43 | 2317 | int cpu; |
cd8a38d3 SE |
2318 | |
2319 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
2320 | if (!cpuc) | |
2321 | return ERR_PTR(-ENOMEM); | |
b430f7c4 | 2322 | cpuc->is_fake = 1; |
d01b1f96 | 2323 | |
d9977c43 KL |
2324 | if (is_hybrid()) { |
2325 | struct x86_hybrid_pmu *h_pmu; | |
2326 | ||
2327 | h_pmu = hybrid_pmu(event_pmu); | |
2328 | if (cpumask_empty(&h_pmu->supported_cpus)) | |
2329 | goto error; | |
2330 | cpu = cpumask_first(&h_pmu->supported_cpus); | |
2331 | } else | |
2332 | cpu = raw_smp_processor_id(); | |
2333 | cpuc->pmu = event_pmu; | |
2334 | ||
d01b1f96 PZI |
2335 | if (intel_cpuc_prepare(cpuc, cpu)) |
2336 | goto error; | |
2337 | ||
cd8a38d3 SE |
2338 | return cpuc; |
2339 | error: | |
2340 | free_fake_cpuc(cpuc); | |
2341 | return ERR_PTR(-ENOMEM); | |
2342 | } | |
4d1c52b0 | 2343 | |
ca037701 PZ |
2344 | /* |
2345 | * validate that we can schedule this event | |
2346 | */ | |
2347 | static int validate_event(struct perf_event *event) | |
2348 | { | |
2349 | struct cpu_hw_events *fake_cpuc; | |
2350 | struct event_constraint *c; | |
2351 | int ret = 0; | |
2352 | ||
d9977c43 | 2353 | fake_cpuc = allocate_fake_cpuc(event->pmu); |
cd8a38d3 SE |
2354 | if (IS_ERR(fake_cpuc)) |
2355 | return PTR_ERR(fake_cpuc); | |
ca037701 | 2356 | |
21d65555 | 2357 | c = x86_pmu.get_event_constraints(fake_cpuc, 0, event); |
ca037701 PZ |
2358 | |
2359 | if (!c || !c->weight) | |
aa2bc1ad | 2360 | ret = -EINVAL; |
ca037701 PZ |
2361 | |
2362 | if (x86_pmu.put_event_constraints) | |
2363 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
2364 | ||
cd8a38d3 | 2365 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
2366 | |
2367 | return ret; | |
2368 | } | |
2369 | ||
1da53e02 SE |
2370 | /* |
2371 | * validate a single event group | |
2372 | * | |
2373 | * validation include: | |
184f412c IM |
2374 | * - check events are compatible which each other |
2375 | * - events do not compete for the same counter | |
2376 | * - number of events <= number of counters | |
1da53e02 SE |
2377 | * |
2378 | * validation ensures the group can be loaded onto the | |
2379 | * PMU if it was the only group available. | |
2380 | */ | |
fe9081cc PZ |
2381 | static int validate_group(struct perf_event *event) |
2382 | { | |
1da53e02 | 2383 | struct perf_event *leader = event->group_leader; |
502568d5 | 2384 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 2385 | int ret = -EINVAL, n; |
fe9081cc | 2386 | |
d9977c43 KL |
2387 | /* |
2388 | * Reject events from different hybrid PMUs. | |
2389 | */ | |
2390 | if (is_hybrid()) { | |
2391 | struct perf_event *sibling; | |
2392 | struct pmu *pmu = NULL; | |
2393 | ||
2394 | if (is_x86_event(leader)) | |
2395 | pmu = leader->pmu; | |
2396 | ||
2397 | for_each_sibling_event(sibling, leader) { | |
2398 | if (!is_x86_event(sibling)) | |
2399 | continue; | |
2400 | if (!pmu) | |
2401 | pmu = sibling->pmu; | |
2402 | else if (pmu != sibling->pmu) | |
2403 | return ret; | |
2404 | } | |
2405 | } | |
2406 | ||
2407 | fake_cpuc = allocate_fake_cpuc(event->pmu); | |
cd8a38d3 SE |
2408 | if (IS_ERR(fake_cpuc)) |
2409 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
2410 | /* |
2411 | * the event is not yet connected with its | |
2412 | * siblings therefore we must first collect | |
2413 | * existing siblings, then add the new event | |
2414 | * before we can simulate the scheduling | |
2415 | */ | |
502568d5 | 2416 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 2417 | if (n < 0) |
cd8a38d3 | 2418 | goto out; |
fe9081cc | 2419 | |
502568d5 PZ |
2420 | fake_cpuc->n_events = n; |
2421 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 2422 | if (n < 0) |
cd8a38d3 | 2423 | goto out; |
fe9081cc | 2424 | |
1f6a1e2d | 2425 | fake_cpuc->n_events = 0; |
a072738e | 2426 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 2427 | |
502568d5 | 2428 | out: |
cd8a38d3 | 2429 | free_fake_cpuc(fake_cpuc); |
502568d5 | 2430 | return ret; |
fe9081cc PZ |
2431 | } |
2432 | ||
dda99116 | 2433 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 2434 | { |
d9977c43 | 2435 | struct x86_hybrid_pmu *pmu = NULL; |
621a01ea IM |
2436 | int err; |
2437 | ||
d9977c43 KL |
2438 | if ((event->attr.type != event->pmu->type) && |
2439 | (event->attr.type != PERF_TYPE_HARDWARE) && | |
2440 | (event->attr.type != PERF_TYPE_HW_CACHE)) | |
b0a873eb | 2441 | return -ENOENT; |
d9977c43 KL |
2442 | |
2443 | if (is_hybrid() && (event->cpu != -1)) { | |
2444 | pmu = hybrid_pmu(event->pmu); | |
2445 | if (!cpumask_test_cpu(event->cpu, &pmu->supported_cpus)) | |
2446 | return -ENOENT; | |
b0a873eb PZ |
2447 | } |
2448 | ||
2449 | err = __x86_pmu_event_init(event); | |
fe9081cc PZ |
2450 | if (!err) { |
2451 | if (event->group_leader != event) | |
2452 | err = validate_group(event); | |
ca037701 PZ |
2453 | else |
2454 | err = validate_event(event); | |
fe9081cc | 2455 | } |
a1792cda | 2456 | if (err) { |
cdd6c482 IM |
2457 | if (event->destroy) |
2458 | event->destroy(event); | |
02d029a4 | 2459 | event->destroy = NULL; |
a1792cda | 2460 | } |
621a01ea | 2461 | |
1af22eba | 2462 | if (READ_ONCE(x86_pmu.attr_rdpmc) && |
174afc3e | 2463 | !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) |
369461ce | 2464 | event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; |
7911d3f7 | 2465 | |
b0a873eb | 2466 | return err; |
621a01ea | 2467 | } |
d7d59fb3 | 2468 | |
5471eea5 KL |
2469 | void perf_clear_dirty_counters(void) |
2470 | { | |
2471 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2472 | int i; | |
2473 | ||
2474 | /* Don't need to clear the assigned counter. */ | |
2475 | for (i = 0; i < cpuc->n_events; i++) | |
2476 | __clear_bit(cpuc->assign[i], cpuc->dirty); | |
2477 | ||
2478 | if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX)) | |
2479 | return; | |
2480 | ||
2481 | for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) { | |
f4b4b456 PZ |
2482 | if (i >= INTEL_PMC_IDX_FIXED) { |
2483 | /* Metrics and fake events don't have corresponding HW counters. */ | |
2484 | if ((i - INTEL_PMC_IDX_FIXED) >= hybrid(cpuc->pmu, num_counters_fixed)) | |
2485 | continue; | |
2486 | ||
5471eea5 | 2487 | wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0); |
f4b4b456 | 2488 | } else { |
5471eea5 | 2489 | wrmsrl(x86_pmu_event_addr(i), 0); |
f4b4b456 | 2490 | } |
5471eea5 KL |
2491 | } |
2492 | ||
2493 | bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX); | |
2494 | } | |
2495 | ||
bfe33492 | 2496 | static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm) |
7911d3f7 | 2497 | { |
369461ce | 2498 | if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT)) |
7911d3f7 AL |
2499 | return; |
2500 | ||
4b07372a AL |
2501 | /* |
2502 | * This function relies on not being called concurrently in two | |
2503 | * tasks in the same mm. Otherwise one task could observe | |
2504 | * perf_rdpmc_allowed > 1 and return all the way back to | |
2505 | * userspace with CR4.PCE clear while another task is still | |
2506 | * doing on_each_cpu_mask() to propagate CR4.PCE. | |
2507 | * | |
c1e8d7c6 | 2508 | * For now, this can't happen because all callers hold mmap_lock |
4b07372a AL |
2509 | * for write. If this changes, we'll need a different solution. |
2510 | */ | |
42fc5414 | 2511 | mmap_assert_write_locked(mm); |
4b07372a | 2512 | |
bfe33492 | 2513 | if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1) |
cb2a0235 | 2514 | on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1); |
7911d3f7 AL |
2515 | } |
2516 | ||
bfe33492 | 2517 | static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm) |
7911d3f7 | 2518 | { |
369461ce | 2519 | if (!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT)) |
7911d3f7 AL |
2520 | return; |
2521 | ||
bfe33492 | 2522 | if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed)) |
cb2a0235 | 2523 | on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1); |
7911d3f7 AL |
2524 | } |
2525 | ||
fe4a3308 PZ |
2526 | static int x86_pmu_event_idx(struct perf_event *event) |
2527 | { | |
75608cb0 | 2528 | struct hw_perf_event *hwc = &event->hw; |
fe4a3308 | 2529 | |
369461ce | 2530 | if (!(hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) |
c7206205 PZ |
2531 | return 0; |
2532 | ||
2cb5383b KL |
2533 | if (is_metric_idx(hwc->idx)) |
2534 | return INTEL_PMC_FIXED_RDPMC_METRICS + 1; | |
2535 | else | |
2536 | return hwc->event_base_rdpmc + 1; | |
fe4a3308 PZ |
2537 | } |
2538 | ||
0c9d42ed PZ |
2539 | static ssize_t get_attr_rdpmc(struct device *cdev, |
2540 | struct device_attribute *attr, | |
2541 | char *buf) | |
2542 | { | |
2543 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
2544 | } | |
2545 | ||
0c9d42ed PZ |
2546 | static ssize_t set_attr_rdpmc(struct device *cdev, |
2547 | struct device_attribute *attr, | |
2548 | const char *buf, size_t count) | |
2549 | { | |
e2b297fc SK |
2550 | unsigned long val; |
2551 | ssize_t ret; | |
2552 | ||
2553 | ret = kstrtoul(buf, 0, &val); | |
2554 | if (ret) | |
2555 | return ret; | |
e97df763 | 2556 | |
a6673429 AL |
2557 | if (val > 2) |
2558 | return -EINVAL; | |
2559 | ||
e97df763 PZ |
2560 | if (x86_pmu.attr_rdpmc_broken) |
2561 | return -ENOTSUPP; | |
0c9d42ed | 2562 | |
405b4537 | 2563 | if (val != x86_pmu.attr_rdpmc) { |
a6673429 | 2564 | /* |
405b4537 AS |
2565 | * Changing into or out of never available or always available, |
2566 | * aka perf-event-bypassing mode. This path is extremely slow, | |
a6673429 AL |
2567 | * but only root can trigger it, so it's okay. |
2568 | */ | |
405b4537 AS |
2569 | if (val == 0) |
2570 | static_branch_inc(&rdpmc_never_available_key); | |
2571 | else if (x86_pmu.attr_rdpmc == 0) | |
2572 | static_branch_dec(&rdpmc_never_available_key); | |
2573 | ||
a6673429 | 2574 | if (val == 2) |
631fe154 | 2575 | static_branch_inc(&rdpmc_always_available_key); |
405b4537 | 2576 | else if (x86_pmu.attr_rdpmc == 2) |
631fe154 | 2577 | static_branch_dec(&rdpmc_always_available_key); |
405b4537 | 2578 | |
cb2a0235 | 2579 | on_each_cpu(cr4_update_pce, NULL, 1); |
405b4537 | 2580 | x86_pmu.attr_rdpmc = val; |
a6673429 AL |
2581 | } |
2582 | ||
0c9d42ed PZ |
2583 | return count; |
2584 | } | |
2585 | ||
2586 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
2587 | ||
2588 | static struct attribute *x86_pmu_attrs[] = { | |
2589 | &dev_attr_rdpmc.attr, | |
2590 | NULL, | |
2591 | }; | |
2592 | ||
2766d2ee | 2593 | static struct attribute_group x86_pmu_attr_group __ro_after_init = { |
0c9d42ed PZ |
2594 | .attrs = x86_pmu_attrs, |
2595 | }; | |
2596 | ||
5da382eb PZ |
2597 | static ssize_t max_precise_show(struct device *cdev, |
2598 | struct device_attribute *attr, | |
2599 | char *buf) | |
2600 | { | |
2601 | return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise()); | |
2602 | } | |
2603 | ||
2604 | static DEVICE_ATTR_RO(max_precise); | |
2605 | ||
2606 | static struct attribute *x86_pmu_caps_attrs[] = { | |
2607 | &dev_attr_max_precise.attr, | |
2608 | NULL | |
2609 | }; | |
2610 | ||
2766d2ee | 2611 | static struct attribute_group x86_pmu_caps_group __ro_after_init = { |
5da382eb PZ |
2612 | .name = "caps", |
2613 | .attrs = x86_pmu_caps_attrs, | |
2614 | }; | |
2615 | ||
0c9d42ed PZ |
2616 | static const struct attribute_group *x86_pmu_attr_groups[] = { |
2617 | &x86_pmu_attr_group, | |
641cc938 | 2618 | &x86_pmu_format_group, |
a4747393 | 2619 | &x86_pmu_events_group, |
b00233b5 | 2620 | &x86_pmu_caps_group, |
0c9d42ed PZ |
2621 | NULL, |
2622 | }; | |
2623 | ||
bd275681 | 2624 | static void x86_pmu_sched_task(struct perf_event_pmu_context *pmu_ctx, bool sched_in) |
d010b332 | 2625 | { |
bd275681 | 2626 | static_call_cond(x86_pmu_sched_task)(pmu_ctx, sched_in); |
d010b332 SE |
2627 | } |
2628 | ||
bd275681 PZ |
2629 | static void x86_pmu_swap_task_ctx(struct perf_event_pmu_context *prev_epc, |
2630 | struct perf_event_pmu_context *next_epc) | |
a4439970 | 2631 | { |
bd275681 | 2632 | static_call_cond(x86_pmu_swap_task_ctx)(prev_epc, next_epc); |
a4439970 AB |
2633 | } |
2634 | ||
c93dc84c PZ |
2635 | void perf_check_microcode(void) |
2636 | { | |
2637 | if (x86_pmu.check_microcode) | |
2638 | x86_pmu.check_microcode(); | |
2639 | } | |
c93dc84c | 2640 | |
81ec3f3c JO |
2641 | static int x86_pmu_check_period(struct perf_event *event, u64 value) |
2642 | { | |
2643 | if (x86_pmu.check_period && x86_pmu.check_period(event, value)) | |
2644 | return -EINVAL; | |
2645 | ||
2646 | if (value && x86_pmu.limit_period) { | |
28f0f3c4 PZ |
2647 | s64 left = value; |
2648 | x86_pmu.limit_period(event, &left); | |
2649 | if (left > value) | |
81ec3f3c JO |
2650 | return -EINVAL; |
2651 | } | |
2652 | ||
2653 | return 0; | |
2654 | } | |
2655 | ||
42880f72 AS |
2656 | static int x86_pmu_aux_output_match(struct perf_event *event) |
2657 | { | |
2658 | if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT)) | |
2659 | return 0; | |
2660 | ||
2661 | if (x86_pmu.aux_output_match) | |
2662 | return x86_pmu.aux_output_match(event); | |
2663 | ||
2664 | return 0; | |
2665 | } | |
2666 | ||
bd275681 | 2667 | static bool x86_pmu_filter(struct pmu *pmu, int cpu) |
3e9a8b21 | 2668 | { |
bd275681 PZ |
2669 | bool ret = false; |
2670 | ||
2671 | static_call_cond(x86_pmu_filter)(pmu, cpu, &ret); | |
3e9a8b21 | 2672 | |
bd275681 | 2673 | return ret; |
3e9a8b21 KL |
2674 | } |
2675 | ||
b0a873eb | 2676 | static struct pmu pmu = { |
d010b332 SE |
2677 | .pmu_enable = x86_pmu_enable, |
2678 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 2679 | |
c93dc84c | 2680 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 2681 | |
c93dc84c | 2682 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 2683 | |
7911d3f7 AL |
2684 | .event_mapped = x86_pmu_event_mapped, |
2685 | .event_unmapped = x86_pmu_event_unmapped, | |
2686 | ||
d010b332 SE |
2687 | .add = x86_pmu_add, |
2688 | .del = x86_pmu_del, | |
2689 | .start = x86_pmu_start, | |
2690 | .stop = x86_pmu_stop, | |
2691 | .read = x86_pmu_read, | |
a4eaf7f1 | 2692 | |
c93dc84c PZ |
2693 | .start_txn = x86_pmu_start_txn, |
2694 | .cancel_txn = x86_pmu_cancel_txn, | |
2695 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 2696 | |
c93dc84c | 2697 | .event_idx = x86_pmu_event_idx, |
ba532500 | 2698 | .sched_task = x86_pmu_sched_task, |
a4439970 | 2699 | .swap_task_ctx = x86_pmu_swap_task_ctx, |
81ec3f3c | 2700 | .check_period = x86_pmu_check_period, |
42880f72 AS |
2701 | |
2702 | .aux_output_match = x86_pmu_aux_output_match, | |
3e9a8b21 | 2703 | |
bd275681 | 2704 | .filter = x86_pmu_filter, |
b0a873eb PZ |
2705 | }; |
2706 | ||
c1317ec2 AL |
2707 | void arch_perf_update_userpage(struct perf_event *event, |
2708 | struct perf_event_mmap_page *userpg, u64 now) | |
e3f3541c | 2709 | { |
59eaef78 | 2710 | struct cyc2ns_data data; |
698eff63 | 2711 | u64 offset; |
20d1c86a | 2712 | |
fa731587 PZ |
2713 | userpg->cap_user_time = 0; |
2714 | userpg->cap_user_time_zero = 0; | |
7911d3f7 | 2715 | userpg->cap_user_rdpmc = |
369461ce | 2716 | !!(event->hw.flags & PERF_EVENT_FLAG_USER_READ_CNT); |
c7206205 PZ |
2717 | userpg->pmc_width = x86_pmu.cntval_bits; |
2718 | ||
698eff63 | 2719 | if (!using_native_sched_clock() || !sched_clock_stable()) |
e3f3541c PZ |
2720 | return; |
2721 | ||
59eaef78 | 2722 | cyc2ns_read_begin(&data); |
20d1c86a | 2723 | |
59eaef78 | 2724 | offset = data.cyc2ns_offset + __sched_clock_offset; |
698eff63 | 2725 | |
34f43927 PZ |
2726 | /* |
2727 | * Internal timekeeping for enabled/running/stopped times | |
2728 | * is always in the local_clock domain. | |
2729 | */ | |
fa731587 | 2730 | userpg->cap_user_time = 1; |
59eaef78 PZ |
2731 | userpg->time_mult = data.cyc2ns_mul; |
2732 | userpg->time_shift = data.cyc2ns_shift; | |
698eff63 | 2733 | userpg->time_offset = offset - now; |
c73deb6a | 2734 | |
34f43927 PZ |
2735 | /* |
2736 | * cap_user_time_zero doesn't make sense when we're using a different | |
2737 | * time base for the records. | |
2738 | */ | |
f454bfdd | 2739 | if (!event->attr.use_clockid) { |
34f43927 | 2740 | userpg->cap_user_time_zero = 1; |
698eff63 | 2741 | userpg->time_zero = offset; |
34f43927 | 2742 | } |
20d1c86a | 2743 | |
59eaef78 | 2744 | cyc2ns_read_end(); |
e3f3541c PZ |
2745 | } |
2746 | ||
d15d3568 KS |
2747 | /* |
2748 | * Determine whether the regs were taken from an irq/exception handler rather | |
2749 | * than from perf_arch_fetch_caller_regs(). | |
2750 | */ | |
2751 | static bool perf_hw_regs(struct pt_regs *regs) | |
2752 | { | |
2753 | return regs->flags & X86_EFLAGS_FIXED; | |
2754 | } | |
2755 | ||
56962b44 | 2756 | void |
cfbcf468 | 2757 | perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) |
d7d59fb3 | 2758 | { |
35f4d9b3 JP |
2759 | struct unwind_state state; |
2760 | unsigned long addr; | |
2761 | ||
1c343051 | 2762 | if (perf_guest_state()) { |
927c7a9e | 2763 | /* TODO: We don't support guest os callchain now */ |
ed805261 | 2764 | return; |
927c7a9e FW |
2765 | } |
2766 | ||
83f44ae0 SL |
2767 | if (perf_callchain_store(entry, regs->ip)) |
2768 | return; | |
2769 | ||
2770 | if (perf_hw_regs(regs)) | |
d15d3568 | 2771 | unwind_start(&state, current, regs, NULL); |
83f44ae0 | 2772 | else |
d15d3568 | 2773 | unwind_start(&state, current, NULL, (void *)regs->sp); |
d7d59fb3 | 2774 | |
d15d3568 | 2775 | for (; !unwind_done(&state); unwind_next_frame(&state)) { |
35f4d9b3 JP |
2776 | addr = unwind_get_return_address(&state); |
2777 | if (!addr || perf_callchain_store(entry, addr)) | |
2778 | return; | |
2779 | } | |
d7d59fb3 PZ |
2780 | } |
2781 | ||
bc6ca7b3 AS |
2782 | static inline int |
2783 | valid_user_frame(const void __user *fp, unsigned long size) | |
2784 | { | |
36903abe | 2785 | return __access_ok(fp, size); |
bc6ca7b3 AS |
2786 | } |
2787 | ||
d07bdfd3 PZ |
2788 | static unsigned long get_segment_base(unsigned int segment) |
2789 | { | |
2790 | struct desc_struct *desc; | |
990e9dc3 | 2791 | unsigned int idx = segment >> 3; |
d07bdfd3 PZ |
2792 | |
2793 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
a5b9e5a2 | 2794 | #ifdef CONFIG_MODIFY_LDT_SYSCALL |
37868fe1 AL |
2795 | struct ldt_struct *ldt; |
2796 | ||
37868fe1 | 2797 | /* IRQs are off, so this synchronizes with smp_store_release */ |
506458ef | 2798 | ldt = READ_ONCE(current->active_mm->context.ldt); |
eaa2f87c | 2799 | if (!ldt || idx >= ldt->nr_entries) |
d07bdfd3 PZ |
2800 | return 0; |
2801 | ||
37868fe1 | 2802 | desc = &ldt->entries[idx]; |
a5b9e5a2 AL |
2803 | #else |
2804 | return 0; | |
2805 | #endif | |
d07bdfd3 | 2806 | } else { |
eaa2f87c | 2807 | if (idx >= GDT_ENTRIES) |
d07bdfd3 PZ |
2808 | return 0; |
2809 | ||
37868fe1 | 2810 | desc = raw_cpu_ptr(gdt_page.gdt) + idx; |
d07bdfd3 PZ |
2811 | } |
2812 | ||
37868fe1 | 2813 | return get_desc_base(desc); |
d07bdfd3 PZ |
2814 | } |
2815 | ||
10ed3493 | 2816 | #ifdef CONFIG_IA32_EMULATION |
d1a797f3 | 2817 | |
0d55303c | 2818 | #include <linux/compat.h> |
d1a797f3 | 2819 | |
257ef9d2 | 2820 | static inline int |
cfbcf468 | 2821 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) |
74193ef0 | 2822 | { |
257ef9d2 | 2823 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2824 | unsigned long ss_base, cs_base; |
257ef9d2 | 2825 | struct stack_frame_ia32 frame; |
c8e3dd86 | 2826 | const struct stack_frame_ia32 __user *fp; |
74193ef0 | 2827 | |
375d4bfd | 2828 | if (user_64bit_mode(regs)) |
257ef9d2 TE |
2829 | return 0; |
2830 | ||
d07bdfd3 PZ |
2831 | cs_base = get_segment_base(regs->cs); |
2832 | ss_base = get_segment_base(regs->ss); | |
2833 | ||
2834 | fp = compat_ptr(ss_base + regs->bp); | |
75925e1a | 2835 | pagefault_disable(); |
3b1fff08 | 2836 | while (entry->nr < entry->max_stack) { |
ae31fe51 | 2837 | if (!valid_user_frame(fp, sizeof(frame))) |
75925e1a AK |
2838 | break; |
2839 | ||
c8e3dd86 | 2840 | if (__get_user(frame.next_frame, &fp->next_frame)) |
75925e1a | 2841 | break; |
c8e3dd86 | 2842 | if (__get_user(frame.return_address, &fp->return_address)) |
257ef9d2 | 2843 | break; |
74193ef0 | 2844 | |
d07bdfd3 PZ |
2845 | perf_callchain_store(entry, cs_base + frame.return_address); |
2846 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 | 2847 | } |
75925e1a | 2848 | pagefault_enable(); |
257ef9d2 | 2849 | return 1; |
d7d59fb3 | 2850 | } |
257ef9d2 TE |
2851 | #else |
2852 | static inline int | |
cfbcf468 | 2853 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) |
257ef9d2 TE |
2854 | { |
2855 | return 0; | |
2856 | } | |
2857 | #endif | |
d7d59fb3 | 2858 | |
56962b44 | 2859 | void |
cfbcf468 | 2860 | perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) |
d7d59fb3 PZ |
2861 | { |
2862 | struct stack_frame frame; | |
c8e3dd86 | 2863 | const struct stack_frame __user *fp; |
d7d59fb3 | 2864 | |
1c343051 | 2865 | if (perf_guest_state()) { |
927c7a9e | 2866 | /* TODO: We don't support guest os callchain now */ |
ed805261 | 2867 | return; |
927c7a9e | 2868 | } |
5a6cec3a | 2869 | |
d07bdfd3 PZ |
2870 | /* |
2871 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2872 | */ | |
2873 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2874 | return; | |
2875 | ||
c8e3dd86 | 2876 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2877 | |
70791ce9 | 2878 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2879 | |
4012e77a | 2880 | if (!nmi_uaccess_okay()) |
20afc60f AV |
2881 | return; |
2882 | ||
257ef9d2 TE |
2883 | if (perf_callchain_user32(regs, entry)) |
2884 | return; | |
2885 | ||
75925e1a | 2886 | pagefault_disable(); |
3b1fff08 | 2887 | while (entry->nr < entry->max_stack) { |
ae31fe51 | 2888 | if (!valid_user_frame(fp, sizeof(frame))) |
75925e1a AK |
2889 | break; |
2890 | ||
c8e3dd86 | 2891 | if (__get_user(frame.next_frame, &fp->next_frame)) |
75925e1a | 2892 | break; |
c8e3dd86 | 2893 | if (__get_user(frame.return_address, &fp->return_address)) |
d7d59fb3 PZ |
2894 | break; |
2895 | ||
70791ce9 | 2896 | perf_callchain_store(entry, frame.return_address); |
75925e1a | 2897 | fp = (void __user *)frame.next_frame; |
d7d59fb3 | 2898 | } |
75925e1a | 2899 | pagefault_enable(); |
d7d59fb3 PZ |
2900 | } |
2901 | ||
d07bdfd3 PZ |
2902 | /* |
2903 | * Deal with code segment offsets for the various execution modes: | |
2904 | * | |
2905 | * VM86 - the good olde 16 bit days, where the linear address is | |
2906 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2907 | * | |
2908 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2909 | * to figure out what the 32bit base address is. | |
2910 | * | |
2911 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2912 | * | |
2913 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2914 | */ | |
2915 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2916 | { |
383f3af3 AL |
2917 | /* |
2918 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2919 | * effective IP to a linear address. | |
2920 | */ | |
2921 | ||
2922 | #ifdef CONFIG_X86_32 | |
d07bdfd3 PZ |
2923 | /* |
2924 | * If we are in VM86 mode, add the segment offset to convert to a | |
2925 | * linear address. | |
2926 | */ | |
2927 | if (regs->flags & X86_VM_MASK) | |
2928 | return 0x10 * regs->cs; | |
2929 | ||
55474c48 | 2930 | if (user_mode(regs) && regs->cs != __USER_CS) |
d07bdfd3 PZ |
2931 | return get_segment_base(regs->cs); |
2932 | #else | |
c56716af AL |
2933 | if (user_mode(regs) && !user_64bit_mode(regs) && |
2934 | regs->cs != __USER32_CS) | |
2935 | return get_segment_base(regs->cs); | |
d07bdfd3 PZ |
2936 | #endif |
2937 | return 0; | |
2938 | } | |
dcf46b94 | 2939 | |
d07bdfd3 PZ |
2940 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2941 | { | |
1c343051 SC |
2942 | if (perf_guest_state()) |
2943 | return perf_guest_get_ip(); | |
dcf46b94 | 2944 | |
d07bdfd3 | 2945 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2946 | } |
2947 | ||
2948 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2949 | { | |
1c343051 | 2950 | unsigned int guest_state = perf_guest_state(); |
39447b38 | 2951 | int misc = 0; |
dcf46b94 | 2952 | |
b9f5621c LX |
2953 | if (guest_state) { |
2954 | if (guest_state & PERF_GUEST_USER) | |
dcf46b94 ZY |
2955 | misc |= PERF_RECORD_MISC_GUEST_USER; |
2956 | else | |
2957 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2958 | } else { | |
d07bdfd3 | 2959 | if (user_mode(regs)) |
dcf46b94 ZY |
2960 | misc |= PERF_RECORD_MISC_USER; |
2961 | else | |
2962 | misc |= PERF_RECORD_MISC_KERNEL; | |
2963 | } | |
2964 | ||
39447b38 | 2965 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2966 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2967 | |
2968 | return misc; | |
2969 | } | |
b3d9468a GN |
2970 | |
2971 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2972 | { | |
4b4191b8 SC |
2973 | /* This API doesn't currently support enumerating hybrid PMUs. */ |
2974 | if (WARN_ON_ONCE(cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) || | |
2975 | !x86_pmu_initialized()) { | |
916e3a4f PB |
2976 | memset(cap, 0, sizeof(*cap)); |
2977 | return; | |
2978 | } | |
2979 | ||
d4b294bf | 2980 | /* |
4b4191b8 SC |
2981 | * Note, hybrid CPU models get tracked as having hybrid PMUs even when |
2982 | * all E-cores are disabled via BIOS. When E-cores are disabled, the | |
2983 | * base PMU holds the correct number of counters for P-cores. | |
d4b294bf | 2984 | */ |
4b4191b8 | 2985 | cap->version = x86_pmu.version; |
b3d9468a GN |
2986 | cap->num_counters_gp = x86_pmu.num_counters; |
2987 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2988 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2989 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2990 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2991 | cap->events_mask_len = x86_pmu.events_mask_len; | |
fb358e0b | 2992 | cap->pebs_ept = x86_pmu.pebs_ept; |
b3d9468a GN |
2993 | } |
2994 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); | |
dc852ff5 LX |
2995 | |
2996 | u64 perf_get_hw_event_config(int hw_event) | |
2997 | { | |
2998 | int max = x86_pmu.max_events; | |
2999 | ||
3000 | if (hw_event < max) | |
3001 | return x86_pmu.event_map(array_index_nospec(hw_event, max)); | |
3002 | ||
3003 | return 0; | |
3004 | } | |
3005 | EXPORT_SYMBOL_GPL(perf_get_hw_event_config); |