Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
90eec103 | 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
eb008eb6 PG |
20 | #include <linux/export.h> |
21 | #include <linux/init.h> | |
241771ef | 22 | #include <linux/kdebug.h> |
589ee628 | 23 | #include <linux/sched/mm.h> |
e6017571 | 24 | #include <linux/sched/clock.h> |
d7d59fb3 | 25 | #include <linux/uaccess.h> |
5a0e3ad6 | 26 | #include <linux/slab.h> |
30dd568c | 27 | #include <linux/cpu.h> |
272d30be | 28 | #include <linux/bitops.h> |
0c9d42ed | 29 | #include <linux/device.h> |
46b1b577 | 30 | #include <linux/nospec.h> |
7c9903c9 | 31 | #include <linux/static_call.h> |
241771ef | 32 | |
241771ef | 33 | #include <asm/apic.h> |
d7d59fb3 | 34 | #include <asm/stacktrace.h> |
4e935e47 | 35 | #include <asm/nmi.h> |
69092624 | 36 | #include <asm/smp.h> |
c8e5910e | 37 | #include <asm/alternative.h> |
7911d3f7 | 38 | #include <asm/mmu_context.h> |
375074cc | 39 | #include <asm/tlbflush.h> |
e3f3541c | 40 | #include <asm/timer.h> |
d07bdfd3 PZ |
41 | #include <asm/desc.h> |
42 | #include <asm/ldt.h> | |
35f4d9b3 | 43 | #include <asm/unwind.h> |
241771ef | 44 | |
27f6d22b | 45 | #include "perf_event.h" |
de0428a7 | 46 | |
de0428a7 | 47 | struct x86_pmu x86_pmu __read_mostly; |
61e76d53 | 48 | static struct pmu pmu; |
efc9f05d | 49 | |
de0428a7 | 50 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e | 51 | .enabled = 1, |
61e76d53 | 52 | .pmu = &pmu, |
b0f3f28e | 53 | }; |
241771ef | 54 | |
405b4537 | 55 | DEFINE_STATIC_KEY_FALSE(rdpmc_never_available_key); |
631fe154 | 56 | DEFINE_STATIC_KEY_FALSE(rdpmc_always_available_key); |
d0946a88 | 57 | DEFINE_STATIC_KEY_FALSE(perf_is_hybrid); |
a6673429 | 58 | |
7c9903c9 PZ |
59 | /* |
60 | * This here uses DEFINE_STATIC_CALL_NULL() to get a static_call defined | |
61 | * from just a typename, as opposed to an actual function. | |
62 | */ | |
63 | DEFINE_STATIC_CALL_NULL(x86_pmu_handle_irq, *x86_pmu.handle_irq); | |
64 | DEFINE_STATIC_CALL_NULL(x86_pmu_disable_all, *x86_pmu.disable_all); | |
65 | DEFINE_STATIC_CALL_NULL(x86_pmu_enable_all, *x86_pmu.enable_all); | |
66 | DEFINE_STATIC_CALL_NULL(x86_pmu_enable, *x86_pmu.enable); | |
67 | DEFINE_STATIC_CALL_NULL(x86_pmu_disable, *x86_pmu.disable); | |
68 | ||
8b8ff8cc AH |
69 | DEFINE_STATIC_CALL_NULL(x86_pmu_assign, *x86_pmu.assign); |
70 | ||
7c9903c9 PZ |
71 | DEFINE_STATIC_CALL_NULL(x86_pmu_add, *x86_pmu.add); |
72 | DEFINE_STATIC_CALL_NULL(x86_pmu_del, *x86_pmu.del); | |
73 | DEFINE_STATIC_CALL_NULL(x86_pmu_read, *x86_pmu.read); | |
74 | ||
75 | DEFINE_STATIC_CALL_NULL(x86_pmu_schedule_events, *x86_pmu.schedule_events); | |
76 | DEFINE_STATIC_CALL_NULL(x86_pmu_get_event_constraints, *x86_pmu.get_event_constraints); | |
77 | DEFINE_STATIC_CALL_NULL(x86_pmu_put_event_constraints, *x86_pmu.put_event_constraints); | |
78 | ||
79 | DEFINE_STATIC_CALL_NULL(x86_pmu_start_scheduling, *x86_pmu.start_scheduling); | |
80 | DEFINE_STATIC_CALL_NULL(x86_pmu_commit_scheduling, *x86_pmu.commit_scheduling); | |
81 | DEFINE_STATIC_CALL_NULL(x86_pmu_stop_scheduling, *x86_pmu.stop_scheduling); | |
82 | ||
83 | DEFINE_STATIC_CALL_NULL(x86_pmu_sched_task, *x86_pmu.sched_task); | |
84 | DEFINE_STATIC_CALL_NULL(x86_pmu_swap_task_ctx, *x86_pmu.swap_task_ctx); | |
85 | ||
86 | DEFINE_STATIC_CALL_NULL(x86_pmu_drain_pebs, *x86_pmu.drain_pebs); | |
87 | DEFINE_STATIC_CALL_NULL(x86_pmu_pebs_aliases, *x86_pmu.pebs_aliases); | |
88 | ||
c8e2fe13 SC |
89 | /* |
90 | * This one is magic, it will get called even when PMU init fails (because | |
91 | * there is no PMU), in which case it should simply return NULL. | |
92 | */ | |
93 | DEFINE_STATIC_CALL_RET0(x86_pmu_guest_get_msrs, *x86_pmu.guest_get_msrs); | |
abd562df | 94 | |
de0428a7 | 95 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
96 | [PERF_COUNT_HW_CACHE_MAX] |
97 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
98 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 99 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
100 | [PERF_COUNT_HW_CACHE_MAX] |
101 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
102 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 103 | |
ee06094f | 104 | /* |
cdd6c482 IM |
105 | * Propagate event elapsed time into the generic event. |
106 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
107 | * Returns the delta events processed. |
108 | */ | |
de0428a7 | 109 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 110 | { |
cc2ad4ba | 111 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 112 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 113 | u64 prev_raw_count, new_raw_count; |
7f612a7f | 114 | u64 delta; |
ee06094f | 115 | |
027440b5 | 116 | if (unlikely(!hwc->event_base)) |
30dd568c MM |
117 | return 0; |
118 | ||
7b2c05a1 KL |
119 | if (unlikely(is_topdown_count(event)) && x86_pmu.update_topdown_event) |
120 | return x86_pmu.update_topdown_event(event); | |
121 | ||
ee06094f | 122 | /* |
cdd6c482 | 123 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
124 | * |
125 | * Our tactic to handle this is to first atomically read and | |
126 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 127 | * count to the generic event atomically: |
ee06094f IM |
128 | */ |
129 | again: | |
e7850595 | 130 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 131 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 132 | |
e7850595 | 133 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
134 | new_raw_count) != prev_raw_count) |
135 | goto again; | |
136 | ||
137 | /* | |
138 | * Now we have the new raw value and have updated the prev | |
139 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 140 | * (event-)time and add that to the generic event. |
ee06094f IM |
141 | * |
142 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 143 | * of the count. |
ee06094f | 144 | */ |
ec3232bd PZ |
145 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
146 | delta >>= shift; | |
ee06094f | 147 | |
e7850595 PZ |
148 | local64_add(delta, &event->count); |
149 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
150 | |
151 | return new_raw_count; | |
ee06094f IM |
152 | } |
153 | ||
a7e3ed1e AK |
154 | /* |
155 | * Find and validate any extra registers to set up. | |
156 | */ | |
157 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
158 | { | |
183af736 | 159 | struct extra_reg *extra_regs = hybrid(event->pmu, extra_regs); |
efc9f05d | 160 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
161 | struct extra_reg *er; |
162 | ||
efc9f05d | 163 | reg = &event->hw.extra_reg; |
a7e3ed1e | 164 | |
183af736 | 165 | if (!extra_regs) |
a7e3ed1e AK |
166 | return 0; |
167 | ||
183af736 | 168 | for (er = extra_regs; er->msr; er++) { |
a7e3ed1e AK |
169 | if (er->event != (config & er->config_mask)) |
170 | continue; | |
171 | if (event->attr.config1 & ~er->valid_mask) | |
172 | return -EINVAL; | |
338b522c KL |
173 | /* Check if the extra msrs can be safely accessed*/ |
174 | if (!er->extra_msr_access) | |
175 | return -ENXIO; | |
efc9f05d SE |
176 | |
177 | reg->idx = er->idx; | |
178 | reg->config = event->attr.config1; | |
179 | reg->reg = er->msr; | |
a7e3ed1e AK |
180 | break; |
181 | } | |
182 | return 0; | |
183 | } | |
184 | ||
cdd6c482 | 185 | static atomic_t active_events; |
1b7b938f | 186 | static atomic_t pmc_refcount; |
4e935e47 PZ |
187 | static DEFINE_MUTEX(pmc_reserve_mutex); |
188 | ||
b27ea29c RR |
189 | #ifdef CONFIG_X86_LOCAL_APIC |
190 | ||
d4b294bf KL |
191 | static inline int get_possible_num_counters(void) |
192 | { | |
193 | int i, num_counters = x86_pmu.num_counters; | |
194 | ||
195 | if (!is_hybrid()) | |
196 | return num_counters; | |
197 | ||
198 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) | |
199 | num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters); | |
200 | ||
201 | return num_counters; | |
202 | } | |
203 | ||
4e935e47 PZ |
204 | static bool reserve_pmc_hardware(void) |
205 | { | |
d4b294bf | 206 | int i, num_counters = get_possible_num_counters(); |
4e935e47 | 207 | |
d4b294bf | 208 | for (i = 0; i < num_counters; i++) { |
41bf4989 | 209 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
210 | goto perfctr_fail; |
211 | } | |
212 | ||
d4b294bf | 213 | for (i = 0; i < num_counters; i++) { |
41bf4989 | 214 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
215 | goto eventsel_fail; |
216 | } | |
217 | ||
218 | return true; | |
219 | ||
220 | eventsel_fail: | |
221 | for (i--; i >= 0; i--) | |
41bf4989 | 222 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 223 | |
d4b294bf | 224 | i = num_counters; |
4e935e47 PZ |
225 | |
226 | perfctr_fail: | |
227 | for (i--; i >= 0; i--) | |
41bf4989 | 228 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 229 | |
4e935e47 PZ |
230 | return false; |
231 | } | |
232 | ||
233 | static void release_pmc_hardware(void) | |
234 | { | |
d4b294bf | 235 | int i, num_counters = get_possible_num_counters(); |
4e935e47 | 236 | |
d4b294bf | 237 | for (i = 0; i < num_counters; i++) { |
41bf4989 RR |
238 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
239 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 240 | } |
4e935e47 PZ |
241 | } |
242 | ||
b27ea29c RR |
243 | #else |
244 | ||
245 | static bool reserve_pmc_hardware(void) { return true; } | |
246 | static void release_pmc_hardware(void) {} | |
247 | ||
248 | #endif | |
249 | ||
fc4b8fca | 250 | bool check_hw_exists(struct pmu *pmu, int num_counters, int num_counters_fixed) |
33c6d6a7 | 251 | { |
11d8b058 AB |
252 | u64 val, val_fail = -1, val_new= ~0; |
253 | int i, reg, reg_fail = -1, ret = 0; | |
a5ebe0ba | 254 | int bios_fail = 0; |
68ab7476 | 255 | int reg_safe = -1; |
33c6d6a7 | 256 | |
4407204c PZ |
257 | /* |
258 | * Check to see if the BIOS enabled any of the counters, if so | |
259 | * complain and bail. | |
260 | */ | |
fc4b8fca | 261 | for (i = 0; i < num_counters; i++) { |
41bf4989 | 262 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
263 | ret = rdmsrl_safe(reg, &val); |
264 | if (ret) | |
265 | goto msr_fail; | |
a5ebe0ba GD |
266 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
267 | bios_fail = 1; | |
268 | val_fail = val; | |
269 | reg_fail = reg; | |
68ab7476 DZ |
270 | } else { |
271 | reg_safe = i; | |
a5ebe0ba | 272 | } |
4407204c PZ |
273 | } |
274 | ||
fc4b8fca | 275 | if (num_counters_fixed) { |
4407204c PZ |
276 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
277 | ret = rdmsrl_safe(reg, &val); | |
278 | if (ret) | |
279 | goto msr_fail; | |
fc4b8fca KL |
280 | for (i = 0; i < num_counters_fixed; i++) { |
281 | if (fixed_counter_disabled(i, pmu)) | |
32451614 | 282 | continue; |
32d35c4a | 283 | if (val & (0x03ULL << i*4)) { |
a5ebe0ba GD |
284 | bios_fail = 1; |
285 | val_fail = val; | |
286 | reg_fail = reg; | |
287 | } | |
4407204c PZ |
288 | } |
289 | } | |
290 | ||
68ab7476 DZ |
291 | /* |
292 | * If all the counters are enabled, the below test will always | |
293 | * fail. The tools will also become useless in this scenario. | |
294 | * Just fail and disable the hardware counters. | |
295 | */ | |
296 | ||
297 | if (reg_safe == -1) { | |
298 | reg = reg_safe; | |
299 | goto msr_fail; | |
300 | } | |
301 | ||
4407204c | 302 | /* |
bffd5fc2 AP |
303 | * Read the current value, change it and read it back to see if it |
304 | * matches, this is needed to detect certain hardware emulators | |
305 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 306 | */ |
68ab7476 | 307 | reg = x86_pmu_event_addr(reg_safe); |
bffd5fc2 AP |
308 | if (rdmsrl_safe(reg, &val)) |
309 | goto msr_fail; | |
310 | val ^= 0xffffUL; | |
f285f92f RR |
311 | ret = wrmsrl_safe(reg, val); |
312 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 313 | if (ret || val != val_new) |
4407204c | 314 | goto msr_fail; |
33c6d6a7 | 315 | |
45daae57 IM |
316 | /* |
317 | * We still allow the PMU driver to operate: | |
318 | */ | |
a5ebe0ba | 319 | if (bios_fail) { |
1b74dde7 CY |
320 | pr_cont("Broken BIOS detected, complain to your hardware vendor.\n"); |
321 | pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", | |
322 | reg_fail, val_fail); | |
a5ebe0ba | 323 | } |
45daae57 IM |
324 | |
325 | return true; | |
4407204c PZ |
326 | |
327 | msr_fail: | |
005bd007 JG |
328 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { |
329 | pr_cont("PMU not available due to virtualization, using software events only.\n"); | |
330 | } else { | |
331 | pr_cont("Broken PMU hardware detected, using software events only.\n"); | |
332 | pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n", | |
333 | reg, val_new); | |
334 | } | |
45daae57 | 335 | |
4407204c | 336 | return false; |
33c6d6a7 DZ |
337 | } |
338 | ||
cdd6c482 | 339 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 340 | { |
6b099d9b | 341 | x86_release_hardware(); |
1b7b938f | 342 | atomic_dec(&active_events); |
4e935e47 PZ |
343 | } |
344 | ||
48070342 AS |
345 | void hw_perf_lbr_event_destroy(struct perf_event *event) |
346 | { | |
347 | hw_perf_event_destroy(event); | |
348 | ||
349 | /* undo the lbr/bts event accounting */ | |
350 | x86_del_exclusive(x86_lbr_exclusive_lbr); | |
351 | } | |
352 | ||
85cf9dba RR |
353 | static inline int x86_pmu_initialized(void) |
354 | { | |
355 | return x86_pmu.handle_irq != NULL; | |
356 | } | |
357 | ||
8326f44d | 358 | static inline int |
e994d7d2 | 359 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 360 | { |
e994d7d2 | 361 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
362 | unsigned int cache_type, cache_op, cache_result; |
363 | u64 config, val; | |
364 | ||
365 | config = attr->config; | |
366 | ||
ef9ee4ad | 367 | cache_type = (config >> 0) & 0xff; |
8326f44d IM |
368 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) |
369 | return -EINVAL; | |
ef9ee4ad | 370 | cache_type = array_index_nospec(cache_type, PERF_COUNT_HW_CACHE_MAX); |
8326f44d IM |
371 | |
372 | cache_op = (config >> 8) & 0xff; | |
373 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
374 | return -EINVAL; | |
ef9ee4ad | 375 | cache_op = array_index_nospec(cache_op, PERF_COUNT_HW_CACHE_OP_MAX); |
8326f44d IM |
376 | |
377 | cache_result = (config >> 16) & 0xff; | |
378 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
379 | return -EINVAL; | |
ef9ee4ad | 380 | cache_result = array_index_nospec(cache_result, PERF_COUNT_HW_CACHE_RESULT_MAX); |
8326f44d | 381 | |
0d18f2df | 382 | val = hybrid_var(event->pmu, hw_cache_event_ids)[cache_type][cache_op][cache_result]; |
8326f44d IM |
383 | if (val == 0) |
384 | return -ENOENT; | |
385 | ||
386 | if (val == -1) | |
387 | return -EINVAL; | |
388 | ||
389 | hwc->config |= val; | |
0d18f2df | 390 | attr->config1 = hybrid_var(event->pmu, hw_cache_extra_regs)[cache_type][cache_op][cache_result]; |
e994d7d2 | 391 | return x86_pmu_extra_regs(val, event); |
8326f44d IM |
392 | } |
393 | ||
6b099d9b AS |
394 | int x86_reserve_hardware(void) |
395 | { | |
396 | int err = 0; | |
397 | ||
1b7b938f | 398 | if (!atomic_inc_not_zero(&pmc_refcount)) { |
6b099d9b | 399 | mutex_lock(&pmc_reserve_mutex); |
1b7b938f | 400 | if (atomic_read(&pmc_refcount) == 0) { |
488e13a4 | 401 | if (!reserve_pmc_hardware()) { |
6b099d9b | 402 | err = -EBUSY; |
488e13a4 | 403 | } else { |
6b099d9b | 404 | reserve_ds_buffers(); |
488e13a4 LX |
405 | reserve_lbr_buffers(); |
406 | } | |
6b099d9b AS |
407 | } |
408 | if (!err) | |
1b7b938f | 409 | atomic_inc(&pmc_refcount); |
6b099d9b AS |
410 | mutex_unlock(&pmc_reserve_mutex); |
411 | } | |
412 | ||
413 | return err; | |
414 | } | |
415 | ||
416 | void x86_release_hardware(void) | |
417 | { | |
1b7b938f | 418 | if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { |
6b099d9b AS |
419 | release_pmc_hardware(); |
420 | release_ds_buffers(); | |
c085fb87 | 421 | release_lbr_buffers(); |
6b099d9b AS |
422 | mutex_unlock(&pmc_reserve_mutex); |
423 | } | |
424 | } | |
425 | ||
48070342 AS |
426 | /* |
427 | * Check if we can create event of a certain type (that no conflicting events | |
428 | * are present). | |
429 | */ | |
430 | int x86_add_exclusive(unsigned int what) | |
431 | { | |
93472aff | 432 | int i; |
48070342 | 433 | |
b0c1ef52 AK |
434 | /* |
435 | * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS. | |
436 | * LBR and BTS are still mutually exclusive. | |
437 | */ | |
438 | if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) | |
92ca7da4 | 439 | goto out; |
ccbebba4 | 440 | |
93472aff PZ |
441 | if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { |
442 | mutex_lock(&pmc_reserve_mutex); | |
443 | for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { | |
444 | if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) | |
445 | goto fail_unlock; | |
446 | } | |
447 | atomic_inc(&x86_pmu.lbr_exclusive[what]); | |
448 | mutex_unlock(&pmc_reserve_mutex); | |
6b099d9b | 449 | } |
48070342 | 450 | |
92ca7da4 | 451 | out: |
93472aff PZ |
452 | atomic_inc(&active_events); |
453 | return 0; | |
48070342 | 454 | |
93472aff | 455 | fail_unlock: |
48070342 | 456 | mutex_unlock(&pmc_reserve_mutex); |
93472aff | 457 | return -EBUSY; |
48070342 AS |
458 | } |
459 | ||
460 | void x86_del_exclusive(unsigned int what) | |
461 | { | |
92ca7da4 AS |
462 | atomic_dec(&active_events); |
463 | ||
464 | /* | |
465 | * See the comment in x86_add_exclusive(). | |
466 | */ | |
b0c1ef52 | 467 | if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) |
ccbebba4 AS |
468 | return; |
469 | ||
48070342 AS |
470 | atomic_dec(&x86_pmu.lbr_exclusive[what]); |
471 | } | |
472 | ||
de0428a7 | 473 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
474 | { |
475 | struct perf_event_attr *attr = &event->attr; | |
476 | struct hw_perf_event *hwc = &event->hw; | |
477 | u64 config; | |
478 | ||
6c7e550f | 479 | if (!is_sampling_event(event)) { |
c1726f34 RR |
480 | hwc->sample_period = x86_pmu.max_period; |
481 | hwc->last_period = hwc->sample_period; | |
e7850595 | 482 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
483 | } |
484 | ||
d9977c43 | 485 | if (attr->type == event->pmu->type) |
ed13ec58 | 486 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
487 | |
488 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 489 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
490 | |
491 | if (attr->config >= x86_pmu.max_events) | |
492 | return -EINVAL; | |
493 | ||
46b1b577 PZ |
494 | attr->config = array_index_nospec((unsigned long)attr->config, x86_pmu.max_events); |
495 | ||
c1726f34 RR |
496 | /* |
497 | * The generic map: | |
498 | */ | |
499 | config = x86_pmu.event_map(attr->config); | |
500 | ||
501 | if (config == 0) | |
502 | return -ENOENT; | |
503 | ||
504 | if (config == -1LL) | |
505 | return -EINVAL; | |
506 | ||
c1726f34 RR |
507 | hwc->config |= config; |
508 | ||
509 | return 0; | |
510 | } | |
4261e0e0 | 511 | |
ff3fb511 SE |
512 | /* |
513 | * check that branch_sample_type is compatible with | |
514 | * settings needed for precise_ip > 1 which implies | |
515 | * using the LBR to capture ALL taken branches at the | |
516 | * priv levels of the measurement | |
517 | */ | |
518 | static inline int precise_br_compat(struct perf_event *event) | |
519 | { | |
520 | u64 m = event->attr.branch_sample_type; | |
521 | u64 b = 0; | |
522 | ||
523 | /* must capture all branches */ | |
524 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
525 | return 0; | |
526 | ||
527 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
528 | ||
529 | if (!event->attr.exclude_user) | |
530 | b |= PERF_SAMPLE_BRANCH_USER; | |
531 | ||
532 | if (!event->attr.exclude_kernel) | |
533 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
534 | ||
535 | /* | |
536 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
537 | */ | |
538 | ||
539 | return m == b; | |
540 | } | |
541 | ||
b00233b5 | 542 | int x86_pmu_max_precise(void) |
a072738e | 543 | { |
b00233b5 AK |
544 | int precise = 0; |
545 | ||
546 | /* Support for constant skid */ | |
547 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { | |
548 | precise++; | |
ab608344 | 549 | |
b00233b5 AK |
550 | /* Support for IP fixup */ |
551 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) | |
ab608344 PZ |
552 | precise++; |
553 | ||
b00233b5 AK |
554 | if (x86_pmu.pebs_prec_dist) |
555 | precise++; | |
556 | } | |
557 | return precise; | |
558 | } | |
72469764 | 559 | |
b00233b5 AK |
560 | int x86_pmu_hw_config(struct perf_event *event) |
561 | { | |
562 | if (event->attr.precise_ip) { | |
563 | int precise = x86_pmu_max_precise(); | |
ab608344 PZ |
564 | |
565 | if (event->attr.precise_ip > precise) | |
566 | return -EOPNOTSUPP; | |
18e7a45a JO |
567 | |
568 | /* There's no sense in having PEBS for non sampling events: */ | |
569 | if (!is_sampling_event(event)) | |
570 | return -EINVAL; | |
4b854900 YZ |
571 | } |
572 | /* | |
573 | * check that PEBS LBR correction does not conflict with | |
574 | * whatever the user is asking with attr->branch_sample_type | |
575 | */ | |
576 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { | |
577 | u64 *br_type = &event->attr.branch_sample_type; | |
578 | ||
579 | if (has_branch_stack(event)) { | |
580 | if (!precise_br_compat(event)) | |
581 | return -EOPNOTSUPP; | |
582 | ||
583 | /* branch_sample_type is compatible */ | |
584 | ||
585 | } else { | |
586 | /* | |
587 | * user did not specify branch_sample_type | |
588 | * | |
589 | * For PEBS fixups, we capture all | |
590 | * the branches at the priv level of the | |
591 | * event. | |
592 | */ | |
593 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
594 | ||
595 | if (!event->attr.exclude_user) | |
596 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
597 | ||
598 | if (!event->attr.exclude_kernel) | |
599 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
ff3fb511 | 600 | } |
ab608344 PZ |
601 | } |
602 | ||
e18bf526 YZ |
603 | if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) |
604 | event->attach_state |= PERF_ATTACH_TASK_DATA; | |
605 | ||
a072738e CG |
606 | /* |
607 | * Generate PMC IRQs: | |
608 | * (keep 'enabled' bit clear for now) | |
609 | */ | |
b4cdc5c2 | 610 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
611 | |
612 | /* | |
613 | * Count user and OS events unless requested not to | |
614 | */ | |
b4cdc5c2 PZ |
615 | if (!event->attr.exclude_user) |
616 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
617 | if (!event->attr.exclude_kernel) | |
618 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 619 | |
d9977c43 | 620 | if (event->attr.type == event->pmu->type) |
b4cdc5c2 | 621 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; |
a072738e | 622 | |
294fe0f5 AK |
623 | if (event->attr.sample_period && x86_pmu.limit_period) { |
624 | if (x86_pmu.limit_period(event, event->attr.sample_period) > | |
625 | event->attr.sample_period) | |
626 | return -EINVAL; | |
627 | } | |
628 | ||
878068ea | 629 | /* sample_regs_user never support XMM registers */ |
dce86ac7 | 630 | if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK)) |
878068ea KL |
631 | return -EINVAL; |
632 | /* | |
633 | * Besides the general purpose registers, XMM registers may | |
634 | * be collected in PEBS on some platforms, e.g. Icelake | |
635 | */ | |
dce86ac7 | 636 | if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) { |
cd6b984f | 637 | if (!(event->pmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS)) |
878068ea KL |
638 | return -EINVAL; |
639 | ||
640 | if (!event->attr.precise_ip) | |
641 | return -EINVAL; | |
642 | } | |
643 | ||
9d0fcba6 | 644 | return x86_setup_perfctr(event); |
a098f448 RR |
645 | } |
646 | ||
241771ef | 647 | /* |
0d48696f | 648 | * Setup the hardware configuration for a given attr_type |
241771ef | 649 | */ |
b0a873eb | 650 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 651 | { |
4e935e47 | 652 | int err; |
241771ef | 653 | |
85cf9dba RR |
654 | if (!x86_pmu_initialized()) |
655 | return -ENODEV; | |
241771ef | 656 | |
6b099d9b | 657 | err = x86_reserve_hardware(); |
4e935e47 PZ |
658 | if (err) |
659 | return err; | |
660 | ||
1b7b938f | 661 | atomic_inc(&active_events); |
cdd6c482 | 662 | event->destroy = hw_perf_event_destroy; |
a1792cda | 663 | |
4261e0e0 RR |
664 | event->hw.idx = -1; |
665 | event->hw.last_cpu = -1; | |
666 | event->hw.last_tag = ~0ULL; | |
b690081d | 667 | |
efc9f05d SE |
668 | /* mark unused */ |
669 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
670 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
671 | ||
9d0fcba6 | 672 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
673 | } |
674 | ||
de0428a7 | 675 | void x86_pmu_disable_all(void) |
f87ad35d | 676 | { |
89cbc767 | 677 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
9e35ad38 PZ |
678 | int idx; |
679 | ||
948b1bb8 | 680 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
57388912 | 681 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e PZ |
682 | u64 val; |
683 | ||
43f6201a | 684 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 685 | continue; |
41bf4989 | 686 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 687 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 688 | continue; |
bb1165d6 | 689 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 690 | wrmsrl(x86_pmu_config_addr(idx), val); |
57388912 KP |
691 | if (is_counter_pair(hwc)) |
692 | wrmsrl(x86_pmu_config_addr(idx + 1), 0); | |
f87ad35d | 693 | } |
f87ad35d JSR |
694 | } |
695 | ||
abd562df LX |
696 | struct perf_guest_switch_msr *perf_guest_get_msrs(int *nr) |
697 | { | |
698 | return static_call(x86_pmu_guest_get_msrs)(nr); | |
699 | } | |
700 | EXPORT_SYMBOL_GPL(perf_guest_get_msrs); | |
701 | ||
c3d266c8 KL |
702 | /* |
703 | * There may be PMI landing after enabled=0. The PMI hitting could be before or | |
704 | * after disable_all. | |
705 | * | |
706 | * If PMI hits before disable_all, the PMU will be disabled in the NMI handler. | |
707 | * It will not be re-enabled in the NMI handler again, because enabled=0. After | |
708 | * handling the NMI, disable_all will be called, which will not change the | |
709 | * state either. If PMI hits after disable_all, the PMU is already disabled | |
710 | * before entering NMI handler. The NMI handler will not change the state | |
711 | * either. | |
712 | * | |
713 | * So either situation is harmless. | |
714 | */ | |
a4eaf7f1 | 715 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 716 | { |
89cbc767 | 717 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 | 718 | |
85cf9dba | 719 | if (!x86_pmu_initialized()) |
9e35ad38 | 720 | return; |
1da53e02 | 721 | |
1a6e21f7 PZ |
722 | if (!cpuc->enabled) |
723 | return; | |
724 | ||
725 | cpuc->n_added = 0; | |
726 | cpuc->enabled = 0; | |
727 | barrier(); | |
1da53e02 | 728 | |
7c9903c9 | 729 | static_call(x86_pmu_disable_all)(); |
b56a3802 | 730 | } |
241771ef | 731 | |
de0428a7 | 732 | void x86_pmu_enable_all(int added) |
f87ad35d | 733 | { |
89cbc767 | 734 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f87ad35d JSR |
735 | int idx; |
736 | ||
948b1bb8 | 737 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 738 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 739 | |
43f6201a | 740 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 741 | continue; |
984b838c | 742 | |
d45dd923 | 743 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
744 | } |
745 | } | |
746 | ||
1da53e02 SE |
747 | static inline int is_x86_event(struct perf_event *event) |
748 | { | |
d9977c43 KL |
749 | int i; |
750 | ||
751 | if (!is_hybrid()) | |
752 | return event->pmu == &pmu; | |
753 | ||
754 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { | |
755 | if (event->pmu == &x86_pmu.hybrid_pmu[i].pmu) | |
756 | return true; | |
757 | } | |
758 | ||
759 | return false; | |
1da53e02 SE |
760 | } |
761 | ||
61e76d53 | 762 | struct pmu *x86_get_pmu(unsigned int cpu) |
f447e4eb | 763 | { |
61e76d53 KL |
764 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
765 | ||
766 | /* | |
767 | * All CPUs of the hybrid type have been offline. | |
768 | * The x86_get_pmu() should not be invoked. | |
769 | */ | |
770 | if (WARN_ON_ONCE(!cpuc->pmu)) | |
771 | return &pmu; | |
772 | ||
773 | return cpuc->pmu; | |
f447e4eb | 774 | } |
1e2ad28f RR |
775 | /* |
776 | * Event scheduler state: | |
777 | * | |
778 | * Assign events iterating over all events and counters, beginning | |
779 | * with events with least weights first. Keep the current iterator | |
780 | * state in struct sched_state. | |
781 | */ | |
782 | struct sched_state { | |
783 | int weight; | |
784 | int event; /* event index */ | |
785 | int counter; /* counter index */ | |
786 | int unassigned; /* number of events to be assigned left */ | |
cc1790cf | 787 | int nr_gp; /* number of GP counters used */ |
57388912 | 788 | u64 used; |
1e2ad28f RR |
789 | }; |
790 | ||
bc1738f6 RR |
791 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
792 | #define SCHED_STATES_MAX 2 | |
793 | ||
1e2ad28f RR |
794 | struct perf_sched { |
795 | int max_weight; | |
796 | int max_events; | |
cc1790cf PZ |
797 | int max_gp; |
798 | int saved_states; | |
b371b594 | 799 | struct event_constraint **constraints; |
1e2ad28f | 800 | struct sched_state state; |
bc1738f6 | 801 | struct sched_state saved[SCHED_STATES_MAX]; |
1e2ad28f RR |
802 | }; |
803 | ||
804 | /* | |
d9f6e12f | 805 | * Initialize iterator that runs through all events and counters. |
1e2ad28f | 806 | */ |
b371b594 | 807 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, |
cc1790cf | 808 | int num, int wmin, int wmax, int gpmax) |
1e2ad28f RR |
809 | { |
810 | int idx; | |
811 | ||
812 | memset(sched, 0, sizeof(*sched)); | |
813 | sched->max_events = num; | |
814 | sched->max_weight = wmax; | |
cc1790cf | 815 | sched->max_gp = gpmax; |
b371b594 | 816 | sched->constraints = constraints; |
1e2ad28f RR |
817 | |
818 | for (idx = 0; idx < num; idx++) { | |
b371b594 | 819 | if (constraints[idx]->weight == wmin) |
1e2ad28f RR |
820 | break; |
821 | } | |
822 | ||
823 | sched->state.event = idx; /* start with min weight */ | |
824 | sched->state.weight = wmin; | |
825 | sched->state.unassigned = num; | |
826 | } | |
827 | ||
bc1738f6 RR |
828 | static void perf_sched_save_state(struct perf_sched *sched) |
829 | { | |
830 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
831 | return; | |
832 | ||
833 | sched->saved[sched->saved_states] = sched->state; | |
834 | sched->saved_states++; | |
835 | } | |
836 | ||
837 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
838 | { | |
839 | if (!sched->saved_states) | |
840 | return false; | |
841 | ||
842 | sched->saved_states--; | |
843 | sched->state = sched->saved[sched->saved_states]; | |
844 | ||
57388912 KP |
845 | /* this assignment didn't work out */ |
846 | /* XXX broken vs EVENT_PAIR */ | |
847 | sched->state.used &= ~BIT_ULL(sched->state.counter); | |
848 | ||
849 | /* try the next one */ | |
850 | sched->state.counter++; | |
bc1738f6 RR |
851 | |
852 | return true; | |
853 | } | |
854 | ||
1e2ad28f RR |
855 | /* |
856 | * Select a counter for the current event to schedule. Return true on | |
857 | * success. | |
858 | */ | |
bc1738f6 | 859 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
860 | { |
861 | struct event_constraint *c; | |
862 | int idx; | |
863 | ||
864 | if (!sched->state.unassigned) | |
865 | return false; | |
866 | ||
867 | if (sched->state.event >= sched->max_events) | |
868 | return false; | |
869 | ||
b371b594 | 870 | c = sched->constraints[sched->state.event]; |
4defea85 | 871 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
872 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
873 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 874 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
57388912 KP |
875 | u64 mask = BIT_ULL(idx); |
876 | ||
877 | if (sched->state.used & mask) | |
878 | continue; | |
879 | ||
880 | sched->state.used |= mask; | |
881 | goto done; | |
4defea85 PZ |
882 | } |
883 | } | |
cc1790cf | 884 | |
1e2ad28f RR |
885 | /* Grab the first unused counter starting with idx */ |
886 | idx = sched->state.counter; | |
15c7ad51 | 887 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
57388912 | 888 | u64 mask = BIT_ULL(idx); |
cc1790cf | 889 | |
57388912 KP |
890 | if (c->flags & PERF_X86_EVENT_PAIR) |
891 | mask |= mask << 1; | |
892 | ||
893 | if (sched->state.used & mask) | |
894 | continue; | |
895 | ||
896 | if (sched->state.nr_gp++ >= sched->max_gp) | |
897 | return false; | |
898 | ||
899 | sched->state.used |= mask; | |
900 | goto done; | |
1e2ad28f | 901 | } |
1e2ad28f | 902 | |
4defea85 PZ |
903 | return false; |
904 | ||
905 | done: | |
906 | sched->state.counter = idx; | |
1e2ad28f | 907 | |
bc1738f6 RR |
908 | if (c->overlap) |
909 | perf_sched_save_state(sched); | |
910 | ||
911 | return true; | |
912 | } | |
913 | ||
914 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
915 | { | |
916 | while (!__perf_sched_find_counter(sched)) { | |
917 | if (!perf_sched_restore_state(sched)) | |
918 | return false; | |
919 | } | |
920 | ||
1e2ad28f RR |
921 | return true; |
922 | } | |
923 | ||
924 | /* | |
925 | * Go through all unassigned events and find the next one to schedule. | |
926 | * Take events with the least weight first. Return true on success. | |
927 | */ | |
928 | static bool perf_sched_next_event(struct perf_sched *sched) | |
929 | { | |
930 | struct event_constraint *c; | |
931 | ||
932 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
933 | return false; | |
934 | ||
935 | do { | |
936 | /* next event */ | |
937 | sched->state.event++; | |
938 | if (sched->state.event >= sched->max_events) { | |
939 | /* next weight */ | |
940 | sched->state.event = 0; | |
941 | sched->state.weight++; | |
942 | if (sched->state.weight > sched->max_weight) | |
943 | return false; | |
944 | } | |
b371b594 | 945 | c = sched->constraints[sched->state.event]; |
1e2ad28f RR |
946 | } while (c->weight != sched->state.weight); |
947 | ||
948 | sched->state.counter = 0; /* start with first counter */ | |
949 | ||
950 | return true; | |
951 | } | |
952 | ||
953 | /* | |
954 | * Assign a counter for each event. | |
955 | */ | |
b371b594 | 956 | int perf_assign_events(struct event_constraint **constraints, int n, |
cc1790cf | 957 | int wmin, int wmax, int gpmax, int *assign) |
1e2ad28f RR |
958 | { |
959 | struct perf_sched sched; | |
960 | ||
cc1790cf | 961 | perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); |
1e2ad28f RR |
962 | |
963 | do { | |
964 | if (!perf_sched_find_counter(&sched)) | |
965 | break; /* failed */ | |
966 | if (assign) | |
967 | assign[sched.state.event] = sched.state.counter; | |
968 | } while (perf_sched_next_event(&sched)); | |
969 | ||
970 | return sched.state.unassigned; | |
971 | } | |
4a3dc121 | 972 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 973 | |
de0428a7 | 974 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 975 | { |
d4b294bf | 976 | int num_counters = hybrid(cpuc->pmu, num_counters); |
43b45780 | 977 | struct event_constraint *c; |
2f7f73a5 | 978 | struct perf_event *e; |
f80deefa | 979 | int n0, i, wmin, wmax, unsched = 0; |
1da53e02 | 980 | struct hw_perf_event *hwc; |
57388912 | 981 | u64 used_mask = 0; |
1da53e02 | 982 | |
f80deefa PZ |
983 | /* |
984 | * Compute the number of events already present; see x86_pmu_add(), | |
985 | * validate_group() and x86_pmu_commit_txn(). For the former two | |
986 | * cpuc->n_events hasn't been updated yet, while for the latter | |
987 | * cpuc->n_txn contains the number of events added in the current | |
988 | * transaction. | |
989 | */ | |
990 | n0 = cpuc->n_events; | |
991 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) | |
992 | n0 -= cpuc->n_txn; | |
993 | ||
7c9903c9 | 994 | static_call_cond(x86_pmu_start_scheduling)(cpuc); |
c5362c0c | 995 | |
1e2ad28f | 996 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
109717de PZ |
997 | c = cpuc->event_constraint[i]; |
998 | ||
f80deefa PZ |
999 | /* |
1000 | * Previously scheduled events should have a cached constraint, | |
1001 | * while new events should not have one. | |
1002 | */ | |
1003 | WARN_ON_ONCE((c && i >= n0) || (!c && i < n0)); | |
1004 | ||
109717de PZ |
1005 | /* |
1006 | * Request constraints for new events; or for those events that | |
1007 | * have a dynamic constraint -- for those the constraint can | |
1008 | * change due to external factors (sibling state, allow_tfa). | |
1009 | */ | |
1010 | if (!c || (c->flags & PERF_X86_EVENT_DYNAMIC)) { | |
7c9903c9 | 1011 | c = static_call(x86_pmu_get_event_constraints)(cpuc, i, cpuc->event_list[i]); |
109717de PZ |
1012 | cpuc->event_constraint[i] = c; |
1013 | } | |
43b45780 | 1014 | |
1e2ad28f RR |
1015 | wmin = min(wmin, c->weight); |
1016 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
1017 | } |
1018 | ||
8113070d SE |
1019 | /* |
1020 | * fastpath, try to reuse previous register | |
1021 | */ | |
c933c1a6 | 1022 | for (i = 0; i < n; i++) { |
57388912 KP |
1023 | u64 mask; |
1024 | ||
8113070d | 1025 | hwc = &cpuc->event_list[i]->hw; |
b371b594 | 1026 | c = cpuc->event_constraint[i]; |
8113070d SE |
1027 | |
1028 | /* never assigned */ | |
1029 | if (hwc->idx == -1) | |
1030 | break; | |
1031 | ||
1032 | /* constraint still honored */ | |
63b14649 | 1033 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
1034 | break; |
1035 | ||
57388912 KP |
1036 | mask = BIT_ULL(hwc->idx); |
1037 | if (is_counter_pair(hwc)) | |
1038 | mask |= mask << 1; | |
1039 | ||
8113070d | 1040 | /* not already used */ |
57388912 | 1041 | if (used_mask & mask) |
8113070d SE |
1042 | break; |
1043 | ||
57388912 KP |
1044 | used_mask |= mask; |
1045 | ||
8113070d SE |
1046 | if (assign) |
1047 | assign[i] = hwc->idx; | |
1048 | } | |
8113070d | 1049 | |
1e2ad28f | 1050 | /* slow path */ |
b371b594 | 1051 | if (i != n) { |
d4b294bf | 1052 | int gpmax = num_counters; |
cc1790cf PZ |
1053 | |
1054 | /* | |
1055 | * Do not allow scheduling of more than half the available | |
1056 | * generic counters. | |
1057 | * | |
1058 | * This helps avoid counter starvation of sibling thread by | |
1059 | * ensuring at most half the counters cannot be in exclusive | |
1060 | * mode. There is no designated counters for the limits. Any | |
1061 | * N/2 counters can be used. This helps with events with | |
1062 | * specific counter constraints. | |
1063 | */ | |
1064 | if (is_ht_workaround_enabled() && !cpuc->is_fake && | |
1065 | READ_ONCE(cpuc->excl_cntrs->exclusive_present)) | |
1066 | gpmax /= 2; | |
1067 | ||
57388912 KP |
1068 | /* |
1069 | * Reduce the amount of available counters to allow fitting | |
1070 | * the extra Merge events needed by large increment events. | |
1071 | */ | |
1072 | if (x86_pmu.flags & PMU_FL_PAIR) { | |
d4b294bf | 1073 | gpmax = num_counters - cpuc->n_pair; |
57388912 KP |
1074 | WARN_ON(gpmax <= 0); |
1075 | } | |
1076 | ||
b371b594 | 1077 | unsched = perf_assign_events(cpuc->event_constraint, n, wmin, |
cc1790cf | 1078 | wmax, gpmax, assign); |
b371b594 | 1079 | } |
8113070d | 1080 | |
2f7f73a5 | 1081 | /* |
e979121b MD |
1082 | * In case of success (unsched = 0), mark events as committed, |
1083 | * so we do not put_constraint() in case new events are added | |
1084 | * and fail to be scheduled | |
1085 | * | |
1086 | * We invoke the lower level commit callback to lock the resource | |
1087 | * | |
1088 | * We do not need to do all of this in case we are called to | |
1089 | * validate an event group (assign == NULL) | |
2f7f73a5 | 1090 | */ |
e979121b | 1091 | if (!unsched && assign) { |
4f32da76 | 1092 | for (i = 0; i < n; i++) |
7c9903c9 | 1093 | static_call_cond(x86_pmu_commit_scheduling)(cpuc, i, assign[i]); |
8736e548 | 1094 | } else { |
f80deefa | 1095 | for (i = n0; i < n; i++) { |
2f7f73a5 | 1096 | e = cpuc->event_list[i]; |
2f7f73a5 | 1097 | |
e979121b MD |
1098 | /* |
1099 | * release events that failed scheduling | |
1100 | */ | |
7c9903c9 | 1101 | static_call_cond(x86_pmu_put_event_constraints)(cpuc, e); |
2c9651c3 PZ |
1102 | |
1103 | cpuc->event_constraint[i] = NULL; | |
1da53e02 SE |
1104 | } |
1105 | } | |
c5362c0c | 1106 | |
7c9903c9 | 1107 | static_call_cond(x86_pmu_stop_scheduling)(cpuc); |
c5362c0c | 1108 | |
e979121b | 1109 | return unsched ? -EINVAL : 0; |
1da53e02 SE |
1110 | } |
1111 | ||
7b2c05a1 KL |
1112 | static int add_nr_metric_event(struct cpu_hw_events *cpuc, |
1113 | struct perf_event *event) | |
1114 | { | |
1115 | if (is_metric_event(event)) { | |
1116 | if (cpuc->n_metric == INTEL_TD_METRIC_NUM) | |
1117 | return -EINVAL; | |
1118 | cpuc->n_metric++; | |
3dbde695 | 1119 | cpuc->n_txn_metric++; |
7b2c05a1 KL |
1120 | } |
1121 | ||
1122 | return 0; | |
1123 | } | |
1124 | ||
1125 | static void del_nr_metric_event(struct cpu_hw_events *cpuc, | |
1126 | struct perf_event *event) | |
1127 | { | |
1128 | if (is_metric_event(event)) | |
1129 | cpuc->n_metric--; | |
1130 | } | |
1131 | ||
1132 | static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event, | |
1133 | int max_count, int n) | |
1134 | { | |
d0946a88 | 1135 | union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap); |
7b2c05a1 | 1136 | |
d0946a88 | 1137 | if (intel_cap.perf_metrics && add_nr_metric_event(cpuc, event)) |
7b2c05a1 KL |
1138 | return -EINVAL; |
1139 | ||
1140 | if (n >= max_count + cpuc->n_metric) | |
1141 | return -EINVAL; | |
1142 | ||
1143 | cpuc->event_list[n] = event; | |
871a93b0 | 1144 | if (is_counter_pair(&event->hw)) { |
7b2c05a1 | 1145 | cpuc->n_pair++; |
871a93b0 PZ |
1146 | cpuc->n_txn_pair++; |
1147 | } | |
7b2c05a1 KL |
1148 | |
1149 | return 0; | |
1150 | } | |
1151 | ||
1da53e02 SE |
1152 | /* |
1153 | * dogrp: true if must collect siblings events (group) | |
1154 | * returns total number of events and error code | |
1155 | */ | |
1156 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
1157 | { | |
d4b294bf KL |
1158 | int num_counters = hybrid(cpuc->pmu, num_counters); |
1159 | int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); | |
1da53e02 SE |
1160 | struct perf_event *event; |
1161 | int n, max_count; | |
1162 | ||
d4b294bf | 1163 | max_count = num_counters + num_counters_fixed; |
1da53e02 SE |
1164 | |
1165 | /* current number of events already accepted */ | |
1166 | n = cpuc->n_events; | |
42880f72 AS |
1167 | if (!cpuc->n_events) |
1168 | cpuc->pebs_output = 0; | |
1169 | ||
1170 | if (!cpuc->is_fake && leader->attr.precise_ip) { | |
1171 | /* | |
1172 | * For PEBS->PT, if !aux_event, the group leader (PT) went | |
1173 | * away, the group was broken down and this singleton event | |
1174 | * can't schedule any more. | |
1175 | */ | |
1176 | if (is_pebs_pt(leader) && !leader->aux_event) | |
1177 | return -EINVAL; | |
1178 | ||
1179 | /* | |
1180 | * pebs_output: 0: no PEBS so far, 1: PT, 2: DS | |
1181 | */ | |
1182 | if (cpuc->pebs_output && | |
1183 | cpuc->pebs_output != is_pebs_pt(leader) + 1) | |
1184 | return -EINVAL; | |
1185 | ||
1186 | cpuc->pebs_output = is_pebs_pt(leader) + 1; | |
1187 | } | |
1da53e02 SE |
1188 | |
1189 | if (is_x86_event(leader)) { | |
7b2c05a1 | 1190 | if (collect_event(cpuc, leader, max_count, n)) |
aa2bc1ad | 1191 | return -EINVAL; |
1da53e02 SE |
1192 | n++; |
1193 | } | |
7b2c05a1 | 1194 | |
1da53e02 SE |
1195 | if (!dogrp) |
1196 | return n; | |
1197 | ||
edb39592 | 1198 | for_each_sibling_event(event, leader) { |
7b2c05a1 | 1199 | if (!is_x86_event(event) || event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
1200 | continue; |
1201 | ||
7b2c05a1 | 1202 | if (collect_event(cpuc, event, max_count, n)) |
aa2bc1ad | 1203 | return -EINVAL; |
1da53e02 | 1204 | |
1da53e02 SE |
1205 | n++; |
1206 | } | |
1207 | return n; | |
1208 | } | |
1209 | ||
1da53e02 | 1210 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 1211 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 1212 | { |
447a194b | 1213 | struct hw_perf_event *hwc = &event->hw; |
027440b5 | 1214 | int idx; |
447a194b | 1215 | |
027440b5 | 1216 | idx = hwc->idx = cpuc->assign[i]; |
447a194b SE |
1217 | hwc->last_cpu = smp_processor_id(); |
1218 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 1219 | |
8b8ff8cc AH |
1220 | static_call_cond(x86_pmu_assign)(event, idx); |
1221 | ||
027440b5 LX |
1222 | switch (hwc->idx) { |
1223 | case INTEL_PMC_IDX_FIXED_BTS: | |
097e4311 | 1224 | case INTEL_PMC_IDX_FIXED_VLBR: |
1da53e02 SE |
1225 | hwc->config_base = 0; |
1226 | hwc->event_base = 0; | |
027440b5 LX |
1227 | break; |
1228 | ||
7b2c05a1 KL |
1229 | case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: |
1230 | /* All the metric events are mapped onto the fixed counter 3. */ | |
1231 | idx = INTEL_PMC_IDX_FIXED_SLOTS; | |
b6459575 | 1232 | fallthrough; |
027440b5 | 1233 | case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS-1: |
1da53e02 | 1234 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
027440b5 LX |
1235 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + |
1236 | (idx - INTEL_PMC_IDX_FIXED); | |
0e2e45e2 KL |
1237 | hwc->event_base_rdpmc = (idx - INTEL_PMC_IDX_FIXED) | |
1238 | INTEL_PMC_FIXED_RDPMC_BASE; | |
027440b5 LX |
1239 | break; |
1240 | ||
1241 | default: | |
73d6e522 RR |
1242 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
1243 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 1244 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
027440b5 | 1245 | break; |
1da53e02 SE |
1246 | } |
1247 | } | |
1248 | ||
1182a495 RC |
1249 | /** |
1250 | * x86_perf_rdpmc_index - Return PMC counter used for event | |
1251 | * @event: the perf_event to which the PMC counter was assigned | |
1252 | * | |
1253 | * The counter assigned to this performance event may change if interrupts | |
1254 | * are enabled. This counter should thus never be used while interrupts are | |
1255 | * enabled. Before this function is used to obtain the assigned counter the | |
1256 | * event should be checked for validity using, for example, | |
1257 | * perf_event_read_local(), within the same interrupt disabled section in | |
1258 | * which this counter is planned to be used. | |
1259 | * | |
1260 | * Return: The index of the performance monitoring counter assigned to | |
1261 | * @perf_event. | |
1262 | */ | |
1263 | int x86_perf_rdpmc_index(struct perf_event *event) | |
1264 | { | |
1265 | lockdep_assert_irqs_disabled(); | |
1266 | ||
1267 | return event->hw.event_base_rdpmc; | |
1268 | } | |
1269 | ||
447a194b SE |
1270 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
1271 | struct cpu_hw_events *cpuc, | |
1272 | int i) | |
1273 | { | |
1274 | return hwc->idx == cpuc->assign[i] && | |
1275 | hwc->last_cpu == smp_processor_id() && | |
1276 | hwc->last_tag == cpuc->tags[i]; | |
1277 | } | |
1278 | ||
a4eaf7f1 | 1279 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 1280 | |
a4eaf7f1 | 1281 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 1282 | { |
89cbc767 | 1283 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1284 | struct perf_event *event; |
1285 | struct hw_perf_event *hwc; | |
11164cd4 | 1286 | int i, added = cpuc->n_added; |
1da53e02 | 1287 | |
85cf9dba | 1288 | if (!x86_pmu_initialized()) |
2b9ff0db | 1289 | return; |
1a6e21f7 PZ |
1290 | |
1291 | if (cpuc->enabled) | |
1292 | return; | |
1293 | ||
1da53e02 | 1294 | if (cpuc->n_added) { |
19925ce7 | 1295 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
1296 | /* |
1297 | * apply assignment obtained either from | |
1298 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
1299 | * | |
1300 | * step1: save events moving to new counters | |
1da53e02 | 1301 | */ |
19925ce7 | 1302 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
1303 | event = cpuc->event_list[i]; |
1304 | hwc = &event->hw; | |
1305 | ||
447a194b SE |
1306 | /* |
1307 | * we can avoid reprogramming counter if: | |
1308 | * - assigned same counter as last time | |
1309 | * - running on same CPU as last time | |
1310 | * - no other event has used the counter since | |
1311 | */ | |
1312 | if (hwc->idx == -1 || | |
1313 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
1314 | continue; |
1315 | ||
a4eaf7f1 PZ |
1316 | /* |
1317 | * Ensure we don't accidentally enable a stopped | |
1318 | * counter simply because we rescheduled. | |
1319 | */ | |
1320 | if (hwc->state & PERF_HES_STOPPED) | |
1321 | hwc->state |= PERF_HES_ARCH; | |
1322 | ||
1323 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
1324 | } |
1325 | ||
c347a2f1 PZ |
1326 | /* |
1327 | * step2: reprogram moved events into new counters | |
1328 | */ | |
1da53e02 | 1329 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
1330 | event = cpuc->event_list[i]; |
1331 | hwc = &event->hw; | |
1332 | ||
45e16a68 | 1333 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 1334 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
1335 | else if (i < n_running) |
1336 | continue; | |
1da53e02 | 1337 | |
a4eaf7f1 PZ |
1338 | if (hwc->state & PERF_HES_ARCH) |
1339 | continue; | |
1340 | ||
1341 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
1342 | } |
1343 | cpuc->n_added = 0; | |
1344 | perf_events_lapic_init(); | |
1345 | } | |
1a6e21f7 PZ |
1346 | |
1347 | cpuc->enabled = 1; | |
1348 | barrier(); | |
1349 | ||
7c9903c9 | 1350 | static_call(x86_pmu_enable_all)(added); |
ee06094f | 1351 | } |
ee06094f | 1352 | |
245b2e70 | 1353 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1354 | |
ee06094f IM |
1355 | /* |
1356 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1357 | * To be called with the event disabled in hw: |
ee06094f | 1358 | */ |
de0428a7 | 1359 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1360 | { |
07088edb | 1361 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1362 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1363 | s64 period = hwc->sample_period; |
7645a24c | 1364 | int ret = 0, idx = hwc->idx; |
ee06094f | 1365 | |
027440b5 | 1366 | if (unlikely(!hwc->event_base)) |
30dd568c MM |
1367 | return 0; |
1368 | ||
7b2c05a1 KL |
1369 | if (unlikely(is_topdown_count(event)) && |
1370 | x86_pmu.set_topdown_event_period) | |
1371 | return x86_pmu.set_topdown_event_period(event); | |
1372 | ||
ee06094f | 1373 | /* |
af901ca1 | 1374 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1375 | */ |
1376 | if (unlikely(left <= -period)) { | |
1377 | left = period; | |
e7850595 | 1378 | local64_set(&hwc->period_left, left); |
9e350de3 | 1379 | hwc->last_period = period; |
e4abb5d4 | 1380 | ret = 1; |
ee06094f IM |
1381 | } |
1382 | ||
1383 | if (unlikely(left <= 0)) { | |
1384 | left += period; | |
e7850595 | 1385 | local64_set(&hwc->period_left, left); |
9e350de3 | 1386 | hwc->last_period = period; |
e4abb5d4 | 1387 | ret = 1; |
ee06094f | 1388 | } |
1c80f4b5 | 1389 | /* |
dfc65094 | 1390 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1391 | */ |
1392 | if (unlikely(left < 2)) | |
1393 | left = 2; | |
241771ef | 1394 | |
e4abb5d4 PZ |
1395 | if (left > x86_pmu.max_period) |
1396 | left = x86_pmu.max_period; | |
1397 | ||
294fe0f5 AK |
1398 | if (x86_pmu.limit_period) |
1399 | left = x86_pmu.limit_period(event, left); | |
1400 | ||
245b2e70 | 1401 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f | 1402 | |
d31fc13f KL |
1403 | /* |
1404 | * The hw event starts counting from this event offset, | |
1405 | * mark it to be able to extra future deltas: | |
1406 | */ | |
1407 | local64_set(&hwc->prev_count, (u64)-left); | |
ee06094f | 1408 | |
d31fc13f | 1409 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1410 | |
57388912 | 1411 | /* |
26e52558 | 1412 | * Sign extend the Merge event counter's upper 16 bits since |
57388912 KP |
1413 | * we currently declare a 48-bit counter width |
1414 | */ | |
1415 | if (is_counter_pair(hwc)) | |
26e52558 | 1416 | wrmsrl(x86_pmu_event_addr(idx + 1), 0xffff); |
57388912 | 1417 | |
68aa00ac CG |
1418 | /* |
1419 | * Due to erratum on certan cpu we need | |
1420 | * a second write to be sure the register | |
1421 | * is updated properly | |
1422 | */ | |
1423 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1424 | wrmsrl(hwc->event_base, |
948b1bb8 | 1425 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1426 | } |
e4abb5d4 | 1427 | |
cdd6c482 | 1428 | perf_event_update_userpage(event); |
194002b2 | 1429 | |
e4abb5d4 | 1430 | return ret; |
2f18d1e8 IM |
1431 | } |
1432 | ||
de0428a7 | 1433 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1434 | { |
0a3aee0d | 1435 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1436 | __x86_pmu_enable_event(&event->hw, |
1437 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1438 | } |
1439 | ||
b690081d | 1440 | /* |
a4eaf7f1 | 1441 | * Add a single event to the PMU. |
1da53e02 SE |
1442 | * |
1443 | * The event is added to the group of enabled events | |
77d76032 | 1444 | * but only if it can be scheduled with existing events. |
fe9081cc | 1445 | */ |
a4eaf7f1 | 1446 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc | 1447 | { |
89cbc767 | 1448 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1449 | struct hw_perf_event *hwc; |
1450 | int assign[X86_PMC_IDX_MAX]; | |
1451 | int n, n0, ret; | |
fe9081cc | 1452 | |
1da53e02 | 1453 | hwc = &event->hw; |
fe9081cc | 1454 | |
1da53e02 | 1455 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1456 | ret = n = collect_events(cpuc, event, false); |
1457 | if (ret < 0) | |
1458 | goto out; | |
53b441a5 | 1459 | |
a4eaf7f1 PZ |
1460 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1461 | if (!(flags & PERF_EF_START)) | |
1462 | hwc->state |= PERF_HES_ARCH; | |
1463 | ||
4d1c52b0 LM |
1464 | /* |
1465 | * If group events scheduling transaction was started, | |
0d2eb44f | 1466 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1467 | * at commit time (->commit_txn) as a whole. |
68f7082f PZ |
1468 | * |
1469 | * If commit fails, we'll call ->del() on all events | |
1470 | * for which ->add() was called. | |
4d1c52b0 | 1471 | */ |
8f3e5684 | 1472 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
24cd7f54 | 1473 | goto done_collect; |
4d1c52b0 | 1474 | |
7c9903c9 | 1475 | ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign); |
1da53e02 | 1476 | if (ret) |
24cd7f54 | 1477 | goto out; |
1da53e02 SE |
1478 | /* |
1479 | * copy new assignment, now we know it is possible | |
1480 | * will be used by hw_perf_enable() | |
1481 | */ | |
1482 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1483 | |
24cd7f54 | 1484 | done_collect: |
c347a2f1 PZ |
1485 | /* |
1486 | * Commit the collect_events() state. See x86_pmu_del() and | |
1487 | * x86_pmu_*_txn(). | |
1488 | */ | |
1da53e02 | 1489 | cpuc->n_events = n; |
356e1f2e | 1490 | cpuc->n_added += n - n0; |
90151c35 | 1491 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1492 | |
7c9903c9 PZ |
1493 | /* |
1494 | * This is before x86_pmu_enable() will call x86_pmu_start(), | |
1495 | * so we enable LBRs before an event needs them etc.. | |
1496 | */ | |
1497 | static_call_cond(x86_pmu_add)(event); | |
68f7082f | 1498 | |
24cd7f54 PZ |
1499 | ret = 0; |
1500 | out: | |
24cd7f54 | 1501 | return ret; |
241771ef IM |
1502 | } |
1503 | ||
a4eaf7f1 | 1504 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1505 | { |
89cbc767 | 1506 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
c08053e6 PZ |
1507 | int idx = event->hw.idx; |
1508 | ||
a4eaf7f1 PZ |
1509 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1510 | return; | |
1511 | ||
1512 | if (WARN_ON_ONCE(idx == -1)) | |
1513 | return; | |
1514 | ||
1515 | if (flags & PERF_EF_RELOAD) { | |
1516 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1517 | x86_perf_event_set_period(event); | |
1518 | } | |
1519 | ||
1520 | event->hw.state = 0; | |
d76a0812 | 1521 | |
c08053e6 PZ |
1522 | cpuc->events[idx] = event; |
1523 | __set_bit(idx, cpuc->active_mask); | |
7c9903c9 | 1524 | static_call(x86_pmu_enable)(event); |
c08053e6 | 1525 | perf_event_update_userpage(event); |
a78ac325 PZ |
1526 | } |
1527 | ||
cdd6c482 | 1528 | void perf_event_print_debug(void) |
241771ef | 1529 | { |
2f18d1e8 | 1530 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
da3e606d | 1531 | u64 pebs, debugctl; |
d4b294bf KL |
1532 | int cpu = smp_processor_id(); |
1533 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
1534 | int num_counters = hybrid(cpuc->pmu, num_counters); | |
1535 | int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed); | |
24ee38ff | 1536 | struct event_constraint *pebs_constraints = hybrid(cpuc->pmu, pebs_constraints); |
5bb9efe3 | 1537 | unsigned long flags; |
d4b294bf | 1538 | int idx; |
1e125676 | 1539 | |
d4b294bf | 1540 | if (!num_counters) |
1e125676 | 1541 | return; |
241771ef | 1542 | |
5bb9efe3 | 1543 | local_irq_save(flags); |
241771ef | 1544 | |
faa28ae0 | 1545 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1546 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1547 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1548 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1549 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1550 | ||
1551 | pr_info("\n"); | |
1552 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1553 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1554 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1555 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
24ee38ff | 1556 | if (pebs_constraints) { |
15fde110 AK |
1557 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); |
1558 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); | |
1559 | } | |
da3e606d AK |
1560 | if (x86_pmu.lbr_nr) { |
1561 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
1562 | pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); | |
1563 | } | |
f87ad35d | 1564 | } |
7645a24c | 1565 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1566 | |
d4b294bf | 1567 | for (idx = 0; idx < num_counters; idx++) { |
41bf4989 RR |
1568 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1569 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1570 | |
245b2e70 | 1571 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1572 | |
a1ef58f4 | 1573 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1574 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1575 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1576 | cpu, idx, pmc_count); |
a1ef58f4 | 1577 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1578 | cpu, idx, prev_left); |
241771ef | 1579 | } |
d4b294bf | 1580 | for (idx = 0; idx < num_counters_fixed; idx++) { |
fc4b8fca | 1581 | if (fixed_counter_disabled(idx, cpuc->pmu)) |
32451614 | 1582 | continue; |
2f18d1e8 IM |
1583 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1584 | ||
a1ef58f4 | 1585 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1586 | cpu, idx, pmc_count); |
1587 | } | |
5bb9efe3 | 1588 | local_irq_restore(flags); |
241771ef IM |
1589 | } |
1590 | ||
de0428a7 | 1591 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1592 | { |
89cbc767 | 1593 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1594 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1595 | |
3966c3fe | 1596 | if (test_bit(hwc->idx, cpuc->active_mask)) { |
7c9903c9 | 1597 | static_call(x86_pmu_disable)(event); |
3966c3fe | 1598 | __clear_bit(hwc->idx, cpuc->active_mask); |
a4eaf7f1 PZ |
1599 | cpuc->events[hwc->idx] = NULL; |
1600 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1601 | hwc->state |= PERF_HES_STOPPED; | |
1602 | } | |
30dd568c | 1603 | |
a4eaf7f1 PZ |
1604 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1605 | /* | |
1606 | * Drain the remaining delta count out of a event | |
1607 | * that we are disabling: | |
1608 | */ | |
1609 | x86_perf_event_update(event); | |
1610 | hwc->state |= PERF_HES_UPTODATE; | |
1611 | } | |
2e841873 PZ |
1612 | } |
1613 | ||
a4eaf7f1 | 1614 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 | 1615 | { |
89cbc767 | 1616 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
d0946a88 | 1617 | union perf_capabilities intel_cap = hybrid(cpuc->pmu, intel_cap); |
2e841873 PZ |
1618 | int i; |
1619 | ||
90151c35 | 1620 | /* |
68f7082f | 1621 | * If we're called during a txn, we only need to undo x86_pmu.add. |
90151c35 SE |
1622 | * The events never got scheduled and ->cancel_txn will truncate |
1623 | * the event_list. | |
c347a2f1 PZ |
1624 | * |
1625 | * XXX assumes any ->del() called during a TXN will only be on | |
1626 | * an event added during that same TXN. | |
90151c35 | 1627 | */ |
8f3e5684 | 1628 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
68f7082f | 1629 | goto do_del; |
90151c35 | 1630 | |
5471eea5 KL |
1631 | __set_bit(event->hw.idx, cpuc->dirty); |
1632 | ||
c347a2f1 PZ |
1633 | /* |
1634 | * Not a TXN, therefore cleanup properly. | |
1635 | */ | |
a4eaf7f1 | 1636 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1637 | |
1da53e02 | 1638 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1639 | if (event == cpuc->event_list[i]) |
1640 | break; | |
1641 | } | |
1da53e02 | 1642 | |
c347a2f1 PZ |
1643 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1644 | return; | |
26e61e89 | 1645 | |
c347a2f1 PZ |
1646 | /* If we have a newly added event; make sure to decrease n_added. */ |
1647 | if (i >= cpuc->n_events - cpuc->n_added) | |
1648 | --cpuc->n_added; | |
1da53e02 | 1649 | |
7c9903c9 | 1650 | static_call_cond(x86_pmu_put_event_constraints)(cpuc, event); |
c347a2f1 PZ |
1651 | |
1652 | /* Delete the array entry. */ | |
b371b594 | 1653 | while (++i < cpuc->n_events) { |
c347a2f1 | 1654 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
b371b594 PZ |
1655 | cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; |
1656 | } | |
2c9651c3 | 1657 | cpuc->event_constraint[i-1] = NULL; |
c347a2f1 | 1658 | --cpuc->n_events; |
d0946a88 | 1659 | if (intel_cap.perf_metrics) |
7b2c05a1 | 1660 | del_nr_metric_event(cpuc, event); |
1da53e02 | 1661 | |
cdd6c482 | 1662 | perf_event_update_userpage(event); |
68f7082f PZ |
1663 | |
1664 | do_del: | |
7c9903c9 PZ |
1665 | |
1666 | /* | |
1667 | * This is after x86_pmu_stop(); so we disable LBRs after any | |
1668 | * event can need them etc.. | |
1669 | */ | |
1670 | static_call_cond(x86_pmu_del)(event); | |
241771ef IM |
1671 | } |
1672 | ||
de0428a7 | 1673 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1674 | { |
df1a132b | 1675 | struct perf_sample_data data; |
cdd6c482 IM |
1676 | struct cpu_hw_events *cpuc; |
1677 | struct perf_event *event; | |
11d1578f | 1678 | int idx, handled = 0; |
9029a5e3 IM |
1679 | u64 val; |
1680 | ||
89cbc767 | 1681 | cpuc = this_cpu_ptr(&cpu_hw_events); |
962bf7a6 | 1682 | |
2bce5dac DZ |
1683 | /* |
1684 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1685 | * inside the nmi handler. As a result, the unmasking was pushed | |
1686 | * into all the nmi handlers. | |
1687 | * | |
1688 | * This generic handler doesn't seem to have any issues where the | |
1689 | * unmasking occurs so it was left at the top. | |
1690 | */ | |
1691 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1692 | ||
948b1bb8 | 1693 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
3966c3fe | 1694 | if (!test_bit(idx, cpuc->active_mask)) |
a29aa8a7 | 1695 | continue; |
962bf7a6 | 1696 | |
cdd6c482 | 1697 | event = cpuc->events[idx]; |
a4016a79 | 1698 | |
cc2ad4ba | 1699 | val = x86_perf_event_update(event); |
948b1bb8 | 1700 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1701 | continue; |
962bf7a6 | 1702 | |
9e350de3 | 1703 | /* |
cdd6c482 | 1704 | * event overflow |
9e350de3 | 1705 | */ |
4177c42a | 1706 | handled++; |
fd0d000b | 1707 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1708 | |
07088edb | 1709 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1710 | continue; |
1711 | ||
a8b0ca17 | 1712 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1713 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1714 | } |
962bf7a6 | 1715 | |
9e350de3 PZ |
1716 | if (handled) |
1717 | inc_irq_stat(apic_perf_irqs); | |
1718 | ||
a29aa8a7 RR |
1719 | return handled; |
1720 | } | |
39d81eab | 1721 | |
cdd6c482 | 1722 | void perf_events_lapic_init(void) |
241771ef | 1723 | { |
04da8a43 | 1724 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1725 | return; |
85cf9dba | 1726 | |
241771ef | 1727 | /* |
c323d95f | 1728 | * Always use NMI for PMU |
241771ef | 1729 | */ |
c323d95f | 1730 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1731 | } |
1732 | ||
9326638c | 1733 | static int |
9c48f1c6 | 1734 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1735 | { |
14c63f17 DH |
1736 | u64 start_clock; |
1737 | u64 finish_clock; | |
e8a923cc | 1738 | int ret; |
14c63f17 | 1739 | |
1b7b938f AS |
1740 | /* |
1741 | * All PMUs/events that share this PMI handler should make sure to | |
1742 | * increment active_events for their events. | |
1743 | */ | |
cdd6c482 | 1744 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1745 | return NMI_DONE; |
4177c42a | 1746 | |
e8a923cc | 1747 | start_clock = sched_clock(); |
7c9903c9 | 1748 | ret = static_call(x86_pmu_handle_irq)(regs); |
e8a923cc | 1749 | finish_clock = sched_clock(); |
14c63f17 DH |
1750 | |
1751 | perf_sample_event_took(finish_clock - start_clock); | |
1752 | ||
1753 | return ret; | |
241771ef | 1754 | } |
9326638c | 1755 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1756 | |
de0428a7 KW |
1757 | struct event_constraint emptyconstraint; |
1758 | struct event_constraint unconstrained; | |
f87ad35d | 1759 | |
95ca792c | 1760 | static int x86_pmu_prepare_cpu(unsigned int cpu) |
3f6da390 | 1761 | { |
7fdba1ca | 1762 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
95ca792c | 1763 | int i; |
3f6da390 | 1764 | |
95ca792c TG |
1765 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) |
1766 | cpuc->kfree_on_online[i] = NULL; | |
1767 | if (x86_pmu.cpu_prepare) | |
1768 | return x86_pmu.cpu_prepare(cpu); | |
1769 | return 0; | |
1770 | } | |
7fdba1ca | 1771 | |
95ca792c TG |
1772 | static int x86_pmu_dead_cpu(unsigned int cpu) |
1773 | { | |
1774 | if (x86_pmu.cpu_dead) | |
1775 | x86_pmu.cpu_dead(cpu); | |
1776 | return 0; | |
1777 | } | |
3f6da390 | 1778 | |
95ca792c TG |
1779 | static int x86_pmu_online_cpu(unsigned int cpu) |
1780 | { | |
1781 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
1782 | int i; | |
3f6da390 | 1783 | |
95ca792c TG |
1784 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { |
1785 | kfree(cpuc->kfree_on_online[i]); | |
1786 | cpuc->kfree_on_online[i] = NULL; | |
3f6da390 | 1787 | } |
95ca792c TG |
1788 | return 0; |
1789 | } | |
3f6da390 | 1790 | |
95ca792c TG |
1791 | static int x86_pmu_starting_cpu(unsigned int cpu) |
1792 | { | |
1793 | if (x86_pmu.cpu_starting) | |
1794 | x86_pmu.cpu_starting(cpu); | |
1795 | return 0; | |
1796 | } | |
1797 | ||
1798 | static int x86_pmu_dying_cpu(unsigned int cpu) | |
1799 | { | |
1800 | if (x86_pmu.cpu_dying) | |
1801 | x86_pmu.cpu_dying(cpu); | |
1802 | return 0; | |
3f6da390 PZ |
1803 | } |
1804 | ||
12558038 CG |
1805 | static void __init pmu_check_apic(void) |
1806 | { | |
93984fbd | 1807 | if (boot_cpu_has(X86_FEATURE_APIC)) |
12558038 CG |
1808 | return; |
1809 | ||
1810 | x86_pmu.apic = 0; | |
1811 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1812 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1813 | |
1814 | /* | |
1815 | * If we have a PMU initialized but no APIC | |
1816 | * interrupts, we cannot sample hardware | |
1817 | * events (user-space has to fall back and | |
1818 | * sample via a hrtimer based software event): | |
1819 | */ | |
1820 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1821 | ||
12558038 CG |
1822 | } |
1823 | ||
2766d2ee | 1824 | static struct attribute_group x86_pmu_format_group __ro_after_init = { |
641cc938 JO |
1825 | .name = "format", |
1826 | .attrs = NULL, | |
1827 | }; | |
1828 | ||
c7ab62bf | 1829 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page) |
a4747393 | 1830 | { |
1e69a0ef | 1831 | struct perf_pmu_events_attr *pmu_attr = |
a4747393 | 1832 | container_of(attr, struct perf_pmu_events_attr, attr); |
1e69a0ef PZ |
1833 | u64 config = 0; |
1834 | ||
1835 | if (pmu_attr->id < x86_pmu.max_events) | |
1836 | config = x86_pmu.event_map(pmu_attr->id); | |
a4747393 | 1837 | |
3a54aaa0 SE |
1838 | /* string trumps id */ |
1839 | if (pmu_attr->event_str) | |
1840 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1841 | |
3a54aaa0 SE |
1842 | return x86_pmu.events_sysfs_show(page, config); |
1843 | } | |
c7ab62bf | 1844 | EXPORT_SYMBOL_GPL(events_sysfs_show); |
a4747393 | 1845 | |
fc07e9f9 AK |
1846 | ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, |
1847 | char *page) | |
1848 | { | |
1849 | struct perf_pmu_events_ht_attr *pmu_attr = | |
1850 | container_of(attr, struct perf_pmu_events_ht_attr, attr); | |
1851 | ||
1852 | /* | |
1853 | * Report conditional events depending on Hyper-Threading. | |
1854 | * | |
1855 | * This is overly conservative as usually the HT special | |
1856 | * handling is not needed if the other CPU thread is idle. | |
1857 | * | |
1858 | * Note this does not (and cannot) handle the case when thread | |
1859 | * siblings are invisible, for example with virtualization | |
1860 | * if they are owned by some other guest. The user tool | |
1861 | * has to re-read when a thread sibling gets onlined later. | |
1862 | */ | |
1863 | return sprintf(page, "%s", | |
1864 | topology_max_smt_threads() > 1 ? | |
1865 | pmu_attr->event_str_ht : | |
1866 | pmu_attr->event_str_noht); | |
1867 | } | |
1868 | ||
a9c81ccd KL |
1869 | ssize_t events_hybrid_sysfs_show(struct device *dev, |
1870 | struct device_attribute *attr, | |
1871 | char *page) | |
1872 | { | |
1873 | struct perf_pmu_events_hybrid_attr *pmu_attr = | |
1874 | container_of(attr, struct perf_pmu_events_hybrid_attr, attr); | |
1875 | struct x86_hybrid_pmu *pmu; | |
1876 | const char *str, *next_str; | |
1877 | int i; | |
1878 | ||
1879 | if (hweight64(pmu_attr->pmu_type) == 1) | |
1880 | return sprintf(page, "%s", pmu_attr->event_str); | |
1881 | ||
1882 | /* | |
1883 | * Hybrid PMUs may support the same event name, but with different | |
1884 | * event encoding, e.g., the mem-loads event on an Atom PMU has | |
1885 | * different event encoding from a Core PMU. | |
1886 | * | |
1887 | * The event_str includes all event encodings. Each event encoding | |
1888 | * is divided by ";". The order of the event encodings must follow | |
1889 | * the order of the hybrid PMU index. | |
1890 | */ | |
1891 | pmu = container_of(dev_get_drvdata(dev), struct x86_hybrid_pmu, pmu); | |
1892 | ||
1893 | str = pmu_attr->event_str; | |
1894 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { | |
1895 | if (!(x86_pmu.hybrid_pmu[i].cpu_type & pmu_attr->pmu_type)) | |
1896 | continue; | |
1897 | if (x86_pmu.hybrid_pmu[i].cpu_type & pmu->cpu_type) { | |
1898 | next_str = strchr(str, ';'); | |
1899 | if (next_str) | |
1900 | return snprintf(page, next_str - str + 1, "%s", str); | |
1901 | else | |
1902 | return sprintf(page, "%s", str); | |
1903 | } | |
1904 | str = strchr(str, ';'); | |
1905 | str++; | |
1906 | } | |
1907 | ||
1908 | return 0; | |
1909 | } | |
1910 | EXPORT_SYMBOL_GPL(events_hybrid_sysfs_show); | |
1911 | ||
a4747393 JO |
1912 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); |
1913 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1914 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1915 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1916 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1917 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1918 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1919 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1920 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1921 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1922 | ||
1923 | static struct attribute *empty_attrs; | |
1924 | ||
95d18aa2 | 1925 | static struct attribute *events_attr[] = { |
a4747393 JO |
1926 | EVENT_PTR(CPU_CYCLES), |
1927 | EVENT_PTR(INSTRUCTIONS), | |
1928 | EVENT_PTR(CACHE_REFERENCES), | |
1929 | EVENT_PTR(CACHE_MISSES), | |
1930 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1931 | EVENT_PTR(BRANCH_MISSES), | |
1932 | EVENT_PTR(BUS_CYCLES), | |
1933 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1934 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1935 | EVENT_PTR(REF_CPU_CYCLES), | |
1936 | NULL, | |
1937 | }; | |
1938 | ||
3d567273 JO |
1939 | /* |
1940 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1941 | * out of events_attr attributes. | |
1942 | */ | |
1943 | static umode_t | |
1944 | is_visible(struct kobject *kobj, struct attribute *attr, int idx) | |
1945 | { | |
1946 | struct perf_pmu_events_attr *pmu_attr; | |
1947 | ||
1e69a0ef PZ |
1948 | if (idx >= x86_pmu.max_events) |
1949 | return 0; | |
1950 | ||
3d567273 JO |
1951 | pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr); |
1952 | /* str trumps id */ | |
1953 | return pmu_attr->event_str || x86_pmu.event_map(idx) ? attr->mode : 0; | |
1954 | } | |
1955 | ||
2766d2ee | 1956 | static struct attribute_group x86_pmu_events_group __ro_after_init = { |
a4747393 JO |
1957 | .name = "events", |
1958 | .attrs = events_attr, | |
3d567273 | 1959 | .is_visible = is_visible, |
a4747393 JO |
1960 | }; |
1961 | ||
0bf79d44 | 1962 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1963 | { |
43c032fe JO |
1964 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1965 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1966 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1967 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1968 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1969 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1970 | ssize_t ret; | |
1971 | ||
1972 | /* | |
1973 | * We have whole page size to spend and just little data | |
1974 | * to write, so we can safely use sprintf. | |
1975 | */ | |
1976 | ret = sprintf(page, "event=0x%02llx", event); | |
1977 | ||
1978 | if (umask) | |
1979 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1980 | ||
1981 | if (edge) | |
1982 | ret += sprintf(page + ret, ",edge"); | |
1983 | ||
1984 | if (pc) | |
1985 | ret += sprintf(page + ret, ",pc"); | |
1986 | ||
1987 | if (any) | |
1988 | ret += sprintf(page + ret, ",any"); | |
1989 | ||
1990 | if (inv) | |
1991 | ret += sprintf(page + ret, ",inv"); | |
1992 | ||
1993 | if (cmask) | |
1994 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1995 | ||
1996 | ret += sprintf(page + ret, "\n"); | |
1997 | ||
1998 | return ret; | |
1999 | } | |
2000 | ||
6089327f | 2001 | static struct attribute_group x86_pmu_attr_group; |
5da382eb | 2002 | static struct attribute_group x86_pmu_caps_group; |
6089327f | 2003 | |
7c9903c9 PZ |
2004 | static void x86_pmu_static_call_update(void) |
2005 | { | |
2006 | static_call_update(x86_pmu_handle_irq, x86_pmu.handle_irq); | |
2007 | static_call_update(x86_pmu_disable_all, x86_pmu.disable_all); | |
2008 | static_call_update(x86_pmu_enable_all, x86_pmu.enable_all); | |
2009 | static_call_update(x86_pmu_enable, x86_pmu.enable); | |
2010 | static_call_update(x86_pmu_disable, x86_pmu.disable); | |
2011 | ||
8b8ff8cc AH |
2012 | static_call_update(x86_pmu_assign, x86_pmu.assign); |
2013 | ||
7c9903c9 PZ |
2014 | static_call_update(x86_pmu_add, x86_pmu.add); |
2015 | static_call_update(x86_pmu_del, x86_pmu.del); | |
2016 | static_call_update(x86_pmu_read, x86_pmu.read); | |
2017 | ||
2018 | static_call_update(x86_pmu_schedule_events, x86_pmu.schedule_events); | |
2019 | static_call_update(x86_pmu_get_event_constraints, x86_pmu.get_event_constraints); | |
2020 | static_call_update(x86_pmu_put_event_constraints, x86_pmu.put_event_constraints); | |
2021 | ||
2022 | static_call_update(x86_pmu_start_scheduling, x86_pmu.start_scheduling); | |
2023 | static_call_update(x86_pmu_commit_scheduling, x86_pmu.commit_scheduling); | |
2024 | static_call_update(x86_pmu_stop_scheduling, x86_pmu.stop_scheduling); | |
2025 | ||
2026 | static_call_update(x86_pmu_sched_task, x86_pmu.sched_task); | |
2027 | static_call_update(x86_pmu_swap_task_ctx, x86_pmu.swap_task_ctx); | |
2028 | ||
2029 | static_call_update(x86_pmu_drain_pebs, x86_pmu.drain_pebs); | |
2030 | static_call_update(x86_pmu_pebs_aliases, x86_pmu.pebs_aliases); | |
abd562df LX |
2031 | |
2032 | static_call_update(x86_pmu_guest_get_msrs, x86_pmu.guest_get_msrs); | |
7c9903c9 PZ |
2033 | } |
2034 | ||
2035 | static void _x86_pmu_read(struct perf_event *event) | |
2036 | { | |
2037 | x86_perf_event_update(event); | |
2038 | } | |
2039 | ||
e11c1a7e KL |
2040 | void x86_pmu_show_pmu_cap(int num_counters, int num_counters_fixed, |
2041 | u64 intel_ctrl) | |
2042 | { | |
2043 | pr_info("... version: %d\n", x86_pmu.version); | |
2044 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); | |
2045 | pr_info("... generic registers: %d\n", num_counters); | |
2046 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
2047 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); | |
2048 | pr_info("... fixed-purpose events: %lu\n", | |
2049 | hweight64((((1ULL << num_counters_fixed) - 1) | |
2050 | << INTEL_PMC_IDX_FIXED) & intel_ctrl)); | |
2051 | pr_info("... event mask: %016Lx\n", intel_ctrl); | |
2052 | } | |
2053 | ||
d9977c43 KL |
2054 | /* |
2055 | * The generic code is not hybrid friendly. The hybrid_pmu->pmu | |
2056 | * of the first registered PMU is unconditionally assigned to | |
2057 | * each possible cpuctx->ctx.pmu. | |
2058 | * Update the correct hybrid PMU to the cpuctx->ctx.pmu. | |
2059 | */ | |
2060 | void x86_pmu_update_cpu_context(struct pmu *pmu, int cpu) | |
2061 | { | |
2062 | struct perf_cpu_context *cpuctx; | |
2063 | ||
2064 | if (!pmu->pmu_cpu_context) | |
2065 | return; | |
2066 | ||
2067 | cpuctx = per_cpu_ptr(pmu->pmu_cpu_context, cpu); | |
2068 | cpuctx->ctx.pmu = pmu; | |
2069 | } | |
2070 | ||
dda99116 | 2071 | static int __init init_hw_perf_events(void) |
b56a3802 | 2072 | { |
c1d6f42f | 2073 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
2074 | int err; |
2075 | ||
cdd6c482 | 2076 | pr_info("Performance Events: "); |
1123e3ad | 2077 | |
b56a3802 JSR |
2078 | switch (boot_cpu_data.x86_vendor) { |
2079 | case X86_VENDOR_INTEL: | |
72eae04d | 2080 | err = intel_pmu_init(); |
b56a3802 | 2081 | break; |
f87ad35d | 2082 | case X86_VENDOR_AMD: |
72eae04d | 2083 | err = amd_pmu_init(); |
f87ad35d | 2084 | break; |
6d0ef316 PW |
2085 | case X86_VENDOR_HYGON: |
2086 | err = amd_pmu_init(); | |
2087 | x86_pmu.name = "HYGON"; | |
2088 | break; | |
3a4ac121 C |
2089 | case X86_VENDOR_ZHAOXIN: |
2090 | case X86_VENDOR_CENTAUR: | |
2091 | err = zhaoxin_pmu_init(); | |
2092 | break; | |
4138960a | 2093 | default: |
8a3da6c7 | 2094 | err = -ENOTSUPP; |
b56a3802 | 2095 | } |
1123e3ad | 2096 | if (err != 0) { |
cdd6c482 | 2097 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 2098 | return 0; |
1123e3ad | 2099 | } |
b56a3802 | 2100 | |
12558038 CG |
2101 | pmu_check_apic(); |
2102 | ||
33c6d6a7 | 2103 | /* sanity check that the hardware exists or is emulated */ |
fc4b8fca | 2104 | if (!check_hw_exists(&pmu, x86_pmu.num_counters, x86_pmu.num_counters_fixed)) |
004417a6 | 2105 | return 0; |
33c6d6a7 | 2106 | |
1123e3ad | 2107 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 2108 | |
e97df763 PZ |
2109 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
2110 | ||
c1d6f42f PZ |
2111 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
2112 | quirk->func(); | |
3c44780b | 2113 | |
a1eac7ac RR |
2114 | if (!x86_pmu.intel_ctrl) |
2115 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 2116 | |
cdd6c482 | 2117 | perf_events_lapic_init(); |
9c48f1c6 | 2118 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 2119 | |
63b14649 | 2120 | unconstrained = (struct event_constraint) |
948b1bb8 | 2121 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 2122 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 2123 | |
641cc938 | 2124 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 2125 | |
a4747393 JO |
2126 | if (!x86_pmu.events_sysfs_show) |
2127 | x86_pmu_events_group.attrs = &empty_attrs; | |
1a6461b1 | 2128 | |
baa0c833 | 2129 | pmu.attr_update = x86_pmu.attr_update; |
6089327f | 2130 | |
d9977c43 KL |
2131 | if (!is_hybrid()) { |
2132 | x86_pmu_show_pmu_cap(x86_pmu.num_counters, | |
2133 | x86_pmu.num_counters_fixed, | |
2134 | x86_pmu.intel_ctrl); | |
2135 | } | |
3f6da390 | 2136 | |
7c9903c9 PZ |
2137 | if (!x86_pmu.read) |
2138 | x86_pmu.read = _x86_pmu_read; | |
2139 | ||
abd562df | 2140 | if (!x86_pmu.guest_get_msrs) |
c8e2fe13 | 2141 | x86_pmu.guest_get_msrs = (void *)&__static_call_return0; |
abd562df | 2142 | |
7c9903c9 PZ |
2143 | x86_pmu_static_call_update(); |
2144 | ||
95ca792c TG |
2145 | /* |
2146 | * Install callbacks. Core will call them for each online | |
2147 | * cpu. | |
2148 | */ | |
73c1b41e | 2149 | err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare", |
95ca792c TG |
2150 | x86_pmu_prepare_cpu, x86_pmu_dead_cpu); |
2151 | if (err) | |
2152 | return err; | |
2153 | ||
2154 | err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING, | |
73c1b41e | 2155 | "perf/x86:starting", x86_pmu_starting_cpu, |
95ca792c TG |
2156 | x86_pmu_dying_cpu); |
2157 | if (err) | |
2158 | goto out; | |
2159 | ||
73c1b41e | 2160 | err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online", |
95ca792c TG |
2161 | x86_pmu_online_cpu, NULL); |
2162 | if (err) | |
2163 | goto out1; | |
2164 | ||
d9977c43 KL |
2165 | if (!is_hybrid()) { |
2166 | err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); | |
2167 | if (err) | |
2168 | goto out2; | |
2169 | } else { | |
2170 | u8 cpu_type = get_this_hybrid_cpu_type(); | |
2171 | struct x86_hybrid_pmu *hybrid_pmu; | |
2172 | int i, j; | |
2173 | ||
2174 | if (!cpu_type && x86_pmu.get_hybrid_cpu_type) | |
2175 | cpu_type = x86_pmu.get_hybrid_cpu_type(); | |
2176 | ||
2177 | for (i = 0; i < x86_pmu.num_hybrid_pmus; i++) { | |
2178 | hybrid_pmu = &x86_pmu.hybrid_pmu[i]; | |
2179 | ||
2180 | hybrid_pmu->pmu = pmu; | |
2181 | hybrid_pmu->pmu.type = -1; | |
2182 | hybrid_pmu->pmu.attr_update = x86_pmu.attr_update; | |
2183 | hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_HETEROGENEOUS_CPUS; | |
55bcf6ef | 2184 | hybrid_pmu->pmu.capabilities |= PERF_PMU_CAP_EXTENDED_HW_TYPE; |
d9977c43 KL |
2185 | |
2186 | err = perf_pmu_register(&hybrid_pmu->pmu, hybrid_pmu->name, | |
2187 | (hybrid_pmu->cpu_type == hybrid_big) ? PERF_TYPE_RAW : -1); | |
2188 | if (err) | |
2189 | break; | |
2190 | ||
2191 | if (cpu_type == hybrid_pmu->cpu_type) | |
2192 | x86_pmu_update_cpu_context(&hybrid_pmu->pmu, raw_smp_processor_id()); | |
2193 | } | |
2194 | ||
2195 | if (i < x86_pmu.num_hybrid_pmus) { | |
2196 | for (j = 0; j < i; j++) | |
2197 | perf_pmu_unregister(&x86_pmu.hybrid_pmu[j].pmu); | |
2198 | pr_warn("Failed to register hybrid PMUs\n"); | |
2199 | kfree(x86_pmu.hybrid_pmu); | |
2200 | x86_pmu.hybrid_pmu = NULL; | |
2201 | x86_pmu.num_hybrid_pmus = 0; | |
2202 | goto out2; | |
2203 | } | |
2204 | } | |
004417a6 PZ |
2205 | |
2206 | return 0; | |
95ca792c TG |
2207 | |
2208 | out2: | |
2209 | cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE); | |
2210 | out1: | |
2211 | cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING); | |
2212 | out: | |
2213 | cpuhp_remove_state(CPUHP_PERF_X86_PREPARE); | |
2214 | return err; | |
241771ef | 2215 | } |
004417a6 | 2216 | early_initcall(init_hw_perf_events); |
621a01ea | 2217 | |
7c9903c9 | 2218 | static void x86_pmu_read(struct perf_event *event) |
ee06094f | 2219 | { |
7c9903c9 | 2220 | static_call(x86_pmu_read)(event); |
ee06094f IM |
2221 | } |
2222 | ||
4d1c52b0 LM |
2223 | /* |
2224 | * Start group events scheduling transaction | |
2225 | * Set the flag to make pmu::enable() not perform the | |
2226 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
2227 | * |
2228 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
2229 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
2230 | * transactions. | |
4d1c52b0 | 2231 | */ |
fbbe0701 | 2232 | static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
4d1c52b0 | 2233 | { |
fbbe0701 SB |
2234 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2235 | ||
2236 | WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ | |
2237 | ||
2238 | cpuc->txn_flags = txn_flags; | |
2239 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
2240 | return; | |
2241 | ||
33696fc0 | 2242 | perf_pmu_disable(pmu); |
0a3aee0d | 2243 | __this_cpu_write(cpu_hw_events.n_txn, 0); |
871a93b0 | 2244 | __this_cpu_write(cpu_hw_events.n_txn_pair, 0); |
3dbde695 | 2245 | __this_cpu_write(cpu_hw_events.n_txn_metric, 0); |
4d1c52b0 LM |
2246 | } |
2247 | ||
2248 | /* | |
2249 | * Stop group events scheduling transaction | |
2250 | * Clear the flag and pmu::enable() will perform the | |
2251 | * schedulability test. | |
2252 | */ | |
51b0fe39 | 2253 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 2254 | { |
fbbe0701 SB |
2255 | unsigned int txn_flags; |
2256 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2257 | ||
2258 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ | |
2259 | ||
2260 | txn_flags = cpuc->txn_flags; | |
2261 | cpuc->txn_flags = 0; | |
2262 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
2263 | return; | |
2264 | ||
90151c35 | 2265 | /* |
c347a2f1 PZ |
2266 | * Truncate collected array by the number of events added in this |
2267 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 2268 | */ |
0a3aee0d TH |
2269 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
2270 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
871a93b0 | 2271 | __this_cpu_sub(cpu_hw_events.n_pair, __this_cpu_read(cpu_hw_events.n_txn_pair)); |
3dbde695 | 2272 | __this_cpu_sub(cpu_hw_events.n_metric, __this_cpu_read(cpu_hw_events.n_txn_metric)); |
33696fc0 | 2273 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
2274 | } |
2275 | ||
2276 | /* | |
2277 | * Commit group events scheduling transaction | |
2278 | * Perform the group schedulability test as a whole | |
2279 | * Return 0 if success | |
c347a2f1 PZ |
2280 | * |
2281 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 2282 | */ |
51b0fe39 | 2283 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 | 2284 | { |
89cbc767 | 2285 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
4d1c52b0 LM |
2286 | int assign[X86_PMC_IDX_MAX]; |
2287 | int n, ret; | |
2288 | ||
fbbe0701 SB |
2289 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ |
2290 | ||
2291 | if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { | |
2292 | cpuc->txn_flags = 0; | |
2293 | return 0; | |
2294 | } | |
2295 | ||
4d1c52b0 LM |
2296 | n = cpuc->n_events; |
2297 | ||
2298 | if (!x86_pmu_initialized()) | |
2299 | return -EAGAIN; | |
2300 | ||
7c9903c9 | 2301 | ret = static_call(x86_pmu_schedule_events)(cpuc, n, assign); |
4d1c52b0 LM |
2302 | if (ret) |
2303 | return ret; | |
2304 | ||
2305 | /* | |
2306 | * copy new assignment, now we know it is possible | |
2307 | * will be used by hw_perf_enable() | |
2308 | */ | |
2309 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
2310 | ||
fbbe0701 | 2311 | cpuc->txn_flags = 0; |
33696fc0 | 2312 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
2313 | return 0; |
2314 | } | |
cd8a38d3 SE |
2315 | /* |
2316 | * a fake_cpuc is used to validate event groups. Due to | |
2317 | * the extra reg logic, we need to also allocate a fake | |
2318 | * per_core and per_cpu structure. Otherwise, group events | |
2319 | * using extra reg may conflict without the kernel being | |
2320 | * able to catch this when the last event gets added to | |
2321 | * the group. | |
2322 | */ | |
2323 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
2324 | { | |
d01b1f96 | 2325 | intel_cpuc_finish(cpuc); |
cd8a38d3 SE |
2326 | kfree(cpuc); |
2327 | } | |
2328 | ||
d9977c43 | 2329 | static struct cpu_hw_events *allocate_fake_cpuc(struct pmu *event_pmu) |
cd8a38d3 SE |
2330 | { |
2331 | struct cpu_hw_events *cpuc; | |
d9977c43 | 2332 | int cpu; |
cd8a38d3 SE |
2333 | |
2334 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
2335 | if (!cpuc) | |
2336 | return ERR_PTR(-ENOMEM); | |
b430f7c4 | 2337 | cpuc->is_fake = 1; |
d01b1f96 | 2338 | |
d9977c43 KL |
2339 | if (is_hybrid()) { |
2340 | struct x86_hybrid_pmu *h_pmu; | |
2341 | ||
2342 | h_pmu = hybrid_pmu(event_pmu); | |
2343 | if (cpumask_empty(&h_pmu->supported_cpus)) | |
2344 | goto error; | |
2345 | cpu = cpumask_first(&h_pmu->supported_cpus); | |
2346 | } else | |
2347 | cpu = raw_smp_processor_id(); | |
2348 | cpuc->pmu = event_pmu; | |
2349 | ||
d01b1f96 PZI |
2350 | if (intel_cpuc_prepare(cpuc, cpu)) |
2351 | goto error; | |
2352 | ||
cd8a38d3 SE |
2353 | return cpuc; |
2354 | error: | |
2355 | free_fake_cpuc(cpuc); | |
2356 | return ERR_PTR(-ENOMEM); | |
2357 | } | |
4d1c52b0 | 2358 | |
ca037701 PZ |
2359 | /* |
2360 | * validate that we can schedule this event | |
2361 | */ | |
2362 | static int validate_event(struct perf_event *event) | |
2363 | { | |
2364 | struct cpu_hw_events *fake_cpuc; | |
2365 | struct event_constraint *c; | |
2366 | int ret = 0; | |
2367 | ||
d9977c43 | 2368 | fake_cpuc = allocate_fake_cpuc(event->pmu); |
cd8a38d3 SE |
2369 | if (IS_ERR(fake_cpuc)) |
2370 | return PTR_ERR(fake_cpuc); | |
ca037701 | 2371 | |
21d65555 | 2372 | c = x86_pmu.get_event_constraints(fake_cpuc, 0, event); |
ca037701 PZ |
2373 | |
2374 | if (!c || !c->weight) | |
aa2bc1ad | 2375 | ret = -EINVAL; |
ca037701 PZ |
2376 | |
2377 | if (x86_pmu.put_event_constraints) | |
2378 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
2379 | ||
cd8a38d3 | 2380 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
2381 | |
2382 | return ret; | |
2383 | } | |
2384 | ||
1da53e02 SE |
2385 | /* |
2386 | * validate a single event group | |
2387 | * | |
2388 | * validation include: | |
184f412c IM |
2389 | * - check events are compatible which each other |
2390 | * - events do not compete for the same counter | |
2391 | * - number of events <= number of counters | |
1da53e02 SE |
2392 | * |
2393 | * validation ensures the group can be loaded onto the | |
2394 | * PMU if it was the only group available. | |
2395 | */ | |
fe9081cc PZ |
2396 | static int validate_group(struct perf_event *event) |
2397 | { | |
1da53e02 | 2398 | struct perf_event *leader = event->group_leader; |
502568d5 | 2399 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 2400 | int ret = -EINVAL, n; |
fe9081cc | 2401 | |
d9977c43 KL |
2402 | /* |
2403 | * Reject events from different hybrid PMUs. | |
2404 | */ | |
2405 | if (is_hybrid()) { | |
2406 | struct perf_event *sibling; | |
2407 | struct pmu *pmu = NULL; | |
2408 | ||
2409 | if (is_x86_event(leader)) | |
2410 | pmu = leader->pmu; | |
2411 | ||
2412 | for_each_sibling_event(sibling, leader) { | |
2413 | if (!is_x86_event(sibling)) | |
2414 | continue; | |
2415 | if (!pmu) | |
2416 | pmu = sibling->pmu; | |
2417 | else if (pmu != sibling->pmu) | |
2418 | return ret; | |
2419 | } | |
2420 | } | |
2421 | ||
2422 | fake_cpuc = allocate_fake_cpuc(event->pmu); | |
cd8a38d3 SE |
2423 | if (IS_ERR(fake_cpuc)) |
2424 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
2425 | /* |
2426 | * the event is not yet connected with its | |
2427 | * siblings therefore we must first collect | |
2428 | * existing siblings, then add the new event | |
2429 | * before we can simulate the scheduling | |
2430 | */ | |
502568d5 | 2431 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 2432 | if (n < 0) |
cd8a38d3 | 2433 | goto out; |
fe9081cc | 2434 | |
502568d5 PZ |
2435 | fake_cpuc->n_events = n; |
2436 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 2437 | if (n < 0) |
cd8a38d3 | 2438 | goto out; |
fe9081cc | 2439 | |
1f6a1e2d | 2440 | fake_cpuc->n_events = 0; |
a072738e | 2441 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 2442 | |
502568d5 | 2443 | out: |
cd8a38d3 | 2444 | free_fake_cpuc(fake_cpuc); |
502568d5 | 2445 | return ret; |
fe9081cc PZ |
2446 | } |
2447 | ||
dda99116 | 2448 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 2449 | { |
d9977c43 | 2450 | struct x86_hybrid_pmu *pmu = NULL; |
621a01ea IM |
2451 | int err; |
2452 | ||
d9977c43 KL |
2453 | if ((event->attr.type != event->pmu->type) && |
2454 | (event->attr.type != PERF_TYPE_HARDWARE) && | |
2455 | (event->attr.type != PERF_TYPE_HW_CACHE)) | |
b0a873eb | 2456 | return -ENOENT; |
d9977c43 KL |
2457 | |
2458 | if (is_hybrid() && (event->cpu != -1)) { | |
2459 | pmu = hybrid_pmu(event->pmu); | |
2460 | if (!cpumask_test_cpu(event->cpu, &pmu->supported_cpus)) | |
2461 | return -ENOENT; | |
b0a873eb PZ |
2462 | } |
2463 | ||
2464 | err = __x86_pmu_event_init(event); | |
fe9081cc PZ |
2465 | if (!err) { |
2466 | if (event->group_leader != event) | |
2467 | err = validate_group(event); | |
ca037701 PZ |
2468 | else |
2469 | err = validate_event(event); | |
fe9081cc | 2470 | } |
a1792cda | 2471 | if (err) { |
cdd6c482 IM |
2472 | if (event->destroy) |
2473 | event->destroy(event); | |
02d029a4 | 2474 | event->destroy = NULL; |
a1792cda | 2475 | } |
621a01ea | 2476 | |
1af22eba | 2477 | if (READ_ONCE(x86_pmu.attr_rdpmc) && |
174afc3e | 2478 | !(event->hw.flags & PERF_X86_EVENT_LARGE_PEBS)) |
7911d3f7 AL |
2479 | event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; |
2480 | ||
b0a873eb | 2481 | return err; |
621a01ea | 2482 | } |
d7d59fb3 | 2483 | |
5471eea5 KL |
2484 | void perf_clear_dirty_counters(void) |
2485 | { | |
2486 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
2487 | int i; | |
2488 | ||
2489 | /* Don't need to clear the assigned counter. */ | |
2490 | for (i = 0; i < cpuc->n_events; i++) | |
2491 | __clear_bit(cpuc->assign[i], cpuc->dirty); | |
2492 | ||
2493 | if (bitmap_empty(cpuc->dirty, X86_PMC_IDX_MAX)) | |
2494 | return; | |
2495 | ||
2496 | for_each_set_bit(i, cpuc->dirty, X86_PMC_IDX_MAX) { | |
f4b4b456 PZ |
2497 | if (i >= INTEL_PMC_IDX_FIXED) { |
2498 | /* Metrics and fake events don't have corresponding HW counters. */ | |
2499 | if ((i - INTEL_PMC_IDX_FIXED) >= hybrid(cpuc->pmu, num_counters_fixed)) | |
2500 | continue; | |
2501 | ||
5471eea5 | 2502 | wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + (i - INTEL_PMC_IDX_FIXED), 0); |
f4b4b456 | 2503 | } else { |
5471eea5 | 2504 | wrmsrl(x86_pmu_event_addr(i), 0); |
f4b4b456 | 2505 | } |
5471eea5 KL |
2506 | } |
2507 | ||
2508 | bitmap_zero(cpuc->dirty, X86_PMC_IDX_MAX); | |
2509 | } | |
2510 | ||
bfe33492 | 2511 | static void x86_pmu_event_mapped(struct perf_event *event, struct mm_struct *mm) |
7911d3f7 AL |
2512 | { |
2513 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
2514 | return; | |
2515 | ||
4b07372a AL |
2516 | /* |
2517 | * This function relies on not being called concurrently in two | |
2518 | * tasks in the same mm. Otherwise one task could observe | |
2519 | * perf_rdpmc_allowed > 1 and return all the way back to | |
2520 | * userspace with CR4.PCE clear while another task is still | |
2521 | * doing on_each_cpu_mask() to propagate CR4.PCE. | |
2522 | * | |
c1e8d7c6 | 2523 | * For now, this can't happen because all callers hold mmap_lock |
4b07372a AL |
2524 | * for write. If this changes, we'll need a different solution. |
2525 | */ | |
42fc5414 | 2526 | mmap_assert_write_locked(mm); |
4b07372a | 2527 | |
bfe33492 | 2528 | if (atomic_inc_return(&mm->context.perf_rdpmc_allowed) == 1) |
cb2a0235 | 2529 | on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1); |
7911d3f7 AL |
2530 | } |
2531 | ||
bfe33492 | 2532 | static void x86_pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm) |
7911d3f7 | 2533 | { |
7911d3f7 AL |
2534 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
2535 | return; | |
2536 | ||
bfe33492 | 2537 | if (atomic_dec_and_test(&mm->context.perf_rdpmc_allowed)) |
cb2a0235 | 2538 | on_each_cpu_mask(mm_cpumask(mm), cr4_update_pce, NULL, 1); |
7911d3f7 AL |
2539 | } |
2540 | ||
fe4a3308 PZ |
2541 | static int x86_pmu_event_idx(struct perf_event *event) |
2542 | { | |
75608cb0 | 2543 | struct hw_perf_event *hwc = &event->hw; |
fe4a3308 | 2544 | |
75608cb0 | 2545 | if (!(hwc->flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
c7206205 PZ |
2546 | return 0; |
2547 | ||
2cb5383b KL |
2548 | if (is_metric_idx(hwc->idx)) |
2549 | return INTEL_PMC_FIXED_RDPMC_METRICS + 1; | |
2550 | else | |
2551 | return hwc->event_base_rdpmc + 1; | |
fe4a3308 PZ |
2552 | } |
2553 | ||
0c9d42ed PZ |
2554 | static ssize_t get_attr_rdpmc(struct device *cdev, |
2555 | struct device_attribute *attr, | |
2556 | char *buf) | |
2557 | { | |
2558 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
2559 | } | |
2560 | ||
0c9d42ed PZ |
2561 | static ssize_t set_attr_rdpmc(struct device *cdev, |
2562 | struct device_attribute *attr, | |
2563 | const char *buf, size_t count) | |
2564 | { | |
e2b297fc SK |
2565 | unsigned long val; |
2566 | ssize_t ret; | |
2567 | ||
2568 | ret = kstrtoul(buf, 0, &val); | |
2569 | if (ret) | |
2570 | return ret; | |
e97df763 | 2571 | |
a6673429 AL |
2572 | if (val > 2) |
2573 | return -EINVAL; | |
2574 | ||
e97df763 PZ |
2575 | if (x86_pmu.attr_rdpmc_broken) |
2576 | return -ENOTSUPP; | |
0c9d42ed | 2577 | |
405b4537 | 2578 | if (val != x86_pmu.attr_rdpmc) { |
a6673429 | 2579 | /* |
405b4537 AS |
2580 | * Changing into or out of never available or always available, |
2581 | * aka perf-event-bypassing mode. This path is extremely slow, | |
a6673429 AL |
2582 | * but only root can trigger it, so it's okay. |
2583 | */ | |
405b4537 AS |
2584 | if (val == 0) |
2585 | static_branch_inc(&rdpmc_never_available_key); | |
2586 | else if (x86_pmu.attr_rdpmc == 0) | |
2587 | static_branch_dec(&rdpmc_never_available_key); | |
2588 | ||
a6673429 | 2589 | if (val == 2) |
631fe154 | 2590 | static_branch_inc(&rdpmc_always_available_key); |
405b4537 | 2591 | else if (x86_pmu.attr_rdpmc == 2) |
631fe154 | 2592 | static_branch_dec(&rdpmc_always_available_key); |
405b4537 | 2593 | |
cb2a0235 | 2594 | on_each_cpu(cr4_update_pce, NULL, 1); |
405b4537 | 2595 | x86_pmu.attr_rdpmc = val; |
a6673429 AL |
2596 | } |
2597 | ||
0c9d42ed PZ |
2598 | return count; |
2599 | } | |
2600 | ||
2601 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
2602 | ||
2603 | static struct attribute *x86_pmu_attrs[] = { | |
2604 | &dev_attr_rdpmc.attr, | |
2605 | NULL, | |
2606 | }; | |
2607 | ||
2766d2ee | 2608 | static struct attribute_group x86_pmu_attr_group __ro_after_init = { |
0c9d42ed PZ |
2609 | .attrs = x86_pmu_attrs, |
2610 | }; | |
2611 | ||
5da382eb PZ |
2612 | static ssize_t max_precise_show(struct device *cdev, |
2613 | struct device_attribute *attr, | |
2614 | char *buf) | |
2615 | { | |
2616 | return snprintf(buf, PAGE_SIZE, "%d\n", x86_pmu_max_precise()); | |
2617 | } | |
2618 | ||
2619 | static DEVICE_ATTR_RO(max_precise); | |
2620 | ||
2621 | static struct attribute *x86_pmu_caps_attrs[] = { | |
2622 | &dev_attr_max_precise.attr, | |
2623 | NULL | |
2624 | }; | |
2625 | ||
2766d2ee | 2626 | static struct attribute_group x86_pmu_caps_group __ro_after_init = { |
5da382eb PZ |
2627 | .name = "caps", |
2628 | .attrs = x86_pmu_caps_attrs, | |
2629 | }; | |
2630 | ||
0c9d42ed PZ |
2631 | static const struct attribute_group *x86_pmu_attr_groups[] = { |
2632 | &x86_pmu_attr_group, | |
641cc938 | 2633 | &x86_pmu_format_group, |
a4747393 | 2634 | &x86_pmu_events_group, |
b00233b5 | 2635 | &x86_pmu_caps_group, |
0c9d42ed PZ |
2636 | NULL, |
2637 | }; | |
2638 | ||
ba532500 | 2639 | static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d010b332 | 2640 | { |
7c9903c9 | 2641 | static_call_cond(x86_pmu_sched_task)(ctx, sched_in); |
d010b332 SE |
2642 | } |
2643 | ||
a4439970 AB |
2644 | static void x86_pmu_swap_task_ctx(struct perf_event_context *prev, |
2645 | struct perf_event_context *next) | |
2646 | { | |
7c9903c9 | 2647 | static_call_cond(x86_pmu_swap_task_ctx)(prev, next); |
a4439970 AB |
2648 | } |
2649 | ||
c93dc84c PZ |
2650 | void perf_check_microcode(void) |
2651 | { | |
2652 | if (x86_pmu.check_microcode) | |
2653 | x86_pmu.check_microcode(); | |
2654 | } | |
c93dc84c | 2655 | |
81ec3f3c JO |
2656 | static int x86_pmu_check_period(struct perf_event *event, u64 value) |
2657 | { | |
2658 | if (x86_pmu.check_period && x86_pmu.check_period(event, value)) | |
2659 | return -EINVAL; | |
2660 | ||
2661 | if (value && x86_pmu.limit_period) { | |
2662 | if (x86_pmu.limit_period(event, value) > value) | |
2663 | return -EINVAL; | |
2664 | } | |
2665 | ||
2666 | return 0; | |
2667 | } | |
2668 | ||
42880f72 AS |
2669 | static int x86_pmu_aux_output_match(struct perf_event *event) |
2670 | { | |
2671 | if (!(pmu.capabilities & PERF_PMU_CAP_AUX_OUTPUT)) | |
2672 | return 0; | |
2673 | ||
2674 | if (x86_pmu.aux_output_match) | |
2675 | return x86_pmu.aux_output_match(event); | |
2676 | ||
2677 | return 0; | |
2678 | } | |
2679 | ||
3e9a8b21 KL |
2680 | static int x86_pmu_filter_match(struct perf_event *event) |
2681 | { | |
2682 | if (x86_pmu.filter_match) | |
2683 | return x86_pmu.filter_match(event); | |
2684 | ||
2685 | return 1; | |
2686 | } | |
2687 | ||
b0a873eb | 2688 | static struct pmu pmu = { |
d010b332 SE |
2689 | .pmu_enable = x86_pmu_enable, |
2690 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 2691 | |
c93dc84c | 2692 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 2693 | |
c93dc84c | 2694 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 2695 | |
7911d3f7 AL |
2696 | .event_mapped = x86_pmu_event_mapped, |
2697 | .event_unmapped = x86_pmu_event_unmapped, | |
2698 | ||
d010b332 SE |
2699 | .add = x86_pmu_add, |
2700 | .del = x86_pmu_del, | |
2701 | .start = x86_pmu_start, | |
2702 | .stop = x86_pmu_stop, | |
2703 | .read = x86_pmu_read, | |
a4eaf7f1 | 2704 | |
c93dc84c PZ |
2705 | .start_txn = x86_pmu_start_txn, |
2706 | .cancel_txn = x86_pmu_cancel_txn, | |
2707 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 2708 | |
c93dc84c | 2709 | .event_idx = x86_pmu_event_idx, |
ba532500 | 2710 | .sched_task = x86_pmu_sched_task, |
a4439970 | 2711 | .swap_task_ctx = x86_pmu_swap_task_ctx, |
81ec3f3c | 2712 | .check_period = x86_pmu_check_period, |
42880f72 AS |
2713 | |
2714 | .aux_output_match = x86_pmu_aux_output_match, | |
3e9a8b21 KL |
2715 | |
2716 | .filter_match = x86_pmu_filter_match, | |
b0a873eb PZ |
2717 | }; |
2718 | ||
c1317ec2 AL |
2719 | void arch_perf_update_userpage(struct perf_event *event, |
2720 | struct perf_event_mmap_page *userpg, u64 now) | |
e3f3541c | 2721 | { |
59eaef78 | 2722 | struct cyc2ns_data data; |
698eff63 | 2723 | u64 offset; |
20d1c86a | 2724 | |
fa731587 PZ |
2725 | userpg->cap_user_time = 0; |
2726 | userpg->cap_user_time_zero = 0; | |
7911d3f7 AL |
2727 | userpg->cap_user_rdpmc = |
2728 | !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); | |
c7206205 PZ |
2729 | userpg->pmc_width = x86_pmu.cntval_bits; |
2730 | ||
698eff63 | 2731 | if (!using_native_sched_clock() || !sched_clock_stable()) |
e3f3541c PZ |
2732 | return; |
2733 | ||
59eaef78 | 2734 | cyc2ns_read_begin(&data); |
20d1c86a | 2735 | |
59eaef78 | 2736 | offset = data.cyc2ns_offset + __sched_clock_offset; |
698eff63 | 2737 | |
34f43927 PZ |
2738 | /* |
2739 | * Internal timekeeping for enabled/running/stopped times | |
2740 | * is always in the local_clock domain. | |
2741 | */ | |
fa731587 | 2742 | userpg->cap_user_time = 1; |
59eaef78 PZ |
2743 | userpg->time_mult = data.cyc2ns_mul; |
2744 | userpg->time_shift = data.cyc2ns_shift; | |
698eff63 | 2745 | userpg->time_offset = offset - now; |
c73deb6a | 2746 | |
34f43927 PZ |
2747 | /* |
2748 | * cap_user_time_zero doesn't make sense when we're using a different | |
2749 | * time base for the records. | |
2750 | */ | |
f454bfdd | 2751 | if (!event->attr.use_clockid) { |
34f43927 | 2752 | userpg->cap_user_time_zero = 1; |
698eff63 | 2753 | userpg->time_zero = offset; |
34f43927 | 2754 | } |
20d1c86a | 2755 | |
59eaef78 | 2756 | cyc2ns_read_end(); |
e3f3541c PZ |
2757 | } |
2758 | ||
d15d3568 KS |
2759 | /* |
2760 | * Determine whether the regs were taken from an irq/exception handler rather | |
2761 | * than from perf_arch_fetch_caller_regs(). | |
2762 | */ | |
2763 | static bool perf_hw_regs(struct pt_regs *regs) | |
2764 | { | |
2765 | return regs->flags & X86_EFLAGS_FIXED; | |
2766 | } | |
2767 | ||
56962b44 | 2768 | void |
cfbcf468 | 2769 | perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) |
d7d59fb3 | 2770 | { |
ff083a2d | 2771 | struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); |
35f4d9b3 JP |
2772 | struct unwind_state state; |
2773 | unsigned long addr; | |
2774 | ||
b9f5621c | 2775 | if (guest_cbs && guest_cbs->state()) { |
927c7a9e | 2776 | /* TODO: We don't support guest os callchain now */ |
ed805261 | 2777 | return; |
927c7a9e FW |
2778 | } |
2779 | ||
83f44ae0 SL |
2780 | if (perf_callchain_store(entry, regs->ip)) |
2781 | return; | |
2782 | ||
2783 | if (perf_hw_regs(regs)) | |
d15d3568 | 2784 | unwind_start(&state, current, regs, NULL); |
83f44ae0 | 2785 | else |
d15d3568 | 2786 | unwind_start(&state, current, NULL, (void *)regs->sp); |
d7d59fb3 | 2787 | |
d15d3568 | 2788 | for (; !unwind_done(&state); unwind_next_frame(&state)) { |
35f4d9b3 JP |
2789 | addr = unwind_get_return_address(&state); |
2790 | if (!addr || perf_callchain_store(entry, addr)) | |
2791 | return; | |
2792 | } | |
d7d59fb3 PZ |
2793 | } |
2794 | ||
bc6ca7b3 AS |
2795 | static inline int |
2796 | valid_user_frame(const void __user *fp, unsigned long size) | |
2797 | { | |
2798 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
2799 | } | |
2800 | ||
d07bdfd3 PZ |
2801 | static unsigned long get_segment_base(unsigned int segment) |
2802 | { | |
2803 | struct desc_struct *desc; | |
990e9dc3 | 2804 | unsigned int idx = segment >> 3; |
d07bdfd3 PZ |
2805 | |
2806 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
a5b9e5a2 | 2807 | #ifdef CONFIG_MODIFY_LDT_SYSCALL |
37868fe1 AL |
2808 | struct ldt_struct *ldt; |
2809 | ||
37868fe1 | 2810 | /* IRQs are off, so this synchronizes with smp_store_release */ |
506458ef | 2811 | ldt = READ_ONCE(current->active_mm->context.ldt); |
eaa2f87c | 2812 | if (!ldt || idx >= ldt->nr_entries) |
d07bdfd3 PZ |
2813 | return 0; |
2814 | ||
37868fe1 | 2815 | desc = &ldt->entries[idx]; |
a5b9e5a2 AL |
2816 | #else |
2817 | return 0; | |
2818 | #endif | |
d07bdfd3 | 2819 | } else { |
eaa2f87c | 2820 | if (idx >= GDT_ENTRIES) |
d07bdfd3 PZ |
2821 | return 0; |
2822 | ||
37868fe1 | 2823 | desc = raw_cpu_ptr(gdt_page.gdt) + idx; |
d07bdfd3 PZ |
2824 | } |
2825 | ||
37868fe1 | 2826 | return get_desc_base(desc); |
d07bdfd3 PZ |
2827 | } |
2828 | ||
10ed3493 | 2829 | #ifdef CONFIG_IA32_EMULATION |
d1a797f3 | 2830 | |
0d55303c | 2831 | #include <linux/compat.h> |
d1a797f3 | 2832 | |
257ef9d2 | 2833 | static inline int |
cfbcf468 | 2834 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) |
74193ef0 | 2835 | { |
257ef9d2 | 2836 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2837 | unsigned long ss_base, cs_base; |
257ef9d2 | 2838 | struct stack_frame_ia32 frame; |
c8e3dd86 | 2839 | const struct stack_frame_ia32 __user *fp; |
74193ef0 | 2840 | |
375d4bfd | 2841 | if (user_64bit_mode(regs)) |
257ef9d2 TE |
2842 | return 0; |
2843 | ||
d07bdfd3 PZ |
2844 | cs_base = get_segment_base(regs->cs); |
2845 | ss_base = get_segment_base(regs->ss); | |
2846 | ||
2847 | fp = compat_ptr(ss_base + regs->bp); | |
75925e1a | 2848 | pagefault_disable(); |
3b1fff08 | 2849 | while (entry->nr < entry->max_stack) { |
ae31fe51 | 2850 | if (!valid_user_frame(fp, sizeof(frame))) |
75925e1a AK |
2851 | break; |
2852 | ||
c8e3dd86 | 2853 | if (__get_user(frame.next_frame, &fp->next_frame)) |
75925e1a | 2854 | break; |
c8e3dd86 | 2855 | if (__get_user(frame.return_address, &fp->return_address)) |
257ef9d2 | 2856 | break; |
74193ef0 | 2857 | |
d07bdfd3 PZ |
2858 | perf_callchain_store(entry, cs_base + frame.return_address); |
2859 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 | 2860 | } |
75925e1a | 2861 | pagefault_enable(); |
257ef9d2 | 2862 | return 1; |
d7d59fb3 | 2863 | } |
257ef9d2 TE |
2864 | #else |
2865 | static inline int | |
cfbcf468 | 2866 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) |
257ef9d2 TE |
2867 | { |
2868 | return 0; | |
2869 | } | |
2870 | #endif | |
d7d59fb3 | 2871 | |
56962b44 | 2872 | void |
cfbcf468 | 2873 | perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) |
d7d59fb3 | 2874 | { |
ff083a2d | 2875 | struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); |
d7d59fb3 | 2876 | struct stack_frame frame; |
c8e3dd86 | 2877 | const struct stack_frame __user *fp; |
d7d59fb3 | 2878 | |
b9f5621c | 2879 | if (guest_cbs && guest_cbs->state()) { |
927c7a9e | 2880 | /* TODO: We don't support guest os callchain now */ |
ed805261 | 2881 | return; |
927c7a9e | 2882 | } |
5a6cec3a | 2883 | |
d07bdfd3 PZ |
2884 | /* |
2885 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2886 | */ | |
2887 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2888 | return; | |
2889 | ||
c8e3dd86 | 2890 | fp = (void __user *)regs->bp; |
d7d59fb3 | 2891 | |
70791ce9 | 2892 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2893 | |
4012e77a | 2894 | if (!nmi_uaccess_okay()) |
20afc60f AV |
2895 | return; |
2896 | ||
257ef9d2 TE |
2897 | if (perf_callchain_user32(regs, entry)) |
2898 | return; | |
2899 | ||
75925e1a | 2900 | pagefault_disable(); |
3b1fff08 | 2901 | while (entry->nr < entry->max_stack) { |
ae31fe51 | 2902 | if (!valid_user_frame(fp, sizeof(frame))) |
75925e1a AK |
2903 | break; |
2904 | ||
c8e3dd86 | 2905 | if (__get_user(frame.next_frame, &fp->next_frame)) |
75925e1a | 2906 | break; |
c8e3dd86 | 2907 | if (__get_user(frame.return_address, &fp->return_address)) |
d7d59fb3 PZ |
2908 | break; |
2909 | ||
70791ce9 | 2910 | perf_callchain_store(entry, frame.return_address); |
75925e1a | 2911 | fp = (void __user *)frame.next_frame; |
d7d59fb3 | 2912 | } |
75925e1a | 2913 | pagefault_enable(); |
d7d59fb3 PZ |
2914 | } |
2915 | ||
d07bdfd3 PZ |
2916 | /* |
2917 | * Deal with code segment offsets for the various execution modes: | |
2918 | * | |
2919 | * VM86 - the good olde 16 bit days, where the linear address is | |
2920 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2921 | * | |
2922 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2923 | * to figure out what the 32bit base address is. | |
2924 | * | |
2925 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2926 | * | |
2927 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2928 | */ | |
2929 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2930 | { |
383f3af3 AL |
2931 | /* |
2932 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2933 | * effective IP to a linear address. | |
2934 | */ | |
2935 | ||
2936 | #ifdef CONFIG_X86_32 | |
d07bdfd3 PZ |
2937 | /* |
2938 | * If we are in VM86 mode, add the segment offset to convert to a | |
2939 | * linear address. | |
2940 | */ | |
2941 | if (regs->flags & X86_VM_MASK) | |
2942 | return 0x10 * regs->cs; | |
2943 | ||
55474c48 | 2944 | if (user_mode(regs) && regs->cs != __USER_CS) |
d07bdfd3 PZ |
2945 | return get_segment_base(regs->cs); |
2946 | #else | |
c56716af AL |
2947 | if (user_mode(regs) && !user_64bit_mode(regs) && |
2948 | regs->cs != __USER32_CS) | |
2949 | return get_segment_base(regs->cs); | |
d07bdfd3 PZ |
2950 | #endif |
2951 | return 0; | |
2952 | } | |
dcf46b94 | 2953 | |
d07bdfd3 PZ |
2954 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2955 | { | |
ff083a2d SC |
2956 | struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); |
2957 | ||
b9f5621c LX |
2958 | if (guest_cbs && guest_cbs->state()) |
2959 | return guest_cbs->get_ip(); | |
dcf46b94 | 2960 | |
d07bdfd3 | 2961 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2962 | } |
2963 | ||
2964 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2965 | { | |
ff083a2d | 2966 | struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); |
b9f5621c | 2967 | unsigned int guest_state = guest_cbs ? guest_cbs->state() : 0; |
39447b38 | 2968 | int misc = 0; |
dcf46b94 | 2969 | |
b9f5621c LX |
2970 | if (guest_state) { |
2971 | if (guest_state & PERF_GUEST_USER) | |
dcf46b94 ZY |
2972 | misc |= PERF_RECORD_MISC_GUEST_USER; |
2973 | else | |
2974 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2975 | } else { | |
d07bdfd3 | 2976 | if (user_mode(regs)) |
dcf46b94 ZY |
2977 | misc |= PERF_RECORD_MISC_USER; |
2978 | else | |
2979 | misc |= PERF_RECORD_MISC_KERNEL; | |
2980 | } | |
2981 | ||
39447b38 | 2982 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2983 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2984 | |
2985 | return misc; | |
2986 | } | |
b3d9468a GN |
2987 | |
2988 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2989 | { | |
2990 | cap->version = x86_pmu.version; | |
d4b294bf KL |
2991 | /* |
2992 | * KVM doesn't support the hybrid PMU yet. | |
2993 | * Return the common value in global x86_pmu, | |
2994 | * which available for all cores. | |
2995 | */ | |
b3d9468a GN |
2996 | cap->num_counters_gp = x86_pmu.num_counters; |
2997 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2998 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2999 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
3000 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
3001 | cap->events_mask_len = x86_pmu.events_mask_len; | |
3002 | } | |
3003 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |