Commit | Line | Data |
---|---|---|
241771ef | 1 | /* |
cdd6c482 | 2 | * Performance events x86 architecture code |
241771ef | 3 | * |
98144511 IM |
4 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> |
5 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
6 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
7 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
90eec103 | 8 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra |
30dd568c | 9 | * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com> |
1da53e02 | 10 | * Copyright (C) 2009 Google, Inc., Stephane Eranian |
241771ef IM |
11 | * |
12 | * For licencing details see kernel-base/COPYING | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
241771ef IM |
16 | #include <linux/capability.h> |
17 | #include <linux/notifier.h> | |
18 | #include <linux/hardirq.h> | |
19 | #include <linux/kprobes.h> | |
eb008eb6 PG |
20 | #include <linux/export.h> |
21 | #include <linux/init.h> | |
241771ef IM |
22 | #include <linux/kdebug.h> |
23 | #include <linux/sched.h> | |
d7d59fb3 | 24 | #include <linux/uaccess.h> |
5a0e3ad6 | 25 | #include <linux/slab.h> |
30dd568c | 26 | #include <linux/cpu.h> |
272d30be | 27 | #include <linux/bitops.h> |
0c9d42ed | 28 | #include <linux/device.h> |
241771ef | 29 | |
241771ef | 30 | #include <asm/apic.h> |
d7d59fb3 | 31 | #include <asm/stacktrace.h> |
4e935e47 | 32 | #include <asm/nmi.h> |
69092624 | 33 | #include <asm/smp.h> |
c8e5910e | 34 | #include <asm/alternative.h> |
7911d3f7 | 35 | #include <asm/mmu_context.h> |
375074cc | 36 | #include <asm/tlbflush.h> |
e3f3541c | 37 | #include <asm/timer.h> |
d07bdfd3 PZ |
38 | #include <asm/desc.h> |
39 | #include <asm/ldt.h> | |
35f4d9b3 | 40 | #include <asm/unwind.h> |
241771ef | 41 | |
27f6d22b | 42 | #include "perf_event.h" |
de0428a7 | 43 | |
de0428a7 | 44 | struct x86_pmu x86_pmu __read_mostly; |
efc9f05d | 45 | |
de0428a7 | 46 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { |
b0f3f28e PZ |
47 | .enabled = 1, |
48 | }; | |
241771ef | 49 | |
a6673429 AL |
50 | struct static_key rdpmc_always_available = STATIC_KEY_INIT_FALSE; |
51 | ||
de0428a7 | 52 | u64 __read_mostly hw_cache_event_ids |
8326f44d IM |
53 | [PERF_COUNT_HW_CACHE_MAX] |
54 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
55 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
de0428a7 | 56 | u64 __read_mostly hw_cache_extra_regs |
e994d7d2 AK |
57 | [PERF_COUNT_HW_CACHE_MAX] |
58 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
59 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
8326f44d | 60 | |
ee06094f | 61 | /* |
cdd6c482 IM |
62 | * Propagate event elapsed time into the generic event. |
63 | * Can only be executed on the CPU where the event is active. | |
ee06094f IM |
64 | * Returns the delta events processed. |
65 | */ | |
de0428a7 | 66 | u64 x86_perf_event_update(struct perf_event *event) |
ee06094f | 67 | { |
cc2ad4ba | 68 | struct hw_perf_event *hwc = &event->hw; |
948b1bb8 | 69 | int shift = 64 - x86_pmu.cntval_bits; |
ec3232bd | 70 | u64 prev_raw_count, new_raw_count; |
cc2ad4ba | 71 | int idx = hwc->idx; |
7f612a7f | 72 | u64 delta; |
ee06094f | 73 | |
15c7ad51 | 74 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
75 | return 0; |
76 | ||
ee06094f | 77 | /* |
cdd6c482 | 78 | * Careful: an NMI might modify the previous event value. |
ee06094f IM |
79 | * |
80 | * Our tactic to handle this is to first atomically read and | |
81 | * exchange a new raw count - then add that new-prev delta | |
cdd6c482 | 82 | * count to the generic event atomically: |
ee06094f IM |
83 | */ |
84 | again: | |
e7850595 | 85 | prev_raw_count = local64_read(&hwc->prev_count); |
c48b6053 | 86 | rdpmcl(hwc->event_base_rdpmc, new_raw_count); |
ee06094f | 87 | |
e7850595 | 88 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
ee06094f IM |
89 | new_raw_count) != prev_raw_count) |
90 | goto again; | |
91 | ||
92 | /* | |
93 | * Now we have the new raw value and have updated the prev | |
94 | * timestamp already. We can now calculate the elapsed delta | |
cdd6c482 | 95 | * (event-)time and add that to the generic event. |
ee06094f IM |
96 | * |
97 | * Careful, not all hw sign-extends above the physical width | |
ec3232bd | 98 | * of the count. |
ee06094f | 99 | */ |
ec3232bd PZ |
100 | delta = (new_raw_count << shift) - (prev_raw_count << shift); |
101 | delta >>= shift; | |
ee06094f | 102 | |
e7850595 PZ |
103 | local64_add(delta, &event->count); |
104 | local64_sub(delta, &hwc->period_left); | |
4b7bfd0d RR |
105 | |
106 | return new_raw_count; | |
ee06094f IM |
107 | } |
108 | ||
a7e3ed1e AK |
109 | /* |
110 | * Find and validate any extra registers to set up. | |
111 | */ | |
112 | static int x86_pmu_extra_regs(u64 config, struct perf_event *event) | |
113 | { | |
efc9f05d | 114 | struct hw_perf_event_extra *reg; |
a7e3ed1e AK |
115 | struct extra_reg *er; |
116 | ||
efc9f05d | 117 | reg = &event->hw.extra_reg; |
a7e3ed1e AK |
118 | |
119 | if (!x86_pmu.extra_regs) | |
120 | return 0; | |
121 | ||
122 | for (er = x86_pmu.extra_regs; er->msr; er++) { | |
123 | if (er->event != (config & er->config_mask)) | |
124 | continue; | |
125 | if (event->attr.config1 & ~er->valid_mask) | |
126 | return -EINVAL; | |
338b522c KL |
127 | /* Check if the extra msrs can be safely accessed*/ |
128 | if (!er->extra_msr_access) | |
129 | return -ENXIO; | |
efc9f05d SE |
130 | |
131 | reg->idx = er->idx; | |
132 | reg->config = event->attr.config1; | |
133 | reg->reg = er->msr; | |
a7e3ed1e AK |
134 | break; |
135 | } | |
136 | return 0; | |
137 | } | |
138 | ||
cdd6c482 | 139 | static atomic_t active_events; |
1b7b938f | 140 | static atomic_t pmc_refcount; |
4e935e47 PZ |
141 | static DEFINE_MUTEX(pmc_reserve_mutex); |
142 | ||
b27ea29c RR |
143 | #ifdef CONFIG_X86_LOCAL_APIC |
144 | ||
4e935e47 PZ |
145 | static bool reserve_pmc_hardware(void) |
146 | { | |
147 | int i; | |
148 | ||
948b1bb8 | 149 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 150 | if (!reserve_perfctr_nmi(x86_pmu_event_addr(i))) |
4e935e47 PZ |
151 | goto perfctr_fail; |
152 | } | |
153 | ||
948b1bb8 | 154 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 | 155 | if (!reserve_evntsel_nmi(x86_pmu_config_addr(i))) |
4e935e47 PZ |
156 | goto eventsel_fail; |
157 | } | |
158 | ||
159 | return true; | |
160 | ||
161 | eventsel_fail: | |
162 | for (i--; i >= 0; i--) | |
41bf4989 | 163 | release_evntsel_nmi(x86_pmu_config_addr(i)); |
4e935e47 | 164 | |
948b1bb8 | 165 | i = x86_pmu.num_counters; |
4e935e47 PZ |
166 | |
167 | perfctr_fail: | |
168 | for (i--; i >= 0; i--) | |
41bf4989 | 169 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
4e935e47 | 170 | |
4e935e47 PZ |
171 | return false; |
172 | } | |
173 | ||
174 | static void release_pmc_hardware(void) | |
175 | { | |
176 | int i; | |
177 | ||
948b1bb8 | 178 | for (i = 0; i < x86_pmu.num_counters; i++) { |
41bf4989 RR |
179 | release_perfctr_nmi(x86_pmu_event_addr(i)); |
180 | release_evntsel_nmi(x86_pmu_config_addr(i)); | |
4e935e47 | 181 | } |
4e935e47 PZ |
182 | } |
183 | ||
b27ea29c RR |
184 | #else |
185 | ||
186 | static bool reserve_pmc_hardware(void) { return true; } | |
187 | static void release_pmc_hardware(void) {} | |
188 | ||
189 | #endif | |
190 | ||
33c6d6a7 DZ |
191 | static bool check_hw_exists(void) |
192 | { | |
a5ebe0ba GD |
193 | u64 val, val_fail, val_new= ~0; |
194 | int i, reg, reg_fail, ret = 0; | |
195 | int bios_fail = 0; | |
68ab7476 | 196 | int reg_safe = -1; |
33c6d6a7 | 197 | |
4407204c PZ |
198 | /* |
199 | * Check to see if the BIOS enabled any of the counters, if so | |
200 | * complain and bail. | |
201 | */ | |
202 | for (i = 0; i < x86_pmu.num_counters; i++) { | |
41bf4989 | 203 | reg = x86_pmu_config_addr(i); |
4407204c PZ |
204 | ret = rdmsrl_safe(reg, &val); |
205 | if (ret) | |
206 | goto msr_fail; | |
a5ebe0ba GD |
207 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { |
208 | bios_fail = 1; | |
209 | val_fail = val; | |
210 | reg_fail = reg; | |
68ab7476 DZ |
211 | } else { |
212 | reg_safe = i; | |
a5ebe0ba | 213 | } |
4407204c PZ |
214 | } |
215 | ||
216 | if (x86_pmu.num_counters_fixed) { | |
217 | reg = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; | |
218 | ret = rdmsrl_safe(reg, &val); | |
219 | if (ret) | |
220 | goto msr_fail; | |
221 | for (i = 0; i < x86_pmu.num_counters_fixed; i++) { | |
a5ebe0ba GD |
222 | if (val & (0x03 << i*4)) { |
223 | bios_fail = 1; | |
224 | val_fail = val; | |
225 | reg_fail = reg; | |
226 | } | |
4407204c PZ |
227 | } |
228 | } | |
229 | ||
68ab7476 DZ |
230 | /* |
231 | * If all the counters are enabled, the below test will always | |
232 | * fail. The tools will also become useless in this scenario. | |
233 | * Just fail and disable the hardware counters. | |
234 | */ | |
235 | ||
236 | if (reg_safe == -1) { | |
237 | reg = reg_safe; | |
238 | goto msr_fail; | |
239 | } | |
240 | ||
4407204c | 241 | /* |
bffd5fc2 AP |
242 | * Read the current value, change it and read it back to see if it |
243 | * matches, this is needed to detect certain hardware emulators | |
244 | * (qemu/kvm) that don't trap on the MSR access and always return 0s. | |
4407204c | 245 | */ |
68ab7476 | 246 | reg = x86_pmu_event_addr(reg_safe); |
bffd5fc2 AP |
247 | if (rdmsrl_safe(reg, &val)) |
248 | goto msr_fail; | |
249 | val ^= 0xffffUL; | |
f285f92f RR |
250 | ret = wrmsrl_safe(reg, val); |
251 | ret |= rdmsrl_safe(reg, &val_new); | |
33c6d6a7 | 252 | if (ret || val != val_new) |
4407204c | 253 | goto msr_fail; |
33c6d6a7 | 254 | |
45daae57 IM |
255 | /* |
256 | * We still allow the PMU driver to operate: | |
257 | */ | |
a5ebe0ba | 258 | if (bios_fail) { |
1b74dde7 CY |
259 | pr_cont("Broken BIOS detected, complain to your hardware vendor.\n"); |
260 | pr_err(FW_BUG "the BIOS has corrupted hw-PMU resources (MSR %x is %Lx)\n", | |
261 | reg_fail, val_fail); | |
a5ebe0ba | 262 | } |
45daae57 IM |
263 | |
264 | return true; | |
4407204c PZ |
265 | |
266 | msr_fail: | |
005bd007 JG |
267 | if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) { |
268 | pr_cont("PMU not available due to virtualization, using software events only.\n"); | |
269 | } else { | |
270 | pr_cont("Broken PMU hardware detected, using software events only.\n"); | |
271 | pr_err("Failed to access perfctr msr (MSR %x is %Lx)\n", | |
272 | reg, val_new); | |
273 | } | |
45daae57 | 274 | |
4407204c | 275 | return false; |
33c6d6a7 DZ |
276 | } |
277 | ||
cdd6c482 | 278 | static void hw_perf_event_destroy(struct perf_event *event) |
4e935e47 | 279 | { |
6b099d9b | 280 | x86_release_hardware(); |
1b7b938f | 281 | atomic_dec(&active_events); |
4e935e47 PZ |
282 | } |
283 | ||
48070342 AS |
284 | void hw_perf_lbr_event_destroy(struct perf_event *event) |
285 | { | |
286 | hw_perf_event_destroy(event); | |
287 | ||
288 | /* undo the lbr/bts event accounting */ | |
289 | x86_del_exclusive(x86_lbr_exclusive_lbr); | |
290 | } | |
291 | ||
85cf9dba RR |
292 | static inline int x86_pmu_initialized(void) |
293 | { | |
294 | return x86_pmu.handle_irq != NULL; | |
295 | } | |
296 | ||
8326f44d | 297 | static inline int |
e994d7d2 | 298 | set_ext_hw_attr(struct hw_perf_event *hwc, struct perf_event *event) |
8326f44d | 299 | { |
e994d7d2 | 300 | struct perf_event_attr *attr = &event->attr; |
8326f44d IM |
301 | unsigned int cache_type, cache_op, cache_result; |
302 | u64 config, val; | |
303 | ||
304 | config = attr->config; | |
305 | ||
306 | cache_type = (config >> 0) & 0xff; | |
307 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
308 | return -EINVAL; | |
309 | ||
310 | cache_op = (config >> 8) & 0xff; | |
311 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
312 | return -EINVAL; | |
313 | ||
314 | cache_result = (config >> 16) & 0xff; | |
315 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
316 | return -EINVAL; | |
317 | ||
318 | val = hw_cache_event_ids[cache_type][cache_op][cache_result]; | |
319 | ||
320 | if (val == 0) | |
321 | return -ENOENT; | |
322 | ||
323 | if (val == -1) | |
324 | return -EINVAL; | |
325 | ||
326 | hwc->config |= val; | |
e994d7d2 AK |
327 | attr->config1 = hw_cache_extra_regs[cache_type][cache_op][cache_result]; |
328 | return x86_pmu_extra_regs(val, event); | |
8326f44d IM |
329 | } |
330 | ||
6b099d9b AS |
331 | int x86_reserve_hardware(void) |
332 | { | |
333 | int err = 0; | |
334 | ||
1b7b938f | 335 | if (!atomic_inc_not_zero(&pmc_refcount)) { |
6b099d9b | 336 | mutex_lock(&pmc_reserve_mutex); |
1b7b938f | 337 | if (atomic_read(&pmc_refcount) == 0) { |
6b099d9b AS |
338 | if (!reserve_pmc_hardware()) |
339 | err = -EBUSY; | |
340 | else | |
341 | reserve_ds_buffers(); | |
342 | } | |
343 | if (!err) | |
1b7b938f | 344 | atomic_inc(&pmc_refcount); |
6b099d9b AS |
345 | mutex_unlock(&pmc_reserve_mutex); |
346 | } | |
347 | ||
348 | return err; | |
349 | } | |
350 | ||
351 | void x86_release_hardware(void) | |
352 | { | |
1b7b938f | 353 | if (atomic_dec_and_mutex_lock(&pmc_refcount, &pmc_reserve_mutex)) { |
6b099d9b AS |
354 | release_pmc_hardware(); |
355 | release_ds_buffers(); | |
356 | mutex_unlock(&pmc_reserve_mutex); | |
357 | } | |
358 | } | |
359 | ||
48070342 AS |
360 | /* |
361 | * Check if we can create event of a certain type (that no conflicting events | |
362 | * are present). | |
363 | */ | |
364 | int x86_add_exclusive(unsigned int what) | |
365 | { | |
93472aff | 366 | int i; |
48070342 | 367 | |
b0c1ef52 AK |
368 | /* |
369 | * When lbr_pt_coexist we allow PT to coexist with either LBR or BTS. | |
370 | * LBR and BTS are still mutually exclusive. | |
371 | */ | |
372 | if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) | |
ccbebba4 AS |
373 | return 0; |
374 | ||
93472aff PZ |
375 | if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { |
376 | mutex_lock(&pmc_reserve_mutex); | |
377 | for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { | |
378 | if (i != what && atomic_read(&x86_pmu.lbr_exclusive[i])) | |
379 | goto fail_unlock; | |
380 | } | |
381 | atomic_inc(&x86_pmu.lbr_exclusive[what]); | |
382 | mutex_unlock(&pmc_reserve_mutex); | |
6b099d9b | 383 | } |
48070342 | 384 | |
93472aff PZ |
385 | atomic_inc(&active_events); |
386 | return 0; | |
48070342 | 387 | |
93472aff | 388 | fail_unlock: |
48070342 | 389 | mutex_unlock(&pmc_reserve_mutex); |
93472aff | 390 | return -EBUSY; |
48070342 AS |
391 | } |
392 | ||
393 | void x86_del_exclusive(unsigned int what) | |
394 | { | |
b0c1ef52 | 395 | if (x86_pmu.lbr_pt_coexist && what == x86_lbr_exclusive_pt) |
ccbebba4 AS |
396 | return; |
397 | ||
48070342 | 398 | atomic_dec(&x86_pmu.lbr_exclusive[what]); |
1b7b938f | 399 | atomic_dec(&active_events); |
48070342 AS |
400 | } |
401 | ||
de0428a7 | 402 | int x86_setup_perfctr(struct perf_event *event) |
c1726f34 RR |
403 | { |
404 | struct perf_event_attr *attr = &event->attr; | |
405 | struct hw_perf_event *hwc = &event->hw; | |
406 | u64 config; | |
407 | ||
6c7e550f | 408 | if (!is_sampling_event(event)) { |
c1726f34 RR |
409 | hwc->sample_period = x86_pmu.max_period; |
410 | hwc->last_period = hwc->sample_period; | |
e7850595 | 411 | local64_set(&hwc->period_left, hwc->sample_period); |
c1726f34 RR |
412 | } |
413 | ||
414 | if (attr->type == PERF_TYPE_RAW) | |
ed13ec58 | 415 | return x86_pmu_extra_regs(event->attr.config, event); |
c1726f34 RR |
416 | |
417 | if (attr->type == PERF_TYPE_HW_CACHE) | |
e994d7d2 | 418 | return set_ext_hw_attr(hwc, event); |
c1726f34 RR |
419 | |
420 | if (attr->config >= x86_pmu.max_events) | |
421 | return -EINVAL; | |
422 | ||
423 | /* | |
424 | * The generic map: | |
425 | */ | |
426 | config = x86_pmu.event_map(attr->config); | |
427 | ||
428 | if (config == 0) | |
429 | return -ENOENT; | |
430 | ||
431 | if (config == -1LL) | |
432 | return -EINVAL; | |
433 | ||
434 | /* | |
435 | * Branch tracing: | |
436 | */ | |
18a073a3 PZ |
437 | if (attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS && |
438 | !attr->freq && hwc->sample_period == 1) { | |
c1726f34 | 439 | /* BTS is not supported by this architecture. */ |
6809b6ea | 440 | if (!x86_pmu.bts_active) |
c1726f34 RR |
441 | return -EOPNOTSUPP; |
442 | ||
443 | /* BTS is currently only allowed for user-mode. */ | |
444 | if (!attr->exclude_kernel) | |
445 | return -EOPNOTSUPP; | |
48070342 AS |
446 | |
447 | /* disallow bts if conflicting events are present */ | |
448 | if (x86_add_exclusive(x86_lbr_exclusive_lbr)) | |
449 | return -EBUSY; | |
450 | ||
451 | event->destroy = hw_perf_lbr_event_destroy; | |
c1726f34 RR |
452 | } |
453 | ||
454 | hwc->config |= config; | |
455 | ||
456 | return 0; | |
457 | } | |
4261e0e0 | 458 | |
ff3fb511 SE |
459 | /* |
460 | * check that branch_sample_type is compatible with | |
461 | * settings needed for precise_ip > 1 which implies | |
462 | * using the LBR to capture ALL taken branches at the | |
463 | * priv levels of the measurement | |
464 | */ | |
465 | static inline int precise_br_compat(struct perf_event *event) | |
466 | { | |
467 | u64 m = event->attr.branch_sample_type; | |
468 | u64 b = 0; | |
469 | ||
470 | /* must capture all branches */ | |
471 | if (!(m & PERF_SAMPLE_BRANCH_ANY)) | |
472 | return 0; | |
473 | ||
474 | m &= PERF_SAMPLE_BRANCH_KERNEL | PERF_SAMPLE_BRANCH_USER; | |
475 | ||
476 | if (!event->attr.exclude_user) | |
477 | b |= PERF_SAMPLE_BRANCH_USER; | |
478 | ||
479 | if (!event->attr.exclude_kernel) | |
480 | b |= PERF_SAMPLE_BRANCH_KERNEL; | |
481 | ||
482 | /* | |
483 | * ignore PERF_SAMPLE_BRANCH_HV, not supported on x86 | |
484 | */ | |
485 | ||
486 | return m == b; | |
487 | } | |
488 | ||
de0428a7 | 489 | int x86_pmu_hw_config(struct perf_event *event) |
a072738e | 490 | { |
ab608344 PZ |
491 | if (event->attr.precise_ip) { |
492 | int precise = 0; | |
493 | ||
494 | /* Support for constant skid */ | |
c93dc84c | 495 | if (x86_pmu.pebs_active && !x86_pmu.pebs_broken) { |
ab608344 PZ |
496 | precise++; |
497 | ||
5553be26 | 498 | /* Support for IP fixup */ |
03de874a | 499 | if (x86_pmu.lbr_nr || x86_pmu.intel_cap.pebs_format >= 2) |
5553be26 | 500 | precise++; |
72469764 AK |
501 | |
502 | if (x86_pmu.pebs_prec_dist) | |
503 | precise++; | |
5553be26 | 504 | } |
ab608344 PZ |
505 | |
506 | if (event->attr.precise_ip > precise) | |
507 | return -EOPNOTSUPP; | |
4b854900 YZ |
508 | } |
509 | /* | |
510 | * check that PEBS LBR correction does not conflict with | |
511 | * whatever the user is asking with attr->branch_sample_type | |
512 | */ | |
513 | if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format < 2) { | |
514 | u64 *br_type = &event->attr.branch_sample_type; | |
515 | ||
516 | if (has_branch_stack(event)) { | |
517 | if (!precise_br_compat(event)) | |
518 | return -EOPNOTSUPP; | |
519 | ||
520 | /* branch_sample_type is compatible */ | |
521 | ||
522 | } else { | |
523 | /* | |
524 | * user did not specify branch_sample_type | |
525 | * | |
526 | * For PEBS fixups, we capture all | |
527 | * the branches at the priv level of the | |
528 | * event. | |
529 | */ | |
530 | *br_type = PERF_SAMPLE_BRANCH_ANY; | |
531 | ||
532 | if (!event->attr.exclude_user) | |
533 | *br_type |= PERF_SAMPLE_BRANCH_USER; | |
534 | ||
535 | if (!event->attr.exclude_kernel) | |
536 | *br_type |= PERF_SAMPLE_BRANCH_KERNEL; | |
ff3fb511 | 537 | } |
ab608344 PZ |
538 | } |
539 | ||
e18bf526 YZ |
540 | if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) |
541 | event->attach_state |= PERF_ATTACH_TASK_DATA; | |
542 | ||
a072738e CG |
543 | /* |
544 | * Generate PMC IRQs: | |
545 | * (keep 'enabled' bit clear for now) | |
546 | */ | |
b4cdc5c2 | 547 | event->hw.config = ARCH_PERFMON_EVENTSEL_INT; |
a072738e CG |
548 | |
549 | /* | |
550 | * Count user and OS events unless requested not to | |
551 | */ | |
b4cdc5c2 PZ |
552 | if (!event->attr.exclude_user) |
553 | event->hw.config |= ARCH_PERFMON_EVENTSEL_USR; | |
554 | if (!event->attr.exclude_kernel) | |
555 | event->hw.config |= ARCH_PERFMON_EVENTSEL_OS; | |
a072738e | 556 | |
b4cdc5c2 PZ |
557 | if (event->attr.type == PERF_TYPE_RAW) |
558 | event->hw.config |= event->attr.config & X86_RAW_EVENT_MASK; | |
a072738e | 559 | |
294fe0f5 AK |
560 | if (event->attr.sample_period && x86_pmu.limit_period) { |
561 | if (x86_pmu.limit_period(event, event->attr.sample_period) > | |
562 | event->attr.sample_period) | |
563 | return -EINVAL; | |
564 | } | |
565 | ||
9d0fcba6 | 566 | return x86_setup_perfctr(event); |
a098f448 RR |
567 | } |
568 | ||
241771ef | 569 | /* |
0d48696f | 570 | * Setup the hardware configuration for a given attr_type |
241771ef | 571 | */ |
b0a873eb | 572 | static int __x86_pmu_event_init(struct perf_event *event) |
241771ef | 573 | { |
4e935e47 | 574 | int err; |
241771ef | 575 | |
85cf9dba RR |
576 | if (!x86_pmu_initialized()) |
577 | return -ENODEV; | |
241771ef | 578 | |
6b099d9b | 579 | err = x86_reserve_hardware(); |
4e935e47 PZ |
580 | if (err) |
581 | return err; | |
582 | ||
1b7b938f | 583 | atomic_inc(&active_events); |
cdd6c482 | 584 | event->destroy = hw_perf_event_destroy; |
a1792cda | 585 | |
4261e0e0 RR |
586 | event->hw.idx = -1; |
587 | event->hw.last_cpu = -1; | |
588 | event->hw.last_tag = ~0ULL; | |
b690081d | 589 | |
efc9f05d SE |
590 | /* mark unused */ |
591 | event->hw.extra_reg.idx = EXTRA_REG_NONE; | |
b36817e8 SE |
592 | event->hw.branch_reg.idx = EXTRA_REG_NONE; |
593 | ||
9d0fcba6 | 594 | return x86_pmu.hw_config(event); |
4261e0e0 RR |
595 | } |
596 | ||
de0428a7 | 597 | void x86_pmu_disable_all(void) |
f87ad35d | 598 | { |
89cbc767 | 599 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
9e35ad38 PZ |
600 | int idx; |
601 | ||
948b1bb8 | 602 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
b0f3f28e PZ |
603 | u64 val; |
604 | ||
43f6201a | 605 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 606 | continue; |
41bf4989 | 607 | rdmsrl(x86_pmu_config_addr(idx), val); |
bb1165d6 | 608 | if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) |
4295ee62 | 609 | continue; |
bb1165d6 | 610 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
41bf4989 | 611 | wrmsrl(x86_pmu_config_addr(idx), val); |
f87ad35d | 612 | } |
f87ad35d JSR |
613 | } |
614 | ||
c3d266c8 KL |
615 | /* |
616 | * There may be PMI landing after enabled=0. The PMI hitting could be before or | |
617 | * after disable_all. | |
618 | * | |
619 | * If PMI hits before disable_all, the PMU will be disabled in the NMI handler. | |
620 | * It will not be re-enabled in the NMI handler again, because enabled=0. After | |
621 | * handling the NMI, disable_all will be called, which will not change the | |
622 | * state either. If PMI hits after disable_all, the PMU is already disabled | |
623 | * before entering NMI handler. The NMI handler will not change the state | |
624 | * either. | |
625 | * | |
626 | * So either situation is harmless. | |
627 | */ | |
a4eaf7f1 | 628 | static void x86_pmu_disable(struct pmu *pmu) |
b56a3802 | 629 | { |
89cbc767 | 630 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 | 631 | |
85cf9dba | 632 | if (!x86_pmu_initialized()) |
9e35ad38 | 633 | return; |
1da53e02 | 634 | |
1a6e21f7 PZ |
635 | if (!cpuc->enabled) |
636 | return; | |
637 | ||
638 | cpuc->n_added = 0; | |
639 | cpuc->enabled = 0; | |
640 | barrier(); | |
1da53e02 SE |
641 | |
642 | x86_pmu.disable_all(); | |
b56a3802 | 643 | } |
241771ef | 644 | |
de0428a7 | 645 | void x86_pmu_enable_all(int added) |
f87ad35d | 646 | { |
89cbc767 | 647 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
f87ad35d JSR |
648 | int idx; |
649 | ||
948b1bb8 | 650 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
d45dd923 | 651 | struct hw_perf_event *hwc = &cpuc->events[idx]->hw; |
b0f3f28e | 652 | |
43f6201a | 653 | if (!test_bit(idx, cpuc->active_mask)) |
4295ee62 | 654 | continue; |
984b838c | 655 | |
d45dd923 | 656 | __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); |
f87ad35d JSR |
657 | } |
658 | } | |
659 | ||
51b0fe39 | 660 | static struct pmu pmu; |
1da53e02 SE |
661 | |
662 | static inline int is_x86_event(struct perf_event *event) | |
663 | { | |
664 | return event->pmu == &pmu; | |
665 | } | |
666 | ||
1e2ad28f RR |
667 | /* |
668 | * Event scheduler state: | |
669 | * | |
670 | * Assign events iterating over all events and counters, beginning | |
671 | * with events with least weights first. Keep the current iterator | |
672 | * state in struct sched_state. | |
673 | */ | |
674 | struct sched_state { | |
675 | int weight; | |
676 | int event; /* event index */ | |
677 | int counter; /* counter index */ | |
678 | int unassigned; /* number of events to be assigned left */ | |
cc1790cf | 679 | int nr_gp; /* number of GP counters used */ |
1e2ad28f RR |
680 | unsigned long used[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
681 | }; | |
682 | ||
bc1738f6 RR |
683 | /* Total max is X86_PMC_IDX_MAX, but we are O(n!) limited */ |
684 | #define SCHED_STATES_MAX 2 | |
685 | ||
1e2ad28f RR |
686 | struct perf_sched { |
687 | int max_weight; | |
688 | int max_events; | |
cc1790cf PZ |
689 | int max_gp; |
690 | int saved_states; | |
b371b594 | 691 | struct event_constraint **constraints; |
1e2ad28f | 692 | struct sched_state state; |
bc1738f6 | 693 | struct sched_state saved[SCHED_STATES_MAX]; |
1e2ad28f RR |
694 | }; |
695 | ||
696 | /* | |
697 | * Initialize interator that runs through all events and counters. | |
698 | */ | |
b371b594 | 699 | static void perf_sched_init(struct perf_sched *sched, struct event_constraint **constraints, |
cc1790cf | 700 | int num, int wmin, int wmax, int gpmax) |
1e2ad28f RR |
701 | { |
702 | int idx; | |
703 | ||
704 | memset(sched, 0, sizeof(*sched)); | |
705 | sched->max_events = num; | |
706 | sched->max_weight = wmax; | |
cc1790cf | 707 | sched->max_gp = gpmax; |
b371b594 | 708 | sched->constraints = constraints; |
1e2ad28f RR |
709 | |
710 | for (idx = 0; idx < num; idx++) { | |
b371b594 | 711 | if (constraints[idx]->weight == wmin) |
1e2ad28f RR |
712 | break; |
713 | } | |
714 | ||
715 | sched->state.event = idx; /* start with min weight */ | |
716 | sched->state.weight = wmin; | |
717 | sched->state.unassigned = num; | |
718 | } | |
719 | ||
bc1738f6 RR |
720 | static void perf_sched_save_state(struct perf_sched *sched) |
721 | { | |
722 | if (WARN_ON_ONCE(sched->saved_states >= SCHED_STATES_MAX)) | |
723 | return; | |
724 | ||
725 | sched->saved[sched->saved_states] = sched->state; | |
726 | sched->saved_states++; | |
727 | } | |
728 | ||
729 | static bool perf_sched_restore_state(struct perf_sched *sched) | |
730 | { | |
731 | if (!sched->saved_states) | |
732 | return false; | |
733 | ||
734 | sched->saved_states--; | |
735 | sched->state = sched->saved[sched->saved_states]; | |
736 | ||
737 | /* continue with next counter: */ | |
738 | clear_bit(sched->state.counter++, sched->state.used); | |
739 | ||
740 | return true; | |
741 | } | |
742 | ||
1e2ad28f RR |
743 | /* |
744 | * Select a counter for the current event to schedule. Return true on | |
745 | * success. | |
746 | */ | |
bc1738f6 | 747 | static bool __perf_sched_find_counter(struct perf_sched *sched) |
1e2ad28f RR |
748 | { |
749 | struct event_constraint *c; | |
750 | int idx; | |
751 | ||
752 | if (!sched->state.unassigned) | |
753 | return false; | |
754 | ||
755 | if (sched->state.event >= sched->max_events) | |
756 | return false; | |
757 | ||
b371b594 | 758 | c = sched->constraints[sched->state.event]; |
4defea85 | 759 | /* Prefer fixed purpose counters */ |
15c7ad51 RR |
760 | if (c->idxmsk64 & (~0ULL << INTEL_PMC_IDX_FIXED)) { |
761 | idx = INTEL_PMC_IDX_FIXED; | |
307b1cd7 | 762 | for_each_set_bit_from(idx, c->idxmsk, X86_PMC_IDX_MAX) { |
4defea85 PZ |
763 | if (!__test_and_set_bit(idx, sched->state.used)) |
764 | goto done; | |
765 | } | |
766 | } | |
cc1790cf | 767 | |
1e2ad28f RR |
768 | /* Grab the first unused counter starting with idx */ |
769 | idx = sched->state.counter; | |
15c7ad51 | 770 | for_each_set_bit_from(idx, c->idxmsk, INTEL_PMC_IDX_FIXED) { |
cc1790cf PZ |
771 | if (!__test_and_set_bit(idx, sched->state.used)) { |
772 | if (sched->state.nr_gp++ >= sched->max_gp) | |
773 | return false; | |
774 | ||
4defea85 | 775 | goto done; |
cc1790cf | 776 | } |
1e2ad28f | 777 | } |
1e2ad28f | 778 | |
4defea85 PZ |
779 | return false; |
780 | ||
781 | done: | |
782 | sched->state.counter = idx; | |
1e2ad28f | 783 | |
bc1738f6 RR |
784 | if (c->overlap) |
785 | perf_sched_save_state(sched); | |
786 | ||
787 | return true; | |
788 | } | |
789 | ||
790 | static bool perf_sched_find_counter(struct perf_sched *sched) | |
791 | { | |
792 | while (!__perf_sched_find_counter(sched)) { | |
793 | if (!perf_sched_restore_state(sched)) | |
794 | return false; | |
795 | } | |
796 | ||
1e2ad28f RR |
797 | return true; |
798 | } | |
799 | ||
800 | /* | |
801 | * Go through all unassigned events and find the next one to schedule. | |
802 | * Take events with the least weight first. Return true on success. | |
803 | */ | |
804 | static bool perf_sched_next_event(struct perf_sched *sched) | |
805 | { | |
806 | struct event_constraint *c; | |
807 | ||
808 | if (!sched->state.unassigned || !--sched->state.unassigned) | |
809 | return false; | |
810 | ||
811 | do { | |
812 | /* next event */ | |
813 | sched->state.event++; | |
814 | if (sched->state.event >= sched->max_events) { | |
815 | /* next weight */ | |
816 | sched->state.event = 0; | |
817 | sched->state.weight++; | |
818 | if (sched->state.weight > sched->max_weight) | |
819 | return false; | |
820 | } | |
b371b594 | 821 | c = sched->constraints[sched->state.event]; |
1e2ad28f RR |
822 | } while (c->weight != sched->state.weight); |
823 | ||
824 | sched->state.counter = 0; /* start with first counter */ | |
825 | ||
826 | return true; | |
827 | } | |
828 | ||
829 | /* | |
830 | * Assign a counter for each event. | |
831 | */ | |
b371b594 | 832 | int perf_assign_events(struct event_constraint **constraints, int n, |
cc1790cf | 833 | int wmin, int wmax, int gpmax, int *assign) |
1e2ad28f RR |
834 | { |
835 | struct perf_sched sched; | |
836 | ||
cc1790cf | 837 | perf_sched_init(&sched, constraints, n, wmin, wmax, gpmax); |
1e2ad28f RR |
838 | |
839 | do { | |
840 | if (!perf_sched_find_counter(&sched)) | |
841 | break; /* failed */ | |
842 | if (assign) | |
843 | assign[sched.state.event] = sched.state.counter; | |
844 | } while (perf_sched_next_event(&sched)); | |
845 | ||
846 | return sched.state.unassigned; | |
847 | } | |
4a3dc121 | 848 | EXPORT_SYMBOL_GPL(perf_assign_events); |
1e2ad28f | 849 | |
de0428a7 | 850 | int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign) |
1da53e02 | 851 | { |
43b45780 | 852 | struct event_constraint *c; |
1da53e02 | 853 | unsigned long used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)]; |
2f7f73a5 | 854 | struct perf_event *e; |
e979121b | 855 | int i, wmin, wmax, unsched = 0; |
1da53e02 SE |
856 | struct hw_perf_event *hwc; |
857 | ||
858 | bitmap_zero(used_mask, X86_PMC_IDX_MAX); | |
859 | ||
c5362c0c MD |
860 | if (x86_pmu.start_scheduling) |
861 | x86_pmu.start_scheduling(cpuc); | |
862 | ||
1e2ad28f | 863 | for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) { |
b371b594 | 864 | cpuc->event_constraint[i] = NULL; |
79cba822 | 865 | c = x86_pmu.get_event_constraints(cpuc, i, cpuc->event_list[i]); |
b371b594 | 866 | cpuc->event_constraint[i] = c; |
43b45780 | 867 | |
1e2ad28f RR |
868 | wmin = min(wmin, c->weight); |
869 | wmax = max(wmax, c->weight); | |
1da53e02 SE |
870 | } |
871 | ||
8113070d SE |
872 | /* |
873 | * fastpath, try to reuse previous register | |
874 | */ | |
c933c1a6 | 875 | for (i = 0; i < n; i++) { |
8113070d | 876 | hwc = &cpuc->event_list[i]->hw; |
b371b594 | 877 | c = cpuc->event_constraint[i]; |
8113070d SE |
878 | |
879 | /* never assigned */ | |
880 | if (hwc->idx == -1) | |
881 | break; | |
882 | ||
883 | /* constraint still honored */ | |
63b14649 | 884 | if (!test_bit(hwc->idx, c->idxmsk)) |
8113070d SE |
885 | break; |
886 | ||
887 | /* not already used */ | |
888 | if (test_bit(hwc->idx, used_mask)) | |
889 | break; | |
890 | ||
34538ee7 | 891 | __set_bit(hwc->idx, used_mask); |
8113070d SE |
892 | if (assign) |
893 | assign[i] = hwc->idx; | |
894 | } | |
8113070d | 895 | |
1e2ad28f | 896 | /* slow path */ |
b371b594 | 897 | if (i != n) { |
cc1790cf PZ |
898 | int gpmax = x86_pmu.num_counters; |
899 | ||
900 | /* | |
901 | * Do not allow scheduling of more than half the available | |
902 | * generic counters. | |
903 | * | |
904 | * This helps avoid counter starvation of sibling thread by | |
905 | * ensuring at most half the counters cannot be in exclusive | |
906 | * mode. There is no designated counters for the limits. Any | |
907 | * N/2 counters can be used. This helps with events with | |
908 | * specific counter constraints. | |
909 | */ | |
910 | if (is_ht_workaround_enabled() && !cpuc->is_fake && | |
911 | READ_ONCE(cpuc->excl_cntrs->exclusive_present)) | |
912 | gpmax /= 2; | |
913 | ||
b371b594 | 914 | unsched = perf_assign_events(cpuc->event_constraint, n, wmin, |
cc1790cf | 915 | wmax, gpmax, assign); |
b371b594 | 916 | } |
8113070d | 917 | |
2f7f73a5 | 918 | /* |
e979121b MD |
919 | * In case of success (unsched = 0), mark events as committed, |
920 | * so we do not put_constraint() in case new events are added | |
921 | * and fail to be scheduled | |
922 | * | |
923 | * We invoke the lower level commit callback to lock the resource | |
924 | * | |
925 | * We do not need to do all of this in case we are called to | |
926 | * validate an event group (assign == NULL) | |
2f7f73a5 | 927 | */ |
e979121b | 928 | if (!unsched && assign) { |
2f7f73a5 SE |
929 | for (i = 0; i < n; i++) { |
930 | e = cpuc->event_list[i]; | |
931 | e->hw.flags |= PERF_X86_EVENT_COMMITTED; | |
c5362c0c | 932 | if (x86_pmu.commit_scheduling) |
b371b594 | 933 | x86_pmu.commit_scheduling(cpuc, i, assign[i]); |
2f7f73a5 | 934 | } |
8736e548 | 935 | } else { |
1da53e02 | 936 | for (i = 0; i < n; i++) { |
2f7f73a5 SE |
937 | e = cpuc->event_list[i]; |
938 | /* | |
939 | * do not put_constraint() on comitted events, | |
940 | * because they are good to go | |
941 | */ | |
942 | if ((e->hw.flags & PERF_X86_EVENT_COMMITTED)) | |
943 | continue; | |
944 | ||
e979121b MD |
945 | /* |
946 | * release events that failed scheduling | |
947 | */ | |
1da53e02 | 948 | if (x86_pmu.put_event_constraints) |
2f7f73a5 | 949 | x86_pmu.put_event_constraints(cpuc, e); |
1da53e02 SE |
950 | } |
951 | } | |
c5362c0c MD |
952 | |
953 | if (x86_pmu.stop_scheduling) | |
954 | x86_pmu.stop_scheduling(cpuc); | |
955 | ||
e979121b | 956 | return unsched ? -EINVAL : 0; |
1da53e02 SE |
957 | } |
958 | ||
959 | /* | |
960 | * dogrp: true if must collect siblings events (group) | |
961 | * returns total number of events and error code | |
962 | */ | |
963 | static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp) | |
964 | { | |
965 | struct perf_event *event; | |
966 | int n, max_count; | |
967 | ||
948b1bb8 | 968 | max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed; |
1da53e02 SE |
969 | |
970 | /* current number of events already accepted */ | |
971 | n = cpuc->n_events; | |
972 | ||
973 | if (is_x86_event(leader)) { | |
974 | if (n >= max_count) | |
aa2bc1ad | 975 | return -EINVAL; |
1da53e02 SE |
976 | cpuc->event_list[n] = leader; |
977 | n++; | |
978 | } | |
979 | if (!dogrp) | |
980 | return n; | |
981 | ||
982 | list_for_each_entry(event, &leader->sibling_list, group_entry) { | |
983 | if (!is_x86_event(event) || | |
8113070d | 984 | event->state <= PERF_EVENT_STATE_OFF) |
1da53e02 SE |
985 | continue; |
986 | ||
987 | if (n >= max_count) | |
aa2bc1ad | 988 | return -EINVAL; |
1da53e02 SE |
989 | |
990 | cpuc->event_list[n] = event; | |
991 | n++; | |
992 | } | |
993 | return n; | |
994 | } | |
995 | ||
1da53e02 | 996 | static inline void x86_assign_hw_event(struct perf_event *event, |
447a194b | 997 | struct cpu_hw_events *cpuc, int i) |
1da53e02 | 998 | { |
447a194b SE |
999 | struct hw_perf_event *hwc = &event->hw; |
1000 | ||
1001 | hwc->idx = cpuc->assign[i]; | |
1002 | hwc->last_cpu = smp_processor_id(); | |
1003 | hwc->last_tag = ++cpuc->tags[i]; | |
1da53e02 | 1004 | |
15c7ad51 | 1005 | if (hwc->idx == INTEL_PMC_IDX_FIXED_BTS) { |
1da53e02 SE |
1006 | hwc->config_base = 0; |
1007 | hwc->event_base = 0; | |
15c7ad51 | 1008 | } else if (hwc->idx >= INTEL_PMC_IDX_FIXED) { |
1da53e02 | 1009 | hwc->config_base = MSR_ARCH_PERFMON_FIXED_CTR_CTRL; |
15c7ad51 RR |
1010 | hwc->event_base = MSR_ARCH_PERFMON_FIXED_CTR0 + (hwc->idx - INTEL_PMC_IDX_FIXED); |
1011 | hwc->event_base_rdpmc = (hwc->idx - INTEL_PMC_IDX_FIXED) | 1<<30; | |
1da53e02 | 1012 | } else { |
73d6e522 RR |
1013 | hwc->config_base = x86_pmu_config_addr(hwc->idx); |
1014 | hwc->event_base = x86_pmu_event_addr(hwc->idx); | |
0fbdad07 | 1015 | hwc->event_base_rdpmc = x86_pmu_rdpmc_index(hwc->idx); |
1da53e02 SE |
1016 | } |
1017 | } | |
1018 | ||
447a194b SE |
1019 | static inline int match_prev_assignment(struct hw_perf_event *hwc, |
1020 | struct cpu_hw_events *cpuc, | |
1021 | int i) | |
1022 | { | |
1023 | return hwc->idx == cpuc->assign[i] && | |
1024 | hwc->last_cpu == smp_processor_id() && | |
1025 | hwc->last_tag == cpuc->tags[i]; | |
1026 | } | |
1027 | ||
a4eaf7f1 | 1028 | static void x86_pmu_start(struct perf_event *event, int flags); |
2e841873 | 1029 | |
a4eaf7f1 | 1030 | static void x86_pmu_enable(struct pmu *pmu) |
ee06094f | 1031 | { |
89cbc767 | 1032 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1033 | struct perf_event *event; |
1034 | struct hw_perf_event *hwc; | |
11164cd4 | 1035 | int i, added = cpuc->n_added; |
1da53e02 | 1036 | |
85cf9dba | 1037 | if (!x86_pmu_initialized()) |
2b9ff0db | 1038 | return; |
1a6e21f7 PZ |
1039 | |
1040 | if (cpuc->enabled) | |
1041 | return; | |
1042 | ||
1da53e02 | 1043 | if (cpuc->n_added) { |
19925ce7 | 1044 | int n_running = cpuc->n_events - cpuc->n_added; |
1da53e02 SE |
1045 | /* |
1046 | * apply assignment obtained either from | |
1047 | * hw_perf_group_sched_in() or x86_pmu_enable() | |
1048 | * | |
1049 | * step1: save events moving to new counters | |
1da53e02 | 1050 | */ |
19925ce7 | 1051 | for (i = 0; i < n_running; i++) { |
1da53e02 SE |
1052 | event = cpuc->event_list[i]; |
1053 | hwc = &event->hw; | |
1054 | ||
447a194b SE |
1055 | /* |
1056 | * we can avoid reprogramming counter if: | |
1057 | * - assigned same counter as last time | |
1058 | * - running on same CPU as last time | |
1059 | * - no other event has used the counter since | |
1060 | */ | |
1061 | if (hwc->idx == -1 || | |
1062 | match_prev_assignment(hwc, cpuc, i)) | |
1da53e02 SE |
1063 | continue; |
1064 | ||
a4eaf7f1 PZ |
1065 | /* |
1066 | * Ensure we don't accidentally enable a stopped | |
1067 | * counter simply because we rescheduled. | |
1068 | */ | |
1069 | if (hwc->state & PERF_HES_STOPPED) | |
1070 | hwc->state |= PERF_HES_ARCH; | |
1071 | ||
1072 | x86_pmu_stop(event, PERF_EF_UPDATE); | |
1da53e02 SE |
1073 | } |
1074 | ||
c347a2f1 PZ |
1075 | /* |
1076 | * step2: reprogram moved events into new counters | |
1077 | */ | |
1da53e02 | 1078 | for (i = 0; i < cpuc->n_events; i++) { |
1da53e02 SE |
1079 | event = cpuc->event_list[i]; |
1080 | hwc = &event->hw; | |
1081 | ||
45e16a68 | 1082 | if (!match_prev_assignment(hwc, cpuc, i)) |
447a194b | 1083 | x86_assign_hw_event(event, cpuc, i); |
45e16a68 PZ |
1084 | else if (i < n_running) |
1085 | continue; | |
1da53e02 | 1086 | |
a4eaf7f1 PZ |
1087 | if (hwc->state & PERF_HES_ARCH) |
1088 | continue; | |
1089 | ||
1090 | x86_pmu_start(event, PERF_EF_RELOAD); | |
1da53e02 SE |
1091 | } |
1092 | cpuc->n_added = 0; | |
1093 | perf_events_lapic_init(); | |
1094 | } | |
1a6e21f7 PZ |
1095 | |
1096 | cpuc->enabled = 1; | |
1097 | barrier(); | |
1098 | ||
11164cd4 | 1099 | x86_pmu.enable_all(added); |
ee06094f | 1100 | } |
ee06094f | 1101 | |
245b2e70 | 1102 | static DEFINE_PER_CPU(u64 [X86_PMC_IDX_MAX], pmc_prev_left); |
241771ef | 1103 | |
ee06094f IM |
1104 | /* |
1105 | * Set the next IRQ period, based on the hwc->period_left value. | |
cdd6c482 | 1106 | * To be called with the event disabled in hw: |
ee06094f | 1107 | */ |
de0428a7 | 1108 | int x86_perf_event_set_period(struct perf_event *event) |
241771ef | 1109 | { |
07088edb | 1110 | struct hw_perf_event *hwc = &event->hw; |
e7850595 | 1111 | s64 left = local64_read(&hwc->period_left); |
e4abb5d4 | 1112 | s64 period = hwc->sample_period; |
7645a24c | 1113 | int ret = 0, idx = hwc->idx; |
ee06094f | 1114 | |
15c7ad51 | 1115 | if (idx == INTEL_PMC_IDX_FIXED_BTS) |
30dd568c MM |
1116 | return 0; |
1117 | ||
ee06094f | 1118 | /* |
af901ca1 | 1119 | * If we are way outside a reasonable range then just skip forward: |
ee06094f IM |
1120 | */ |
1121 | if (unlikely(left <= -period)) { | |
1122 | left = period; | |
e7850595 | 1123 | local64_set(&hwc->period_left, left); |
9e350de3 | 1124 | hwc->last_period = period; |
e4abb5d4 | 1125 | ret = 1; |
ee06094f IM |
1126 | } |
1127 | ||
1128 | if (unlikely(left <= 0)) { | |
1129 | left += period; | |
e7850595 | 1130 | local64_set(&hwc->period_left, left); |
9e350de3 | 1131 | hwc->last_period = period; |
e4abb5d4 | 1132 | ret = 1; |
ee06094f | 1133 | } |
1c80f4b5 | 1134 | /* |
dfc65094 | 1135 | * Quirk: certain CPUs dont like it if just 1 hw_event is left: |
1c80f4b5 IM |
1136 | */ |
1137 | if (unlikely(left < 2)) | |
1138 | left = 2; | |
241771ef | 1139 | |
e4abb5d4 PZ |
1140 | if (left > x86_pmu.max_period) |
1141 | left = x86_pmu.max_period; | |
1142 | ||
294fe0f5 AK |
1143 | if (x86_pmu.limit_period) |
1144 | left = x86_pmu.limit_period(event, left); | |
1145 | ||
245b2e70 | 1146 | per_cpu(pmc_prev_left[idx], smp_processor_id()) = left; |
ee06094f | 1147 | |
851559e3 YZ |
1148 | if (!(hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) || |
1149 | local64_read(&hwc->prev_count) != (u64)-left) { | |
1150 | /* | |
1151 | * The hw event starts counting from this event offset, | |
1152 | * mark it to be able to extra future deltas: | |
1153 | */ | |
1154 | local64_set(&hwc->prev_count, (u64)-left); | |
ee06094f | 1155 | |
851559e3 YZ |
1156 | wrmsrl(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); |
1157 | } | |
68aa00ac CG |
1158 | |
1159 | /* | |
1160 | * Due to erratum on certan cpu we need | |
1161 | * a second write to be sure the register | |
1162 | * is updated properly | |
1163 | */ | |
1164 | if (x86_pmu.perfctr_second_write) { | |
73d6e522 | 1165 | wrmsrl(hwc->event_base, |
948b1bb8 | 1166 | (u64)(-left) & x86_pmu.cntval_mask); |
68aa00ac | 1167 | } |
e4abb5d4 | 1168 | |
cdd6c482 | 1169 | perf_event_update_userpage(event); |
194002b2 | 1170 | |
e4abb5d4 | 1171 | return ret; |
2f18d1e8 IM |
1172 | } |
1173 | ||
de0428a7 | 1174 | void x86_pmu_enable_event(struct perf_event *event) |
7c90cc45 | 1175 | { |
0a3aee0d | 1176 | if (__this_cpu_read(cpu_hw_events.enabled)) |
31fa58af RR |
1177 | __x86_pmu_enable_event(&event->hw, |
1178 | ARCH_PERFMON_EVENTSEL_ENABLE); | |
241771ef IM |
1179 | } |
1180 | ||
b690081d | 1181 | /* |
a4eaf7f1 | 1182 | * Add a single event to the PMU. |
1da53e02 SE |
1183 | * |
1184 | * The event is added to the group of enabled events | |
1185 | * but only if it can be scehduled with existing events. | |
fe9081cc | 1186 | */ |
a4eaf7f1 | 1187 | static int x86_pmu_add(struct perf_event *event, int flags) |
fe9081cc | 1188 | { |
89cbc767 | 1189 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1da53e02 SE |
1190 | struct hw_perf_event *hwc; |
1191 | int assign[X86_PMC_IDX_MAX]; | |
1192 | int n, n0, ret; | |
fe9081cc | 1193 | |
1da53e02 | 1194 | hwc = &event->hw; |
fe9081cc | 1195 | |
1da53e02 | 1196 | n0 = cpuc->n_events; |
24cd7f54 PZ |
1197 | ret = n = collect_events(cpuc, event, false); |
1198 | if (ret < 0) | |
1199 | goto out; | |
53b441a5 | 1200 | |
a4eaf7f1 PZ |
1201 | hwc->state = PERF_HES_UPTODATE | PERF_HES_STOPPED; |
1202 | if (!(flags & PERF_EF_START)) | |
1203 | hwc->state |= PERF_HES_ARCH; | |
1204 | ||
4d1c52b0 LM |
1205 | /* |
1206 | * If group events scheduling transaction was started, | |
0d2eb44f | 1207 | * skip the schedulability test here, it will be performed |
c347a2f1 | 1208 | * at commit time (->commit_txn) as a whole. |
68f7082f PZ |
1209 | * |
1210 | * If commit fails, we'll call ->del() on all events | |
1211 | * for which ->add() was called. | |
4d1c52b0 | 1212 | */ |
8f3e5684 | 1213 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
24cd7f54 | 1214 | goto done_collect; |
4d1c52b0 | 1215 | |
a072738e | 1216 | ret = x86_pmu.schedule_events(cpuc, n, assign); |
1da53e02 | 1217 | if (ret) |
24cd7f54 | 1218 | goto out; |
1da53e02 SE |
1219 | /* |
1220 | * copy new assignment, now we know it is possible | |
1221 | * will be used by hw_perf_enable() | |
1222 | */ | |
1223 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
7e2ae347 | 1224 | |
24cd7f54 | 1225 | done_collect: |
c347a2f1 PZ |
1226 | /* |
1227 | * Commit the collect_events() state. See x86_pmu_del() and | |
1228 | * x86_pmu_*_txn(). | |
1229 | */ | |
1da53e02 | 1230 | cpuc->n_events = n; |
356e1f2e | 1231 | cpuc->n_added += n - n0; |
90151c35 | 1232 | cpuc->n_txn += n - n0; |
95cdd2e7 | 1233 | |
68f7082f PZ |
1234 | if (x86_pmu.add) { |
1235 | /* | |
1236 | * This is before x86_pmu_enable() will call x86_pmu_start(), | |
1237 | * so we enable LBRs before an event needs them etc.. | |
1238 | */ | |
1239 | x86_pmu.add(event); | |
1240 | } | |
1241 | ||
24cd7f54 PZ |
1242 | ret = 0; |
1243 | out: | |
24cd7f54 | 1244 | return ret; |
241771ef IM |
1245 | } |
1246 | ||
a4eaf7f1 | 1247 | static void x86_pmu_start(struct perf_event *event, int flags) |
d76a0812 | 1248 | { |
89cbc767 | 1249 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
c08053e6 PZ |
1250 | int idx = event->hw.idx; |
1251 | ||
a4eaf7f1 PZ |
1252 | if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED))) |
1253 | return; | |
1254 | ||
1255 | if (WARN_ON_ONCE(idx == -1)) | |
1256 | return; | |
1257 | ||
1258 | if (flags & PERF_EF_RELOAD) { | |
1259 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
1260 | x86_perf_event_set_period(event); | |
1261 | } | |
1262 | ||
1263 | event->hw.state = 0; | |
d76a0812 | 1264 | |
c08053e6 PZ |
1265 | cpuc->events[idx] = event; |
1266 | __set_bit(idx, cpuc->active_mask); | |
63e6be6d | 1267 | __set_bit(idx, cpuc->running); |
aff3d91a | 1268 | x86_pmu.enable(event); |
c08053e6 | 1269 | perf_event_update_userpage(event); |
a78ac325 PZ |
1270 | } |
1271 | ||
cdd6c482 | 1272 | void perf_event_print_debug(void) |
241771ef | 1273 | { |
2f18d1e8 | 1274 | u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed; |
da3e606d | 1275 | u64 pebs, debugctl; |
cdd6c482 | 1276 | struct cpu_hw_events *cpuc; |
5bb9efe3 | 1277 | unsigned long flags; |
1e125676 IM |
1278 | int cpu, idx; |
1279 | ||
948b1bb8 | 1280 | if (!x86_pmu.num_counters) |
1e125676 | 1281 | return; |
241771ef | 1282 | |
5bb9efe3 | 1283 | local_irq_save(flags); |
241771ef IM |
1284 | |
1285 | cpu = smp_processor_id(); | |
cdd6c482 | 1286 | cpuc = &per_cpu(cpu_hw_events, cpu); |
241771ef | 1287 | |
faa28ae0 | 1288 | if (x86_pmu.version >= 2) { |
a1ef58f4 JSR |
1289 | rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); |
1290 | rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status); | |
1291 | rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); | |
1292 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); | |
1293 | ||
1294 | pr_info("\n"); | |
1295 | pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); | |
1296 | pr_info("CPU#%d: status: %016llx\n", cpu, status); | |
1297 | pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); | |
1298 | pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); | |
15fde110 AK |
1299 | if (x86_pmu.pebs_constraints) { |
1300 | rdmsrl(MSR_IA32_PEBS_ENABLE, pebs); | |
1301 | pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); | |
1302 | } | |
da3e606d AK |
1303 | if (x86_pmu.lbr_nr) { |
1304 | rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); | |
1305 | pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); | |
1306 | } | |
f87ad35d | 1307 | } |
7645a24c | 1308 | pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); |
241771ef | 1309 | |
948b1bb8 | 1310 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
41bf4989 RR |
1311 | rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl); |
1312 | rdmsrl(x86_pmu_event_addr(idx), pmc_count); | |
241771ef | 1313 | |
245b2e70 | 1314 | prev_left = per_cpu(pmc_prev_left[idx], cpu); |
241771ef | 1315 | |
a1ef58f4 | 1316 | pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n", |
241771ef | 1317 | cpu, idx, pmc_ctrl); |
a1ef58f4 | 1318 | pr_info("CPU#%d: gen-PMC%d count: %016llx\n", |
241771ef | 1319 | cpu, idx, pmc_count); |
a1ef58f4 | 1320 | pr_info("CPU#%d: gen-PMC%d left: %016llx\n", |
ee06094f | 1321 | cpu, idx, prev_left); |
241771ef | 1322 | } |
948b1bb8 | 1323 | for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) { |
2f18d1e8 IM |
1324 | rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count); |
1325 | ||
a1ef58f4 | 1326 | pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", |
2f18d1e8 IM |
1327 | cpu, idx, pmc_count); |
1328 | } | |
5bb9efe3 | 1329 | local_irq_restore(flags); |
241771ef IM |
1330 | } |
1331 | ||
de0428a7 | 1332 | void x86_pmu_stop(struct perf_event *event, int flags) |
241771ef | 1333 | { |
89cbc767 | 1334 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
cdd6c482 | 1335 | struct hw_perf_event *hwc = &event->hw; |
241771ef | 1336 | |
a4eaf7f1 PZ |
1337 | if (__test_and_clear_bit(hwc->idx, cpuc->active_mask)) { |
1338 | x86_pmu.disable(event); | |
1339 | cpuc->events[hwc->idx] = NULL; | |
1340 | WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED); | |
1341 | hwc->state |= PERF_HES_STOPPED; | |
1342 | } | |
30dd568c | 1343 | |
a4eaf7f1 PZ |
1344 | if ((flags & PERF_EF_UPDATE) && !(hwc->state & PERF_HES_UPTODATE)) { |
1345 | /* | |
1346 | * Drain the remaining delta count out of a event | |
1347 | * that we are disabling: | |
1348 | */ | |
1349 | x86_perf_event_update(event); | |
1350 | hwc->state |= PERF_HES_UPTODATE; | |
1351 | } | |
2e841873 PZ |
1352 | } |
1353 | ||
a4eaf7f1 | 1354 | static void x86_pmu_del(struct perf_event *event, int flags) |
2e841873 | 1355 | { |
89cbc767 | 1356 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
2e841873 PZ |
1357 | int i; |
1358 | ||
2f7f73a5 SE |
1359 | /* |
1360 | * event is descheduled | |
1361 | */ | |
1362 | event->hw.flags &= ~PERF_X86_EVENT_COMMITTED; | |
1363 | ||
90151c35 | 1364 | /* |
68f7082f | 1365 | * If we're called during a txn, we only need to undo x86_pmu.add. |
90151c35 SE |
1366 | * The events never got scheduled and ->cancel_txn will truncate |
1367 | * the event_list. | |
c347a2f1 PZ |
1368 | * |
1369 | * XXX assumes any ->del() called during a TXN will only be on | |
1370 | * an event added during that same TXN. | |
90151c35 | 1371 | */ |
8f3e5684 | 1372 | if (cpuc->txn_flags & PERF_PMU_TXN_ADD) |
68f7082f | 1373 | goto do_del; |
90151c35 | 1374 | |
c347a2f1 PZ |
1375 | /* |
1376 | * Not a TXN, therefore cleanup properly. | |
1377 | */ | |
a4eaf7f1 | 1378 | x86_pmu_stop(event, PERF_EF_UPDATE); |
194002b2 | 1379 | |
1da53e02 | 1380 | for (i = 0; i < cpuc->n_events; i++) { |
c347a2f1 PZ |
1381 | if (event == cpuc->event_list[i]) |
1382 | break; | |
1383 | } | |
1da53e02 | 1384 | |
c347a2f1 PZ |
1385 | if (WARN_ON_ONCE(i == cpuc->n_events)) /* called ->del() without ->add() ? */ |
1386 | return; | |
26e61e89 | 1387 | |
c347a2f1 PZ |
1388 | /* If we have a newly added event; make sure to decrease n_added. */ |
1389 | if (i >= cpuc->n_events - cpuc->n_added) | |
1390 | --cpuc->n_added; | |
1da53e02 | 1391 | |
c347a2f1 PZ |
1392 | if (x86_pmu.put_event_constraints) |
1393 | x86_pmu.put_event_constraints(cpuc, event); | |
1394 | ||
1395 | /* Delete the array entry. */ | |
b371b594 | 1396 | while (++i < cpuc->n_events) { |
c347a2f1 | 1397 | cpuc->event_list[i-1] = cpuc->event_list[i]; |
b371b594 PZ |
1398 | cpuc->event_constraint[i-1] = cpuc->event_constraint[i]; |
1399 | } | |
c347a2f1 | 1400 | --cpuc->n_events; |
1da53e02 | 1401 | |
cdd6c482 | 1402 | perf_event_update_userpage(event); |
68f7082f PZ |
1403 | |
1404 | do_del: | |
1405 | if (x86_pmu.del) { | |
1406 | /* | |
1407 | * This is after x86_pmu_stop(); so we disable LBRs after any | |
1408 | * event can need them etc.. | |
1409 | */ | |
1410 | x86_pmu.del(event); | |
1411 | } | |
241771ef IM |
1412 | } |
1413 | ||
de0428a7 | 1414 | int x86_pmu_handle_irq(struct pt_regs *regs) |
a29aa8a7 | 1415 | { |
df1a132b | 1416 | struct perf_sample_data data; |
cdd6c482 IM |
1417 | struct cpu_hw_events *cpuc; |
1418 | struct perf_event *event; | |
11d1578f | 1419 | int idx, handled = 0; |
9029a5e3 IM |
1420 | u64 val; |
1421 | ||
89cbc767 | 1422 | cpuc = this_cpu_ptr(&cpu_hw_events); |
962bf7a6 | 1423 | |
2bce5dac DZ |
1424 | /* |
1425 | * Some chipsets need to unmask the LVTPC in a particular spot | |
1426 | * inside the nmi handler. As a result, the unmasking was pushed | |
1427 | * into all the nmi handlers. | |
1428 | * | |
1429 | * This generic handler doesn't seem to have any issues where the | |
1430 | * unmasking occurs so it was left at the top. | |
1431 | */ | |
1432 | apic_write(APIC_LVTPC, APIC_DM_NMI); | |
1433 | ||
948b1bb8 | 1434 | for (idx = 0; idx < x86_pmu.num_counters; idx++) { |
63e6be6d RR |
1435 | if (!test_bit(idx, cpuc->active_mask)) { |
1436 | /* | |
1437 | * Though we deactivated the counter some cpus | |
1438 | * might still deliver spurious interrupts still | |
1439 | * in flight. Catch them: | |
1440 | */ | |
1441 | if (__test_and_clear_bit(idx, cpuc->running)) | |
1442 | handled++; | |
a29aa8a7 | 1443 | continue; |
63e6be6d | 1444 | } |
962bf7a6 | 1445 | |
cdd6c482 | 1446 | event = cpuc->events[idx]; |
a4016a79 | 1447 | |
cc2ad4ba | 1448 | val = x86_perf_event_update(event); |
948b1bb8 | 1449 | if (val & (1ULL << (x86_pmu.cntval_bits - 1))) |
48e22d56 | 1450 | continue; |
962bf7a6 | 1451 | |
9e350de3 | 1452 | /* |
cdd6c482 | 1453 | * event overflow |
9e350de3 | 1454 | */ |
4177c42a | 1455 | handled++; |
fd0d000b | 1456 | perf_sample_data_init(&data, 0, event->hw.last_period); |
9e350de3 | 1457 | |
07088edb | 1458 | if (!x86_perf_event_set_period(event)) |
e4abb5d4 PZ |
1459 | continue; |
1460 | ||
a8b0ca17 | 1461 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1462 | x86_pmu_stop(event, 0); |
a29aa8a7 | 1463 | } |
962bf7a6 | 1464 | |
9e350de3 PZ |
1465 | if (handled) |
1466 | inc_irq_stat(apic_perf_irqs); | |
1467 | ||
a29aa8a7 RR |
1468 | return handled; |
1469 | } | |
39d81eab | 1470 | |
cdd6c482 | 1471 | void perf_events_lapic_init(void) |
241771ef | 1472 | { |
04da8a43 | 1473 | if (!x86_pmu.apic || !x86_pmu_initialized()) |
241771ef | 1474 | return; |
85cf9dba | 1475 | |
241771ef | 1476 | /* |
c323d95f | 1477 | * Always use NMI for PMU |
241771ef | 1478 | */ |
c323d95f | 1479 | apic_write(APIC_LVTPC, APIC_DM_NMI); |
241771ef IM |
1480 | } |
1481 | ||
9326638c | 1482 | static int |
9c48f1c6 | 1483 | perf_event_nmi_handler(unsigned int cmd, struct pt_regs *regs) |
241771ef | 1484 | { |
14c63f17 DH |
1485 | u64 start_clock; |
1486 | u64 finish_clock; | |
e8a923cc | 1487 | int ret; |
14c63f17 | 1488 | |
1b7b938f AS |
1489 | /* |
1490 | * All PMUs/events that share this PMI handler should make sure to | |
1491 | * increment active_events for their events. | |
1492 | */ | |
cdd6c482 | 1493 | if (!atomic_read(&active_events)) |
9c48f1c6 | 1494 | return NMI_DONE; |
4177c42a | 1495 | |
e8a923cc | 1496 | start_clock = sched_clock(); |
14c63f17 | 1497 | ret = x86_pmu.handle_irq(regs); |
e8a923cc | 1498 | finish_clock = sched_clock(); |
14c63f17 DH |
1499 | |
1500 | perf_sample_event_took(finish_clock - start_clock); | |
1501 | ||
1502 | return ret; | |
241771ef | 1503 | } |
9326638c | 1504 | NOKPROBE_SYMBOL(perf_event_nmi_handler); |
241771ef | 1505 | |
de0428a7 KW |
1506 | struct event_constraint emptyconstraint; |
1507 | struct event_constraint unconstrained; | |
f87ad35d | 1508 | |
95ca792c | 1509 | static int x86_pmu_prepare_cpu(unsigned int cpu) |
3f6da390 | 1510 | { |
7fdba1ca | 1511 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); |
95ca792c | 1512 | int i; |
3f6da390 | 1513 | |
95ca792c TG |
1514 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) |
1515 | cpuc->kfree_on_online[i] = NULL; | |
1516 | if (x86_pmu.cpu_prepare) | |
1517 | return x86_pmu.cpu_prepare(cpu); | |
1518 | return 0; | |
1519 | } | |
7fdba1ca | 1520 | |
95ca792c TG |
1521 | static int x86_pmu_dead_cpu(unsigned int cpu) |
1522 | { | |
1523 | if (x86_pmu.cpu_dead) | |
1524 | x86_pmu.cpu_dead(cpu); | |
1525 | return 0; | |
1526 | } | |
3f6da390 | 1527 | |
95ca792c TG |
1528 | static int x86_pmu_online_cpu(unsigned int cpu) |
1529 | { | |
1530 | struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu); | |
1531 | int i; | |
3f6da390 | 1532 | |
95ca792c TG |
1533 | for (i = 0 ; i < X86_PERF_KFREE_MAX; i++) { |
1534 | kfree(cpuc->kfree_on_online[i]); | |
1535 | cpuc->kfree_on_online[i] = NULL; | |
3f6da390 | 1536 | } |
95ca792c TG |
1537 | return 0; |
1538 | } | |
3f6da390 | 1539 | |
95ca792c TG |
1540 | static int x86_pmu_starting_cpu(unsigned int cpu) |
1541 | { | |
1542 | if (x86_pmu.cpu_starting) | |
1543 | x86_pmu.cpu_starting(cpu); | |
1544 | return 0; | |
1545 | } | |
1546 | ||
1547 | static int x86_pmu_dying_cpu(unsigned int cpu) | |
1548 | { | |
1549 | if (x86_pmu.cpu_dying) | |
1550 | x86_pmu.cpu_dying(cpu); | |
1551 | return 0; | |
3f6da390 PZ |
1552 | } |
1553 | ||
12558038 CG |
1554 | static void __init pmu_check_apic(void) |
1555 | { | |
93984fbd | 1556 | if (boot_cpu_has(X86_FEATURE_APIC)) |
12558038 CG |
1557 | return; |
1558 | ||
1559 | x86_pmu.apic = 0; | |
1560 | pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n"); | |
1561 | pr_info("no hardware sampling interrupt available.\n"); | |
c184c980 VW |
1562 | |
1563 | /* | |
1564 | * If we have a PMU initialized but no APIC | |
1565 | * interrupts, we cannot sample hardware | |
1566 | * events (user-space has to fall back and | |
1567 | * sample via a hrtimer based software event): | |
1568 | */ | |
1569 | pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; | |
1570 | ||
12558038 CG |
1571 | } |
1572 | ||
641cc938 JO |
1573 | static struct attribute_group x86_pmu_format_group = { |
1574 | .name = "format", | |
1575 | .attrs = NULL, | |
1576 | }; | |
1577 | ||
8300daa2 JO |
1578 | /* |
1579 | * Remove all undefined events (x86_pmu.event_map(id) == 0) | |
1580 | * out of events_attr attributes. | |
1581 | */ | |
1582 | static void __init filter_events(struct attribute **attrs) | |
1583 | { | |
3a54aaa0 SE |
1584 | struct device_attribute *d; |
1585 | struct perf_pmu_events_attr *pmu_attr; | |
61b87cae | 1586 | int offset = 0; |
8300daa2 JO |
1587 | int i, j; |
1588 | ||
1589 | for (i = 0; attrs[i]; i++) { | |
3a54aaa0 SE |
1590 | d = (struct device_attribute *)attrs[i]; |
1591 | pmu_attr = container_of(d, struct perf_pmu_events_attr, attr); | |
1592 | /* str trumps id */ | |
1593 | if (pmu_attr->event_str) | |
1594 | continue; | |
61b87cae | 1595 | if (x86_pmu.event_map(i + offset)) |
8300daa2 JO |
1596 | continue; |
1597 | ||
1598 | for (j = i; attrs[j]; j++) | |
1599 | attrs[j] = attrs[j + 1]; | |
1600 | ||
1601 | /* Check the shifted attr. */ | |
1602 | i--; | |
61b87cae SE |
1603 | |
1604 | /* | |
1605 | * event_map() is index based, the attrs array is organized | |
1606 | * by increasing event index. If we shift the events, then | |
1607 | * we need to compensate for the event_map(), otherwise | |
1608 | * we are looking up the wrong event in the map | |
1609 | */ | |
1610 | offset++; | |
8300daa2 JO |
1611 | } |
1612 | } | |
1613 | ||
1a6461b1 | 1614 | /* Merge two pointer arrays */ |
47732d88 | 1615 | __init struct attribute **merge_attr(struct attribute **a, struct attribute **b) |
1a6461b1 AK |
1616 | { |
1617 | struct attribute **new; | |
1618 | int j, i; | |
1619 | ||
1620 | for (j = 0; a[j]; j++) | |
1621 | ; | |
1622 | for (i = 0; b[i]; i++) | |
1623 | j++; | |
1624 | j++; | |
1625 | ||
1626 | new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); | |
1627 | if (!new) | |
1628 | return NULL; | |
1629 | ||
1630 | j = 0; | |
1631 | for (i = 0; a[i]; i++) | |
1632 | new[j++] = a[i]; | |
1633 | for (i = 0; b[i]; i++) | |
1634 | new[j++] = b[i]; | |
1635 | new[j] = NULL; | |
1636 | ||
1637 | return new; | |
1638 | } | |
1639 | ||
c7ab62bf | 1640 | ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr, char *page) |
a4747393 JO |
1641 | { |
1642 | struct perf_pmu_events_attr *pmu_attr = \ | |
1643 | container_of(attr, struct perf_pmu_events_attr, attr); | |
a4747393 | 1644 | u64 config = x86_pmu.event_map(pmu_attr->id); |
a4747393 | 1645 | |
3a54aaa0 SE |
1646 | /* string trumps id */ |
1647 | if (pmu_attr->event_str) | |
1648 | return sprintf(page, "%s", pmu_attr->event_str); | |
a4747393 | 1649 | |
3a54aaa0 SE |
1650 | return x86_pmu.events_sysfs_show(page, config); |
1651 | } | |
c7ab62bf | 1652 | EXPORT_SYMBOL_GPL(events_sysfs_show); |
a4747393 | 1653 | |
fc07e9f9 AK |
1654 | ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr, |
1655 | char *page) | |
1656 | { | |
1657 | struct perf_pmu_events_ht_attr *pmu_attr = | |
1658 | container_of(attr, struct perf_pmu_events_ht_attr, attr); | |
1659 | ||
1660 | /* | |
1661 | * Report conditional events depending on Hyper-Threading. | |
1662 | * | |
1663 | * This is overly conservative as usually the HT special | |
1664 | * handling is not needed if the other CPU thread is idle. | |
1665 | * | |
1666 | * Note this does not (and cannot) handle the case when thread | |
1667 | * siblings are invisible, for example with virtualization | |
1668 | * if they are owned by some other guest. The user tool | |
1669 | * has to re-read when a thread sibling gets onlined later. | |
1670 | */ | |
1671 | return sprintf(page, "%s", | |
1672 | topology_max_smt_threads() > 1 ? | |
1673 | pmu_attr->event_str_ht : | |
1674 | pmu_attr->event_str_noht); | |
1675 | } | |
1676 | ||
a4747393 JO |
1677 | EVENT_ATTR(cpu-cycles, CPU_CYCLES ); |
1678 | EVENT_ATTR(instructions, INSTRUCTIONS ); | |
1679 | EVENT_ATTR(cache-references, CACHE_REFERENCES ); | |
1680 | EVENT_ATTR(cache-misses, CACHE_MISSES ); | |
1681 | EVENT_ATTR(branch-instructions, BRANCH_INSTRUCTIONS ); | |
1682 | EVENT_ATTR(branch-misses, BRANCH_MISSES ); | |
1683 | EVENT_ATTR(bus-cycles, BUS_CYCLES ); | |
1684 | EVENT_ATTR(stalled-cycles-frontend, STALLED_CYCLES_FRONTEND ); | |
1685 | EVENT_ATTR(stalled-cycles-backend, STALLED_CYCLES_BACKEND ); | |
1686 | EVENT_ATTR(ref-cycles, REF_CPU_CYCLES ); | |
1687 | ||
1688 | static struct attribute *empty_attrs; | |
1689 | ||
95d18aa2 | 1690 | static struct attribute *events_attr[] = { |
a4747393 JO |
1691 | EVENT_PTR(CPU_CYCLES), |
1692 | EVENT_PTR(INSTRUCTIONS), | |
1693 | EVENT_PTR(CACHE_REFERENCES), | |
1694 | EVENT_PTR(CACHE_MISSES), | |
1695 | EVENT_PTR(BRANCH_INSTRUCTIONS), | |
1696 | EVENT_PTR(BRANCH_MISSES), | |
1697 | EVENT_PTR(BUS_CYCLES), | |
1698 | EVENT_PTR(STALLED_CYCLES_FRONTEND), | |
1699 | EVENT_PTR(STALLED_CYCLES_BACKEND), | |
1700 | EVENT_PTR(REF_CPU_CYCLES), | |
1701 | NULL, | |
1702 | }; | |
1703 | ||
1704 | static struct attribute_group x86_pmu_events_group = { | |
1705 | .name = "events", | |
1706 | .attrs = events_attr, | |
1707 | }; | |
1708 | ||
0bf79d44 | 1709 | ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event) |
43c032fe | 1710 | { |
43c032fe JO |
1711 | u64 umask = (config & ARCH_PERFMON_EVENTSEL_UMASK) >> 8; |
1712 | u64 cmask = (config & ARCH_PERFMON_EVENTSEL_CMASK) >> 24; | |
1713 | bool edge = (config & ARCH_PERFMON_EVENTSEL_EDGE); | |
1714 | bool pc = (config & ARCH_PERFMON_EVENTSEL_PIN_CONTROL); | |
1715 | bool any = (config & ARCH_PERFMON_EVENTSEL_ANY); | |
1716 | bool inv = (config & ARCH_PERFMON_EVENTSEL_INV); | |
1717 | ssize_t ret; | |
1718 | ||
1719 | /* | |
1720 | * We have whole page size to spend and just little data | |
1721 | * to write, so we can safely use sprintf. | |
1722 | */ | |
1723 | ret = sprintf(page, "event=0x%02llx", event); | |
1724 | ||
1725 | if (umask) | |
1726 | ret += sprintf(page + ret, ",umask=0x%02llx", umask); | |
1727 | ||
1728 | if (edge) | |
1729 | ret += sprintf(page + ret, ",edge"); | |
1730 | ||
1731 | if (pc) | |
1732 | ret += sprintf(page + ret, ",pc"); | |
1733 | ||
1734 | if (any) | |
1735 | ret += sprintf(page + ret, ",any"); | |
1736 | ||
1737 | if (inv) | |
1738 | ret += sprintf(page + ret, ",inv"); | |
1739 | ||
1740 | if (cmask) | |
1741 | ret += sprintf(page + ret, ",cmask=0x%02llx", cmask); | |
1742 | ||
1743 | ret += sprintf(page + ret, "\n"); | |
1744 | ||
1745 | return ret; | |
1746 | } | |
1747 | ||
dda99116 | 1748 | static int __init init_hw_perf_events(void) |
b56a3802 | 1749 | { |
c1d6f42f | 1750 | struct x86_pmu_quirk *quirk; |
72eae04d RR |
1751 | int err; |
1752 | ||
cdd6c482 | 1753 | pr_info("Performance Events: "); |
1123e3ad | 1754 | |
b56a3802 JSR |
1755 | switch (boot_cpu_data.x86_vendor) { |
1756 | case X86_VENDOR_INTEL: | |
72eae04d | 1757 | err = intel_pmu_init(); |
b56a3802 | 1758 | break; |
f87ad35d | 1759 | case X86_VENDOR_AMD: |
72eae04d | 1760 | err = amd_pmu_init(); |
f87ad35d | 1761 | break; |
4138960a | 1762 | default: |
8a3da6c7 | 1763 | err = -ENOTSUPP; |
b56a3802 | 1764 | } |
1123e3ad | 1765 | if (err != 0) { |
cdd6c482 | 1766 | pr_cont("no PMU driver, software events only.\n"); |
004417a6 | 1767 | return 0; |
1123e3ad | 1768 | } |
b56a3802 | 1769 | |
12558038 CG |
1770 | pmu_check_apic(); |
1771 | ||
33c6d6a7 | 1772 | /* sanity check that the hardware exists or is emulated */ |
4407204c | 1773 | if (!check_hw_exists()) |
004417a6 | 1774 | return 0; |
33c6d6a7 | 1775 | |
1123e3ad | 1776 | pr_cont("%s PMU driver.\n", x86_pmu.name); |
faa28ae0 | 1777 | |
e97df763 PZ |
1778 | x86_pmu.attr_rdpmc = 1; /* enable userspace RDPMC usage by default */ |
1779 | ||
c1d6f42f PZ |
1780 | for (quirk = x86_pmu.quirks; quirk; quirk = quirk->next) |
1781 | quirk->func(); | |
3c44780b | 1782 | |
a1eac7ac RR |
1783 | if (!x86_pmu.intel_ctrl) |
1784 | x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; | |
241771ef | 1785 | |
cdd6c482 | 1786 | perf_events_lapic_init(); |
9c48f1c6 | 1787 | register_nmi_handler(NMI_LOCAL, perf_event_nmi_handler, 0, "PMI"); |
1123e3ad | 1788 | |
63b14649 | 1789 | unconstrained = (struct event_constraint) |
948b1bb8 | 1790 | __EVENT_CONSTRAINT(0, (1ULL << x86_pmu.num_counters) - 1, |
9fac2cf3 | 1791 | 0, x86_pmu.num_counters, 0, 0); |
63b14649 | 1792 | |
641cc938 | 1793 | x86_pmu_format_group.attrs = x86_pmu.format_attrs; |
0c9d42ed | 1794 | |
f20093ee SE |
1795 | if (x86_pmu.event_attrs) |
1796 | x86_pmu_events_group.attrs = x86_pmu.event_attrs; | |
1797 | ||
a4747393 JO |
1798 | if (!x86_pmu.events_sysfs_show) |
1799 | x86_pmu_events_group.attrs = &empty_attrs; | |
8300daa2 JO |
1800 | else |
1801 | filter_events(x86_pmu_events_group.attrs); | |
a4747393 | 1802 | |
1a6461b1 AK |
1803 | if (x86_pmu.cpu_events) { |
1804 | struct attribute **tmp; | |
1805 | ||
1806 | tmp = merge_attr(x86_pmu_events_group.attrs, x86_pmu.cpu_events); | |
1807 | if (!WARN_ON(!tmp)) | |
1808 | x86_pmu_events_group.attrs = tmp; | |
1809 | } | |
1810 | ||
57c0c15b | 1811 | pr_info("... version: %d\n", x86_pmu.version); |
948b1bb8 RR |
1812 | pr_info("... bit width: %d\n", x86_pmu.cntval_bits); |
1813 | pr_info("... generic registers: %d\n", x86_pmu.num_counters); | |
1814 | pr_info("... value mask: %016Lx\n", x86_pmu.cntval_mask); | |
57c0c15b | 1815 | pr_info("... max period: %016Lx\n", x86_pmu.max_period); |
948b1bb8 | 1816 | pr_info("... fixed-purpose events: %d\n", x86_pmu.num_counters_fixed); |
d6dc0b4e | 1817 | pr_info("... event mask: %016Lx\n", x86_pmu.intel_ctrl); |
3f6da390 | 1818 | |
95ca792c TG |
1819 | /* |
1820 | * Install callbacks. Core will call them for each online | |
1821 | * cpu. | |
1822 | */ | |
73c1b41e | 1823 | err = cpuhp_setup_state(CPUHP_PERF_X86_PREPARE, "perf/x86:prepare", |
95ca792c TG |
1824 | x86_pmu_prepare_cpu, x86_pmu_dead_cpu); |
1825 | if (err) | |
1826 | return err; | |
1827 | ||
1828 | err = cpuhp_setup_state(CPUHP_AP_PERF_X86_STARTING, | |
73c1b41e | 1829 | "perf/x86:starting", x86_pmu_starting_cpu, |
95ca792c TG |
1830 | x86_pmu_dying_cpu); |
1831 | if (err) | |
1832 | goto out; | |
1833 | ||
73c1b41e | 1834 | err = cpuhp_setup_state(CPUHP_AP_PERF_X86_ONLINE, "perf/x86:online", |
95ca792c TG |
1835 | x86_pmu_online_cpu, NULL); |
1836 | if (err) | |
1837 | goto out1; | |
1838 | ||
1839 | err = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); | |
1840 | if (err) | |
1841 | goto out2; | |
004417a6 PZ |
1842 | |
1843 | return 0; | |
95ca792c TG |
1844 | |
1845 | out2: | |
1846 | cpuhp_remove_state(CPUHP_AP_PERF_X86_ONLINE); | |
1847 | out1: | |
1848 | cpuhp_remove_state(CPUHP_AP_PERF_X86_STARTING); | |
1849 | out: | |
1850 | cpuhp_remove_state(CPUHP_PERF_X86_PREPARE); | |
1851 | return err; | |
241771ef | 1852 | } |
004417a6 | 1853 | early_initcall(init_hw_perf_events); |
621a01ea | 1854 | |
cdd6c482 | 1855 | static inline void x86_pmu_read(struct perf_event *event) |
ee06094f | 1856 | { |
cc2ad4ba | 1857 | x86_perf_event_update(event); |
ee06094f IM |
1858 | } |
1859 | ||
4d1c52b0 LM |
1860 | /* |
1861 | * Start group events scheduling transaction | |
1862 | * Set the flag to make pmu::enable() not perform the | |
1863 | * schedulability test, it will be performed at commit time | |
fbbe0701 SB |
1864 | * |
1865 | * We only support PERF_PMU_TXN_ADD transactions. Save the | |
1866 | * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD | |
1867 | * transactions. | |
4d1c52b0 | 1868 | */ |
fbbe0701 | 1869 | static void x86_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) |
4d1c52b0 | 1870 | { |
fbbe0701 SB |
1871 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
1872 | ||
1873 | WARN_ON_ONCE(cpuc->txn_flags); /* txn already in flight */ | |
1874 | ||
1875 | cpuc->txn_flags = txn_flags; | |
1876 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1877 | return; | |
1878 | ||
33696fc0 | 1879 | perf_pmu_disable(pmu); |
0a3aee0d | 1880 | __this_cpu_write(cpu_hw_events.n_txn, 0); |
4d1c52b0 LM |
1881 | } |
1882 | ||
1883 | /* | |
1884 | * Stop group events scheduling transaction | |
1885 | * Clear the flag and pmu::enable() will perform the | |
1886 | * schedulability test. | |
1887 | */ | |
51b0fe39 | 1888 | static void x86_pmu_cancel_txn(struct pmu *pmu) |
4d1c52b0 | 1889 | { |
fbbe0701 SB |
1890 | unsigned int txn_flags; |
1891 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); | |
1892 | ||
1893 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ | |
1894 | ||
1895 | txn_flags = cpuc->txn_flags; | |
1896 | cpuc->txn_flags = 0; | |
1897 | if (txn_flags & ~PERF_PMU_TXN_ADD) | |
1898 | return; | |
1899 | ||
90151c35 | 1900 | /* |
c347a2f1 PZ |
1901 | * Truncate collected array by the number of events added in this |
1902 | * transaction. See x86_pmu_add() and x86_pmu_*_txn(). | |
90151c35 | 1903 | */ |
0a3aee0d TH |
1904 | __this_cpu_sub(cpu_hw_events.n_added, __this_cpu_read(cpu_hw_events.n_txn)); |
1905 | __this_cpu_sub(cpu_hw_events.n_events, __this_cpu_read(cpu_hw_events.n_txn)); | |
33696fc0 | 1906 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1907 | } |
1908 | ||
1909 | /* | |
1910 | * Commit group events scheduling transaction | |
1911 | * Perform the group schedulability test as a whole | |
1912 | * Return 0 if success | |
c347a2f1 PZ |
1913 | * |
1914 | * Does not cancel the transaction on failure; expects the caller to do this. | |
4d1c52b0 | 1915 | */ |
51b0fe39 | 1916 | static int x86_pmu_commit_txn(struct pmu *pmu) |
4d1c52b0 | 1917 | { |
89cbc767 | 1918 | struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); |
4d1c52b0 LM |
1919 | int assign[X86_PMC_IDX_MAX]; |
1920 | int n, ret; | |
1921 | ||
fbbe0701 SB |
1922 | WARN_ON_ONCE(!cpuc->txn_flags); /* no txn in flight */ |
1923 | ||
1924 | if (cpuc->txn_flags & ~PERF_PMU_TXN_ADD) { | |
1925 | cpuc->txn_flags = 0; | |
1926 | return 0; | |
1927 | } | |
1928 | ||
4d1c52b0 LM |
1929 | n = cpuc->n_events; |
1930 | ||
1931 | if (!x86_pmu_initialized()) | |
1932 | return -EAGAIN; | |
1933 | ||
1934 | ret = x86_pmu.schedule_events(cpuc, n, assign); | |
1935 | if (ret) | |
1936 | return ret; | |
1937 | ||
1938 | /* | |
1939 | * copy new assignment, now we know it is possible | |
1940 | * will be used by hw_perf_enable() | |
1941 | */ | |
1942 | memcpy(cpuc->assign, assign, n*sizeof(int)); | |
1943 | ||
fbbe0701 | 1944 | cpuc->txn_flags = 0; |
33696fc0 | 1945 | perf_pmu_enable(pmu); |
4d1c52b0 LM |
1946 | return 0; |
1947 | } | |
cd8a38d3 SE |
1948 | /* |
1949 | * a fake_cpuc is used to validate event groups. Due to | |
1950 | * the extra reg logic, we need to also allocate a fake | |
1951 | * per_core and per_cpu structure. Otherwise, group events | |
1952 | * using extra reg may conflict without the kernel being | |
1953 | * able to catch this when the last event gets added to | |
1954 | * the group. | |
1955 | */ | |
1956 | static void free_fake_cpuc(struct cpu_hw_events *cpuc) | |
1957 | { | |
1958 | kfree(cpuc->shared_regs); | |
1959 | kfree(cpuc); | |
1960 | } | |
1961 | ||
1962 | static struct cpu_hw_events *allocate_fake_cpuc(void) | |
1963 | { | |
1964 | struct cpu_hw_events *cpuc; | |
1965 | int cpu = raw_smp_processor_id(); | |
1966 | ||
1967 | cpuc = kzalloc(sizeof(*cpuc), GFP_KERNEL); | |
1968 | if (!cpuc) | |
1969 | return ERR_PTR(-ENOMEM); | |
1970 | ||
1971 | /* only needed, if we have extra_regs */ | |
1972 | if (x86_pmu.extra_regs) { | |
1973 | cpuc->shared_regs = allocate_shared_regs(cpu); | |
1974 | if (!cpuc->shared_regs) | |
1975 | goto error; | |
1976 | } | |
b430f7c4 | 1977 | cpuc->is_fake = 1; |
cd8a38d3 SE |
1978 | return cpuc; |
1979 | error: | |
1980 | free_fake_cpuc(cpuc); | |
1981 | return ERR_PTR(-ENOMEM); | |
1982 | } | |
4d1c52b0 | 1983 | |
ca037701 PZ |
1984 | /* |
1985 | * validate that we can schedule this event | |
1986 | */ | |
1987 | static int validate_event(struct perf_event *event) | |
1988 | { | |
1989 | struct cpu_hw_events *fake_cpuc; | |
1990 | struct event_constraint *c; | |
1991 | int ret = 0; | |
1992 | ||
cd8a38d3 SE |
1993 | fake_cpuc = allocate_fake_cpuc(); |
1994 | if (IS_ERR(fake_cpuc)) | |
1995 | return PTR_ERR(fake_cpuc); | |
ca037701 | 1996 | |
79cba822 | 1997 | c = x86_pmu.get_event_constraints(fake_cpuc, -1, event); |
ca037701 PZ |
1998 | |
1999 | if (!c || !c->weight) | |
aa2bc1ad | 2000 | ret = -EINVAL; |
ca037701 PZ |
2001 | |
2002 | if (x86_pmu.put_event_constraints) | |
2003 | x86_pmu.put_event_constraints(fake_cpuc, event); | |
2004 | ||
cd8a38d3 | 2005 | free_fake_cpuc(fake_cpuc); |
ca037701 PZ |
2006 | |
2007 | return ret; | |
2008 | } | |
2009 | ||
1da53e02 SE |
2010 | /* |
2011 | * validate a single event group | |
2012 | * | |
2013 | * validation include: | |
184f412c IM |
2014 | * - check events are compatible which each other |
2015 | * - events do not compete for the same counter | |
2016 | * - number of events <= number of counters | |
1da53e02 SE |
2017 | * |
2018 | * validation ensures the group can be loaded onto the | |
2019 | * PMU if it was the only group available. | |
2020 | */ | |
fe9081cc PZ |
2021 | static int validate_group(struct perf_event *event) |
2022 | { | |
1da53e02 | 2023 | struct perf_event *leader = event->group_leader; |
502568d5 | 2024 | struct cpu_hw_events *fake_cpuc; |
aa2bc1ad | 2025 | int ret = -EINVAL, n; |
fe9081cc | 2026 | |
cd8a38d3 SE |
2027 | fake_cpuc = allocate_fake_cpuc(); |
2028 | if (IS_ERR(fake_cpuc)) | |
2029 | return PTR_ERR(fake_cpuc); | |
1da53e02 SE |
2030 | /* |
2031 | * the event is not yet connected with its | |
2032 | * siblings therefore we must first collect | |
2033 | * existing siblings, then add the new event | |
2034 | * before we can simulate the scheduling | |
2035 | */ | |
502568d5 | 2036 | n = collect_events(fake_cpuc, leader, true); |
1da53e02 | 2037 | if (n < 0) |
cd8a38d3 | 2038 | goto out; |
fe9081cc | 2039 | |
502568d5 PZ |
2040 | fake_cpuc->n_events = n; |
2041 | n = collect_events(fake_cpuc, event, false); | |
1da53e02 | 2042 | if (n < 0) |
cd8a38d3 | 2043 | goto out; |
fe9081cc | 2044 | |
502568d5 | 2045 | fake_cpuc->n_events = n; |
1da53e02 | 2046 | |
a072738e | 2047 | ret = x86_pmu.schedule_events(fake_cpuc, n, NULL); |
502568d5 | 2048 | |
502568d5 | 2049 | out: |
cd8a38d3 | 2050 | free_fake_cpuc(fake_cpuc); |
502568d5 | 2051 | return ret; |
fe9081cc PZ |
2052 | } |
2053 | ||
dda99116 | 2054 | static int x86_pmu_event_init(struct perf_event *event) |
621a01ea | 2055 | { |
51b0fe39 | 2056 | struct pmu *tmp; |
621a01ea IM |
2057 | int err; |
2058 | ||
b0a873eb PZ |
2059 | switch (event->attr.type) { |
2060 | case PERF_TYPE_RAW: | |
2061 | case PERF_TYPE_HARDWARE: | |
2062 | case PERF_TYPE_HW_CACHE: | |
2063 | break; | |
2064 | ||
2065 | default: | |
2066 | return -ENOENT; | |
2067 | } | |
2068 | ||
2069 | err = __x86_pmu_event_init(event); | |
fe9081cc | 2070 | if (!err) { |
8113070d SE |
2071 | /* |
2072 | * we temporarily connect event to its pmu | |
2073 | * such that validate_group() can classify | |
2074 | * it as an x86 event using is_x86_event() | |
2075 | */ | |
2076 | tmp = event->pmu; | |
2077 | event->pmu = &pmu; | |
2078 | ||
fe9081cc PZ |
2079 | if (event->group_leader != event) |
2080 | err = validate_group(event); | |
ca037701 PZ |
2081 | else |
2082 | err = validate_event(event); | |
8113070d SE |
2083 | |
2084 | event->pmu = tmp; | |
fe9081cc | 2085 | } |
a1792cda | 2086 | if (err) { |
cdd6c482 IM |
2087 | if (event->destroy) |
2088 | event->destroy(event); | |
a1792cda | 2089 | } |
621a01ea | 2090 | |
7911d3f7 AL |
2091 | if (ACCESS_ONCE(x86_pmu.attr_rdpmc)) |
2092 | event->hw.flags |= PERF_X86_EVENT_RDPMC_ALLOWED; | |
2093 | ||
b0a873eb | 2094 | return err; |
621a01ea | 2095 | } |
d7d59fb3 | 2096 | |
7911d3f7 AL |
2097 | static void refresh_pce(void *ignored) |
2098 | { | |
2099 | if (current->mm) | |
2100 | load_mm_cr4(current->mm); | |
2101 | } | |
2102 | ||
2103 | static void x86_pmu_event_mapped(struct perf_event *event) | |
2104 | { | |
2105 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
2106 | return; | |
2107 | ||
2108 | if (atomic_inc_return(¤t->mm->context.perf_rdpmc_allowed) == 1) | |
2109 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
2110 | } | |
2111 | ||
2112 | static void x86_pmu_event_unmapped(struct perf_event *event) | |
2113 | { | |
2114 | if (!current->mm) | |
2115 | return; | |
2116 | ||
2117 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) | |
2118 | return; | |
2119 | ||
2120 | if (atomic_dec_and_test(¤t->mm->context.perf_rdpmc_allowed)) | |
2121 | on_each_cpu_mask(mm_cpumask(current->mm), refresh_pce, NULL, 1); | |
2122 | } | |
2123 | ||
fe4a3308 PZ |
2124 | static int x86_pmu_event_idx(struct perf_event *event) |
2125 | { | |
2126 | int idx = event->hw.idx; | |
2127 | ||
7911d3f7 | 2128 | if (!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED)) |
c7206205 PZ |
2129 | return 0; |
2130 | ||
15c7ad51 RR |
2131 | if (x86_pmu.num_counters_fixed && idx >= INTEL_PMC_IDX_FIXED) { |
2132 | idx -= INTEL_PMC_IDX_FIXED; | |
fe4a3308 PZ |
2133 | idx |= 1 << 30; |
2134 | } | |
2135 | ||
2136 | return idx + 1; | |
2137 | } | |
2138 | ||
0c9d42ed PZ |
2139 | static ssize_t get_attr_rdpmc(struct device *cdev, |
2140 | struct device_attribute *attr, | |
2141 | char *buf) | |
2142 | { | |
2143 | return snprintf(buf, 40, "%d\n", x86_pmu.attr_rdpmc); | |
2144 | } | |
2145 | ||
0c9d42ed PZ |
2146 | static ssize_t set_attr_rdpmc(struct device *cdev, |
2147 | struct device_attribute *attr, | |
2148 | const char *buf, size_t count) | |
2149 | { | |
e2b297fc SK |
2150 | unsigned long val; |
2151 | ssize_t ret; | |
2152 | ||
2153 | ret = kstrtoul(buf, 0, &val); | |
2154 | if (ret) | |
2155 | return ret; | |
e97df763 | 2156 | |
a6673429 AL |
2157 | if (val > 2) |
2158 | return -EINVAL; | |
2159 | ||
e97df763 PZ |
2160 | if (x86_pmu.attr_rdpmc_broken) |
2161 | return -ENOTSUPP; | |
0c9d42ed | 2162 | |
a6673429 AL |
2163 | if ((val == 2) != (x86_pmu.attr_rdpmc == 2)) { |
2164 | /* | |
2165 | * Changing into or out of always available, aka | |
2166 | * perf-event-bypassing mode. This path is extremely slow, | |
2167 | * but only root can trigger it, so it's okay. | |
2168 | */ | |
2169 | if (val == 2) | |
2170 | static_key_slow_inc(&rdpmc_always_available); | |
2171 | else | |
2172 | static_key_slow_dec(&rdpmc_always_available); | |
2173 | on_each_cpu(refresh_pce, NULL, 1); | |
2174 | } | |
2175 | ||
2176 | x86_pmu.attr_rdpmc = val; | |
2177 | ||
0c9d42ed PZ |
2178 | return count; |
2179 | } | |
2180 | ||
2181 | static DEVICE_ATTR(rdpmc, S_IRUSR | S_IWUSR, get_attr_rdpmc, set_attr_rdpmc); | |
2182 | ||
2183 | static struct attribute *x86_pmu_attrs[] = { | |
2184 | &dev_attr_rdpmc.attr, | |
2185 | NULL, | |
2186 | }; | |
2187 | ||
2188 | static struct attribute_group x86_pmu_attr_group = { | |
2189 | .attrs = x86_pmu_attrs, | |
2190 | }; | |
2191 | ||
2192 | static const struct attribute_group *x86_pmu_attr_groups[] = { | |
2193 | &x86_pmu_attr_group, | |
641cc938 | 2194 | &x86_pmu_format_group, |
a4747393 | 2195 | &x86_pmu_events_group, |
0c9d42ed PZ |
2196 | NULL, |
2197 | }; | |
2198 | ||
ba532500 | 2199 | static void x86_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) |
d010b332 | 2200 | { |
ba532500 YZ |
2201 | if (x86_pmu.sched_task) |
2202 | x86_pmu.sched_task(ctx, sched_in); | |
d010b332 SE |
2203 | } |
2204 | ||
c93dc84c PZ |
2205 | void perf_check_microcode(void) |
2206 | { | |
2207 | if (x86_pmu.check_microcode) | |
2208 | x86_pmu.check_microcode(); | |
2209 | } | |
2210 | EXPORT_SYMBOL_GPL(perf_check_microcode); | |
2211 | ||
b0a873eb | 2212 | static struct pmu pmu = { |
d010b332 SE |
2213 | .pmu_enable = x86_pmu_enable, |
2214 | .pmu_disable = x86_pmu_disable, | |
a4eaf7f1 | 2215 | |
c93dc84c | 2216 | .attr_groups = x86_pmu_attr_groups, |
0c9d42ed | 2217 | |
c93dc84c | 2218 | .event_init = x86_pmu_event_init, |
a4eaf7f1 | 2219 | |
7911d3f7 AL |
2220 | .event_mapped = x86_pmu_event_mapped, |
2221 | .event_unmapped = x86_pmu_event_unmapped, | |
2222 | ||
d010b332 SE |
2223 | .add = x86_pmu_add, |
2224 | .del = x86_pmu_del, | |
2225 | .start = x86_pmu_start, | |
2226 | .stop = x86_pmu_stop, | |
2227 | .read = x86_pmu_read, | |
a4eaf7f1 | 2228 | |
c93dc84c PZ |
2229 | .start_txn = x86_pmu_start_txn, |
2230 | .cancel_txn = x86_pmu_cancel_txn, | |
2231 | .commit_txn = x86_pmu_commit_txn, | |
fe4a3308 | 2232 | |
c93dc84c | 2233 | .event_idx = x86_pmu_event_idx, |
ba532500 | 2234 | .sched_task = x86_pmu_sched_task, |
e18bf526 | 2235 | .task_ctx_size = sizeof(struct x86_perf_task_context), |
b0a873eb PZ |
2236 | }; |
2237 | ||
c1317ec2 AL |
2238 | void arch_perf_update_userpage(struct perf_event *event, |
2239 | struct perf_event_mmap_page *userpg, u64 now) | |
e3f3541c | 2240 | { |
20d1c86a PZ |
2241 | struct cyc2ns_data *data; |
2242 | ||
fa731587 PZ |
2243 | userpg->cap_user_time = 0; |
2244 | userpg->cap_user_time_zero = 0; | |
7911d3f7 AL |
2245 | userpg->cap_user_rdpmc = |
2246 | !!(event->hw.flags & PERF_X86_EVENT_RDPMC_ALLOWED); | |
c7206205 PZ |
2247 | userpg->pmc_width = x86_pmu.cntval_bits; |
2248 | ||
35af99e6 | 2249 | if (!sched_clock_stable()) |
e3f3541c PZ |
2250 | return; |
2251 | ||
20d1c86a PZ |
2252 | data = cyc2ns_read_begin(); |
2253 | ||
34f43927 PZ |
2254 | /* |
2255 | * Internal timekeeping for enabled/running/stopped times | |
2256 | * is always in the local_clock domain. | |
2257 | */ | |
fa731587 | 2258 | userpg->cap_user_time = 1; |
20d1c86a PZ |
2259 | userpg->time_mult = data->cyc2ns_mul; |
2260 | userpg->time_shift = data->cyc2ns_shift; | |
2261 | userpg->time_offset = data->cyc2ns_offset - now; | |
c73deb6a | 2262 | |
34f43927 PZ |
2263 | /* |
2264 | * cap_user_time_zero doesn't make sense when we're using a different | |
2265 | * time base for the records. | |
2266 | */ | |
f454bfdd | 2267 | if (!event->attr.use_clockid) { |
34f43927 PZ |
2268 | userpg->cap_user_time_zero = 1; |
2269 | userpg->time_zero = data->cyc2ns_offset; | |
2270 | } | |
20d1c86a PZ |
2271 | |
2272 | cyc2ns_read_end(data); | |
e3f3541c PZ |
2273 | } |
2274 | ||
56962b44 | 2275 | void |
cfbcf468 | 2276 | perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) |
d7d59fb3 | 2277 | { |
35f4d9b3 JP |
2278 | struct unwind_state state; |
2279 | unsigned long addr; | |
2280 | ||
927c7a9e FW |
2281 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2282 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2283 | return; |
927c7a9e FW |
2284 | } |
2285 | ||
019e579d JP |
2286 | if (perf_callchain_store(entry, regs->ip)) |
2287 | return; | |
d7d59fb3 | 2288 | |
35f4d9b3 JP |
2289 | for (unwind_start(&state, current, regs, NULL); !unwind_done(&state); |
2290 | unwind_next_frame(&state)) { | |
2291 | addr = unwind_get_return_address(&state); | |
2292 | if (!addr || perf_callchain_store(entry, addr)) | |
2293 | return; | |
2294 | } | |
d7d59fb3 PZ |
2295 | } |
2296 | ||
bc6ca7b3 AS |
2297 | static inline int |
2298 | valid_user_frame(const void __user *fp, unsigned long size) | |
2299 | { | |
2300 | return (__range_not_ok(fp, size, TASK_SIZE) == 0); | |
2301 | } | |
2302 | ||
d07bdfd3 PZ |
2303 | static unsigned long get_segment_base(unsigned int segment) |
2304 | { | |
2305 | struct desc_struct *desc; | |
990e9dc3 | 2306 | unsigned int idx = segment >> 3; |
d07bdfd3 PZ |
2307 | |
2308 | if ((segment & SEGMENT_TI_MASK) == SEGMENT_LDT) { | |
a5b9e5a2 | 2309 | #ifdef CONFIG_MODIFY_LDT_SYSCALL |
37868fe1 AL |
2310 | struct ldt_struct *ldt; |
2311 | ||
d07bdfd3 PZ |
2312 | if (idx > LDT_ENTRIES) |
2313 | return 0; | |
2314 | ||
37868fe1 AL |
2315 | /* IRQs are off, so this synchronizes with smp_store_release */ |
2316 | ldt = lockless_dereference(current->active_mm->context.ldt); | |
2317 | if (!ldt || idx > ldt->size) | |
d07bdfd3 PZ |
2318 | return 0; |
2319 | ||
37868fe1 | 2320 | desc = &ldt->entries[idx]; |
a5b9e5a2 AL |
2321 | #else |
2322 | return 0; | |
2323 | #endif | |
d07bdfd3 PZ |
2324 | } else { |
2325 | if (idx > GDT_ENTRIES) | |
2326 | return 0; | |
2327 | ||
37868fe1 | 2328 | desc = raw_cpu_ptr(gdt_page.gdt) + idx; |
d07bdfd3 PZ |
2329 | } |
2330 | ||
37868fe1 | 2331 | return get_desc_base(desc); |
d07bdfd3 PZ |
2332 | } |
2333 | ||
10ed3493 | 2334 | #ifdef CONFIG_IA32_EMULATION |
d1a797f3 PA |
2335 | |
2336 | #include <asm/compat.h> | |
2337 | ||
257ef9d2 | 2338 | static inline int |
cfbcf468 | 2339 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) |
74193ef0 | 2340 | { |
257ef9d2 | 2341 | /* 32-bit process in 64-bit kernel. */ |
d07bdfd3 | 2342 | unsigned long ss_base, cs_base; |
257ef9d2 TE |
2343 | struct stack_frame_ia32 frame; |
2344 | const void __user *fp; | |
74193ef0 | 2345 | |
257ef9d2 TE |
2346 | if (!test_thread_flag(TIF_IA32)) |
2347 | return 0; | |
2348 | ||
d07bdfd3 PZ |
2349 | cs_base = get_segment_base(regs->cs); |
2350 | ss_base = get_segment_base(regs->ss); | |
2351 | ||
2352 | fp = compat_ptr(ss_base + regs->bp); | |
75925e1a | 2353 | pagefault_disable(); |
3b1fff08 | 2354 | while (entry->nr < entry->max_stack) { |
257ef9d2 TE |
2355 | unsigned long bytes; |
2356 | frame.next_frame = 0; | |
2357 | frame.return_address = 0; | |
2358 | ||
ae31fe51 | 2359 | if (!valid_user_frame(fp, sizeof(frame))) |
75925e1a AK |
2360 | break; |
2361 | ||
2362 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, 4); | |
2363 | if (bytes != 0) | |
2364 | break; | |
2365 | bytes = __copy_from_user_nmi(&frame.return_address, fp+4, 4); | |
0a196848 | 2366 | if (bytes != 0) |
257ef9d2 | 2367 | break; |
74193ef0 | 2368 | |
d07bdfd3 PZ |
2369 | perf_callchain_store(entry, cs_base + frame.return_address); |
2370 | fp = compat_ptr(ss_base + frame.next_frame); | |
257ef9d2 | 2371 | } |
75925e1a | 2372 | pagefault_enable(); |
257ef9d2 | 2373 | return 1; |
d7d59fb3 | 2374 | } |
257ef9d2 TE |
2375 | #else |
2376 | static inline int | |
cfbcf468 | 2377 | perf_callchain_user32(struct pt_regs *regs, struct perf_callchain_entry_ctx *entry) |
257ef9d2 TE |
2378 | { |
2379 | return 0; | |
2380 | } | |
2381 | #endif | |
d7d59fb3 | 2382 | |
56962b44 | 2383 | void |
cfbcf468 | 2384 | perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) |
d7d59fb3 PZ |
2385 | { |
2386 | struct stack_frame frame; | |
fc188225 | 2387 | const unsigned long __user *fp; |
d7d59fb3 | 2388 | |
927c7a9e FW |
2389 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
2390 | /* TODO: We don't support guest os callchain now */ | |
ed805261 | 2391 | return; |
927c7a9e | 2392 | } |
5a6cec3a | 2393 | |
d07bdfd3 PZ |
2394 | /* |
2395 | * We don't know what to do with VM86 stacks.. ignore them for now. | |
2396 | */ | |
2397 | if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM)) | |
2398 | return; | |
2399 | ||
fc188225 | 2400 | fp = (unsigned long __user *)regs->bp; |
d7d59fb3 | 2401 | |
70791ce9 | 2402 | perf_callchain_store(entry, regs->ip); |
d7d59fb3 | 2403 | |
20afc60f AV |
2404 | if (!current->mm) |
2405 | return; | |
2406 | ||
257ef9d2 TE |
2407 | if (perf_callchain_user32(regs, entry)) |
2408 | return; | |
2409 | ||
75925e1a | 2410 | pagefault_disable(); |
3b1fff08 | 2411 | while (entry->nr < entry->max_stack) { |
257ef9d2 | 2412 | unsigned long bytes; |
fc188225 | 2413 | |
038e836e | 2414 | frame.next_frame = NULL; |
d7d59fb3 PZ |
2415 | frame.return_address = 0; |
2416 | ||
ae31fe51 | 2417 | if (!valid_user_frame(fp, sizeof(frame))) |
75925e1a AK |
2418 | break; |
2419 | ||
fc188225 | 2420 | bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp)); |
75925e1a AK |
2421 | if (bytes != 0) |
2422 | break; | |
fc188225 | 2423 | bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp)); |
0a196848 | 2424 | if (bytes != 0) |
d7d59fb3 PZ |
2425 | break; |
2426 | ||
70791ce9 | 2427 | perf_callchain_store(entry, frame.return_address); |
75925e1a | 2428 | fp = (void __user *)frame.next_frame; |
d7d59fb3 | 2429 | } |
75925e1a | 2430 | pagefault_enable(); |
d7d59fb3 PZ |
2431 | } |
2432 | ||
d07bdfd3 PZ |
2433 | /* |
2434 | * Deal with code segment offsets for the various execution modes: | |
2435 | * | |
2436 | * VM86 - the good olde 16 bit days, where the linear address is | |
2437 | * 20 bits and we use regs->ip + 0x10 * regs->cs. | |
2438 | * | |
2439 | * IA32 - Where we need to look at GDT/LDT segment descriptor tables | |
2440 | * to figure out what the 32bit base address is. | |
2441 | * | |
2442 | * X32 - has TIF_X32 set, but is running in x86_64 | |
2443 | * | |
2444 | * X86_64 - CS,DS,SS,ES are all zero based. | |
2445 | */ | |
2446 | static unsigned long code_segment_base(struct pt_regs *regs) | |
39447b38 | 2447 | { |
383f3af3 AL |
2448 | /* |
2449 | * For IA32 we look at the GDT/LDT segment base to convert the | |
2450 | * effective IP to a linear address. | |
2451 | */ | |
2452 | ||
2453 | #ifdef CONFIG_X86_32 | |
d07bdfd3 PZ |
2454 | /* |
2455 | * If we are in VM86 mode, add the segment offset to convert to a | |
2456 | * linear address. | |
2457 | */ | |
2458 | if (regs->flags & X86_VM_MASK) | |
2459 | return 0x10 * regs->cs; | |
2460 | ||
55474c48 | 2461 | if (user_mode(regs) && regs->cs != __USER_CS) |
d07bdfd3 PZ |
2462 | return get_segment_base(regs->cs); |
2463 | #else | |
c56716af AL |
2464 | if (user_mode(regs) && !user_64bit_mode(regs) && |
2465 | regs->cs != __USER32_CS) | |
2466 | return get_segment_base(regs->cs); | |
d07bdfd3 PZ |
2467 | #endif |
2468 | return 0; | |
2469 | } | |
dcf46b94 | 2470 | |
d07bdfd3 PZ |
2471 | unsigned long perf_instruction_pointer(struct pt_regs *regs) |
2472 | { | |
39447b38 | 2473 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) |
d07bdfd3 | 2474 | return perf_guest_cbs->get_guest_ip(); |
dcf46b94 | 2475 | |
d07bdfd3 | 2476 | return regs->ip + code_segment_base(regs); |
39447b38 ZY |
2477 | } |
2478 | ||
2479 | unsigned long perf_misc_flags(struct pt_regs *regs) | |
2480 | { | |
2481 | int misc = 0; | |
dcf46b94 | 2482 | |
39447b38 | 2483 | if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { |
dcf46b94 ZY |
2484 | if (perf_guest_cbs->is_user_mode()) |
2485 | misc |= PERF_RECORD_MISC_GUEST_USER; | |
2486 | else | |
2487 | misc |= PERF_RECORD_MISC_GUEST_KERNEL; | |
2488 | } else { | |
d07bdfd3 | 2489 | if (user_mode(regs)) |
dcf46b94 ZY |
2490 | misc |= PERF_RECORD_MISC_USER; |
2491 | else | |
2492 | misc |= PERF_RECORD_MISC_KERNEL; | |
2493 | } | |
2494 | ||
39447b38 | 2495 | if (regs->flags & PERF_EFLAGS_EXACT) |
ab608344 | 2496 | misc |= PERF_RECORD_MISC_EXACT_IP; |
39447b38 ZY |
2497 | |
2498 | return misc; | |
2499 | } | |
b3d9468a GN |
2500 | |
2501 | void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap) | |
2502 | { | |
2503 | cap->version = x86_pmu.version; | |
2504 | cap->num_counters_gp = x86_pmu.num_counters; | |
2505 | cap->num_counters_fixed = x86_pmu.num_counters_fixed; | |
2506 | cap->bit_width_gp = x86_pmu.cntval_bits; | |
2507 | cap->bit_width_fixed = x86_pmu.cntval_bits; | |
2508 | cap->events_mask = (unsigned int)x86_pmu.events_maskl; | |
2509 | cap->events_mask_len = x86_pmu.events_mask_len; | |
2510 | } | |
2511 | EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability); |