Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * linux/arch/x86_64/entry.S | |
3 | * | |
4 | * Copyright (C) 1991, 1992 Linus Torvalds | |
5 | * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs | |
6 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
4d732138 | 7 | * |
1da177e4 LT |
8 | * entry.S contains the system-call and fault low-level handling routines. |
9 | * | |
8b4777a4 AL |
10 | * Some of this is documented in Documentation/x86/entry_64.txt |
11 | * | |
0bd7b798 | 12 | * A note on terminology: |
4d732138 IM |
13 | * - iret frame: Architecture defined interrupt frame from SS to RIP |
14 | * at the top of the kernel process stack. | |
2e91a17b AK |
15 | * |
16 | * Some macro usage: | |
4d732138 IM |
17 | * - ENTRY/END: Define functions in the symbol table. |
18 | * - TRACE_IRQ_*: Trace hardirq state for lock debugging. | |
19 | * - idtentry: Define exception entry points. | |
1da177e4 | 20 | */ |
1da177e4 LT |
21 | #include <linux/linkage.h> |
22 | #include <asm/segment.h> | |
1da177e4 LT |
23 | #include <asm/cache.h> |
24 | #include <asm/errno.h> | |
d36f9479 | 25 | #include "calling.h" |
e2d5df93 | 26 | #include <asm/asm-offsets.h> |
1da177e4 LT |
27 | #include <asm/msr.h> |
28 | #include <asm/unistd.h> | |
29 | #include <asm/thread_info.h> | |
30 | #include <asm/hw_irq.h> | |
0341c14d | 31 | #include <asm/page_types.h> |
2601e64d | 32 | #include <asm/irqflags.h> |
72fe4858 | 33 | #include <asm/paravirt.h> |
9939ddaf | 34 | #include <asm/percpu.h> |
d7abc0fa | 35 | #include <asm/asm.h> |
63bcff2a | 36 | #include <asm/smap.h> |
3891a04a | 37 | #include <asm/pgtable_types.h> |
d7e7528b | 38 | #include <linux/err.h> |
1da177e4 | 39 | |
86a1c34a RM |
40 | /* Avoid __ASSEMBLER__'ifying <linux/audit.h> just for this. */ |
41 | #include <linux/elf-em.h> | |
4d732138 IM |
42 | #define AUDIT_ARCH_X86_64 (EM_X86_64|__AUDIT_ARCH_64BIT|__AUDIT_ARCH_LE) |
43 | #define __AUDIT_ARCH_64BIT 0x80000000 | |
44 | #define __AUDIT_ARCH_LE 0x40000000 | |
ea714547 | 45 | |
4d732138 IM |
46 | .code64 |
47 | .section .entry.text, "ax" | |
16444a8a | 48 | |
72fe4858 | 49 | #ifdef CONFIG_PARAVIRT |
2be29982 | 50 | ENTRY(native_usergs_sysret64) |
72fe4858 GOC |
51 | swapgs |
52 | sysretq | |
b3baaa13 | 53 | ENDPROC(native_usergs_sysret64) |
72fe4858 GOC |
54 | #endif /* CONFIG_PARAVIRT */ |
55 | ||
f2db9382 | 56 | .macro TRACE_IRQS_IRETQ |
2601e64d | 57 | #ifdef CONFIG_TRACE_IRQFLAGS |
4d732138 IM |
58 | bt $9, EFLAGS(%rsp) /* interrupts off? */ |
59 | jnc 1f | |
2601e64d IM |
60 | TRACE_IRQS_ON |
61 | 1: | |
62 | #endif | |
63 | .endm | |
64 | ||
5963e317 SR |
65 | /* |
66 | * When dynamic function tracer is enabled it will add a breakpoint | |
67 | * to all locations that it is about to modify, sync CPUs, update | |
68 | * all the code, sync CPUs, then remove the breakpoints. In this time | |
69 | * if lockdep is enabled, it might jump back into the debug handler | |
70 | * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). | |
71 | * | |
72 | * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to | |
73 | * make sure the stack pointer does not get reset back to the top | |
74 | * of the debug stack, and instead just reuses the current stack. | |
75 | */ | |
76 | #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) | |
77 | ||
78 | .macro TRACE_IRQS_OFF_DEBUG | |
4d732138 | 79 | call debug_stack_set_zero |
5963e317 | 80 | TRACE_IRQS_OFF |
4d732138 | 81 | call debug_stack_reset |
5963e317 SR |
82 | .endm |
83 | ||
84 | .macro TRACE_IRQS_ON_DEBUG | |
4d732138 | 85 | call debug_stack_set_zero |
5963e317 | 86 | TRACE_IRQS_ON |
4d732138 | 87 | call debug_stack_reset |
5963e317 SR |
88 | .endm |
89 | ||
f2db9382 | 90 | .macro TRACE_IRQS_IRETQ_DEBUG |
4d732138 IM |
91 | bt $9, EFLAGS(%rsp) /* interrupts off? */ |
92 | jnc 1f | |
5963e317 SR |
93 | TRACE_IRQS_ON_DEBUG |
94 | 1: | |
95 | .endm | |
96 | ||
97 | #else | |
4d732138 IM |
98 | # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF |
99 | # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON | |
100 | # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ | |
5963e317 SR |
101 | #endif |
102 | ||
1da177e4 | 103 | /* |
4d732138 | 104 | * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. |
1da177e4 | 105 | * |
fda57b22 AL |
106 | * This is the only entry point used for 64-bit system calls. The |
107 | * hardware interface is reasonably well designed and the register to | |
108 | * argument mapping Linux uses fits well with the registers that are | |
109 | * available when SYSCALL is used. | |
110 | * | |
111 | * SYSCALL instructions can be found inlined in libc implementations as | |
112 | * well as some other programs and libraries. There are also a handful | |
113 | * of SYSCALL instructions in the vDSO used, for example, as a | |
114 | * clock_gettimeofday fallback. | |
115 | * | |
4d732138 | 116 | * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, |
b87cf63e DV |
117 | * then loads new ss, cs, and rip from previously programmed MSRs. |
118 | * rflags gets masked by a value from another MSR (so CLD and CLAC | |
119 | * are not needed). SYSCALL does not save anything on the stack | |
120 | * and does not change rsp. | |
121 | * | |
122 | * Registers on entry: | |
1da177e4 | 123 | * rax system call number |
b87cf63e DV |
124 | * rcx return address |
125 | * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) | |
1da177e4 | 126 | * rdi arg0 |
1da177e4 | 127 | * rsi arg1 |
0bd7b798 | 128 | * rdx arg2 |
b87cf63e | 129 | * r10 arg3 (needs to be moved to rcx to conform to C ABI) |
1da177e4 LT |
130 | * r8 arg4 |
131 | * r9 arg5 | |
4d732138 | 132 | * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) |
0bd7b798 | 133 | * |
1da177e4 LT |
134 | * Only called from user space. |
135 | * | |
7fcb3bc3 | 136 | * When user can change pt_regs->foo always force IRET. That is because |
7bf36bbc AK |
137 | * it deals with uncanonical addresses better. SYSRET has trouble |
138 | * with them due to bugs in both AMD and Intel CPUs. | |
0bd7b798 | 139 | */ |
1da177e4 | 140 | |
b2502b41 | 141 | ENTRY(entry_SYSCALL_64) |
9ed8e7d8 DV |
142 | /* |
143 | * Interrupts are off on entry. | |
144 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
145 | * it is too small to ever cause noticeable irq latency. | |
146 | */ | |
72fe4858 GOC |
147 | SWAPGS_UNSAFE_STACK |
148 | /* | |
149 | * A hypervisor implementation might want to use a label | |
150 | * after the swapgs, so that it can do the swapgs | |
151 | * for the guest and jump here on syscall. | |
152 | */ | |
b2502b41 | 153 | GLOBAL(entry_SYSCALL_64_after_swapgs) |
72fe4858 | 154 | |
4d732138 IM |
155 | movq %rsp, PER_CPU_VAR(rsp_scratch) |
156 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
9ed8e7d8 | 157 | |
1e423bff AL |
158 | TRACE_IRQS_OFF |
159 | ||
9ed8e7d8 | 160 | /* Construct struct pt_regs on stack */ |
4d732138 IM |
161 | pushq $__USER_DS /* pt_regs->ss */ |
162 | pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ | |
4d732138 IM |
163 | pushq %r11 /* pt_regs->flags */ |
164 | pushq $__USER_CS /* pt_regs->cs */ | |
165 | pushq %rcx /* pt_regs->ip */ | |
166 | pushq %rax /* pt_regs->orig_ax */ | |
167 | pushq %rdi /* pt_regs->di */ | |
168 | pushq %rsi /* pt_regs->si */ | |
169 | pushq %rdx /* pt_regs->dx */ | |
170 | pushq %rcx /* pt_regs->cx */ | |
171 | pushq $-ENOSYS /* pt_regs->ax */ | |
172 | pushq %r8 /* pt_regs->r8 */ | |
173 | pushq %r9 /* pt_regs->r9 */ | |
174 | pushq %r10 /* pt_regs->r10 */ | |
175 | pushq %r11 /* pt_regs->r11 */ | |
176 | sub $(6*8), %rsp /* pt_regs->bp, bx, r12-15 not saved */ | |
177 | ||
1e423bff AL |
178 | /* |
179 | * If we need to do entry work or if we guess we'll need to do | |
180 | * exit work, go straight to the slow path. | |
181 | */ | |
182 | testl $_TIF_WORK_SYSCALL_ENTRY|_TIF_ALLWORK_MASK, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) | |
183 | jnz entry_SYSCALL64_slow_path | |
184 | ||
b2502b41 | 185 | entry_SYSCALL_64_fastpath: |
1e423bff AL |
186 | /* |
187 | * Easy case: enable interrupts and issue the syscall. If the syscall | |
188 | * needs pt_regs, we'll call a stub that disables interrupts again | |
189 | * and jumps to the slow path. | |
190 | */ | |
191 | TRACE_IRQS_ON | |
192 | ENABLE_INTERRUPTS(CLBR_NONE) | |
fca460f9 | 193 | #if __SYSCALL_MASK == ~0 |
4d732138 | 194 | cmpq $__NR_syscall_max, %rax |
fca460f9 | 195 | #else |
4d732138 IM |
196 | andl $__SYSCALL_MASK, %eax |
197 | cmpl $__NR_syscall_max, %eax | |
fca460f9 | 198 | #endif |
4d732138 IM |
199 | ja 1f /* return -ENOSYS (already in pt_regs->ax) */ |
200 | movq %r10, %rcx | |
302f5b26 AL |
201 | |
202 | /* | |
203 | * This call instruction is handled specially in stub_ptregs_64. | |
b7765086 AL |
204 | * It might end up jumping to the slow path. If it jumps, RAX |
205 | * and all argument registers are clobbered. | |
302f5b26 | 206 | */ |
4d732138 | 207 | call *sys_call_table(, %rax, 8) |
302f5b26 AL |
208 | .Lentry_SYSCALL_64_after_fastpath_call: |
209 | ||
4d732138 | 210 | movq %rax, RAX(%rsp) |
146b2b09 | 211 | 1: |
b3494a4a AL |
212 | |
213 | /* | |
1e423bff AL |
214 | * If we get here, then we know that pt_regs is clean for SYSRET64. |
215 | * If we see that no exit work is required (which we are required | |
216 | * to check with IRQs off), then we can go straight to SYSRET64. | |
b3494a4a | 217 | */ |
1e423bff AL |
218 | DISABLE_INTERRUPTS(CLBR_NONE) |
219 | TRACE_IRQS_OFF | |
4d732138 | 220 | testl $_TIF_ALLWORK_MASK, ASM_THREAD_INFO(TI_flags, %rsp, SIZEOF_PTREGS) |
1e423bff | 221 | jnz 1f |
b3494a4a | 222 | |
1e423bff AL |
223 | LOCKDEP_SYS_EXIT |
224 | TRACE_IRQS_ON /* user mode is traced as IRQs on */ | |
eb2a54c3 AL |
225 | movq RIP(%rsp), %rcx |
226 | movq EFLAGS(%rsp), %r11 | |
227 | RESTORE_C_REGS_EXCEPT_RCX_R11 | |
4d732138 | 228 | movq RSP(%rsp), %rsp |
2be29982 | 229 | USERGS_SYSRET64 |
1da177e4 | 230 | |
1e423bff AL |
231 | 1: |
232 | /* | |
233 | * The fast path looked good when we started, but something changed | |
234 | * along the way and we need to switch to the slow path. Calling | |
235 | * raise(3) will trigger this, for example. IRQs are off. | |
236 | */ | |
29ea1b25 AL |
237 | TRACE_IRQS_ON |
238 | ENABLE_INTERRUPTS(CLBR_NONE) | |
76f5df43 | 239 | SAVE_EXTRA_REGS |
4d732138 | 240 | movq %rsp, %rdi |
1e423bff AL |
241 | call syscall_return_slowpath /* returns with IRQs disabled */ |
242 | jmp return_from_SYSCALL_64 | |
0bd7b798 | 243 | |
1e423bff AL |
244 | entry_SYSCALL64_slow_path: |
245 | /* IRQs are off. */ | |
76f5df43 | 246 | SAVE_EXTRA_REGS |
29ea1b25 | 247 | movq %rsp, %rdi |
1e423bff AL |
248 | call do_syscall_64 /* returns with IRQs disabled */ |
249 | ||
250 | return_from_SYSCALL_64: | |
76f5df43 | 251 | RESTORE_EXTRA_REGS |
29ea1b25 | 252 | TRACE_IRQS_IRETQ /* we're about to change IF */ |
fffbb5dc DV |
253 | |
254 | /* | |
255 | * Try to use SYSRET instead of IRET if we're returning to | |
256 | * a completely clean 64-bit userspace context. | |
257 | */ | |
4d732138 IM |
258 | movq RCX(%rsp), %rcx |
259 | movq RIP(%rsp), %r11 | |
260 | cmpq %rcx, %r11 /* RCX == RIP */ | |
261 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
262 | |
263 | /* | |
264 | * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP | |
265 | * in kernel space. This essentially lets the user take over | |
17be0aec | 266 | * the kernel, since userspace controls RSP. |
fffbb5dc | 267 | * |
17be0aec | 268 | * If width of "canonical tail" ever becomes variable, this will need |
fffbb5dc DV |
269 | * to be updated to remain correct on both old and new CPUs. |
270 | */ | |
271 | .ifne __VIRTUAL_MASK_SHIFT - 47 | |
272 | .error "virtual address width changed -- SYSRET checks need update" | |
273 | .endif | |
4d732138 | 274 | |
17be0aec DV |
275 | /* Change top 16 bits to be the sign-extension of 47th bit */ |
276 | shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
277 | sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
4d732138 | 278 | |
17be0aec DV |
279 | /* If this changed %rcx, it was not canonical */ |
280 | cmpq %rcx, %r11 | |
281 | jne opportunistic_sysret_failed | |
fffbb5dc | 282 | |
4d732138 IM |
283 | cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ |
284 | jne opportunistic_sysret_failed | |
fffbb5dc | 285 | |
4d732138 IM |
286 | movq R11(%rsp), %r11 |
287 | cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ | |
288 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
289 | |
290 | /* | |
291 | * SYSRET can't restore RF. SYSRET can restore TF, but unlike IRET, | |
292 | * restoring TF results in a trap from userspace immediately after | |
293 | * SYSRET. This would cause an infinite loop whenever #DB happens | |
294 | * with register state that satisfies the opportunistic SYSRET | |
295 | * conditions. For example, single-stepping this user code: | |
296 | * | |
4d732138 | 297 | * movq $stuck_here, %rcx |
fffbb5dc DV |
298 | * pushfq |
299 | * popq %r11 | |
300 | * stuck_here: | |
301 | * | |
302 | * would never get past 'stuck_here'. | |
303 | */ | |
4d732138 IM |
304 | testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 |
305 | jnz opportunistic_sysret_failed | |
fffbb5dc DV |
306 | |
307 | /* nothing to check for RSP */ | |
308 | ||
4d732138 IM |
309 | cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ |
310 | jne opportunistic_sysret_failed | |
fffbb5dc DV |
311 | |
312 | /* | |
4d732138 IM |
313 | * We win! This label is here just for ease of understanding |
314 | * perf profiles. Nothing jumps here. | |
fffbb5dc DV |
315 | */ |
316 | syscall_return_via_sysret: | |
17be0aec DV |
317 | /* rcx and r11 are already restored (see code above) */ |
318 | RESTORE_C_REGS_EXCEPT_RCX_R11 | |
4d732138 | 319 | movq RSP(%rsp), %rsp |
fffbb5dc | 320 | USERGS_SYSRET64 |
fffbb5dc DV |
321 | |
322 | opportunistic_sysret_failed: | |
323 | SWAPGS | |
324 | jmp restore_c_regs_and_iret | |
b2502b41 | 325 | END(entry_SYSCALL_64) |
0bd7b798 | 326 | |
302f5b26 AL |
327 | ENTRY(stub_ptregs_64) |
328 | /* | |
329 | * Syscalls marked as needing ptregs land here. | |
b7765086 AL |
330 | * If we are on the fast path, we need to save the extra regs, |
331 | * which we achieve by trying again on the slow path. If we are on | |
332 | * the slow path, the extra regs are already saved. | |
302f5b26 AL |
333 | * |
334 | * RAX stores a pointer to the C function implementing the syscall. | |
b7765086 | 335 | * IRQs are on. |
302f5b26 AL |
336 | */ |
337 | cmpq $.Lentry_SYSCALL_64_after_fastpath_call, (%rsp) | |
338 | jne 1f | |
339 | ||
b7765086 AL |
340 | /* |
341 | * Called from fast path -- disable IRQs again, pop return address | |
342 | * and jump to slow path | |
343 | */ | |
344 | DISABLE_INTERRUPTS(CLBR_NONE) | |
345 | TRACE_IRQS_OFF | |
302f5b26 | 346 | popq %rax |
b7765086 | 347 | jmp entry_SYSCALL64_slow_path |
302f5b26 AL |
348 | |
349 | 1: | |
b3830e8d | 350 | jmp *%rax /* Called from C */ |
302f5b26 AL |
351 | END(stub_ptregs_64) |
352 | ||
353 | .macro ptregs_stub func | |
354 | ENTRY(ptregs_\func) | |
355 | leaq \func(%rip), %rax | |
356 | jmp stub_ptregs_64 | |
357 | END(ptregs_\func) | |
358 | .endm | |
359 | ||
360 | /* Instantiate ptregs_stub for each ptregs-using syscall */ | |
361 | #define __SYSCALL_64_QUAL_(sym) | |
362 | #define __SYSCALL_64_QUAL_ptregs(sym) ptregs_stub sym | |
363 | #define __SYSCALL_64(nr, sym, qual) __SYSCALL_64_QUAL_##qual(sym) | |
364 | #include <asm/syscalls_64.h> | |
fffbb5dc | 365 | |
1eeb207f DV |
366 | /* |
367 | * A newly forked process directly context switches into this address. | |
368 | * | |
369 | * rdi: prev task we switched from | |
370 | */ | |
371 | ENTRY(ret_from_fork) | |
4d732138 | 372 | LOCK ; btr $TIF_FORK, TI_flags(%r8) |
1eeb207f | 373 | |
4d732138 | 374 | call schedule_tail /* rdi: 'prev' task parameter */ |
1eeb207f | 375 | |
4d732138 | 376 | testb $3, CS(%rsp) /* from kernel_thread? */ |
24d978b7 | 377 | jnz 1f |
1eeb207f | 378 | |
1e3fbb8a | 379 | /* |
24d978b7 AL |
380 | * We came from kernel_thread. This code path is quite twisted, and |
381 | * someone should clean it up. | |
382 | * | |
383 | * copy_thread_tls stashes the function pointer in RBX and the | |
384 | * parameter to be passed in RBP. The called function is permitted | |
385 | * to call do_execve and thereby jump to user mode. | |
1e3fbb8a | 386 | */ |
24d978b7 AL |
387 | movq RBP(%rsp), %rdi |
388 | call *RBX(%rsp) | |
389 | movl $0, RAX(%rsp) | |
1eeb207f | 390 | |
4d732138 | 391 | /* |
24d978b7 AL |
392 | * Fall through as though we're exiting a syscall. This makes a |
393 | * twisted sort of sense if we just called do_execve. | |
4d732138 | 394 | */ |
24d978b7 AL |
395 | |
396 | 1: | |
397 | movq %rsp, %rdi | |
398 | call syscall_return_slowpath /* returns with IRQs disabled */ | |
399 | TRACE_IRQS_ON /* user mode is traced as IRQS on */ | |
400 | SWAPGS | |
401 | jmp restore_regs_and_iret | |
1eeb207f DV |
402 | END(ret_from_fork) |
403 | ||
939b7871 | 404 | /* |
3304c9c3 DV |
405 | * Build the entry stubs with some assembler magic. |
406 | * We pack 1 stub into every 8-byte block. | |
939b7871 | 407 | */ |
3304c9c3 | 408 | .align 8 |
939b7871 | 409 | ENTRY(irq_entries_start) |
3304c9c3 DV |
410 | vector=FIRST_EXTERNAL_VECTOR |
411 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
4d732138 | 412 | pushq $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 DV |
413 | vector=vector+1 |
414 | jmp common_interrupt | |
3304c9c3 DV |
415 | .align 8 |
416 | .endr | |
939b7871 PA |
417 | END(irq_entries_start) |
418 | ||
d99015b1 | 419 | /* |
1da177e4 LT |
420 | * Interrupt entry/exit. |
421 | * | |
422 | * Interrupt entry points save only callee clobbered registers in fast path. | |
d99015b1 AH |
423 | * |
424 | * Entry runs with interrupts off. | |
425 | */ | |
1da177e4 | 426 | |
722024db | 427 | /* 0(%rsp): ~(interrupt number) */ |
1da177e4 | 428 | .macro interrupt func |
f6f64681 | 429 | cld |
ff467594 AL |
430 | ALLOC_PT_GPREGS_ON_STACK |
431 | SAVE_C_REGS | |
432 | SAVE_EXTRA_REGS | |
76f5df43 | 433 | |
ff467594 | 434 | testb $3, CS(%rsp) |
dde74f2e | 435 | jz 1f |
02bc7768 AL |
436 | |
437 | /* | |
438 | * IRQ from user mode. Switch to kernel gsbase and inform context | |
439 | * tracking that we're in kernel mode. | |
440 | */ | |
f6f64681 | 441 | SWAPGS |
f1075053 AL |
442 | |
443 | /* | |
444 | * We need to tell lockdep that IRQs are off. We can't do this until | |
445 | * we fix gsbase, and we should do it before enter_from_user_mode | |
446 | * (which can take locks). Since TRACE_IRQS_OFF idempotent, | |
447 | * the simplest way to handle it is to just call it twice if | |
448 | * we enter from user mode. There's no reason to optimize this since | |
449 | * TRACE_IRQS_OFF is a no-op if lockdep is off. | |
450 | */ | |
451 | TRACE_IRQS_OFF | |
452 | ||
478dc89c | 453 | CALL_enter_from_user_mode |
02bc7768 | 454 | |
76f5df43 | 455 | 1: |
f6f64681 | 456 | /* |
e90e147c | 457 | * Save previous stack pointer, optionally switch to interrupt stack. |
f6f64681 DV |
458 | * irq_count is used to check if a CPU is already on an interrupt stack |
459 | * or not. While this is essentially redundant with preempt_count it is | |
460 | * a little cheaper to use a separate counter in the PDA (short of | |
461 | * moving irq_enter into assembly, which would be too much work) | |
462 | */ | |
a586f98e | 463 | movq %rsp, %rdi |
4d732138 IM |
464 | incl PER_CPU_VAR(irq_count) |
465 | cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp | |
a586f98e | 466 | pushq %rdi |
f6f64681 DV |
467 | /* We entered an interrupt context - irqs are off: */ |
468 | TRACE_IRQS_OFF | |
469 | ||
a586f98e | 470 | call \func /* rdi points to pt_regs */ |
1da177e4 LT |
471 | .endm |
472 | ||
722024db AH |
473 | /* |
474 | * The interrupt stubs push (~vector+0x80) onto the stack and | |
475 | * then jump to common_interrupt. | |
476 | */ | |
939b7871 PA |
477 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
478 | common_interrupt: | |
ee4eb87b | 479 | ASM_CLAC |
4d732138 | 480 | addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ |
1da177e4 | 481 | interrupt do_IRQ |
34061f13 | 482 | /* 0(%rsp): old RSP */ |
7effaa88 | 483 | ret_from_intr: |
72fe4858 | 484 | DISABLE_INTERRUPTS(CLBR_NONE) |
2601e64d | 485 | TRACE_IRQS_OFF |
4d732138 | 486 | decl PER_CPU_VAR(irq_count) |
625dbc3b | 487 | |
a2bbe750 | 488 | /* Restore saved previous stack */ |
ff467594 | 489 | popq %rsp |
625dbc3b | 490 | |
03335e95 | 491 | testb $3, CS(%rsp) |
dde74f2e | 492 | jz retint_kernel |
4d732138 | 493 | |
02bc7768 | 494 | /* Interrupt came from user space */ |
02bc7768 AL |
495 | GLOBAL(retint_user) |
496 | mov %rsp,%rdi | |
497 | call prepare_exit_to_usermode | |
2601e64d | 498 | TRACE_IRQS_IRETQ |
72fe4858 | 499 | SWAPGS |
ff467594 | 500 | jmp restore_regs_and_iret |
2601e64d | 501 | |
627276cb | 502 | /* Returning to kernel space */ |
6ba71b76 | 503 | retint_kernel: |
627276cb DV |
504 | #ifdef CONFIG_PREEMPT |
505 | /* Interrupts are off */ | |
506 | /* Check if we need preemption */ | |
4d732138 | 507 | bt $9, EFLAGS(%rsp) /* were interrupts off? */ |
6ba71b76 | 508 | jnc 1f |
4d732138 | 509 | 0: cmpl $0, PER_CPU_VAR(__preempt_count) |
36acef25 | 510 | jnz 1f |
627276cb | 511 | call preempt_schedule_irq |
36acef25 | 512 | jmp 0b |
6ba71b76 | 513 | 1: |
627276cb | 514 | #endif |
2601e64d IM |
515 | /* |
516 | * The iretq could re-enable interrupts: | |
517 | */ | |
518 | TRACE_IRQS_IRETQ | |
fffbb5dc DV |
519 | |
520 | /* | |
521 | * At this label, code paths which return to kernel and to user, | |
522 | * which come from interrupts/exception and from syscalls, merge. | |
523 | */ | |
ee08c6bd | 524 | GLOBAL(restore_regs_and_iret) |
ff467594 | 525 | RESTORE_EXTRA_REGS |
fffbb5dc | 526 | restore_c_regs_and_iret: |
76f5df43 DV |
527 | RESTORE_C_REGS |
528 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
7209a75d AL |
529 | INTERRUPT_RETURN |
530 | ||
531 | ENTRY(native_iret) | |
3891a04a PA |
532 | /* |
533 | * Are we returning to a stack segment from the LDT? Note: in | |
534 | * 64-bit mode SS:RSP on the exception stack is always valid. | |
535 | */ | |
34273f41 | 536 | #ifdef CONFIG_X86_ESPFIX64 |
4d732138 IM |
537 | testb $4, (SS-RIP)(%rsp) |
538 | jnz native_irq_return_ldt | |
34273f41 | 539 | #endif |
3891a04a | 540 | |
af726f21 | 541 | .global native_irq_return_iret |
7209a75d | 542 | native_irq_return_iret: |
b645af2d AL |
543 | /* |
544 | * This may fault. Non-paranoid faults on return to userspace are | |
545 | * handled by fixup_bad_iret. These include #SS, #GP, and #NP. | |
546 | * Double-faults due to espfix64 are handled in do_double_fault. | |
547 | * Other faults here are fatal. | |
548 | */ | |
1da177e4 | 549 | iretq |
3701d863 | 550 | |
34273f41 | 551 | #ifdef CONFIG_X86_ESPFIX64 |
7209a75d | 552 | native_irq_return_ldt: |
4d732138 IM |
553 | pushq %rax |
554 | pushq %rdi | |
3891a04a | 555 | SWAPGS |
4d732138 IM |
556 | movq PER_CPU_VAR(espfix_waddr), %rdi |
557 | movq %rax, (0*8)(%rdi) /* RAX */ | |
558 | movq (2*8)(%rsp), %rax /* RIP */ | |
559 | movq %rax, (1*8)(%rdi) | |
560 | movq (3*8)(%rsp), %rax /* CS */ | |
561 | movq %rax, (2*8)(%rdi) | |
562 | movq (4*8)(%rsp), %rax /* RFLAGS */ | |
563 | movq %rax, (3*8)(%rdi) | |
564 | movq (6*8)(%rsp), %rax /* SS */ | |
565 | movq %rax, (5*8)(%rdi) | |
566 | movq (5*8)(%rsp), %rax /* RSP */ | |
567 | movq %rax, (4*8)(%rdi) | |
568 | andl $0xffff0000, %eax | |
569 | popq %rdi | |
570 | orq PER_CPU_VAR(espfix_stack), %rax | |
3891a04a | 571 | SWAPGS |
4d732138 IM |
572 | movq %rax, %rsp |
573 | popq %rax | |
574 | jmp native_irq_return_iret | |
34273f41 | 575 | #endif |
4b787e0b | 576 | END(common_interrupt) |
3891a04a | 577 | |
1da177e4 LT |
578 | /* |
579 | * APIC interrupts. | |
0bd7b798 | 580 | */ |
cf910e83 | 581 | .macro apicinterrupt3 num sym do_sym |
322648d1 | 582 | ENTRY(\sym) |
ee4eb87b | 583 | ASM_CLAC |
4d732138 | 584 | pushq $~(\num) |
39e95433 | 585 | .Lcommon_\sym: |
322648d1 | 586 | interrupt \do_sym |
4d732138 | 587 | jmp ret_from_intr |
322648d1 AH |
588 | END(\sym) |
589 | .endm | |
1da177e4 | 590 | |
cf910e83 SA |
591 | #ifdef CONFIG_TRACING |
592 | #define trace(sym) trace_##sym | |
593 | #define smp_trace(sym) smp_trace_##sym | |
594 | ||
595 | .macro trace_apicinterrupt num sym | |
596 | apicinterrupt3 \num trace(\sym) smp_trace(\sym) | |
597 | .endm | |
598 | #else | |
599 | .macro trace_apicinterrupt num sym do_sym | |
600 | .endm | |
601 | #endif | |
602 | ||
603 | .macro apicinterrupt num sym do_sym | |
604 | apicinterrupt3 \num \sym \do_sym | |
605 | trace_apicinterrupt \num \sym | |
606 | .endm | |
607 | ||
322648d1 | 608 | #ifdef CONFIG_SMP |
4d732138 IM |
609 | apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt |
610 | apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt | |
322648d1 | 611 | #endif |
1da177e4 | 612 | |
03b48632 | 613 | #ifdef CONFIG_X86_UV |
4d732138 | 614 | apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt |
03b48632 | 615 | #endif |
4d732138 IM |
616 | |
617 | apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt | |
618 | apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi | |
89b831ef | 619 | |
d78f2664 | 620 | #ifdef CONFIG_HAVE_KVM |
4d732138 IM |
621 | apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi |
622 | apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi | |
d78f2664 YZ |
623 | #endif |
624 | ||
33e5ff63 | 625 | #ifdef CONFIG_X86_MCE_THRESHOLD |
4d732138 | 626 | apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt |
33e5ff63 SA |
627 | #endif |
628 | ||
24fd78a8 | 629 | #ifdef CONFIG_X86_MCE_AMD |
4d732138 | 630 | apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt |
24fd78a8 AG |
631 | #endif |
632 | ||
33e5ff63 | 633 | #ifdef CONFIG_X86_THERMAL_VECTOR |
4d732138 | 634 | apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt |
33e5ff63 | 635 | #endif |
1812924b | 636 | |
322648d1 | 637 | #ifdef CONFIG_SMP |
4d732138 IM |
638 | apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt |
639 | apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt | |
640 | apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt | |
322648d1 | 641 | #endif |
1da177e4 | 642 | |
4d732138 IM |
643 | apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt |
644 | apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt | |
0bd7b798 | 645 | |
e360adbe | 646 | #ifdef CONFIG_IRQ_WORK |
4d732138 | 647 | apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt |
241771ef IM |
648 | #endif |
649 | ||
1da177e4 LT |
650 | /* |
651 | * Exception entry points. | |
0bd7b798 | 652 | */ |
9b476688 | 653 | #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss) + (TSS_ist + ((x) - 1) * 8) |
577ed45e AL |
654 | |
655 | .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 | |
322648d1 | 656 | ENTRY(\sym) |
577ed45e AL |
657 | /* Sanity check */ |
658 | .if \shift_ist != -1 && \paranoid == 0 | |
659 | .error "using shift_ist requires paranoid=1" | |
660 | .endif | |
661 | ||
ee4eb87b | 662 | ASM_CLAC |
b8b1d08b | 663 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
cb5dd2c5 AL |
664 | |
665 | .ifeq \has_error_code | |
4d732138 | 666 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
cb5dd2c5 AL |
667 | .endif |
668 | ||
76f5df43 | 669 | ALLOC_PT_GPREGS_ON_STACK |
cb5dd2c5 AL |
670 | |
671 | .if \paranoid | |
48e08d0f | 672 | .if \paranoid == 1 |
4d732138 IM |
673 | testb $3, CS(%rsp) /* If coming from userspace, switch stacks */ |
674 | jnz 1f | |
48e08d0f | 675 | .endif |
4d732138 | 676 | call paranoid_entry |
cb5dd2c5 | 677 | .else |
4d732138 | 678 | call error_entry |
cb5dd2c5 | 679 | .endif |
ebfc453e | 680 | /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ |
cb5dd2c5 | 681 | |
cb5dd2c5 | 682 | .if \paranoid |
577ed45e | 683 | .if \shift_ist != -1 |
4d732138 | 684 | TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ |
577ed45e | 685 | .else |
b8b1d08b | 686 | TRACE_IRQS_OFF |
cb5dd2c5 | 687 | .endif |
577ed45e | 688 | .endif |
cb5dd2c5 | 689 | |
4d732138 | 690 | movq %rsp, %rdi /* pt_regs pointer */ |
cb5dd2c5 AL |
691 | |
692 | .if \has_error_code | |
4d732138 IM |
693 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
694 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
cb5dd2c5 | 695 | .else |
4d732138 | 696 | xorl %esi, %esi /* no error code */ |
cb5dd2c5 AL |
697 | .endif |
698 | ||
577ed45e | 699 | .if \shift_ist != -1 |
4d732138 | 700 | subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
701 | .endif |
702 | ||
4d732138 | 703 | call \do_sym |
cb5dd2c5 | 704 | |
577ed45e | 705 | .if \shift_ist != -1 |
4d732138 | 706 | addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
707 | .endif |
708 | ||
ebfc453e | 709 | /* these procedures expect "no swapgs" flag in ebx */ |
cb5dd2c5 | 710 | .if \paranoid |
4d732138 | 711 | jmp paranoid_exit |
cb5dd2c5 | 712 | .else |
4d732138 | 713 | jmp error_exit |
cb5dd2c5 AL |
714 | .endif |
715 | ||
48e08d0f | 716 | .if \paranoid == 1 |
48e08d0f AL |
717 | /* |
718 | * Paranoid entry from userspace. Switch stacks and treat it | |
719 | * as a normal entry. This means that paranoid handlers | |
720 | * run in real process context if user_mode(regs). | |
721 | */ | |
722 | 1: | |
4d732138 | 723 | call error_entry |
48e08d0f | 724 | |
48e08d0f | 725 | |
4d732138 IM |
726 | movq %rsp, %rdi /* pt_regs pointer */ |
727 | call sync_regs | |
728 | movq %rax, %rsp /* switch stack */ | |
48e08d0f | 729 | |
4d732138 | 730 | movq %rsp, %rdi /* pt_regs pointer */ |
48e08d0f AL |
731 | |
732 | .if \has_error_code | |
4d732138 IM |
733 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
734 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
48e08d0f | 735 | .else |
4d732138 | 736 | xorl %esi, %esi /* no error code */ |
48e08d0f AL |
737 | .endif |
738 | ||
4d732138 | 739 | call \do_sym |
48e08d0f | 740 | |
4d732138 | 741 | jmp error_exit /* %ebx: no swapgs flag */ |
48e08d0f | 742 | .endif |
ddeb8f21 | 743 | END(\sym) |
322648d1 | 744 | .endm |
b8b1d08b | 745 | |
25c74b10 | 746 | #ifdef CONFIG_TRACING |
cb5dd2c5 AL |
747 | .macro trace_idtentry sym do_sym has_error_code:req |
748 | idtentry trace(\sym) trace(\do_sym) has_error_code=\has_error_code | |
749 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
750 | .endm |
751 | #else | |
cb5dd2c5 AL |
752 | .macro trace_idtentry sym do_sym has_error_code:req |
753 | idtentry \sym \do_sym has_error_code=\has_error_code | |
25c74b10 SA |
754 | .endm |
755 | #endif | |
756 | ||
4d732138 IM |
757 | idtentry divide_error do_divide_error has_error_code=0 |
758 | idtentry overflow do_overflow has_error_code=0 | |
759 | idtentry bounds do_bounds has_error_code=0 | |
760 | idtentry invalid_op do_invalid_op has_error_code=0 | |
761 | idtentry device_not_available do_device_not_available has_error_code=0 | |
762 | idtentry double_fault do_double_fault has_error_code=1 paranoid=2 | |
763 | idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 | |
764 | idtentry invalid_TSS do_invalid_TSS has_error_code=1 | |
765 | idtentry segment_not_present do_segment_not_present has_error_code=1 | |
766 | idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 | |
767 | idtentry coprocessor_error do_coprocessor_error has_error_code=0 | |
768 | idtentry alignment_check do_alignment_check has_error_code=1 | |
769 | idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 | |
770 | ||
771 | ||
772 | /* | |
773 | * Reload gs selector with exception handling | |
774 | * edi: new selector | |
775 | */ | |
9f9d489a | 776 | ENTRY(native_load_gs_index) |
131484c8 | 777 | pushfq |
b8aa287f | 778 | DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) |
9f1e87ea | 779 | SWAPGS |
42c748bb | 780 | .Lgs_change: |
4d732138 | 781 | movl %edi, %gs |
96e5d28a | 782 | 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE |
72fe4858 | 783 | SWAPGS |
131484c8 | 784 | popfq |
9f1e87ea | 785 | ret |
6efdcfaf | 786 | END(native_load_gs_index) |
0bd7b798 | 787 | |
42c748bb | 788 | _ASM_EXTABLE(.Lgs_change, bad_gs) |
4d732138 | 789 | .section .fixup, "ax" |
1da177e4 | 790 | /* running with kernelgs */ |
0bd7b798 | 791 | bad_gs: |
4d732138 | 792 | SWAPGS /* switch back to user gs */ |
b038c842 AL |
793 | .macro ZAP_GS |
794 | /* This can't be a string because the preprocessor needs to see it. */ | |
795 | movl $__USER_DS, %eax | |
796 | movl %eax, %gs | |
797 | .endm | |
798 | ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG | |
4d732138 IM |
799 | xorl %eax, %eax |
800 | movl %eax, %gs | |
801 | jmp 2b | |
9f1e87ea | 802 | .previous |
0bd7b798 | 803 | |
2699500b | 804 | /* Call softirq on interrupt stack. Interrupts are off. */ |
7d65f4a6 | 805 | ENTRY(do_softirq_own_stack) |
4d732138 IM |
806 | pushq %rbp |
807 | mov %rsp, %rbp | |
808 | incl PER_CPU_VAR(irq_count) | |
809 | cmove PER_CPU_VAR(irq_stack_ptr), %rsp | |
810 | push %rbp /* frame pointer backlink */ | |
811 | call __do_softirq | |
2699500b | 812 | leaveq |
4d732138 | 813 | decl PER_CPU_VAR(irq_count) |
ed6b676c | 814 | ret |
7d65f4a6 | 815 | END(do_softirq_own_stack) |
75154f40 | 816 | |
3d75e1b8 | 817 | #ifdef CONFIG_XEN |
cb5dd2c5 | 818 | idtentry xen_hypervisor_callback xen_do_hypervisor_callback has_error_code=0 |
3d75e1b8 JF |
819 | |
820 | /* | |
9f1e87ea CG |
821 | * A note on the "critical region" in our callback handler. |
822 | * We want to avoid stacking callback handlers due to events occurring | |
823 | * during handling of the last event. To do this, we keep events disabled | |
824 | * until we've done all processing. HOWEVER, we must enable events before | |
825 | * popping the stack frame (can't be done atomically) and so it would still | |
826 | * be possible to get enough handler activations to overflow the stack. | |
827 | * Although unlikely, bugs of that kind are hard to track down, so we'd | |
828 | * like to avoid the possibility. | |
829 | * So, on entry to the handler we detect whether we interrupted an | |
830 | * existing activation in its critical region -- if so, we pop the current | |
831 | * activation and restart the handler using the previous one. | |
832 | */ | |
4d732138 IM |
833 | ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ |
834 | ||
9f1e87ea CG |
835 | /* |
836 | * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will | |
837 | * see the correct pointer to the pt_regs | |
838 | */ | |
4d732138 IM |
839 | movq %rdi, %rsp /* we don't return, adjust the stack frame */ |
840 | 11: incl PER_CPU_VAR(irq_count) | |
841 | movq %rsp, %rbp | |
842 | cmovzq PER_CPU_VAR(irq_stack_ptr), %rsp | |
843 | pushq %rbp /* frame pointer backlink */ | |
844 | call xen_evtchn_do_upcall | |
845 | popq %rsp | |
846 | decl PER_CPU_VAR(irq_count) | |
fdfd811d | 847 | #ifndef CONFIG_PREEMPT |
4d732138 | 848 | call xen_maybe_preempt_hcall |
fdfd811d | 849 | #endif |
4d732138 | 850 | jmp error_exit |
371c394a | 851 | END(xen_do_hypervisor_callback) |
3d75e1b8 JF |
852 | |
853 | /* | |
9f1e87ea CG |
854 | * Hypervisor uses this for application faults while it executes. |
855 | * We get here for two reasons: | |
856 | * 1. Fault while reloading DS, ES, FS or GS | |
857 | * 2. Fault while executing IRET | |
858 | * Category 1 we do not need to fix up as Xen has already reloaded all segment | |
859 | * registers that could be reloaded and zeroed the others. | |
860 | * Category 2 we fix up by killing the current process. We cannot use the | |
861 | * normal Linux return path in this case because if we use the IRET hypercall | |
862 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
863 | * We distinguish between categories by comparing each saved segment register | |
864 | * with its current contents: any discrepancy means we in category 1. | |
865 | */ | |
3d75e1b8 | 866 | ENTRY(xen_failsafe_callback) |
4d732138 IM |
867 | movl %ds, %ecx |
868 | cmpw %cx, 0x10(%rsp) | |
869 | jne 1f | |
870 | movl %es, %ecx | |
871 | cmpw %cx, 0x18(%rsp) | |
872 | jne 1f | |
873 | movl %fs, %ecx | |
874 | cmpw %cx, 0x20(%rsp) | |
875 | jne 1f | |
876 | movl %gs, %ecx | |
877 | cmpw %cx, 0x28(%rsp) | |
878 | jne 1f | |
3d75e1b8 | 879 | /* All segments match their saved values => Category 2 (Bad IRET). */ |
4d732138 IM |
880 | movq (%rsp), %rcx |
881 | movq 8(%rsp), %r11 | |
882 | addq $0x30, %rsp | |
883 | pushq $0 /* RIP */ | |
884 | pushq %r11 | |
885 | pushq %rcx | |
886 | jmp general_protection | |
3d75e1b8 | 887 | 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ |
4d732138 IM |
888 | movq (%rsp), %rcx |
889 | movq 8(%rsp), %r11 | |
890 | addq $0x30, %rsp | |
891 | pushq $-1 /* orig_ax = -1 => not a system call */ | |
76f5df43 DV |
892 | ALLOC_PT_GPREGS_ON_STACK |
893 | SAVE_C_REGS | |
894 | SAVE_EXTRA_REGS | |
4d732138 | 895 | jmp error_exit |
3d75e1b8 JF |
896 | END(xen_failsafe_callback) |
897 | ||
cf910e83 | 898 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
38e20b07 SY |
899 | xen_hvm_callback_vector xen_evtchn_do_upcall |
900 | ||
3d75e1b8 | 901 | #endif /* CONFIG_XEN */ |
ddeb8f21 | 902 | |
bc2b0331 | 903 | #if IS_ENABLED(CONFIG_HYPERV) |
cf910e83 | 904 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
bc2b0331 S |
905 | hyperv_callback_vector hyperv_vector_handler |
906 | #endif /* CONFIG_HYPERV */ | |
907 | ||
4d732138 IM |
908 | idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK |
909 | idtentry int3 do_int3 has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK | |
910 | idtentry stack_segment do_stack_segment has_error_code=1 | |
911 | ||
6cac5a92 | 912 | #ifdef CONFIG_XEN |
4d732138 IM |
913 | idtentry xen_debug do_debug has_error_code=0 |
914 | idtentry xen_int3 do_int3 has_error_code=0 | |
915 | idtentry xen_stack_segment do_stack_segment has_error_code=1 | |
6cac5a92 | 916 | #endif |
4d732138 IM |
917 | |
918 | idtentry general_protection do_general_protection has_error_code=1 | |
919 | trace_idtentry page_fault do_page_fault has_error_code=1 | |
920 | ||
631bc487 | 921 | #ifdef CONFIG_KVM_GUEST |
4d732138 | 922 | idtentry async_page_fault do_async_page_fault has_error_code=1 |
631bc487 | 923 | #endif |
4d732138 | 924 | |
ddeb8f21 | 925 | #ifdef CONFIG_X86_MCE |
4d732138 | 926 | idtentry machine_check has_error_code=0 paranoid=1 do_sym=*machine_check_vector(%rip) |
ddeb8f21 AH |
927 | #endif |
928 | ||
ebfc453e DV |
929 | /* |
930 | * Save all registers in pt_regs, and switch gs if needed. | |
931 | * Use slow, but surefire "are we in kernel?" check. | |
932 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
933 | */ | |
934 | ENTRY(paranoid_entry) | |
1eeb207f DV |
935 | cld |
936 | SAVE_C_REGS 8 | |
937 | SAVE_EXTRA_REGS 8 | |
4d732138 IM |
938 | movl $1, %ebx |
939 | movl $MSR_GS_BASE, %ecx | |
1eeb207f | 940 | rdmsr |
4d732138 IM |
941 | testl %edx, %edx |
942 | js 1f /* negative -> in kernel */ | |
1eeb207f | 943 | SWAPGS |
4d732138 | 944 | xorl %ebx, %ebx |
1eeb207f | 945 | 1: ret |
ebfc453e | 946 | END(paranoid_entry) |
ddeb8f21 | 947 | |
ebfc453e DV |
948 | /* |
949 | * "Paranoid" exit path from exception stack. This is invoked | |
950 | * only on return from non-NMI IST interrupts that came | |
951 | * from kernel space. | |
952 | * | |
953 | * We may be returning to very strange contexts (e.g. very early | |
954 | * in syscall entry), so checking for preemption here would | |
955 | * be complicated. Fortunately, we there's no good reason | |
956 | * to try to handle preemption here. | |
4d732138 IM |
957 | * |
958 | * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) | |
ebfc453e | 959 | */ |
ddeb8f21 | 960 | ENTRY(paranoid_exit) |
ddeb8f21 | 961 | DISABLE_INTERRUPTS(CLBR_NONE) |
5963e317 | 962 | TRACE_IRQS_OFF_DEBUG |
4d732138 IM |
963 | testl %ebx, %ebx /* swapgs needed? */ |
964 | jnz paranoid_exit_no_swapgs | |
f2db9382 | 965 | TRACE_IRQS_IRETQ |
ddeb8f21 | 966 | SWAPGS_UNSAFE_STACK |
4d732138 | 967 | jmp paranoid_exit_restore |
0d550836 | 968 | paranoid_exit_no_swapgs: |
f2db9382 | 969 | TRACE_IRQS_IRETQ_DEBUG |
0d550836 | 970 | paranoid_exit_restore: |
76f5df43 DV |
971 | RESTORE_EXTRA_REGS |
972 | RESTORE_C_REGS | |
973 | REMOVE_PT_GPREGS_FROM_STACK 8 | |
48e08d0f | 974 | INTERRUPT_RETURN |
ddeb8f21 AH |
975 | END(paranoid_exit) |
976 | ||
977 | /* | |
ebfc453e | 978 | * Save all registers in pt_regs, and switch gs if needed. |
539f5113 | 979 | * Return: EBX=0: came from user mode; EBX=1: otherwise |
ddeb8f21 AH |
980 | */ |
981 | ENTRY(error_entry) | |
ddeb8f21 | 982 | cld |
76f5df43 DV |
983 | SAVE_C_REGS 8 |
984 | SAVE_EXTRA_REGS 8 | |
4d732138 | 985 | xorl %ebx, %ebx |
03335e95 | 986 | testb $3, CS+8(%rsp) |
cb6f64ed | 987 | jz .Lerror_kernelspace |
539f5113 | 988 | |
cb6f64ed AL |
989 | .Lerror_entry_from_usermode_swapgs: |
990 | /* | |
991 | * We entered from user mode or we're pretending to have entered | |
992 | * from user mode due to an IRET fault. | |
993 | */ | |
ddeb8f21 | 994 | SWAPGS |
539f5113 | 995 | |
cb6f64ed | 996 | .Lerror_entry_from_usermode_after_swapgs: |
f1075053 AL |
997 | /* |
998 | * We need to tell lockdep that IRQs are off. We can't do this until | |
999 | * we fix gsbase, and we should do it before enter_from_user_mode | |
1000 | * (which can take locks). | |
1001 | */ | |
1002 | TRACE_IRQS_OFF | |
478dc89c | 1003 | CALL_enter_from_user_mode |
f1075053 | 1004 | ret |
02bc7768 | 1005 | |
cb6f64ed | 1006 | .Lerror_entry_done: |
ddeb8f21 AH |
1007 | TRACE_IRQS_OFF |
1008 | ret | |
ddeb8f21 | 1009 | |
ebfc453e DV |
1010 | /* |
1011 | * There are two places in the kernel that can potentially fault with | |
1012 | * usergs. Handle them here. B stepping K8s sometimes report a | |
1013 | * truncated RIP for IRET exceptions returning to compat mode. Check | |
1014 | * for these here too. | |
1015 | */ | |
cb6f64ed | 1016 | .Lerror_kernelspace: |
4d732138 IM |
1017 | incl %ebx |
1018 | leaq native_irq_return_iret(%rip), %rcx | |
1019 | cmpq %rcx, RIP+8(%rsp) | |
cb6f64ed | 1020 | je .Lerror_bad_iret |
4d732138 IM |
1021 | movl %ecx, %eax /* zero extend */ |
1022 | cmpq %rax, RIP+8(%rsp) | |
cb6f64ed | 1023 | je .Lbstep_iret |
42c748bb | 1024 | cmpq $.Lgs_change, RIP+8(%rsp) |
cb6f64ed | 1025 | jne .Lerror_entry_done |
539f5113 AL |
1026 | |
1027 | /* | |
42c748bb | 1028 | * hack: .Lgs_change can fail with user gsbase. If this happens, fix up |
539f5113 | 1029 | * gsbase and proceed. We'll fix up the exception and land in |
42c748bb | 1030 | * .Lgs_change's error handler with kernel gsbase. |
539f5113 | 1031 | */ |
cb6f64ed | 1032 | jmp .Lerror_entry_from_usermode_swapgs |
ae24ffe5 | 1033 | |
cb6f64ed | 1034 | .Lbstep_iret: |
ae24ffe5 | 1035 | /* Fix truncated RIP */ |
4d732138 | 1036 | movq %rcx, RIP+8(%rsp) |
b645af2d AL |
1037 | /* fall through */ |
1038 | ||
cb6f64ed | 1039 | .Lerror_bad_iret: |
539f5113 AL |
1040 | /* |
1041 | * We came from an IRET to user mode, so we have user gsbase. | |
1042 | * Switch to kernel gsbase: | |
1043 | */ | |
b645af2d | 1044 | SWAPGS |
539f5113 AL |
1045 | |
1046 | /* | |
1047 | * Pretend that the exception came from user mode: set up pt_regs | |
1048 | * as if we faulted immediately after IRET and clear EBX so that | |
1049 | * error_exit knows that we will be returning to user mode. | |
1050 | */ | |
4d732138 IM |
1051 | mov %rsp, %rdi |
1052 | call fixup_bad_iret | |
1053 | mov %rax, %rsp | |
539f5113 | 1054 | decl %ebx |
cb6f64ed | 1055 | jmp .Lerror_entry_from_usermode_after_swapgs |
ddeb8f21 AH |
1056 | END(error_entry) |
1057 | ||
1058 | ||
539f5113 AL |
1059 | /* |
1060 | * On entry, EBS is a "return to kernel mode" flag: | |
1061 | * 1: already in kernel mode, don't need SWAPGS | |
1062 | * 0: user gsbase is loaded, we need SWAPGS and standard preparation for return to usermode | |
1063 | */ | |
ddeb8f21 | 1064 | ENTRY(error_exit) |
4d732138 | 1065 | movl %ebx, %eax |
ddeb8f21 AH |
1066 | DISABLE_INTERRUPTS(CLBR_NONE) |
1067 | TRACE_IRQS_OFF | |
4d732138 IM |
1068 | testl %eax, %eax |
1069 | jnz retint_kernel | |
1070 | jmp retint_user | |
ddeb8f21 AH |
1071 | END(error_exit) |
1072 | ||
0784b364 | 1073 | /* Runs on exception stack */ |
ddeb8f21 | 1074 | ENTRY(nmi) |
fc57a7c6 AL |
1075 | /* |
1076 | * Fix up the exception frame if we're on Xen. | |
1077 | * PARAVIRT_ADJUST_EXCEPTION_FRAME is guaranteed to push at most | |
1078 | * one value to the stack on native, so it may clobber the rdx | |
1079 | * scratch slot, but it won't clobber any of the important | |
1080 | * slots past it. | |
1081 | * | |
1082 | * Xen is a different story, because the Xen frame itself overlaps | |
1083 | * the "NMI executing" variable. | |
1084 | */ | |
ddeb8f21 | 1085 | PARAVIRT_ADJUST_EXCEPTION_FRAME |
fc57a7c6 | 1086 | |
3f3c8b8c SR |
1087 | /* |
1088 | * We allow breakpoints in NMIs. If a breakpoint occurs, then | |
1089 | * the iretq it performs will take us out of NMI context. | |
1090 | * This means that we can have nested NMIs where the next | |
1091 | * NMI is using the top of the stack of the previous NMI. We | |
1092 | * can't let it execute because the nested NMI will corrupt the | |
1093 | * stack of the previous NMI. NMI handlers are not re-entrant | |
1094 | * anyway. | |
1095 | * | |
1096 | * To handle this case we do the following: | |
1097 | * Check the a special location on the stack that contains | |
1098 | * a variable that is set when NMIs are executing. | |
1099 | * The interrupted task's stack is also checked to see if it | |
1100 | * is an NMI stack. | |
1101 | * If the variable is not set and the stack is not the NMI | |
1102 | * stack then: | |
1103 | * o Set the special variable on the stack | |
0b22930e AL |
1104 | * o Copy the interrupt frame into an "outermost" location on the |
1105 | * stack | |
1106 | * o Copy the interrupt frame into an "iret" location on the stack | |
3f3c8b8c SR |
1107 | * o Continue processing the NMI |
1108 | * If the variable is set or the previous stack is the NMI stack: | |
0b22930e | 1109 | * o Modify the "iret" location to jump to the repeat_nmi |
3f3c8b8c SR |
1110 | * o return back to the first NMI |
1111 | * | |
1112 | * Now on exit of the first NMI, we first clear the stack variable | |
1113 | * The NMI stack will tell any nested NMIs at that point that it is | |
1114 | * nested. Then we pop the stack normally with iret, and if there was | |
1115 | * a nested NMI that updated the copy interrupt stack frame, a | |
1116 | * jump will be made to the repeat_nmi code that will handle the second | |
1117 | * NMI. | |
9b6e6a83 AL |
1118 | * |
1119 | * However, espfix prevents us from directly returning to userspace | |
1120 | * with a single IRET instruction. Similarly, IRET to user mode | |
1121 | * can fault. We therefore handle NMIs from user space like | |
1122 | * other IST entries. | |
3f3c8b8c SR |
1123 | */ |
1124 | ||
146b2b09 | 1125 | /* Use %rdx as our temp variable throughout */ |
4d732138 | 1126 | pushq %rdx |
3f3c8b8c | 1127 | |
9b6e6a83 AL |
1128 | testb $3, CS-RIP+8(%rsp) |
1129 | jz .Lnmi_from_kernel | |
1130 | ||
1131 | /* | |
1132 | * NMI from user mode. We need to run on the thread stack, but we | |
1133 | * can't go through the normal entry paths: NMIs are masked, and | |
1134 | * we don't want to enable interrupts, because then we'll end | |
1135 | * up in an awkward situation in which IRQs are on but NMIs | |
1136 | * are off. | |
83c133cf AL |
1137 | * |
1138 | * We also must not push anything to the stack before switching | |
1139 | * stacks lest we corrupt the "NMI executing" variable. | |
9b6e6a83 AL |
1140 | */ |
1141 | ||
83c133cf | 1142 | SWAPGS_UNSAFE_STACK |
9b6e6a83 AL |
1143 | cld |
1144 | movq %rsp, %rdx | |
1145 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
1146 | pushq 5*8(%rdx) /* pt_regs->ss */ | |
1147 | pushq 4*8(%rdx) /* pt_regs->rsp */ | |
1148 | pushq 3*8(%rdx) /* pt_regs->flags */ | |
1149 | pushq 2*8(%rdx) /* pt_regs->cs */ | |
1150 | pushq 1*8(%rdx) /* pt_regs->rip */ | |
1151 | pushq $-1 /* pt_regs->orig_ax */ | |
1152 | pushq %rdi /* pt_regs->di */ | |
1153 | pushq %rsi /* pt_regs->si */ | |
1154 | pushq (%rdx) /* pt_regs->dx */ | |
1155 | pushq %rcx /* pt_regs->cx */ | |
1156 | pushq %rax /* pt_regs->ax */ | |
1157 | pushq %r8 /* pt_regs->r8 */ | |
1158 | pushq %r9 /* pt_regs->r9 */ | |
1159 | pushq %r10 /* pt_regs->r10 */ | |
1160 | pushq %r11 /* pt_regs->r11 */ | |
1161 | pushq %rbx /* pt_regs->rbx */ | |
1162 | pushq %rbp /* pt_regs->rbp */ | |
1163 | pushq %r12 /* pt_regs->r12 */ | |
1164 | pushq %r13 /* pt_regs->r13 */ | |
1165 | pushq %r14 /* pt_regs->r14 */ | |
1166 | pushq %r15 /* pt_regs->r15 */ | |
1167 | ||
1168 | /* | |
1169 | * At this point we no longer need to worry about stack damage | |
1170 | * due to nesting -- we're on the normal thread stack and we're | |
1171 | * done with the NMI stack. | |
1172 | */ | |
1173 | ||
1174 | movq %rsp, %rdi | |
1175 | movq $-1, %rsi | |
1176 | call do_nmi | |
1177 | ||
45d5a168 | 1178 | /* |
9b6e6a83 AL |
1179 | * Return back to user mode. We must *not* do the normal exit |
1180 | * work, because we don't want to enable interrupts. Fortunately, | |
1181 | * do_nmi doesn't modify pt_regs. | |
45d5a168 | 1182 | */ |
9b6e6a83 AL |
1183 | SWAPGS |
1184 | jmp restore_c_regs_and_iret | |
45d5a168 | 1185 | |
9b6e6a83 | 1186 | .Lnmi_from_kernel: |
3f3c8b8c | 1187 | /* |
0b22930e AL |
1188 | * Here's what our stack frame will look like: |
1189 | * +---------------------------------------------------------+ | |
1190 | * | original SS | | |
1191 | * | original Return RSP | | |
1192 | * | original RFLAGS | | |
1193 | * | original CS | | |
1194 | * | original RIP | | |
1195 | * +---------------------------------------------------------+ | |
1196 | * | temp storage for rdx | | |
1197 | * +---------------------------------------------------------+ | |
1198 | * | "NMI executing" variable | | |
1199 | * +---------------------------------------------------------+ | |
1200 | * | iret SS } Copied from "outermost" frame | | |
1201 | * | iret Return RSP } on each loop iteration; overwritten | | |
1202 | * | iret RFLAGS } by a nested NMI to force another | | |
1203 | * | iret CS } iteration if needed. | | |
1204 | * | iret RIP } | | |
1205 | * +---------------------------------------------------------+ | |
1206 | * | outermost SS } initialized in first_nmi; | | |
1207 | * | outermost Return RSP } will not be changed before | | |
1208 | * | outermost RFLAGS } NMI processing is done. | | |
1209 | * | outermost CS } Copied to "iret" frame on each | | |
1210 | * | outermost RIP } iteration. | | |
1211 | * +---------------------------------------------------------+ | |
1212 | * | pt_regs | | |
1213 | * +---------------------------------------------------------+ | |
1214 | * | |
1215 | * The "original" frame is used by hardware. Before re-enabling | |
1216 | * NMIs, we need to be done with it, and we need to leave enough | |
1217 | * space for the asm code here. | |
1218 | * | |
1219 | * We return by executing IRET while RSP points to the "iret" frame. | |
1220 | * That will either return for real or it will loop back into NMI | |
1221 | * processing. | |
1222 | * | |
1223 | * The "outermost" frame is copied to the "iret" frame on each | |
1224 | * iteration of the loop, so each iteration starts with the "iret" | |
1225 | * frame pointing to the final return target. | |
1226 | */ | |
1227 | ||
45d5a168 | 1228 | /* |
0b22930e AL |
1229 | * Determine whether we're a nested NMI. |
1230 | * | |
a27507ca AL |
1231 | * If we interrupted kernel code between repeat_nmi and |
1232 | * end_repeat_nmi, then we are a nested NMI. We must not | |
1233 | * modify the "iret" frame because it's being written by | |
1234 | * the outer NMI. That's okay; the outer NMI handler is | |
1235 | * about to about to call do_nmi anyway, so we can just | |
1236 | * resume the outer NMI. | |
45d5a168 | 1237 | */ |
a27507ca AL |
1238 | |
1239 | movq $repeat_nmi, %rdx | |
1240 | cmpq 8(%rsp), %rdx | |
1241 | ja 1f | |
1242 | movq $end_repeat_nmi, %rdx | |
1243 | cmpq 8(%rsp), %rdx | |
1244 | ja nested_nmi_out | |
1245 | 1: | |
45d5a168 | 1246 | |
3f3c8b8c | 1247 | /* |
a27507ca | 1248 | * Now check "NMI executing". If it's set, then we're nested. |
0b22930e AL |
1249 | * This will not detect if we interrupted an outer NMI just |
1250 | * before IRET. | |
3f3c8b8c | 1251 | */ |
4d732138 IM |
1252 | cmpl $1, -8(%rsp) |
1253 | je nested_nmi | |
3f3c8b8c SR |
1254 | |
1255 | /* | |
0b22930e AL |
1256 | * Now test if the previous stack was an NMI stack. This covers |
1257 | * the case where we interrupt an outer NMI after it clears | |
810bc075 AL |
1258 | * "NMI executing" but before IRET. We need to be careful, though: |
1259 | * there is one case in which RSP could point to the NMI stack | |
1260 | * despite there being no NMI active: naughty userspace controls | |
1261 | * RSP at the very beginning of the SYSCALL targets. We can | |
1262 | * pull a fast one on naughty userspace, though: we program | |
1263 | * SYSCALL to mask DF, so userspace cannot cause DF to be set | |
1264 | * if it controls the kernel's RSP. We set DF before we clear | |
1265 | * "NMI executing". | |
3f3c8b8c | 1266 | */ |
0784b364 DV |
1267 | lea 6*8(%rsp), %rdx |
1268 | /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ | |
1269 | cmpq %rdx, 4*8(%rsp) | |
1270 | /* If the stack pointer is above the NMI stack, this is a normal NMI */ | |
1271 | ja first_nmi | |
4d732138 | 1272 | |
0784b364 DV |
1273 | subq $EXCEPTION_STKSZ, %rdx |
1274 | cmpq %rdx, 4*8(%rsp) | |
1275 | /* If it is below the NMI stack, it is a normal NMI */ | |
1276 | jb first_nmi | |
810bc075 AL |
1277 | |
1278 | /* Ah, it is within the NMI stack. */ | |
1279 | ||
1280 | testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) | |
1281 | jz first_nmi /* RSP was user controlled. */ | |
1282 | ||
1283 | /* This is a nested NMI. */ | |
0784b364 | 1284 | |
3f3c8b8c SR |
1285 | nested_nmi: |
1286 | /* | |
0b22930e AL |
1287 | * Modify the "iret" frame to point to repeat_nmi, forcing another |
1288 | * iteration of NMI handling. | |
3f3c8b8c | 1289 | */ |
23a781e9 | 1290 | subq $8, %rsp |
4d732138 IM |
1291 | leaq -10*8(%rsp), %rdx |
1292 | pushq $__KERNEL_DS | |
1293 | pushq %rdx | |
131484c8 | 1294 | pushfq |
4d732138 IM |
1295 | pushq $__KERNEL_CS |
1296 | pushq $repeat_nmi | |
3f3c8b8c SR |
1297 | |
1298 | /* Put stack back */ | |
4d732138 | 1299 | addq $(6*8), %rsp |
3f3c8b8c SR |
1300 | |
1301 | nested_nmi_out: | |
4d732138 | 1302 | popq %rdx |
3f3c8b8c | 1303 | |
0b22930e | 1304 | /* We are returning to kernel mode, so this cannot result in a fault. */ |
3f3c8b8c SR |
1305 | INTERRUPT_RETURN |
1306 | ||
1307 | first_nmi: | |
0b22930e | 1308 | /* Restore rdx. */ |
4d732138 | 1309 | movq (%rsp), %rdx |
62610913 | 1310 | |
36f1a77b AL |
1311 | /* Make room for "NMI executing". */ |
1312 | pushq $0 | |
3f3c8b8c | 1313 | |
0b22930e | 1314 | /* Leave room for the "iret" frame */ |
4d732138 | 1315 | subq $(5*8), %rsp |
28696f43 | 1316 | |
0b22930e | 1317 | /* Copy the "original" frame to the "outermost" frame */ |
3f3c8b8c | 1318 | .rept 5 |
4d732138 | 1319 | pushq 11*8(%rsp) |
3f3c8b8c | 1320 | .endr |
62610913 | 1321 | |
79fb4ad6 SR |
1322 | /* Everything up to here is safe from nested NMIs */ |
1323 | ||
a97439aa AL |
1324 | #ifdef CONFIG_DEBUG_ENTRY |
1325 | /* | |
1326 | * For ease of testing, unmask NMIs right away. Disabled by | |
1327 | * default because IRET is very expensive. | |
1328 | */ | |
1329 | pushq $0 /* SS */ | |
1330 | pushq %rsp /* RSP (minus 8 because of the previous push) */ | |
1331 | addq $8, (%rsp) /* Fix up RSP */ | |
1332 | pushfq /* RFLAGS */ | |
1333 | pushq $__KERNEL_CS /* CS */ | |
1334 | pushq $1f /* RIP */ | |
1335 | INTERRUPT_RETURN /* continues at repeat_nmi below */ | |
1336 | 1: | |
1337 | #endif | |
1338 | ||
0b22930e | 1339 | repeat_nmi: |
62610913 JB |
1340 | /* |
1341 | * If there was a nested NMI, the first NMI's iret will return | |
1342 | * here. But NMIs are still enabled and we can take another | |
1343 | * nested NMI. The nested NMI checks the interrupted RIP to see | |
1344 | * if it is between repeat_nmi and end_repeat_nmi, and if so | |
1345 | * it will just return, as we are about to repeat an NMI anyway. | |
1346 | * This makes it safe to copy to the stack frame that a nested | |
1347 | * NMI will update. | |
0b22930e AL |
1348 | * |
1349 | * RSP is pointing to "outermost RIP". gsbase is unknown, but, if | |
1350 | * we're repeating an NMI, gsbase has the same value that it had on | |
1351 | * the first iteration. paranoid_entry will load the kernel | |
36f1a77b AL |
1352 | * gsbase if needed before we call do_nmi. "NMI executing" |
1353 | * is zero. | |
62610913 | 1354 | */ |
36f1a77b | 1355 | movq $1, 10*8(%rsp) /* Set "NMI executing". */ |
3f3c8b8c | 1356 | |
62610913 | 1357 | /* |
0b22930e AL |
1358 | * Copy the "outermost" frame to the "iret" frame. NMIs that nest |
1359 | * here must not modify the "iret" frame while we're writing to | |
1360 | * it or it will end up containing garbage. | |
62610913 | 1361 | */ |
4d732138 | 1362 | addq $(10*8), %rsp |
3f3c8b8c | 1363 | .rept 5 |
4d732138 | 1364 | pushq -6*8(%rsp) |
3f3c8b8c | 1365 | .endr |
4d732138 | 1366 | subq $(5*8), %rsp |
62610913 | 1367 | end_repeat_nmi: |
3f3c8b8c SR |
1368 | |
1369 | /* | |
0b22930e AL |
1370 | * Everything below this point can be preempted by a nested NMI. |
1371 | * If this happens, then the inner NMI will change the "iret" | |
1372 | * frame to point back to repeat_nmi. | |
3f3c8b8c | 1373 | */ |
4d732138 | 1374 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
76f5df43 DV |
1375 | ALLOC_PT_GPREGS_ON_STACK |
1376 | ||
1fd466ef | 1377 | /* |
ebfc453e | 1378 | * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit |
1fd466ef SR |
1379 | * as we should not be calling schedule in NMI context. |
1380 | * Even with normal interrupts enabled. An NMI should not be | |
1381 | * setting NEED_RESCHED or anything that normal interrupts and | |
1382 | * exceptions might do. | |
1383 | */ | |
4d732138 | 1384 | call paranoid_entry |
7fbb98c5 | 1385 | |
ddeb8f21 | 1386 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
4d732138 IM |
1387 | movq %rsp, %rdi |
1388 | movq $-1, %rsi | |
1389 | call do_nmi | |
7fbb98c5 | 1390 | |
4d732138 IM |
1391 | testl %ebx, %ebx /* swapgs needed? */ |
1392 | jnz nmi_restore | |
ddeb8f21 AH |
1393 | nmi_swapgs: |
1394 | SWAPGS_UNSAFE_STACK | |
1395 | nmi_restore: | |
76f5df43 DV |
1396 | RESTORE_EXTRA_REGS |
1397 | RESTORE_C_REGS | |
0b22930e AL |
1398 | |
1399 | /* Point RSP at the "iret" frame. */ | |
76f5df43 | 1400 | REMOVE_PT_GPREGS_FROM_STACK 6*8 |
28696f43 | 1401 | |
810bc075 AL |
1402 | /* |
1403 | * Clear "NMI executing". Set DF first so that we can easily | |
1404 | * distinguish the remaining code between here and IRET from | |
1405 | * the SYSCALL entry and exit paths. On a native kernel, we | |
1406 | * could just inspect RIP, but, on paravirt kernels, | |
1407 | * INTERRUPT_RETURN can translate into a jump into a | |
1408 | * hypercall page. | |
1409 | */ | |
1410 | std | |
1411 | movq $0, 5*8(%rsp) /* clear "NMI executing" */ | |
0b22930e AL |
1412 | |
1413 | /* | |
1414 | * INTERRUPT_RETURN reads the "iret" frame and exits the NMI | |
1415 | * stack in a single instruction. We are returning to kernel | |
1416 | * mode, so this cannot result in a fault. | |
1417 | */ | |
5ca6f70f | 1418 | INTERRUPT_RETURN |
ddeb8f21 AH |
1419 | END(nmi) |
1420 | ||
1421 | ENTRY(ignore_sysret) | |
4d732138 | 1422 | mov $-ENOSYS, %eax |
ddeb8f21 | 1423 | sysret |
ddeb8f21 | 1424 | END(ignore_sysret) |
2deb4be2 AL |
1425 | |
1426 | ENTRY(rewind_stack_do_exit) | |
1427 | /* Prevent any naive code from trying to unwind to our caller. */ | |
1428 | xorl %ebp, %ebp | |
1429 | ||
1430 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rax | |
1431 | leaq -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%rax), %rsp | |
1432 | ||
1433 | call do_exit | |
1434 | 1: jmp 1b | |
1435 | END(rewind_stack_do_exit) |