Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 LT |
2 | /* |
3 | * linux/arch/x86_64/entry.S | |
4 | * | |
5 | * Copyright (C) 1991, 1992 Linus Torvalds | |
6 | * Copyright (C) 2000, 2001, 2002 Andi Kleen SuSE Labs | |
7 | * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> | |
4d732138 | 8 | * |
1da177e4 LT |
9 | * entry.S contains the system-call and fault low-level handling routines. |
10 | * | |
8b4777a4 AL |
11 | * Some of this is documented in Documentation/x86/entry_64.txt |
12 | * | |
0bd7b798 | 13 | * A note on terminology: |
4d732138 IM |
14 | * - iret frame: Architecture defined interrupt frame from SS to RIP |
15 | * at the top of the kernel process stack. | |
2e91a17b AK |
16 | * |
17 | * Some macro usage: | |
4d732138 IM |
18 | * - ENTRY/END: Define functions in the symbol table. |
19 | * - TRACE_IRQ_*: Trace hardirq state for lock debugging. | |
20 | * - idtentry: Define exception entry points. | |
1da177e4 | 21 | */ |
1da177e4 LT |
22 | #include <linux/linkage.h> |
23 | #include <asm/segment.h> | |
1da177e4 LT |
24 | #include <asm/cache.h> |
25 | #include <asm/errno.h> | |
e2d5df93 | 26 | #include <asm/asm-offsets.h> |
1da177e4 LT |
27 | #include <asm/msr.h> |
28 | #include <asm/unistd.h> | |
29 | #include <asm/thread_info.h> | |
30 | #include <asm/hw_irq.h> | |
0341c14d | 31 | #include <asm/page_types.h> |
2601e64d | 32 | #include <asm/irqflags.h> |
72fe4858 | 33 | #include <asm/paravirt.h> |
9939ddaf | 34 | #include <asm/percpu.h> |
d7abc0fa | 35 | #include <asm/asm.h> |
63bcff2a | 36 | #include <asm/smap.h> |
3891a04a | 37 | #include <asm/pgtable_types.h> |
784d5699 | 38 | #include <asm/export.h> |
8c1f7558 | 39 | #include <asm/frame.h> |
2641f08b | 40 | #include <asm/nospec-branch.h> |
d7e7528b | 41 | #include <linux/err.h> |
1da177e4 | 42 | |
6fd166aa PZ |
43 | #include "calling.h" |
44 | ||
4d732138 IM |
45 | .code64 |
46 | .section .entry.text, "ax" | |
16444a8a | 47 | |
72fe4858 | 48 | #ifdef CONFIG_PARAVIRT |
2be29982 | 49 | ENTRY(native_usergs_sysret64) |
8c1f7558 | 50 | UNWIND_HINT_EMPTY |
72fe4858 GOC |
51 | swapgs |
52 | sysretq | |
8c1f7558 | 53 | END(native_usergs_sysret64) |
72fe4858 GOC |
54 | #endif /* CONFIG_PARAVIRT */ |
55 | ||
ca37e57b | 56 | .macro TRACE_IRQS_FLAGS flags:req |
2601e64d | 57 | #ifdef CONFIG_TRACE_IRQFLAGS |
a368d7fd | 58 | btl $9, \flags /* interrupts off? */ |
4d732138 | 59 | jnc 1f |
2601e64d IM |
60 | TRACE_IRQS_ON |
61 | 1: | |
62 | #endif | |
63 | .endm | |
64 | ||
ca37e57b AL |
65 | .macro TRACE_IRQS_IRETQ |
66 | TRACE_IRQS_FLAGS EFLAGS(%rsp) | |
67 | .endm | |
68 | ||
5963e317 SR |
69 | /* |
70 | * When dynamic function tracer is enabled it will add a breakpoint | |
71 | * to all locations that it is about to modify, sync CPUs, update | |
72 | * all the code, sync CPUs, then remove the breakpoints. In this time | |
73 | * if lockdep is enabled, it might jump back into the debug handler | |
74 | * outside the updating of the IST protection. (TRACE_IRQS_ON/OFF). | |
75 | * | |
76 | * We need to change the IDT table before calling TRACE_IRQS_ON/OFF to | |
77 | * make sure the stack pointer does not get reset back to the top | |
78 | * of the debug stack, and instead just reuses the current stack. | |
79 | */ | |
80 | #if defined(CONFIG_DYNAMIC_FTRACE) && defined(CONFIG_TRACE_IRQFLAGS) | |
81 | ||
82 | .macro TRACE_IRQS_OFF_DEBUG | |
4d732138 | 83 | call debug_stack_set_zero |
5963e317 | 84 | TRACE_IRQS_OFF |
4d732138 | 85 | call debug_stack_reset |
5963e317 SR |
86 | .endm |
87 | ||
88 | .macro TRACE_IRQS_ON_DEBUG | |
4d732138 | 89 | call debug_stack_set_zero |
5963e317 | 90 | TRACE_IRQS_ON |
4d732138 | 91 | call debug_stack_reset |
5963e317 SR |
92 | .endm |
93 | ||
f2db9382 | 94 | .macro TRACE_IRQS_IRETQ_DEBUG |
6709812f | 95 | btl $9, EFLAGS(%rsp) /* interrupts off? */ |
4d732138 | 96 | jnc 1f |
5963e317 SR |
97 | TRACE_IRQS_ON_DEBUG |
98 | 1: | |
99 | .endm | |
100 | ||
101 | #else | |
4d732138 IM |
102 | # define TRACE_IRQS_OFF_DEBUG TRACE_IRQS_OFF |
103 | # define TRACE_IRQS_ON_DEBUG TRACE_IRQS_ON | |
104 | # define TRACE_IRQS_IRETQ_DEBUG TRACE_IRQS_IRETQ | |
5963e317 SR |
105 | #endif |
106 | ||
1da177e4 | 107 | /* |
4d732138 | 108 | * 64-bit SYSCALL instruction entry. Up to 6 arguments in registers. |
1da177e4 | 109 | * |
fda57b22 AL |
110 | * This is the only entry point used for 64-bit system calls. The |
111 | * hardware interface is reasonably well designed and the register to | |
112 | * argument mapping Linux uses fits well with the registers that are | |
113 | * available when SYSCALL is used. | |
114 | * | |
115 | * SYSCALL instructions can be found inlined in libc implementations as | |
116 | * well as some other programs and libraries. There are also a handful | |
117 | * of SYSCALL instructions in the vDSO used, for example, as a | |
118 | * clock_gettimeofday fallback. | |
119 | * | |
4d732138 | 120 | * 64-bit SYSCALL saves rip to rcx, clears rflags.RF, then saves rflags to r11, |
b87cf63e DV |
121 | * then loads new ss, cs, and rip from previously programmed MSRs. |
122 | * rflags gets masked by a value from another MSR (so CLD and CLAC | |
123 | * are not needed). SYSCALL does not save anything on the stack | |
124 | * and does not change rsp. | |
125 | * | |
126 | * Registers on entry: | |
1da177e4 | 127 | * rax system call number |
b87cf63e DV |
128 | * rcx return address |
129 | * r11 saved rflags (note: r11 is callee-clobbered register in C ABI) | |
1da177e4 | 130 | * rdi arg0 |
1da177e4 | 131 | * rsi arg1 |
0bd7b798 | 132 | * rdx arg2 |
b87cf63e | 133 | * r10 arg3 (needs to be moved to rcx to conform to C ABI) |
1da177e4 LT |
134 | * r8 arg4 |
135 | * r9 arg5 | |
4d732138 | 136 | * (note: r12-r15, rbp, rbx are callee-preserved in C ABI) |
0bd7b798 | 137 | * |
1da177e4 LT |
138 | * Only called from user space. |
139 | * | |
7fcb3bc3 | 140 | * When user can change pt_regs->foo always force IRET. That is because |
7bf36bbc AK |
141 | * it deals with uncanonical addresses better. SYSRET has trouble |
142 | * with them due to bugs in both AMD and Intel CPUs. | |
0bd7b798 | 143 | */ |
1da177e4 | 144 | |
3386bc8a AL |
145 | .pushsection .entry_trampoline, "ax" |
146 | ||
147 | /* | |
148 | * The code in here gets remapped into cpu_entry_area's trampoline. This means | |
149 | * that the assembler and linker have the wrong idea as to where this code | |
150 | * lives (and, in fact, it's mapped more than once, so it's not even at a | |
151 | * fixed address). So we can't reference any symbols outside the entry | |
152 | * trampoline and expect it to work. | |
153 | * | |
154 | * Instead, we carefully abuse %rip-relative addressing. | |
155 | * _entry_trampoline(%rip) refers to the start of the remapped) entry | |
156 | * trampoline. We can thus find cpu_entry_area with this macro: | |
157 | */ | |
158 | ||
159 | #define CPU_ENTRY_AREA \ | |
160 | _entry_trampoline - CPU_ENTRY_AREA_entry_trampoline(%rip) | |
161 | ||
162 | /* The top word of the SYSENTER stack is hot and is usable as scratch space. */ | |
4fe2d8b1 DH |
163 | #define RSP_SCRATCH CPU_ENTRY_AREA_entry_stack + \ |
164 | SIZEOF_entry_stack - 8 + CPU_ENTRY_AREA | |
3386bc8a AL |
165 | |
166 | ENTRY(entry_SYSCALL_64_trampoline) | |
167 | UNWIND_HINT_EMPTY | |
168 | swapgs | |
169 | ||
170 | /* Stash the user RSP. */ | |
171 | movq %rsp, RSP_SCRATCH | |
172 | ||
8a09317b DH |
173 | /* Note: using %rsp as a scratch reg. */ |
174 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rsp | |
175 | ||
3386bc8a AL |
176 | /* Load the top of the task stack into RSP */ |
177 | movq CPU_ENTRY_AREA_tss + TSS_sp1 + CPU_ENTRY_AREA, %rsp | |
178 | ||
179 | /* Start building the simulated IRET frame. */ | |
180 | pushq $__USER_DS /* pt_regs->ss */ | |
181 | pushq RSP_SCRATCH /* pt_regs->sp */ | |
182 | pushq %r11 /* pt_regs->flags */ | |
183 | pushq $__USER_CS /* pt_regs->cs */ | |
184 | pushq %rcx /* pt_regs->ip */ | |
185 | ||
186 | /* | |
187 | * x86 lacks a near absolute jump, and we can't jump to the real | |
188 | * entry text with a relative jump. We could push the target | |
189 | * address and then use retq, but this destroys the pipeline on | |
190 | * many CPUs (wasting over 20 cycles on Sandy Bridge). Instead, | |
191 | * spill RDI and restore it in a second-stage trampoline. | |
192 | */ | |
193 | pushq %rdi | |
194 | movq $entry_SYSCALL_64_stage2, %rdi | |
2641f08b | 195 | JMP_NOSPEC %rdi |
3386bc8a AL |
196 | END(entry_SYSCALL_64_trampoline) |
197 | ||
198 | .popsection | |
199 | ||
200 | ENTRY(entry_SYSCALL_64_stage2) | |
201 | UNWIND_HINT_EMPTY | |
202 | popq %rdi | |
203 | jmp entry_SYSCALL_64_after_hwframe | |
204 | END(entry_SYSCALL_64_stage2) | |
205 | ||
b2502b41 | 206 | ENTRY(entry_SYSCALL_64) |
8c1f7558 | 207 | UNWIND_HINT_EMPTY |
9ed8e7d8 DV |
208 | /* |
209 | * Interrupts are off on entry. | |
210 | * We do not frame this tiny irq-off block with TRACE_IRQS_OFF/ON, | |
211 | * it is too small to ever cause noticeable irq latency. | |
212 | */ | |
72fe4858 | 213 | |
8a9949bc | 214 | swapgs |
8a09317b | 215 | /* |
14b1fcc6 | 216 | * This path is only taken when PAGE_TABLE_ISOLATION is disabled so it |
8a09317b DH |
217 | * is not required to switch CR3. |
218 | */ | |
4d732138 IM |
219 | movq %rsp, PER_CPU_VAR(rsp_scratch) |
220 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
9ed8e7d8 DV |
221 | |
222 | /* Construct struct pt_regs on stack */ | |
4d732138 IM |
223 | pushq $__USER_DS /* pt_regs->ss */ |
224 | pushq PER_CPU_VAR(rsp_scratch) /* pt_regs->sp */ | |
4d732138 IM |
225 | pushq %r11 /* pt_regs->flags */ |
226 | pushq $__USER_CS /* pt_regs->cs */ | |
227 | pushq %rcx /* pt_regs->ip */ | |
8a9949bc | 228 | GLOBAL(entry_SYSCALL_64_after_hwframe) |
4d732138 | 229 | pushq %rax /* pt_regs->orig_ax */ |
30907fd1 DB |
230 | |
231 | PUSH_AND_CLEAR_REGS rax=$-ENOSYS | |
4d732138 | 232 | |
548c3050 AL |
233 | TRACE_IRQS_OFF |
234 | ||
1e423bff | 235 | /* IRQs are off. */ |
dfe64506 LT |
236 | movq %rax, %rdi |
237 | movq %rsp, %rsi | |
1e423bff AL |
238 | call do_syscall_64 /* returns with IRQs disabled */ |
239 | ||
29ea1b25 | 240 | TRACE_IRQS_IRETQ /* we're about to change IF */ |
fffbb5dc DV |
241 | |
242 | /* | |
243 | * Try to use SYSRET instead of IRET if we're returning to | |
8a055d7f AL |
244 | * a completely clean 64-bit userspace context. If we're not, |
245 | * go to the slow exit path. | |
fffbb5dc | 246 | */ |
4d732138 IM |
247 | movq RCX(%rsp), %rcx |
248 | movq RIP(%rsp), %r11 | |
8a055d7f AL |
249 | |
250 | cmpq %rcx, %r11 /* SYSRET requires RCX == RIP */ | |
251 | jne swapgs_restore_regs_and_return_to_usermode | |
fffbb5dc DV |
252 | |
253 | /* | |
254 | * On Intel CPUs, SYSRET with non-canonical RCX/RIP will #GP | |
255 | * in kernel space. This essentially lets the user take over | |
17be0aec | 256 | * the kernel, since userspace controls RSP. |
fffbb5dc | 257 | * |
17be0aec | 258 | * If width of "canonical tail" ever becomes variable, this will need |
fffbb5dc | 259 | * to be updated to remain correct on both old and new CPUs. |
361b4b58 | 260 | * |
cbe0317b KS |
261 | * Change top bits to match most significant bit (47th or 56th bit |
262 | * depending on paging mode) in the address. | |
fffbb5dc | 263 | */ |
09e61a77 | 264 | #ifdef CONFIG_X86_5LEVEL |
39b95522 KS |
265 | ALTERNATIVE "shl $(64 - 48), %rcx; sar $(64 - 48), %rcx", \ |
266 | "shl $(64 - 57), %rcx; sar $(64 - 57), %rcx", X86_FEATURE_LA57 | |
09e61a77 | 267 | #else |
17be0aec DV |
268 | shl $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx |
269 | sar $(64 - (__VIRTUAL_MASK_SHIFT+1)), %rcx | |
09e61a77 | 270 | #endif |
4d732138 | 271 | |
17be0aec DV |
272 | /* If this changed %rcx, it was not canonical */ |
273 | cmpq %rcx, %r11 | |
8a055d7f | 274 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc | 275 | |
4d732138 | 276 | cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */ |
8a055d7f | 277 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc | 278 | |
4d732138 IM |
279 | movq R11(%rsp), %r11 |
280 | cmpq %r11, EFLAGS(%rsp) /* R11 == RFLAGS */ | |
8a055d7f | 281 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc DV |
282 | |
283 | /* | |
3e035305 BP |
284 | * SYSCALL clears RF when it saves RFLAGS in R11 and SYSRET cannot |
285 | * restore RF properly. If the slowpath sets it for whatever reason, we | |
286 | * need to restore it correctly. | |
287 | * | |
288 | * SYSRET can restore TF, but unlike IRET, restoring TF results in a | |
289 | * trap from userspace immediately after SYSRET. This would cause an | |
290 | * infinite loop whenever #DB happens with register state that satisfies | |
291 | * the opportunistic SYSRET conditions. For example, single-stepping | |
292 | * this user code: | |
fffbb5dc | 293 | * |
4d732138 | 294 | * movq $stuck_here, %rcx |
fffbb5dc DV |
295 | * pushfq |
296 | * popq %r11 | |
297 | * stuck_here: | |
298 | * | |
299 | * would never get past 'stuck_here'. | |
300 | */ | |
4d732138 | 301 | testq $(X86_EFLAGS_RF|X86_EFLAGS_TF), %r11 |
8a055d7f | 302 | jnz swapgs_restore_regs_and_return_to_usermode |
fffbb5dc DV |
303 | |
304 | /* nothing to check for RSP */ | |
305 | ||
4d732138 | 306 | cmpq $__USER_DS, SS(%rsp) /* SS must match SYSRET */ |
8a055d7f | 307 | jne swapgs_restore_regs_and_return_to_usermode |
fffbb5dc DV |
308 | |
309 | /* | |
4d732138 IM |
310 | * We win! This label is here just for ease of understanding |
311 | * perf profiles. Nothing jumps here. | |
fffbb5dc DV |
312 | */ |
313 | syscall_return_via_sysret: | |
17be0aec | 314 | /* rcx and r11 are already restored (see code above) */ |
8c1f7558 | 315 | UNWIND_HINT_EMPTY |
502af0d7 | 316 | POP_REGS pop_rdi=0 skip_r11rcx=1 |
3e3b9293 AL |
317 | |
318 | /* | |
319 | * Now all regs are restored except RSP and RDI. | |
320 | * Save old stack pointer and switch to trampoline stack. | |
321 | */ | |
322 | movq %rsp, %rdi | |
c482feef | 323 | movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp |
3e3b9293 AL |
324 | |
325 | pushq RSP-RDI(%rdi) /* RSP */ | |
326 | pushq (%rdi) /* RDI */ | |
327 | ||
328 | /* | |
329 | * We are on the trampoline stack. All regs except RDI are live. | |
330 | * We can do future final exit work right here. | |
331 | */ | |
6fd166aa | 332 | SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi |
3e3b9293 | 333 | |
4fbb3910 | 334 | popq %rdi |
3e3b9293 | 335 | popq %rsp |
fffbb5dc | 336 | USERGS_SYSRET64 |
b2502b41 | 337 | END(entry_SYSCALL_64) |
0bd7b798 | 338 | |
0100301b BG |
339 | /* |
340 | * %rdi: prev task | |
341 | * %rsi: next task | |
342 | */ | |
343 | ENTRY(__switch_to_asm) | |
8c1f7558 | 344 | UNWIND_HINT_FUNC |
0100301b BG |
345 | /* |
346 | * Save callee-saved registers | |
347 | * This must match the order in inactive_task_frame | |
348 | */ | |
349 | pushq %rbp | |
350 | pushq %rbx | |
351 | pushq %r12 | |
352 | pushq %r13 | |
353 | pushq %r14 | |
354 | pushq %r15 | |
355 | ||
356 | /* switch stack */ | |
357 | movq %rsp, TASK_threadsp(%rdi) | |
358 | movq TASK_threadsp(%rsi), %rsp | |
359 | ||
050e9baa | 360 | #ifdef CONFIG_STACKPROTECTOR |
0100301b BG |
361 | movq TASK_stack_canary(%rsi), %rbx |
362 | movq %rbx, PER_CPU_VAR(irq_stack_union)+stack_canary_offset | |
363 | #endif | |
364 | ||
c995efd5 DW |
365 | #ifdef CONFIG_RETPOLINE |
366 | /* | |
367 | * When switching from a shallower to a deeper call stack | |
368 | * the RSB may either underflow or use entries populated | |
369 | * with userspace addresses. On CPUs where those concerns | |
370 | * exist, overwrite the RSB with entries which capture | |
371 | * speculative execution to prevent attack. | |
372 | */ | |
d1c99108 | 373 | FILL_RETURN_BUFFER %r12, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW |
c995efd5 DW |
374 | #endif |
375 | ||
0100301b BG |
376 | /* restore callee-saved registers */ |
377 | popq %r15 | |
378 | popq %r14 | |
379 | popq %r13 | |
380 | popq %r12 | |
381 | popq %rbx | |
382 | popq %rbp | |
383 | ||
384 | jmp __switch_to | |
385 | END(__switch_to_asm) | |
386 | ||
1eeb207f DV |
387 | /* |
388 | * A newly forked process directly context switches into this address. | |
389 | * | |
0100301b | 390 | * rax: prev task we switched from |
616d2483 BG |
391 | * rbx: kernel thread func (NULL for user thread) |
392 | * r12: kernel thread arg | |
1eeb207f DV |
393 | */ |
394 | ENTRY(ret_from_fork) | |
8c1f7558 | 395 | UNWIND_HINT_EMPTY |
0100301b | 396 | movq %rax, %rdi |
ebd57499 | 397 | call schedule_tail /* rdi: 'prev' task parameter */ |
1eeb207f | 398 | |
ebd57499 JP |
399 | testq %rbx, %rbx /* from kernel_thread? */ |
400 | jnz 1f /* kernel threads are uncommon */ | |
24d978b7 | 401 | |
616d2483 | 402 | 2: |
8c1f7558 | 403 | UNWIND_HINT_REGS |
ebd57499 | 404 | movq %rsp, %rdi |
24d978b7 AL |
405 | call syscall_return_slowpath /* returns with IRQs disabled */ |
406 | TRACE_IRQS_ON /* user mode is traced as IRQS on */ | |
8a055d7f | 407 | jmp swapgs_restore_regs_and_return_to_usermode |
616d2483 BG |
408 | |
409 | 1: | |
410 | /* kernel thread */ | |
d31a5802 | 411 | UNWIND_HINT_EMPTY |
616d2483 | 412 | movq %r12, %rdi |
2641f08b | 413 | CALL_NOSPEC %rbx |
616d2483 BG |
414 | /* |
415 | * A kernel thread is allowed to return here after successfully | |
416 | * calling do_execve(). Exit to userspace to complete the execve() | |
417 | * syscall. | |
418 | */ | |
419 | movq $0, RAX(%rsp) | |
420 | jmp 2b | |
1eeb207f DV |
421 | END(ret_from_fork) |
422 | ||
939b7871 | 423 | /* |
3304c9c3 DV |
424 | * Build the entry stubs with some assembler magic. |
425 | * We pack 1 stub into every 8-byte block. | |
939b7871 | 426 | */ |
3304c9c3 | 427 | .align 8 |
939b7871 | 428 | ENTRY(irq_entries_start) |
3304c9c3 DV |
429 | vector=FIRST_EXTERNAL_VECTOR |
430 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
8c1f7558 | 431 | UNWIND_HINT_IRET_REGS |
4d732138 | 432 | pushq $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 | 433 | jmp common_interrupt |
3304c9c3 | 434 | .align 8 |
8c1f7558 | 435 | vector=vector+1 |
3304c9c3 | 436 | .endr |
939b7871 PA |
437 | END(irq_entries_start) |
438 | ||
1d3e53e8 AL |
439 | .macro DEBUG_ENTRY_ASSERT_IRQS_OFF |
440 | #ifdef CONFIG_DEBUG_ENTRY | |
e17f8234 BO |
441 | pushq %rax |
442 | SAVE_FLAGS(CLBR_RAX) | |
443 | testl $X86_EFLAGS_IF, %eax | |
1d3e53e8 AL |
444 | jz .Lokay_\@ |
445 | ud2 | |
446 | .Lokay_\@: | |
e17f8234 | 447 | popq %rax |
1d3e53e8 AL |
448 | #endif |
449 | .endm | |
450 | ||
451 | /* | |
452 | * Enters the IRQ stack if we're not already using it. NMI-safe. Clobbers | |
453 | * flags and puts old RSP into old_rsp, and leaves all other GPRs alone. | |
454 | * Requires kernel GSBASE. | |
455 | * | |
456 | * The invariant is that, if irq_count != -1, then the IRQ stack is in use. | |
457 | */ | |
2ba64741 | 458 | .macro ENTER_IRQ_STACK regs=1 old_rsp save_ret=0 |
1d3e53e8 | 459 | DEBUG_ENTRY_ASSERT_IRQS_OFF |
2ba64741 DB |
460 | |
461 | .if \save_ret | |
462 | /* | |
463 | * If save_ret is set, the original stack contains one additional | |
464 | * entry -- the return address. Therefore, move the address one | |
465 | * entry below %rsp to \old_rsp. | |
466 | */ | |
467 | leaq 8(%rsp), \old_rsp | |
468 | .else | |
1d3e53e8 | 469 | movq %rsp, \old_rsp |
2ba64741 | 470 | .endif |
8c1f7558 JP |
471 | |
472 | .if \regs | |
473 | UNWIND_HINT_REGS base=\old_rsp | |
474 | .endif | |
475 | ||
1d3e53e8 | 476 | incl PER_CPU_VAR(irq_count) |
29955909 | 477 | jnz .Lirq_stack_push_old_rsp_\@ |
1d3e53e8 AL |
478 | |
479 | /* | |
480 | * Right now, if we just incremented irq_count to zero, we've | |
481 | * claimed the IRQ stack but we haven't switched to it yet. | |
482 | * | |
483 | * If anything is added that can interrupt us here without using IST, | |
484 | * it must be *extremely* careful to limit its stack usage. This | |
485 | * could include kprobes and a hypothetical future IST-less #DB | |
486 | * handler. | |
29955909 AL |
487 | * |
488 | * The OOPS unwinder relies on the word at the top of the IRQ | |
489 | * stack linking back to the previous RSP for the entire time we're | |
490 | * on the IRQ stack. For this to work reliably, we need to write | |
491 | * it before we actually move ourselves to the IRQ stack. | |
492 | */ | |
493 | ||
494 | movq \old_rsp, PER_CPU_VAR(irq_stack_union + IRQ_STACK_SIZE - 8) | |
495 | movq PER_CPU_VAR(irq_stack_ptr), %rsp | |
496 | ||
497 | #ifdef CONFIG_DEBUG_ENTRY | |
498 | /* | |
499 | * If the first movq above becomes wrong due to IRQ stack layout | |
500 | * changes, the only way we'll notice is if we try to unwind right | |
501 | * here. Assert that we set up the stack right to catch this type | |
502 | * of bug quickly. | |
1d3e53e8 | 503 | */ |
29955909 AL |
504 | cmpq -8(%rsp), \old_rsp |
505 | je .Lirq_stack_okay\@ | |
506 | ud2 | |
507 | .Lirq_stack_okay\@: | |
508 | #endif | |
1d3e53e8 | 509 | |
29955909 | 510 | .Lirq_stack_push_old_rsp_\@: |
1d3e53e8 | 511 | pushq \old_rsp |
8c1f7558 JP |
512 | |
513 | .if \regs | |
514 | UNWIND_HINT_REGS indirect=1 | |
515 | .endif | |
2ba64741 DB |
516 | |
517 | .if \save_ret | |
518 | /* | |
519 | * Push the return address to the stack. This return address can | |
520 | * be found at the "real" original RSP, which was offset by 8 at | |
521 | * the beginning of this macro. | |
522 | */ | |
523 | pushq -8(\old_rsp) | |
524 | .endif | |
1d3e53e8 AL |
525 | .endm |
526 | ||
527 | /* | |
528 | * Undoes ENTER_IRQ_STACK. | |
529 | */ | |
8c1f7558 | 530 | .macro LEAVE_IRQ_STACK regs=1 |
1d3e53e8 AL |
531 | DEBUG_ENTRY_ASSERT_IRQS_OFF |
532 | /* We need to be off the IRQ stack before decrementing irq_count. */ | |
533 | popq %rsp | |
534 | ||
8c1f7558 JP |
535 | .if \regs |
536 | UNWIND_HINT_REGS | |
537 | .endif | |
538 | ||
1d3e53e8 AL |
539 | /* |
540 | * As in ENTER_IRQ_STACK, irq_count == 0, we are still claiming | |
541 | * the irq stack but we're not on it. | |
542 | */ | |
543 | ||
544 | decl PER_CPU_VAR(irq_count) | |
545 | .endm | |
546 | ||
d99015b1 | 547 | /* |
f3d415ea | 548 | * Interrupt entry helper function. |
d99015b1 | 549 | * |
f3d415ea DB |
550 | * Entry runs with interrupts off. Stack layout at entry: |
551 | * +----------------------------------------------------+ | |
552 | * | regs->ss | | |
553 | * | regs->rsp | | |
554 | * | regs->eflags | | |
555 | * | regs->cs | | |
556 | * | regs->ip | | |
557 | * +----------------------------------------------------+ | |
558 | * | regs->orig_ax = ~(interrupt number) | | |
559 | * +----------------------------------------------------+ | |
560 | * | return address | | |
561 | * +----------------------------------------------------+ | |
d99015b1 | 562 | */ |
f3d415ea DB |
563 | ENTRY(interrupt_entry) |
564 | UNWIND_HINT_FUNC | |
565 | ASM_CLAC | |
f6f64681 | 566 | cld |
7f2590a1 | 567 | |
f3d415ea | 568 | testb $3, CS-ORIG_RAX+8(%rsp) |
7f2590a1 AL |
569 | jz 1f |
570 | SWAPGS | |
f3d415ea DB |
571 | |
572 | /* | |
573 | * Switch to the thread stack. The IRET frame and orig_ax are | |
574 | * on the stack, as well as the return address. RDI..R12 are | |
575 | * not (yet) on the stack and space has not (yet) been | |
576 | * allocated for them. | |
577 | */ | |
90a6acc4 | 578 | pushq %rdi |
f3d415ea | 579 | |
90a6acc4 DB |
580 | /* Need to switch before accessing the thread stack. */ |
581 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi | |
582 | movq %rsp, %rdi | |
583 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
f3d415ea DB |
584 | |
585 | /* | |
586 | * We have RDI, return address, and orig_ax on the stack on | |
587 | * top of the IRET frame. That means offset=24 | |
588 | */ | |
589 | UNWIND_HINT_IRET_REGS base=%rdi offset=24 | |
90a6acc4 DB |
590 | |
591 | pushq 7*8(%rdi) /* regs->ss */ | |
592 | pushq 6*8(%rdi) /* regs->rsp */ | |
593 | pushq 5*8(%rdi) /* regs->eflags */ | |
594 | pushq 4*8(%rdi) /* regs->cs */ | |
595 | pushq 3*8(%rdi) /* regs->ip */ | |
596 | pushq 2*8(%rdi) /* regs->orig_ax */ | |
597 | pushq 8(%rdi) /* return address */ | |
598 | UNWIND_HINT_FUNC | |
599 | ||
600 | movq (%rdi), %rdi | |
7f2590a1 AL |
601 | 1: |
602 | ||
0e34d226 DB |
603 | PUSH_AND_CLEAR_REGS save_ret=1 |
604 | ENCODE_FRAME_POINTER 8 | |
76f5df43 | 605 | |
2ba64741 | 606 | testb $3, CS+8(%rsp) |
dde74f2e | 607 | jz 1f |
02bc7768 AL |
608 | |
609 | /* | |
7f2590a1 AL |
610 | * IRQ from user mode. |
611 | * | |
f1075053 AL |
612 | * We need to tell lockdep that IRQs are off. We can't do this until |
613 | * we fix gsbase, and we should do it before enter_from_user_mode | |
f3d415ea | 614 | * (which can take locks). Since TRACE_IRQS_OFF is idempotent, |
f1075053 AL |
615 | * the simplest way to handle it is to just call it twice if |
616 | * we enter from user mode. There's no reason to optimize this since | |
617 | * TRACE_IRQS_OFF is a no-op if lockdep is off. | |
618 | */ | |
619 | TRACE_IRQS_OFF | |
620 | ||
478dc89c | 621 | CALL_enter_from_user_mode |
02bc7768 | 622 | |
76f5df43 | 623 | 1: |
2ba64741 | 624 | ENTER_IRQ_STACK old_rsp=%rdi save_ret=1 |
f6f64681 DV |
625 | /* We entered an interrupt context - irqs are off: */ |
626 | TRACE_IRQS_OFF | |
627 | ||
2ba64741 DB |
628 | ret |
629 | END(interrupt_entry) | |
630 | ||
f3d415ea DB |
631 | |
632 | /* Interrupt entry/exit. */ | |
1da177e4 | 633 | |
722024db AH |
634 | /* |
635 | * The interrupt stubs push (~vector+0x80) onto the stack and | |
636 | * then jump to common_interrupt. | |
637 | */ | |
939b7871 PA |
638 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
639 | common_interrupt: | |
4d732138 | 640 | addq $-0x80, (%rsp) /* Adjust vector to [-256, -1] range */ |
3aa99fc3 DB |
641 | call interrupt_entry |
642 | UNWIND_HINT_REGS indirect=1 | |
643 | call do_IRQ /* rdi points to pt_regs */ | |
34061f13 | 644 | /* 0(%rsp): old RSP */ |
7effaa88 | 645 | ret_from_intr: |
2140a994 | 646 | DISABLE_INTERRUPTS(CLBR_ANY) |
2601e64d | 647 | TRACE_IRQS_OFF |
625dbc3b | 648 | |
1d3e53e8 | 649 | LEAVE_IRQ_STACK |
625dbc3b | 650 | |
03335e95 | 651 | testb $3, CS(%rsp) |
dde74f2e | 652 | jz retint_kernel |
4d732138 | 653 | |
02bc7768 | 654 | /* Interrupt came from user space */ |
02bc7768 AL |
655 | GLOBAL(retint_user) |
656 | mov %rsp,%rdi | |
657 | call prepare_exit_to_usermode | |
2601e64d | 658 | TRACE_IRQS_IRETQ |
26c4ef9c | 659 | |
8a055d7f | 660 | GLOBAL(swapgs_restore_regs_and_return_to_usermode) |
26c4ef9c AL |
661 | #ifdef CONFIG_DEBUG_ENTRY |
662 | /* Assert that pt_regs indicates user mode. */ | |
1e4c4f61 | 663 | testb $3, CS(%rsp) |
26c4ef9c AL |
664 | jnz 1f |
665 | ud2 | |
666 | 1: | |
667 | #endif | |
502af0d7 | 668 | POP_REGS pop_rdi=0 |
3e3b9293 AL |
669 | |
670 | /* | |
671 | * The stack is now user RDI, orig_ax, RIP, CS, EFLAGS, RSP, SS. | |
672 | * Save old stack pointer and switch to trampoline stack. | |
673 | */ | |
674 | movq %rsp, %rdi | |
c482feef | 675 | movq PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %rsp |
3e3b9293 AL |
676 | |
677 | /* Copy the IRET frame to the trampoline stack. */ | |
678 | pushq 6*8(%rdi) /* SS */ | |
679 | pushq 5*8(%rdi) /* RSP */ | |
680 | pushq 4*8(%rdi) /* EFLAGS */ | |
681 | pushq 3*8(%rdi) /* CS */ | |
682 | pushq 2*8(%rdi) /* RIP */ | |
683 | ||
684 | /* Push user RDI on the trampoline stack. */ | |
685 | pushq (%rdi) | |
686 | ||
687 | /* | |
688 | * We are on the trampoline stack. All regs except RDI are live. | |
689 | * We can do future final exit work right here. | |
690 | */ | |
691 | ||
6fd166aa | 692 | SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi |
8a09317b | 693 | |
3e3b9293 AL |
694 | /* Restore RDI. */ |
695 | popq %rdi | |
696 | SWAPGS | |
26c4ef9c AL |
697 | INTERRUPT_RETURN |
698 | ||
2601e64d | 699 | |
627276cb | 700 | /* Returning to kernel space */ |
6ba71b76 | 701 | retint_kernel: |
627276cb DV |
702 | #ifdef CONFIG_PREEMPT |
703 | /* Interrupts are off */ | |
704 | /* Check if we need preemption */ | |
6709812f | 705 | btl $9, EFLAGS(%rsp) /* were interrupts off? */ |
6ba71b76 | 706 | jnc 1f |
4d732138 | 707 | 0: cmpl $0, PER_CPU_VAR(__preempt_count) |
36acef25 | 708 | jnz 1f |
627276cb | 709 | call preempt_schedule_irq |
36acef25 | 710 | jmp 0b |
6ba71b76 | 711 | 1: |
627276cb | 712 | #endif |
2601e64d IM |
713 | /* |
714 | * The iretq could re-enable interrupts: | |
715 | */ | |
716 | TRACE_IRQS_IRETQ | |
fffbb5dc | 717 | |
26c4ef9c AL |
718 | GLOBAL(restore_regs_and_return_to_kernel) |
719 | #ifdef CONFIG_DEBUG_ENTRY | |
720 | /* Assert that pt_regs indicates kernel mode. */ | |
1e4c4f61 | 721 | testb $3, CS(%rsp) |
26c4ef9c AL |
722 | jz 1f |
723 | ud2 | |
724 | 1: | |
725 | #endif | |
502af0d7 | 726 | POP_REGS |
e872045b | 727 | addq $8, %rsp /* skip regs->orig_ax */ |
10bcc80e MD |
728 | /* |
729 | * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization | |
730 | * when returning from IPI handler. | |
731 | */ | |
7209a75d AL |
732 | INTERRUPT_RETURN |
733 | ||
734 | ENTRY(native_iret) | |
8c1f7558 | 735 | UNWIND_HINT_IRET_REGS |
3891a04a PA |
736 | /* |
737 | * Are we returning to a stack segment from the LDT? Note: in | |
738 | * 64-bit mode SS:RSP on the exception stack is always valid. | |
739 | */ | |
34273f41 | 740 | #ifdef CONFIG_X86_ESPFIX64 |
4d732138 IM |
741 | testb $4, (SS-RIP)(%rsp) |
742 | jnz native_irq_return_ldt | |
34273f41 | 743 | #endif |
3891a04a | 744 | |
af726f21 | 745 | .global native_irq_return_iret |
7209a75d | 746 | native_irq_return_iret: |
b645af2d AL |
747 | /* |
748 | * This may fault. Non-paranoid faults on return to userspace are | |
749 | * handled by fixup_bad_iret. These include #SS, #GP, and #NP. | |
750 | * Double-faults due to espfix64 are handled in do_double_fault. | |
751 | * Other faults here are fatal. | |
752 | */ | |
1da177e4 | 753 | iretq |
3701d863 | 754 | |
34273f41 | 755 | #ifdef CONFIG_X86_ESPFIX64 |
7209a75d | 756 | native_irq_return_ldt: |
85063fac AL |
757 | /* |
758 | * We are running with user GSBASE. All GPRs contain their user | |
759 | * values. We have a percpu ESPFIX stack that is eight slots | |
760 | * long (see ESPFIX_STACK_SIZE). espfix_waddr points to the bottom | |
761 | * of the ESPFIX stack. | |
762 | * | |
763 | * We clobber RAX and RDI in this code. We stash RDI on the | |
764 | * normal stack and RAX on the ESPFIX stack. | |
765 | * | |
766 | * The ESPFIX stack layout we set up looks like this: | |
767 | * | |
768 | * --- top of ESPFIX stack --- | |
769 | * SS | |
770 | * RSP | |
771 | * RFLAGS | |
772 | * CS | |
773 | * RIP <-- RSP points here when we're done | |
774 | * RAX <-- espfix_waddr points here | |
775 | * --- bottom of ESPFIX stack --- | |
776 | */ | |
777 | ||
778 | pushq %rdi /* Stash user RDI */ | |
8a09317b DH |
779 | SWAPGS /* to kernel GS */ |
780 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdi /* to kernel CR3 */ | |
781 | ||
4d732138 | 782 | movq PER_CPU_VAR(espfix_waddr), %rdi |
85063fac AL |
783 | movq %rax, (0*8)(%rdi) /* user RAX */ |
784 | movq (1*8)(%rsp), %rax /* user RIP */ | |
4d732138 | 785 | movq %rax, (1*8)(%rdi) |
85063fac | 786 | movq (2*8)(%rsp), %rax /* user CS */ |
4d732138 | 787 | movq %rax, (2*8)(%rdi) |
85063fac | 788 | movq (3*8)(%rsp), %rax /* user RFLAGS */ |
4d732138 | 789 | movq %rax, (3*8)(%rdi) |
85063fac | 790 | movq (5*8)(%rsp), %rax /* user SS */ |
4d732138 | 791 | movq %rax, (5*8)(%rdi) |
85063fac | 792 | movq (4*8)(%rsp), %rax /* user RSP */ |
4d732138 | 793 | movq %rax, (4*8)(%rdi) |
85063fac AL |
794 | /* Now RAX == RSP. */ |
795 | ||
796 | andl $0xffff0000, %eax /* RAX = (RSP & 0xffff0000) */ | |
85063fac AL |
797 | |
798 | /* | |
799 | * espfix_stack[31:16] == 0. The page tables are set up such that | |
800 | * (espfix_stack | (X & 0xffff0000)) points to a read-only alias of | |
801 | * espfix_waddr for any X. That is, there are 65536 RO aliases of | |
802 | * the same page. Set up RSP so that RSP[31:16] contains the | |
803 | * respective 16 bits of the /userspace/ RSP and RSP nonetheless | |
804 | * still points to an RO alias of the ESPFIX stack. | |
805 | */ | |
4d732138 | 806 | orq PER_CPU_VAR(espfix_stack), %rax |
8a09317b | 807 | |
6fd166aa | 808 | SWITCH_TO_USER_CR3_STACK scratch_reg=%rdi |
8a09317b DH |
809 | SWAPGS /* to user GS */ |
810 | popq %rdi /* Restore user RDI */ | |
811 | ||
4d732138 | 812 | movq %rax, %rsp |
8c1f7558 | 813 | UNWIND_HINT_IRET_REGS offset=8 |
85063fac AL |
814 | |
815 | /* | |
816 | * At this point, we cannot write to the stack any more, but we can | |
817 | * still read. | |
818 | */ | |
819 | popq %rax /* Restore user RAX */ | |
820 | ||
821 | /* | |
822 | * RSP now points to an ordinary IRET frame, except that the page | |
823 | * is read-only and RSP[31:16] are preloaded with the userspace | |
824 | * values. We can now IRET back to userspace. | |
825 | */ | |
4d732138 | 826 | jmp native_irq_return_iret |
34273f41 | 827 | #endif |
4b787e0b | 828 | END(common_interrupt) |
3891a04a | 829 | |
1da177e4 LT |
830 | /* |
831 | * APIC interrupts. | |
0bd7b798 | 832 | */ |
cf910e83 | 833 | .macro apicinterrupt3 num sym do_sym |
322648d1 | 834 | ENTRY(\sym) |
8c1f7558 | 835 | UNWIND_HINT_IRET_REGS |
4d732138 | 836 | pushq $~(\num) |
39e95433 | 837 | .Lcommon_\sym: |
3aa99fc3 DB |
838 | call interrupt_entry |
839 | UNWIND_HINT_REGS indirect=1 | |
840 | call \do_sym /* rdi points to pt_regs */ | |
4d732138 | 841 | jmp ret_from_intr |
322648d1 AH |
842 | END(\sym) |
843 | .endm | |
1da177e4 | 844 | |
469f0023 | 845 | /* Make sure APIC interrupt handlers end up in the irqentry section: */ |
229a7186 MH |
846 | #define PUSH_SECTION_IRQENTRY .pushsection .irqentry.text, "ax" |
847 | #define POP_SECTION_IRQENTRY .popsection | |
469f0023 | 848 | |
cf910e83 | 849 | .macro apicinterrupt num sym do_sym |
469f0023 | 850 | PUSH_SECTION_IRQENTRY |
cf910e83 | 851 | apicinterrupt3 \num \sym \do_sym |
469f0023 | 852 | POP_SECTION_IRQENTRY |
cf910e83 SA |
853 | .endm |
854 | ||
322648d1 | 855 | #ifdef CONFIG_SMP |
4d732138 IM |
856 | apicinterrupt3 IRQ_MOVE_CLEANUP_VECTOR irq_move_cleanup_interrupt smp_irq_move_cleanup_interrupt |
857 | apicinterrupt3 REBOOT_VECTOR reboot_interrupt smp_reboot_interrupt | |
322648d1 | 858 | #endif |
1da177e4 | 859 | |
03b48632 | 860 | #ifdef CONFIG_X86_UV |
4d732138 | 861 | apicinterrupt3 UV_BAU_MESSAGE uv_bau_message_intr1 uv_bau_message_interrupt |
03b48632 | 862 | #endif |
4d732138 IM |
863 | |
864 | apicinterrupt LOCAL_TIMER_VECTOR apic_timer_interrupt smp_apic_timer_interrupt | |
865 | apicinterrupt X86_PLATFORM_IPI_VECTOR x86_platform_ipi smp_x86_platform_ipi | |
89b831ef | 866 | |
d78f2664 | 867 | #ifdef CONFIG_HAVE_KVM |
4d732138 IM |
868 | apicinterrupt3 POSTED_INTR_VECTOR kvm_posted_intr_ipi smp_kvm_posted_intr_ipi |
869 | apicinterrupt3 POSTED_INTR_WAKEUP_VECTOR kvm_posted_intr_wakeup_ipi smp_kvm_posted_intr_wakeup_ipi | |
210f84b0 | 870 | apicinterrupt3 POSTED_INTR_NESTED_VECTOR kvm_posted_intr_nested_ipi smp_kvm_posted_intr_nested_ipi |
d78f2664 YZ |
871 | #endif |
872 | ||
33e5ff63 | 873 | #ifdef CONFIG_X86_MCE_THRESHOLD |
4d732138 | 874 | apicinterrupt THRESHOLD_APIC_VECTOR threshold_interrupt smp_threshold_interrupt |
33e5ff63 SA |
875 | #endif |
876 | ||
24fd78a8 | 877 | #ifdef CONFIG_X86_MCE_AMD |
4d732138 | 878 | apicinterrupt DEFERRED_ERROR_VECTOR deferred_error_interrupt smp_deferred_error_interrupt |
24fd78a8 AG |
879 | #endif |
880 | ||
33e5ff63 | 881 | #ifdef CONFIG_X86_THERMAL_VECTOR |
4d732138 | 882 | apicinterrupt THERMAL_APIC_VECTOR thermal_interrupt smp_thermal_interrupt |
33e5ff63 | 883 | #endif |
1812924b | 884 | |
322648d1 | 885 | #ifdef CONFIG_SMP |
4d732138 IM |
886 | apicinterrupt CALL_FUNCTION_SINGLE_VECTOR call_function_single_interrupt smp_call_function_single_interrupt |
887 | apicinterrupt CALL_FUNCTION_VECTOR call_function_interrupt smp_call_function_interrupt | |
888 | apicinterrupt RESCHEDULE_VECTOR reschedule_interrupt smp_reschedule_interrupt | |
322648d1 | 889 | #endif |
1da177e4 | 890 | |
4d732138 IM |
891 | apicinterrupt ERROR_APIC_VECTOR error_interrupt smp_error_interrupt |
892 | apicinterrupt SPURIOUS_APIC_VECTOR spurious_interrupt smp_spurious_interrupt | |
0bd7b798 | 893 | |
e360adbe | 894 | #ifdef CONFIG_IRQ_WORK |
4d732138 | 895 | apicinterrupt IRQ_WORK_VECTOR irq_work_interrupt smp_irq_work_interrupt |
241771ef IM |
896 | #endif |
897 | ||
1da177e4 LT |
898 | /* |
899 | * Exception entry points. | |
0bd7b798 | 900 | */ |
c482feef | 901 | #define CPU_TSS_IST(x) PER_CPU_VAR(cpu_tss_rw) + (TSS_ist + ((x) - 1) * 8) |
577ed45e AL |
902 | |
903 | .macro idtentry sym do_sym has_error_code:req paranoid=0 shift_ist=-1 | |
322648d1 | 904 | ENTRY(\sym) |
98990a33 | 905 | UNWIND_HINT_IRET_REGS offset=\has_error_code*8 |
8c1f7558 | 906 | |
577ed45e AL |
907 | /* Sanity check */ |
908 | .if \shift_ist != -1 && \paranoid == 0 | |
909 | .error "using shift_ist requires paranoid=1" | |
910 | .endif | |
911 | ||
ee4eb87b | 912 | ASM_CLAC |
cb5dd2c5 | 913 | |
82c62fa0 | 914 | .if \has_error_code == 0 |
4d732138 | 915 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
cb5dd2c5 AL |
916 | .endif |
917 | ||
071ccc96 | 918 | .if \paranoid == 1 |
9e809d15 | 919 | testb $3, CS-ORIG_RAX(%rsp) /* If coming from userspace, switch stacks */ |
7f2590a1 | 920 | jnz .Lfrom_usermode_switch_stack_\@ |
48e08d0f | 921 | .endif |
7f2590a1 AL |
922 | |
923 | .if \paranoid | |
4d732138 | 924 | call paranoid_entry |
cb5dd2c5 | 925 | .else |
4d732138 | 926 | call error_entry |
cb5dd2c5 | 927 | .endif |
8c1f7558 | 928 | UNWIND_HINT_REGS |
ebfc453e | 929 | /* returned flag: ebx=0: need swapgs on exit, ebx=1: don't need it */ |
cb5dd2c5 | 930 | |
cb5dd2c5 | 931 | .if \paranoid |
577ed45e | 932 | .if \shift_ist != -1 |
4d732138 | 933 | TRACE_IRQS_OFF_DEBUG /* reload IDT in case of recursion */ |
577ed45e | 934 | .else |
b8b1d08b | 935 | TRACE_IRQS_OFF |
cb5dd2c5 | 936 | .endif |
577ed45e | 937 | .endif |
cb5dd2c5 | 938 | |
4d732138 | 939 | movq %rsp, %rdi /* pt_regs pointer */ |
cb5dd2c5 AL |
940 | |
941 | .if \has_error_code | |
4d732138 IM |
942 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
943 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
cb5dd2c5 | 944 | .else |
4d732138 | 945 | xorl %esi, %esi /* no error code */ |
cb5dd2c5 AL |
946 | .endif |
947 | ||
577ed45e | 948 | .if \shift_ist != -1 |
4d732138 | 949 | subq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
950 | .endif |
951 | ||
4d732138 | 952 | call \do_sym |
cb5dd2c5 | 953 | |
577ed45e | 954 | .if \shift_ist != -1 |
4d732138 | 955 | addq $EXCEPTION_STKSZ, CPU_TSS_IST(\shift_ist) |
577ed45e AL |
956 | .endif |
957 | ||
ebfc453e | 958 | /* these procedures expect "no swapgs" flag in ebx */ |
cb5dd2c5 | 959 | .if \paranoid |
4d732138 | 960 | jmp paranoid_exit |
cb5dd2c5 | 961 | .else |
4d732138 | 962 | jmp error_exit |
cb5dd2c5 AL |
963 | .endif |
964 | ||
071ccc96 | 965 | .if \paranoid == 1 |
48e08d0f | 966 | /* |
7f2590a1 | 967 | * Entry from userspace. Switch stacks and treat it |
48e08d0f AL |
968 | * as a normal entry. This means that paranoid handlers |
969 | * run in real process context if user_mode(regs). | |
970 | */ | |
7f2590a1 | 971 | .Lfrom_usermode_switch_stack_\@: |
4d732138 | 972 | call error_entry |
48e08d0f | 973 | |
4d732138 | 974 | movq %rsp, %rdi /* pt_regs pointer */ |
48e08d0f AL |
975 | |
976 | .if \has_error_code | |
4d732138 IM |
977 | movq ORIG_RAX(%rsp), %rsi /* get error code */ |
978 | movq $-1, ORIG_RAX(%rsp) /* no syscall to restart */ | |
48e08d0f | 979 | .else |
4d732138 | 980 | xorl %esi, %esi /* no error code */ |
48e08d0f AL |
981 | .endif |
982 | ||
4d732138 | 983 | call \do_sym |
48e08d0f | 984 | |
b3681dd5 | 985 | jmp error_exit |
48e08d0f | 986 | .endif |
ddeb8f21 | 987 | END(\sym) |
322648d1 | 988 | .endm |
b8b1d08b | 989 | |
4d732138 IM |
990 | idtentry divide_error do_divide_error has_error_code=0 |
991 | idtentry overflow do_overflow has_error_code=0 | |
992 | idtentry bounds do_bounds has_error_code=0 | |
993 | idtentry invalid_op do_invalid_op has_error_code=0 | |
994 | idtentry device_not_available do_device_not_available has_error_code=0 | |
995 | idtentry double_fault do_double_fault has_error_code=1 paranoid=2 | |
996 | idtentry coprocessor_segment_overrun do_coprocessor_segment_overrun has_error_code=0 | |
997 | idtentry invalid_TSS do_invalid_TSS has_error_code=1 | |
998 | idtentry segment_not_present do_segment_not_present has_error_code=1 | |
999 | idtentry spurious_interrupt_bug do_spurious_interrupt_bug has_error_code=0 | |
1000 | idtentry coprocessor_error do_coprocessor_error has_error_code=0 | |
1001 | idtentry alignment_check do_alignment_check has_error_code=1 | |
1002 | idtentry simd_coprocessor_error do_simd_coprocessor_error has_error_code=0 | |
1003 | ||
1004 | ||
1005 | /* | |
1006 | * Reload gs selector with exception handling | |
1007 | * edi: new selector | |
1008 | */ | |
9f9d489a | 1009 | ENTRY(native_load_gs_index) |
8c1f7558 | 1010 | FRAME_BEGIN |
131484c8 | 1011 | pushfq |
b8aa287f | 1012 | DISABLE_INTERRUPTS(CLBR_ANY & ~CLBR_RDI) |
ca37e57b | 1013 | TRACE_IRQS_OFF |
9f1e87ea | 1014 | SWAPGS |
42c748bb | 1015 | .Lgs_change: |
4d732138 | 1016 | movl %edi, %gs |
96e5d28a | 1017 | 2: ALTERNATIVE "", "mfence", X86_BUG_SWAPGS_FENCE |
72fe4858 | 1018 | SWAPGS |
ca37e57b | 1019 | TRACE_IRQS_FLAGS (%rsp) |
131484c8 | 1020 | popfq |
8c1f7558 | 1021 | FRAME_END |
9f1e87ea | 1022 | ret |
8c1f7558 | 1023 | ENDPROC(native_load_gs_index) |
784d5699 | 1024 | EXPORT_SYMBOL(native_load_gs_index) |
0bd7b798 | 1025 | |
42c748bb | 1026 | _ASM_EXTABLE(.Lgs_change, bad_gs) |
4d732138 | 1027 | .section .fixup, "ax" |
1da177e4 | 1028 | /* running with kernelgs */ |
0bd7b798 | 1029 | bad_gs: |
4d732138 | 1030 | SWAPGS /* switch back to user gs */ |
b038c842 AL |
1031 | .macro ZAP_GS |
1032 | /* This can't be a string because the preprocessor needs to see it. */ | |
1033 | movl $__USER_DS, %eax | |
1034 | movl %eax, %gs | |
1035 | .endm | |
1036 | ALTERNATIVE "", "ZAP_GS", X86_BUG_NULL_SEG | |
4d732138 IM |
1037 | xorl %eax, %eax |
1038 | movl %eax, %gs | |
1039 | jmp 2b | |
9f1e87ea | 1040 | .previous |
0bd7b798 | 1041 | |
2699500b | 1042 | /* Call softirq on interrupt stack. Interrupts are off. */ |
7d65f4a6 | 1043 | ENTRY(do_softirq_own_stack) |
4d732138 IM |
1044 | pushq %rbp |
1045 | mov %rsp, %rbp | |
8c1f7558 | 1046 | ENTER_IRQ_STACK regs=0 old_rsp=%r11 |
4d732138 | 1047 | call __do_softirq |
8c1f7558 | 1048 | LEAVE_IRQ_STACK regs=0 |
2699500b | 1049 | leaveq |
ed6b676c | 1050 | ret |
8c1f7558 | 1051 | ENDPROC(do_softirq_own_stack) |
75154f40 | 1052 | |
3d75e1b8 | 1053 | #ifdef CONFIG_XEN |
5878d5d6 | 1054 | idtentry hypervisor_callback xen_do_hypervisor_callback has_error_code=0 |
3d75e1b8 JF |
1055 | |
1056 | /* | |
9f1e87ea CG |
1057 | * A note on the "critical region" in our callback handler. |
1058 | * We want to avoid stacking callback handlers due to events occurring | |
1059 | * during handling of the last event. To do this, we keep events disabled | |
1060 | * until we've done all processing. HOWEVER, we must enable events before | |
1061 | * popping the stack frame (can't be done atomically) and so it would still | |
1062 | * be possible to get enough handler activations to overflow the stack. | |
1063 | * Although unlikely, bugs of that kind are hard to track down, so we'd | |
1064 | * like to avoid the possibility. | |
1065 | * So, on entry to the handler we detect whether we interrupted an | |
1066 | * existing activation in its critical region -- if so, we pop the current | |
1067 | * activation and restart the handler using the previous one. | |
1068 | */ | |
4d732138 IM |
1069 | ENTRY(xen_do_hypervisor_callback) /* do_hypervisor_callback(struct *pt_regs) */ |
1070 | ||
9f1e87ea CG |
1071 | /* |
1072 | * Since we don't modify %rdi, evtchn_do_upall(struct *pt_regs) will | |
1073 | * see the correct pointer to the pt_regs | |
1074 | */ | |
8c1f7558 | 1075 | UNWIND_HINT_FUNC |
4d732138 | 1076 | movq %rdi, %rsp /* we don't return, adjust the stack frame */ |
8c1f7558 | 1077 | UNWIND_HINT_REGS |
1d3e53e8 AL |
1078 | |
1079 | ENTER_IRQ_STACK old_rsp=%r10 | |
4d732138 | 1080 | call xen_evtchn_do_upcall |
1d3e53e8 AL |
1081 | LEAVE_IRQ_STACK |
1082 | ||
fdfd811d | 1083 | #ifndef CONFIG_PREEMPT |
4d732138 | 1084 | call xen_maybe_preempt_hcall |
fdfd811d | 1085 | #endif |
4d732138 | 1086 | jmp error_exit |
371c394a | 1087 | END(xen_do_hypervisor_callback) |
3d75e1b8 JF |
1088 | |
1089 | /* | |
9f1e87ea CG |
1090 | * Hypervisor uses this for application faults while it executes. |
1091 | * We get here for two reasons: | |
1092 | * 1. Fault while reloading DS, ES, FS or GS | |
1093 | * 2. Fault while executing IRET | |
1094 | * Category 1 we do not need to fix up as Xen has already reloaded all segment | |
1095 | * registers that could be reloaded and zeroed the others. | |
1096 | * Category 2 we fix up by killing the current process. We cannot use the | |
1097 | * normal Linux return path in this case because if we use the IRET hypercall | |
1098 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
1099 | * We distinguish between categories by comparing each saved segment register | |
1100 | * with its current contents: any discrepancy means we in category 1. | |
1101 | */ | |
3d75e1b8 | 1102 | ENTRY(xen_failsafe_callback) |
8c1f7558 | 1103 | UNWIND_HINT_EMPTY |
4d732138 IM |
1104 | movl %ds, %ecx |
1105 | cmpw %cx, 0x10(%rsp) | |
1106 | jne 1f | |
1107 | movl %es, %ecx | |
1108 | cmpw %cx, 0x18(%rsp) | |
1109 | jne 1f | |
1110 | movl %fs, %ecx | |
1111 | cmpw %cx, 0x20(%rsp) | |
1112 | jne 1f | |
1113 | movl %gs, %ecx | |
1114 | cmpw %cx, 0x28(%rsp) | |
1115 | jne 1f | |
3d75e1b8 | 1116 | /* All segments match their saved values => Category 2 (Bad IRET). */ |
4d732138 IM |
1117 | movq (%rsp), %rcx |
1118 | movq 8(%rsp), %r11 | |
1119 | addq $0x30, %rsp | |
1120 | pushq $0 /* RIP */ | |
8c1f7558 | 1121 | UNWIND_HINT_IRET_REGS offset=8 |
4d732138 | 1122 | jmp general_protection |
3d75e1b8 | 1123 | 1: /* Segment mismatch => Category 1 (Bad segment). Retry the IRET. */ |
4d732138 IM |
1124 | movq (%rsp), %rcx |
1125 | movq 8(%rsp), %r11 | |
1126 | addq $0x30, %rsp | |
8c1f7558 | 1127 | UNWIND_HINT_IRET_REGS |
4d732138 | 1128 | pushq $-1 /* orig_ax = -1 => not a system call */ |
3f01daec | 1129 | PUSH_AND_CLEAR_REGS |
946c1911 | 1130 | ENCODE_FRAME_POINTER |
4d732138 | 1131 | jmp error_exit |
3d75e1b8 JF |
1132 | END(xen_failsafe_callback) |
1133 | ||
cf910e83 | 1134 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
38e20b07 SY |
1135 | xen_hvm_callback_vector xen_evtchn_do_upcall |
1136 | ||
3d75e1b8 | 1137 | #endif /* CONFIG_XEN */ |
ddeb8f21 | 1138 | |
bc2b0331 | 1139 | #if IS_ENABLED(CONFIG_HYPERV) |
cf910e83 | 1140 | apicinterrupt3 HYPERVISOR_CALLBACK_VECTOR \ |
bc2b0331 | 1141 | hyperv_callback_vector hyperv_vector_handler |
93286261 VK |
1142 | |
1143 | apicinterrupt3 HYPERV_REENLIGHTENMENT_VECTOR \ | |
1144 | hyperv_reenlightenment_vector hyperv_reenlightenment_intr | |
248e742a MK |
1145 | |
1146 | apicinterrupt3 HYPERV_STIMER0_VECTOR \ | |
1147 | hv_stimer0_callback_vector hv_stimer0_vector_handler | |
bc2b0331 S |
1148 | #endif /* CONFIG_HYPERV */ |
1149 | ||
4d732138 | 1150 | idtentry debug do_debug has_error_code=0 paranoid=1 shift_ist=DEBUG_STACK |
d8ba61ba | 1151 | idtentry int3 do_int3 has_error_code=0 |
4d732138 IM |
1152 | idtentry stack_segment do_stack_segment has_error_code=1 |
1153 | ||
6cac5a92 | 1154 | #ifdef CONFIG_XEN |
43e41110 | 1155 | idtentry xennmi do_nmi has_error_code=0 |
5878d5d6 JG |
1156 | idtentry xendebug do_debug has_error_code=0 |
1157 | idtentry xenint3 do_int3 has_error_code=0 | |
6cac5a92 | 1158 | #endif |
4d732138 IM |
1159 | |
1160 | idtentry general_protection do_general_protection has_error_code=1 | |
11a7ffb0 | 1161 | idtentry page_fault do_page_fault has_error_code=1 |
4d732138 | 1162 | |
631bc487 | 1163 | #ifdef CONFIG_KVM_GUEST |
4d732138 | 1164 | idtentry async_page_fault do_async_page_fault has_error_code=1 |
631bc487 | 1165 | #endif |
4d732138 | 1166 | |
ddeb8f21 | 1167 | #ifdef CONFIG_X86_MCE |
6f41c34d | 1168 | idtentry machine_check do_mce has_error_code=0 paranoid=1 |
ddeb8f21 AH |
1169 | #endif |
1170 | ||
ebfc453e | 1171 | /* |
9e809d15 | 1172 | * Save all registers in pt_regs, and switch gs if needed. |
ebfc453e DV |
1173 | * Use slow, but surefire "are we in kernel?" check. |
1174 | * Return: ebx=0: need swapgs on exit, ebx=1: otherwise | |
1175 | */ | |
1176 | ENTRY(paranoid_entry) | |
8c1f7558 | 1177 | UNWIND_HINT_FUNC |
1eeb207f | 1178 | cld |
9e809d15 DB |
1179 | PUSH_AND_CLEAR_REGS save_ret=1 |
1180 | ENCODE_FRAME_POINTER 8 | |
4d732138 IM |
1181 | movl $1, %ebx |
1182 | movl $MSR_GS_BASE, %ecx | |
1eeb207f | 1183 | rdmsr |
4d732138 IM |
1184 | testl %edx, %edx |
1185 | js 1f /* negative -> in kernel */ | |
1eeb207f | 1186 | SWAPGS |
4d732138 | 1187 | xorl %ebx, %ebx |
8a09317b DH |
1188 | |
1189 | 1: | |
1190 | SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14 | |
1191 | ||
1192 | ret | |
ebfc453e | 1193 | END(paranoid_entry) |
ddeb8f21 | 1194 | |
ebfc453e DV |
1195 | /* |
1196 | * "Paranoid" exit path from exception stack. This is invoked | |
1197 | * only on return from non-NMI IST interrupts that came | |
1198 | * from kernel space. | |
1199 | * | |
1200 | * We may be returning to very strange contexts (e.g. very early | |
1201 | * in syscall entry), so checking for preemption here would | |
1202 | * be complicated. Fortunately, we there's no good reason | |
1203 | * to try to handle preemption here. | |
4d732138 IM |
1204 | * |
1205 | * On entry, ebx is "no swapgs" flag (1: don't need swapgs, 0: need it) | |
ebfc453e | 1206 | */ |
ddeb8f21 | 1207 | ENTRY(paranoid_exit) |
8c1f7558 | 1208 | UNWIND_HINT_REGS |
2140a994 | 1209 | DISABLE_INTERRUPTS(CLBR_ANY) |
5963e317 | 1210 | TRACE_IRQS_OFF_DEBUG |
4d732138 | 1211 | testl %ebx, %ebx /* swapgs needed? */ |
e5317832 | 1212 | jnz .Lparanoid_exit_no_swapgs |
f2db9382 | 1213 | TRACE_IRQS_IRETQ |
21e94459 | 1214 | RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 |
ddeb8f21 | 1215 | SWAPGS_UNSAFE_STACK |
e5317832 AL |
1216 | jmp .Lparanoid_exit_restore |
1217 | .Lparanoid_exit_no_swapgs: | |
f2db9382 | 1218 | TRACE_IRQS_IRETQ_DEBUG |
e4865757 | 1219 | RESTORE_CR3 scratch_reg=%rbx save_reg=%r14 |
e5317832 AL |
1220 | .Lparanoid_exit_restore: |
1221 | jmp restore_regs_and_return_to_kernel | |
ddeb8f21 AH |
1222 | END(paranoid_exit) |
1223 | ||
1224 | /* | |
9e809d15 | 1225 | * Save all registers in pt_regs, and switch GS if needed. |
ddeb8f21 AH |
1226 | */ |
1227 | ENTRY(error_entry) | |
9e809d15 | 1228 | UNWIND_HINT_FUNC |
ddeb8f21 | 1229 | cld |
9e809d15 DB |
1230 | PUSH_AND_CLEAR_REGS save_ret=1 |
1231 | ENCODE_FRAME_POINTER 8 | |
03335e95 | 1232 | testb $3, CS+8(%rsp) |
cb6f64ed | 1233 | jz .Lerror_kernelspace |
539f5113 | 1234 | |
cb6f64ed AL |
1235 | /* |
1236 | * We entered from user mode or we're pretending to have entered | |
1237 | * from user mode due to an IRET fault. | |
1238 | */ | |
ddeb8f21 | 1239 | SWAPGS |
8a09317b DH |
1240 | /* We have user CR3. Change to kernel CR3. */ |
1241 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax | |
539f5113 | 1242 | |
cb6f64ed | 1243 | .Lerror_entry_from_usermode_after_swapgs: |
7f2590a1 AL |
1244 | /* Put us onto the real thread stack. */ |
1245 | popq %r12 /* save return addr in %12 */ | |
1246 | movq %rsp, %rdi /* arg0 = pt_regs pointer */ | |
1247 | call sync_regs | |
1248 | movq %rax, %rsp /* switch stack */ | |
1249 | ENCODE_FRAME_POINTER | |
1250 | pushq %r12 | |
1251 | ||
f1075053 AL |
1252 | /* |
1253 | * We need to tell lockdep that IRQs are off. We can't do this until | |
1254 | * we fix gsbase, and we should do it before enter_from_user_mode | |
1255 | * (which can take locks). | |
1256 | */ | |
1257 | TRACE_IRQS_OFF | |
478dc89c | 1258 | CALL_enter_from_user_mode |
f1075053 | 1259 | ret |
02bc7768 | 1260 | |
cb6f64ed | 1261 | .Lerror_entry_done: |
ddeb8f21 AH |
1262 | TRACE_IRQS_OFF |
1263 | ret | |
ddeb8f21 | 1264 | |
ebfc453e DV |
1265 | /* |
1266 | * There are two places in the kernel that can potentially fault with | |
1267 | * usergs. Handle them here. B stepping K8s sometimes report a | |
1268 | * truncated RIP for IRET exceptions returning to compat mode. Check | |
1269 | * for these here too. | |
1270 | */ | |
cb6f64ed | 1271 | .Lerror_kernelspace: |
4d732138 IM |
1272 | leaq native_irq_return_iret(%rip), %rcx |
1273 | cmpq %rcx, RIP+8(%rsp) | |
cb6f64ed | 1274 | je .Lerror_bad_iret |
4d732138 IM |
1275 | movl %ecx, %eax /* zero extend */ |
1276 | cmpq %rax, RIP+8(%rsp) | |
cb6f64ed | 1277 | je .Lbstep_iret |
42c748bb | 1278 | cmpq $.Lgs_change, RIP+8(%rsp) |
cb6f64ed | 1279 | jne .Lerror_entry_done |
539f5113 AL |
1280 | |
1281 | /* | |
42c748bb | 1282 | * hack: .Lgs_change can fail with user gsbase. If this happens, fix up |
539f5113 | 1283 | * gsbase and proceed. We'll fix up the exception and land in |
42c748bb | 1284 | * .Lgs_change's error handler with kernel gsbase. |
539f5113 | 1285 | */ |
2fa5f04f | 1286 | SWAPGS |
8a09317b | 1287 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax |
2fa5f04f | 1288 | jmp .Lerror_entry_done |
ae24ffe5 | 1289 | |
cb6f64ed | 1290 | .Lbstep_iret: |
ae24ffe5 | 1291 | /* Fix truncated RIP */ |
4d732138 | 1292 | movq %rcx, RIP+8(%rsp) |
b645af2d AL |
1293 | /* fall through */ |
1294 | ||
cb6f64ed | 1295 | .Lerror_bad_iret: |
539f5113 | 1296 | /* |
8a09317b DH |
1297 | * We came from an IRET to user mode, so we have user |
1298 | * gsbase and CR3. Switch to kernel gsbase and CR3: | |
539f5113 | 1299 | */ |
b645af2d | 1300 | SWAPGS |
8a09317b | 1301 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rax |
539f5113 AL |
1302 | |
1303 | /* | |
1304 | * Pretend that the exception came from user mode: set up pt_regs | |
b3681dd5 | 1305 | * as if we faulted immediately after IRET. |
539f5113 | 1306 | */ |
4d732138 IM |
1307 | mov %rsp, %rdi |
1308 | call fixup_bad_iret | |
1309 | mov %rax, %rsp | |
cb6f64ed | 1310 | jmp .Lerror_entry_from_usermode_after_swapgs |
ddeb8f21 AH |
1311 | END(error_entry) |
1312 | ||
ddeb8f21 | 1313 | ENTRY(error_exit) |
8c1f7558 | 1314 | UNWIND_HINT_REGS |
2140a994 | 1315 | DISABLE_INTERRUPTS(CLBR_ANY) |
ddeb8f21 | 1316 | TRACE_IRQS_OFF |
b3681dd5 AL |
1317 | testb $3, CS(%rsp) |
1318 | jz retint_kernel | |
4d732138 | 1319 | jmp retint_user |
ddeb8f21 AH |
1320 | END(error_exit) |
1321 | ||
929bacec AL |
1322 | /* |
1323 | * Runs on exception stack. Xen PV does not go through this path at all, | |
1324 | * so we can use real assembly here. | |
8a09317b DH |
1325 | * |
1326 | * Registers: | |
1327 | * %r14: Used to save/restore the CR3 of the interrupted context | |
1328 | * when PAGE_TABLE_ISOLATION is in use. Do not clobber. | |
929bacec | 1329 | */ |
ddeb8f21 | 1330 | ENTRY(nmi) |
8c1f7558 | 1331 | UNWIND_HINT_IRET_REGS |
929bacec | 1332 | |
3f3c8b8c SR |
1333 | /* |
1334 | * We allow breakpoints in NMIs. If a breakpoint occurs, then | |
1335 | * the iretq it performs will take us out of NMI context. | |
1336 | * This means that we can have nested NMIs where the next | |
1337 | * NMI is using the top of the stack of the previous NMI. We | |
1338 | * can't let it execute because the nested NMI will corrupt the | |
1339 | * stack of the previous NMI. NMI handlers are not re-entrant | |
1340 | * anyway. | |
1341 | * | |
1342 | * To handle this case we do the following: | |
1343 | * Check the a special location on the stack that contains | |
1344 | * a variable that is set when NMIs are executing. | |
1345 | * The interrupted task's stack is also checked to see if it | |
1346 | * is an NMI stack. | |
1347 | * If the variable is not set and the stack is not the NMI | |
1348 | * stack then: | |
1349 | * o Set the special variable on the stack | |
0b22930e AL |
1350 | * o Copy the interrupt frame into an "outermost" location on the |
1351 | * stack | |
1352 | * o Copy the interrupt frame into an "iret" location on the stack | |
3f3c8b8c SR |
1353 | * o Continue processing the NMI |
1354 | * If the variable is set or the previous stack is the NMI stack: | |
0b22930e | 1355 | * o Modify the "iret" location to jump to the repeat_nmi |
3f3c8b8c SR |
1356 | * o return back to the first NMI |
1357 | * | |
1358 | * Now on exit of the first NMI, we first clear the stack variable | |
1359 | * The NMI stack will tell any nested NMIs at that point that it is | |
1360 | * nested. Then we pop the stack normally with iret, and if there was | |
1361 | * a nested NMI that updated the copy interrupt stack frame, a | |
1362 | * jump will be made to the repeat_nmi code that will handle the second | |
1363 | * NMI. | |
9b6e6a83 AL |
1364 | * |
1365 | * However, espfix prevents us from directly returning to userspace | |
1366 | * with a single IRET instruction. Similarly, IRET to user mode | |
1367 | * can fault. We therefore handle NMIs from user space like | |
1368 | * other IST entries. | |
3f3c8b8c SR |
1369 | */ |
1370 | ||
e93c1730 AL |
1371 | ASM_CLAC |
1372 | ||
146b2b09 | 1373 | /* Use %rdx as our temp variable throughout */ |
4d732138 | 1374 | pushq %rdx |
3f3c8b8c | 1375 | |
9b6e6a83 AL |
1376 | testb $3, CS-RIP+8(%rsp) |
1377 | jz .Lnmi_from_kernel | |
1378 | ||
1379 | /* | |
1380 | * NMI from user mode. We need to run on the thread stack, but we | |
1381 | * can't go through the normal entry paths: NMIs are masked, and | |
1382 | * we don't want to enable interrupts, because then we'll end | |
1383 | * up in an awkward situation in which IRQs are on but NMIs | |
1384 | * are off. | |
83c133cf AL |
1385 | * |
1386 | * We also must not push anything to the stack before switching | |
1387 | * stacks lest we corrupt the "NMI executing" variable. | |
9b6e6a83 AL |
1388 | */ |
1389 | ||
929bacec | 1390 | swapgs |
9b6e6a83 | 1391 | cld |
8a09317b | 1392 | SWITCH_TO_KERNEL_CR3 scratch_reg=%rdx |
9b6e6a83 AL |
1393 | movq %rsp, %rdx |
1394 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rsp | |
8c1f7558 | 1395 | UNWIND_HINT_IRET_REGS base=%rdx offset=8 |
9b6e6a83 AL |
1396 | pushq 5*8(%rdx) /* pt_regs->ss */ |
1397 | pushq 4*8(%rdx) /* pt_regs->rsp */ | |
1398 | pushq 3*8(%rdx) /* pt_regs->flags */ | |
1399 | pushq 2*8(%rdx) /* pt_regs->cs */ | |
1400 | pushq 1*8(%rdx) /* pt_regs->rip */ | |
8c1f7558 | 1401 | UNWIND_HINT_IRET_REGS |
9b6e6a83 | 1402 | pushq $-1 /* pt_regs->orig_ax */ |
30907fd1 | 1403 | PUSH_AND_CLEAR_REGS rdx=(%rdx) |
946c1911 | 1404 | ENCODE_FRAME_POINTER |
9b6e6a83 AL |
1405 | |
1406 | /* | |
1407 | * At this point we no longer need to worry about stack damage | |
1408 | * due to nesting -- we're on the normal thread stack and we're | |
1409 | * done with the NMI stack. | |
1410 | */ | |
1411 | ||
1412 | movq %rsp, %rdi | |
1413 | movq $-1, %rsi | |
1414 | call do_nmi | |
1415 | ||
45d5a168 | 1416 | /* |
9b6e6a83 | 1417 | * Return back to user mode. We must *not* do the normal exit |
946c1911 | 1418 | * work, because we don't want to enable interrupts. |
45d5a168 | 1419 | */ |
8a055d7f | 1420 | jmp swapgs_restore_regs_and_return_to_usermode |
45d5a168 | 1421 | |
9b6e6a83 | 1422 | .Lnmi_from_kernel: |
3f3c8b8c | 1423 | /* |
0b22930e AL |
1424 | * Here's what our stack frame will look like: |
1425 | * +---------------------------------------------------------+ | |
1426 | * | original SS | | |
1427 | * | original Return RSP | | |
1428 | * | original RFLAGS | | |
1429 | * | original CS | | |
1430 | * | original RIP | | |
1431 | * +---------------------------------------------------------+ | |
1432 | * | temp storage for rdx | | |
1433 | * +---------------------------------------------------------+ | |
1434 | * | "NMI executing" variable | | |
1435 | * +---------------------------------------------------------+ | |
1436 | * | iret SS } Copied from "outermost" frame | | |
1437 | * | iret Return RSP } on each loop iteration; overwritten | | |
1438 | * | iret RFLAGS } by a nested NMI to force another | | |
1439 | * | iret CS } iteration if needed. | | |
1440 | * | iret RIP } | | |
1441 | * +---------------------------------------------------------+ | |
1442 | * | outermost SS } initialized in first_nmi; | | |
1443 | * | outermost Return RSP } will not be changed before | | |
1444 | * | outermost RFLAGS } NMI processing is done. | | |
1445 | * | outermost CS } Copied to "iret" frame on each | | |
1446 | * | outermost RIP } iteration. | | |
1447 | * +---------------------------------------------------------+ | |
1448 | * | pt_regs | | |
1449 | * +---------------------------------------------------------+ | |
1450 | * | |
1451 | * The "original" frame is used by hardware. Before re-enabling | |
1452 | * NMIs, we need to be done with it, and we need to leave enough | |
1453 | * space for the asm code here. | |
1454 | * | |
1455 | * We return by executing IRET while RSP points to the "iret" frame. | |
1456 | * That will either return for real or it will loop back into NMI | |
1457 | * processing. | |
1458 | * | |
1459 | * The "outermost" frame is copied to the "iret" frame on each | |
1460 | * iteration of the loop, so each iteration starts with the "iret" | |
1461 | * frame pointing to the final return target. | |
1462 | */ | |
1463 | ||
45d5a168 | 1464 | /* |
0b22930e AL |
1465 | * Determine whether we're a nested NMI. |
1466 | * | |
a27507ca AL |
1467 | * If we interrupted kernel code between repeat_nmi and |
1468 | * end_repeat_nmi, then we are a nested NMI. We must not | |
1469 | * modify the "iret" frame because it's being written by | |
1470 | * the outer NMI. That's okay; the outer NMI handler is | |
1471 | * about to about to call do_nmi anyway, so we can just | |
1472 | * resume the outer NMI. | |
45d5a168 | 1473 | */ |
a27507ca AL |
1474 | |
1475 | movq $repeat_nmi, %rdx | |
1476 | cmpq 8(%rsp), %rdx | |
1477 | ja 1f | |
1478 | movq $end_repeat_nmi, %rdx | |
1479 | cmpq 8(%rsp), %rdx | |
1480 | ja nested_nmi_out | |
1481 | 1: | |
45d5a168 | 1482 | |
3f3c8b8c | 1483 | /* |
a27507ca | 1484 | * Now check "NMI executing". If it's set, then we're nested. |
0b22930e AL |
1485 | * This will not detect if we interrupted an outer NMI just |
1486 | * before IRET. | |
3f3c8b8c | 1487 | */ |
4d732138 IM |
1488 | cmpl $1, -8(%rsp) |
1489 | je nested_nmi | |
3f3c8b8c SR |
1490 | |
1491 | /* | |
0b22930e AL |
1492 | * Now test if the previous stack was an NMI stack. This covers |
1493 | * the case where we interrupt an outer NMI after it clears | |
810bc075 AL |
1494 | * "NMI executing" but before IRET. We need to be careful, though: |
1495 | * there is one case in which RSP could point to the NMI stack | |
1496 | * despite there being no NMI active: naughty userspace controls | |
1497 | * RSP at the very beginning of the SYSCALL targets. We can | |
1498 | * pull a fast one on naughty userspace, though: we program | |
1499 | * SYSCALL to mask DF, so userspace cannot cause DF to be set | |
1500 | * if it controls the kernel's RSP. We set DF before we clear | |
1501 | * "NMI executing". | |
3f3c8b8c | 1502 | */ |
0784b364 DV |
1503 | lea 6*8(%rsp), %rdx |
1504 | /* Compare the NMI stack (rdx) with the stack we came from (4*8(%rsp)) */ | |
1505 | cmpq %rdx, 4*8(%rsp) | |
1506 | /* If the stack pointer is above the NMI stack, this is a normal NMI */ | |
1507 | ja first_nmi | |
4d732138 | 1508 | |
0784b364 DV |
1509 | subq $EXCEPTION_STKSZ, %rdx |
1510 | cmpq %rdx, 4*8(%rsp) | |
1511 | /* If it is below the NMI stack, it is a normal NMI */ | |
1512 | jb first_nmi | |
810bc075 AL |
1513 | |
1514 | /* Ah, it is within the NMI stack. */ | |
1515 | ||
1516 | testb $(X86_EFLAGS_DF >> 8), (3*8 + 1)(%rsp) | |
1517 | jz first_nmi /* RSP was user controlled. */ | |
1518 | ||
1519 | /* This is a nested NMI. */ | |
0784b364 | 1520 | |
3f3c8b8c SR |
1521 | nested_nmi: |
1522 | /* | |
0b22930e AL |
1523 | * Modify the "iret" frame to point to repeat_nmi, forcing another |
1524 | * iteration of NMI handling. | |
3f3c8b8c | 1525 | */ |
23a781e9 | 1526 | subq $8, %rsp |
4d732138 IM |
1527 | leaq -10*8(%rsp), %rdx |
1528 | pushq $__KERNEL_DS | |
1529 | pushq %rdx | |
131484c8 | 1530 | pushfq |
4d732138 IM |
1531 | pushq $__KERNEL_CS |
1532 | pushq $repeat_nmi | |
3f3c8b8c SR |
1533 | |
1534 | /* Put stack back */ | |
4d732138 | 1535 | addq $(6*8), %rsp |
3f3c8b8c SR |
1536 | |
1537 | nested_nmi_out: | |
4d732138 | 1538 | popq %rdx |
3f3c8b8c | 1539 | |
0b22930e | 1540 | /* We are returning to kernel mode, so this cannot result in a fault. */ |
929bacec | 1541 | iretq |
3f3c8b8c SR |
1542 | |
1543 | first_nmi: | |
0b22930e | 1544 | /* Restore rdx. */ |
4d732138 | 1545 | movq (%rsp), %rdx |
62610913 | 1546 | |
36f1a77b AL |
1547 | /* Make room for "NMI executing". */ |
1548 | pushq $0 | |
3f3c8b8c | 1549 | |
0b22930e | 1550 | /* Leave room for the "iret" frame */ |
4d732138 | 1551 | subq $(5*8), %rsp |
28696f43 | 1552 | |
0b22930e | 1553 | /* Copy the "original" frame to the "outermost" frame */ |
3f3c8b8c | 1554 | .rept 5 |
4d732138 | 1555 | pushq 11*8(%rsp) |
3f3c8b8c | 1556 | .endr |
8c1f7558 | 1557 | UNWIND_HINT_IRET_REGS |
62610913 | 1558 | |
79fb4ad6 SR |
1559 | /* Everything up to here is safe from nested NMIs */ |
1560 | ||
a97439aa AL |
1561 | #ifdef CONFIG_DEBUG_ENTRY |
1562 | /* | |
1563 | * For ease of testing, unmask NMIs right away. Disabled by | |
1564 | * default because IRET is very expensive. | |
1565 | */ | |
1566 | pushq $0 /* SS */ | |
1567 | pushq %rsp /* RSP (minus 8 because of the previous push) */ | |
1568 | addq $8, (%rsp) /* Fix up RSP */ | |
1569 | pushfq /* RFLAGS */ | |
1570 | pushq $__KERNEL_CS /* CS */ | |
1571 | pushq $1f /* RIP */ | |
929bacec | 1572 | iretq /* continues at repeat_nmi below */ |
8c1f7558 | 1573 | UNWIND_HINT_IRET_REGS |
a97439aa AL |
1574 | 1: |
1575 | #endif | |
1576 | ||
0b22930e | 1577 | repeat_nmi: |
62610913 JB |
1578 | /* |
1579 | * If there was a nested NMI, the first NMI's iret will return | |
1580 | * here. But NMIs are still enabled and we can take another | |
1581 | * nested NMI. The nested NMI checks the interrupted RIP to see | |
1582 | * if it is between repeat_nmi and end_repeat_nmi, and if so | |
1583 | * it will just return, as we are about to repeat an NMI anyway. | |
1584 | * This makes it safe to copy to the stack frame that a nested | |
1585 | * NMI will update. | |
0b22930e AL |
1586 | * |
1587 | * RSP is pointing to "outermost RIP". gsbase is unknown, but, if | |
1588 | * we're repeating an NMI, gsbase has the same value that it had on | |
1589 | * the first iteration. paranoid_entry will load the kernel | |
36f1a77b AL |
1590 | * gsbase if needed before we call do_nmi. "NMI executing" |
1591 | * is zero. | |
62610913 | 1592 | */ |
36f1a77b | 1593 | movq $1, 10*8(%rsp) /* Set "NMI executing". */ |
3f3c8b8c | 1594 | |
62610913 | 1595 | /* |
0b22930e AL |
1596 | * Copy the "outermost" frame to the "iret" frame. NMIs that nest |
1597 | * here must not modify the "iret" frame while we're writing to | |
1598 | * it or it will end up containing garbage. | |
62610913 | 1599 | */ |
4d732138 | 1600 | addq $(10*8), %rsp |
3f3c8b8c | 1601 | .rept 5 |
4d732138 | 1602 | pushq -6*8(%rsp) |
3f3c8b8c | 1603 | .endr |
4d732138 | 1604 | subq $(5*8), %rsp |
62610913 | 1605 | end_repeat_nmi: |
3f3c8b8c SR |
1606 | |
1607 | /* | |
0b22930e AL |
1608 | * Everything below this point can be preempted by a nested NMI. |
1609 | * If this happens, then the inner NMI will change the "iret" | |
1610 | * frame to point back to repeat_nmi. | |
3f3c8b8c | 1611 | */ |
4d732138 | 1612 | pushq $-1 /* ORIG_RAX: no syscall to restart */ |
76f5df43 | 1613 | |
1fd466ef | 1614 | /* |
ebfc453e | 1615 | * Use paranoid_entry to handle SWAPGS, but no need to use paranoid_exit |
1fd466ef SR |
1616 | * as we should not be calling schedule in NMI context. |
1617 | * Even with normal interrupts enabled. An NMI should not be | |
1618 | * setting NEED_RESCHED or anything that normal interrupts and | |
1619 | * exceptions might do. | |
1620 | */ | |
4d732138 | 1621 | call paranoid_entry |
8c1f7558 | 1622 | UNWIND_HINT_REGS |
7fbb98c5 | 1623 | |
ddeb8f21 | 1624 | /* paranoidentry do_nmi, 0; without TRACE_IRQS_OFF */ |
4d732138 IM |
1625 | movq %rsp, %rdi |
1626 | movq $-1, %rsi | |
1627 | call do_nmi | |
7fbb98c5 | 1628 | |
21e94459 | 1629 | RESTORE_CR3 scratch_reg=%r15 save_reg=%r14 |
8a09317b | 1630 | |
4d732138 IM |
1631 | testl %ebx, %ebx /* swapgs needed? */ |
1632 | jnz nmi_restore | |
ddeb8f21 AH |
1633 | nmi_swapgs: |
1634 | SWAPGS_UNSAFE_STACK | |
1635 | nmi_restore: | |
502af0d7 | 1636 | POP_REGS |
0b22930e | 1637 | |
471ee483 AL |
1638 | /* |
1639 | * Skip orig_ax and the "outermost" frame to point RSP at the "iret" | |
1640 | * at the "iret" frame. | |
1641 | */ | |
1642 | addq $6*8, %rsp | |
28696f43 | 1643 | |
810bc075 AL |
1644 | /* |
1645 | * Clear "NMI executing". Set DF first so that we can easily | |
1646 | * distinguish the remaining code between here and IRET from | |
929bacec AL |
1647 | * the SYSCALL entry and exit paths. |
1648 | * | |
1649 | * We arguably should just inspect RIP instead, but I (Andy) wrote | |
1650 | * this code when I had the misapprehension that Xen PV supported | |
1651 | * NMIs, and Xen PV would break that approach. | |
810bc075 AL |
1652 | */ |
1653 | std | |
1654 | movq $0, 5*8(%rsp) /* clear "NMI executing" */ | |
0b22930e AL |
1655 | |
1656 | /* | |
929bacec AL |
1657 | * iretq reads the "iret" frame and exits the NMI stack in a |
1658 | * single instruction. We are returning to kernel mode, so this | |
1659 | * cannot result in a fault. Similarly, we don't need to worry | |
1660 | * about espfix64 on the way back to kernel mode. | |
0b22930e | 1661 | */ |
929bacec | 1662 | iretq |
ddeb8f21 AH |
1663 | END(nmi) |
1664 | ||
1665 | ENTRY(ignore_sysret) | |
8c1f7558 | 1666 | UNWIND_HINT_EMPTY |
4d732138 | 1667 | mov $-ENOSYS, %eax |
ddeb8f21 | 1668 | sysret |
ddeb8f21 | 1669 | END(ignore_sysret) |
2deb4be2 AL |
1670 | |
1671 | ENTRY(rewind_stack_do_exit) | |
8c1f7558 | 1672 | UNWIND_HINT_FUNC |
2deb4be2 AL |
1673 | /* Prevent any naive code from trying to unwind to our caller. */ |
1674 | xorl %ebp, %ebp | |
1675 | ||
1676 | movq PER_CPU_VAR(cpu_current_top_of_stack), %rax | |
8c1f7558 JP |
1677 | leaq -PTREGS_SIZE(%rax), %rsp |
1678 | UNWIND_HINT_FUNC sp_offset=PTREGS_SIZE | |
2deb4be2 AL |
1679 | |
1680 | call do_exit | |
2deb4be2 | 1681 | END(rewind_stack_do_exit) |