Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 | 2 | /* |
a49976d1 | 3 | * Copyright (C) 1991,1992 Linus Torvalds |
1da177e4 | 4 | * |
a49976d1 | 5 | * entry_32.S contains the system-call and low-level fault and trap handling routines. |
1da177e4 | 6 | * |
39e8701f | 7 | * Stack layout while running C code: |
a49976d1 IM |
8 | * ptrace needs to have all registers on the stack. |
9 | * If the order here is changed, it needs to be | |
10 | * updated in fork.c:copy_process(), signal.c:do_signal(), | |
1da177e4 LT |
11 | * ptrace.c and ptrace.h |
12 | * | |
13 | * 0(%esp) - %ebx | |
14 | * 4(%esp) - %ecx | |
15 | * 8(%esp) - %edx | |
9b47feb7 | 16 | * C(%esp) - %esi |
1da177e4 LT |
17 | * 10(%esp) - %edi |
18 | * 14(%esp) - %ebp | |
19 | * 18(%esp) - %eax | |
20 | * 1C(%esp) - %ds | |
21 | * 20(%esp) - %es | |
464d1a78 | 22 | * 24(%esp) - %fs |
ccbeed3a TH |
23 | * 28(%esp) - %gs saved iff !CONFIG_X86_32_LAZY_GS |
24 | * 2C(%esp) - orig_eax | |
25 | * 30(%esp) - %eip | |
26 | * 34(%esp) - %cs | |
27 | * 38(%esp) - %eflags | |
28 | * 3C(%esp) - %oldesp | |
29 | * 40(%esp) - %oldss | |
1da177e4 LT |
30 | */ |
31 | ||
1da177e4 | 32 | #include <linux/linkage.h> |
d7e7528b | 33 | #include <linux/err.h> |
1da177e4 | 34 | #include <asm/thread_info.h> |
55f327fa | 35 | #include <asm/irqflags.h> |
1da177e4 LT |
36 | #include <asm/errno.h> |
37 | #include <asm/segment.h> | |
38 | #include <asm/smp.h> | |
be44d2aa | 39 | #include <asm/percpu.h> |
ab68ed98 | 40 | #include <asm/processor-flags.h> |
9b7dc567 | 41 | #include <asm/irq_vectors.h> |
cd4d09ec | 42 | #include <asm/cpufeatures.h> |
b4ca46e4 | 43 | #include <asm/alternative-asm.h> |
6837a54d | 44 | #include <asm/asm.h> |
e59d1b0a | 45 | #include <asm/smap.h> |
4d516f41 | 46 | #include <asm/frame.h> |
2641f08b | 47 | #include <asm/nospec-branch.h> |
1da177e4 | 48 | |
afaef01c AP |
49 | #include "calling.h" |
50 | ||
ea714547 JO |
51 | .section .entry.text, "ax" |
52 | ||
139ec7c4 RR |
53 | /* |
54 | * We use macros for low-level operations which need to be overridden | |
55 | * for paravirtualization. The following will never clobber any registers: | |
56 | * INTERRUPT_RETURN (aka. "iret") | |
57 | * GET_CR0_INTO_EAX (aka. "movl %cr0, %eax") | |
d75cd22f | 58 | * ENABLE_INTERRUPTS_SYSEXIT (aka "sti; sysexit"). |
139ec7c4 RR |
59 | * |
60 | * For DISABLE_INTERRUPTS/ENABLE_INTERRUPTS (aka "cli"/"sti"), you must | |
61 | * specify what registers can be overwritten (CLBR_NONE, CLBR_EAX/EDX/ECX/ANY). | |
62 | * Allowing a register to be clobbered can shrink the paravirt replacement | |
63 | * enough to patch inline, increasing performance. | |
64 | */ | |
65 | ||
48593975 | 66 | #ifdef CONFIG_PREEMPTION |
a49976d1 | 67 | # define preempt_stop(clobbers) DISABLE_INTERRUPTS(clobbers); TRACE_IRQS_OFF |
1da177e4 | 68 | #else |
a49976d1 | 69 | # define preempt_stop(clobbers) |
1da177e4 LT |
70 | #endif |
71 | ||
55f327fa IM |
72 | .macro TRACE_IRQS_IRET |
73 | #ifdef CONFIG_TRACE_IRQFLAGS | |
a49976d1 IM |
74 | testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off? |
75 | jz 1f | |
55f327fa IM |
76 | TRACE_IRQS_ON |
77 | 1: | |
78 | #endif | |
79 | .endm | |
80 | ||
e464fb9f JR |
81 | #define PTI_SWITCH_MASK (1 << PAGE_SHIFT) |
82 | ||
ccbeed3a TH |
83 | /* |
84 | * User gs save/restore | |
85 | * | |
86 | * %gs is used for userland TLS and kernel only uses it for stack | |
87 | * canary which is required to be at %gs:20 by gcc. Read the comment | |
88 | * at the top of stackprotector.h for more info. | |
89 | * | |
90 | * Local labels 98 and 99 are used. | |
91 | */ | |
92 | #ifdef CONFIG_X86_32_LAZY_GS | |
93 | ||
94 | /* unfortunately push/pop can't be no-op */ | |
95 | .macro PUSH_GS | |
a49976d1 | 96 | pushl $0 |
ccbeed3a TH |
97 | .endm |
98 | .macro POP_GS pop=0 | |
a49976d1 | 99 | addl $(4 + \pop), %esp |
ccbeed3a TH |
100 | .endm |
101 | .macro POP_GS_EX | |
102 | .endm | |
103 | ||
104 | /* all the rest are no-op */ | |
105 | .macro PTGS_TO_GS | |
106 | .endm | |
107 | .macro PTGS_TO_GS_EX | |
108 | .endm | |
109 | .macro GS_TO_REG reg | |
110 | .endm | |
111 | .macro REG_TO_PTGS reg | |
112 | .endm | |
113 | .macro SET_KERNEL_GS reg | |
114 | .endm | |
115 | ||
116 | #else /* CONFIG_X86_32_LAZY_GS */ | |
117 | ||
118 | .macro PUSH_GS | |
a49976d1 | 119 | pushl %gs |
ccbeed3a TH |
120 | .endm |
121 | ||
122 | .macro POP_GS pop=0 | |
a49976d1 | 123 | 98: popl %gs |
ccbeed3a | 124 | .if \pop <> 0 |
9b47feb7 | 125 | add $\pop, %esp |
ccbeed3a TH |
126 | .endif |
127 | .endm | |
128 | .macro POP_GS_EX | |
129 | .pushsection .fixup, "ax" | |
a49976d1 IM |
130 | 99: movl $0, (%esp) |
131 | jmp 98b | |
ccbeed3a | 132 | .popsection |
a49976d1 | 133 | _ASM_EXTABLE(98b, 99b) |
ccbeed3a TH |
134 | .endm |
135 | ||
136 | .macro PTGS_TO_GS | |
a49976d1 | 137 | 98: mov PT_GS(%esp), %gs |
ccbeed3a TH |
138 | .endm |
139 | .macro PTGS_TO_GS_EX | |
140 | .pushsection .fixup, "ax" | |
a49976d1 IM |
141 | 99: movl $0, PT_GS(%esp) |
142 | jmp 98b | |
ccbeed3a | 143 | .popsection |
a49976d1 | 144 | _ASM_EXTABLE(98b, 99b) |
ccbeed3a TH |
145 | .endm |
146 | ||
147 | .macro GS_TO_REG reg | |
a49976d1 | 148 | movl %gs, \reg |
ccbeed3a TH |
149 | .endm |
150 | .macro REG_TO_PTGS reg | |
a49976d1 | 151 | movl \reg, PT_GS(%esp) |
ccbeed3a TH |
152 | .endm |
153 | .macro SET_KERNEL_GS reg | |
a49976d1 IM |
154 | movl $(__KERNEL_STACK_CANARY), \reg |
155 | movl \reg, %gs | |
ccbeed3a TH |
156 | .endm |
157 | ||
a49976d1 | 158 | #endif /* CONFIG_X86_32_LAZY_GS */ |
ccbeed3a | 159 | |
e464fb9f JR |
160 | /* Unconditionally switch to user cr3 */ |
161 | .macro SWITCH_TO_USER_CR3 scratch_reg:req | |
162 | ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI | |
163 | ||
164 | movl %cr3, \scratch_reg | |
165 | orl $PTI_SWITCH_MASK, \scratch_reg | |
166 | movl \scratch_reg, %cr3 | |
167 | .Lend_\@: | |
168 | .endm | |
169 | ||
97193702 JR |
170 | .macro BUG_IF_WRONG_CR3 no_user_check=0 |
171 | #ifdef CONFIG_DEBUG_ENTRY | |
172 | ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI | |
173 | .if \no_user_check == 0 | |
174 | /* coming from usermode? */ | |
81ff2c37 | 175 | testl $USER_SEGMENT_RPL_MASK, PT_CS(%esp) |
97193702 JR |
176 | jz .Lend_\@ |
177 | .endif | |
178 | /* On user-cr3? */ | |
179 | movl %cr3, %eax | |
180 | testl $PTI_SWITCH_MASK, %eax | |
181 | jnz .Lend_\@ | |
182 | /* From userspace with kernel cr3 - BUG */ | |
183 | ud2 | |
184 | .Lend_\@: | |
185 | #endif | |
186 | .endm | |
187 | ||
e464fb9f JR |
188 | /* |
189 | * Switch to kernel cr3 if not already loaded and return current cr3 in | |
190 | * \scratch_reg | |
191 | */ | |
192 | .macro SWITCH_TO_KERNEL_CR3 scratch_reg:req | |
193 | ALTERNATIVE "jmp .Lend_\@", "", X86_FEATURE_PTI | |
194 | movl %cr3, \scratch_reg | |
195 | /* Test if we are already on kernel CR3 */ | |
196 | testl $PTI_SWITCH_MASK, \scratch_reg | |
197 | jz .Lend_\@ | |
198 | andl $(~PTI_SWITCH_MASK), \scratch_reg | |
199 | movl \scratch_reg, %cr3 | |
200 | /* Return original CR3 in \scratch_reg */ | |
201 | orl $PTI_SWITCH_MASK, \scratch_reg | |
202 | .Lend_\@: | |
203 | .endm | |
204 | ||
3c88c692 PZ |
205 | #define CS_FROM_ENTRY_STACK (1 << 31) |
206 | #define CS_FROM_USER_CR3 (1 << 30) | |
207 | #define CS_FROM_KERNEL (1 << 29) | |
208 | ||
209 | .macro FIXUP_FRAME | |
210 | /* | |
211 | * The high bits of the CS dword (__csh) are used for CS_FROM_*. | |
212 | * Clear them in case hardware didn't do this for us. | |
4c4fd55d AL |
213 | * |
214 | * Be careful: we may have nonzero SS base due to ESPFIX. | |
3c88c692 | 215 | */ |
82cb8a0b | 216 | andl $0x0000ffff, 4*4(%esp) |
3c88c692 PZ |
217 | |
218 | #ifdef CONFIG_VM86 | |
82cb8a0b | 219 | testl $X86_EFLAGS_VM, 5*4(%esp) |
3c88c692 PZ |
220 | jnz .Lfrom_usermode_no_fixup_\@ |
221 | #endif | |
82cb8a0b | 222 | testl $USER_SEGMENT_RPL_MASK, 4*4(%esp) |
3c88c692 PZ |
223 | jnz .Lfrom_usermode_no_fixup_\@ |
224 | ||
82cb8a0b | 225 | orl $CS_FROM_KERNEL, 4*4(%esp) |
3c88c692 PZ |
226 | |
227 | /* | |
228 | * When we're here from kernel mode; the (exception) stack looks like: | |
229 | * | |
82cb8a0b AL |
230 | * 6*4(%esp) - <previous context> |
231 | * 5*4(%esp) - flags | |
232 | * 4*4(%esp) - cs | |
233 | * 3*4(%esp) - ip | |
234 | * 2*4(%esp) - orig_eax | |
235 | * 1*4(%esp) - gs / function | |
236 | * 0*4(%esp) - fs | |
3c88c692 PZ |
237 | * |
238 | * Lets build a 5 entry IRET frame after that, such that struct pt_regs | |
239 | * is complete and in particular regs->sp is correct. This gives us | |
82cb8a0b | 240 | * the original 6 enties as gap: |
3c88c692 | 241 | * |
82cb8a0b AL |
242 | * 14*4(%esp) - <previous context> |
243 | * 13*4(%esp) - gap / flags | |
244 | * 12*4(%esp) - gap / cs | |
245 | * 11*4(%esp) - gap / ip | |
246 | * 10*4(%esp) - gap / orig_eax | |
247 | * 9*4(%esp) - gap / gs / function | |
248 | * 8*4(%esp) - gap / fs | |
249 | * 7*4(%esp) - ss | |
250 | * 6*4(%esp) - sp | |
251 | * 5*4(%esp) - flags | |
252 | * 4*4(%esp) - cs | |
253 | * 3*4(%esp) - ip | |
254 | * 2*4(%esp) - orig_eax | |
255 | * 1*4(%esp) - gs / function | |
256 | * 0*4(%esp) - fs | |
3c88c692 PZ |
257 | */ |
258 | ||
259 | pushl %ss # ss | |
260 | pushl %esp # sp (points at ss) | |
82cb8a0b AL |
261 | addl $7*4, (%esp) # point sp back at the previous context |
262 | pushl 7*4(%esp) # flags | |
263 | pushl 7*4(%esp) # cs | |
264 | pushl 7*4(%esp) # ip | |
265 | pushl 7*4(%esp) # orig_eax | |
266 | pushl 7*4(%esp) # gs / function | |
267 | pushl 7*4(%esp) # fs | |
3c88c692 PZ |
268 | .Lfrom_usermode_no_fixup_\@: |
269 | .endm | |
270 | ||
271 | .macro IRET_FRAME | |
4c4fd55d AL |
272 | /* |
273 | * We're called with %ds, %es, %fs, and %gs from the interrupted | |
274 | * frame, so we shouldn't use them. Also, we may be in ESPFIX | |
275 | * mode and therefore have a nonzero SS base and an offset ESP, | |
276 | * so any attempt to access the stack needs to use SS. (except for | |
277 | * accesses through %esp, which automatically use SS.) | |
278 | */ | |
3c88c692 PZ |
279 | testl $CS_FROM_KERNEL, 1*4(%esp) |
280 | jz .Lfinished_frame_\@ | |
281 | ||
282 | /* | |
283 | * Reconstruct the 3 entry IRET frame right after the (modified) | |
284 | * regs->sp without lowering %esp in between, such that an NMI in the | |
285 | * middle doesn't scribble our stack. | |
286 | */ | |
287 | pushl %eax | |
288 | pushl %ecx | |
289 | movl 5*4(%esp), %eax # (modified) regs->sp | |
290 | ||
291 | movl 4*4(%esp), %ecx # flags | |
4c4fd55d | 292 | movl %ecx, %ss:-1*4(%eax) |
3c88c692 PZ |
293 | |
294 | movl 3*4(%esp), %ecx # cs | |
295 | andl $0x0000ffff, %ecx | |
4c4fd55d | 296 | movl %ecx, %ss:-2*4(%eax) |
3c88c692 PZ |
297 | |
298 | movl 2*4(%esp), %ecx # ip | |
4c4fd55d | 299 | movl %ecx, %ss:-3*4(%eax) |
3c88c692 PZ |
300 | |
301 | movl 1*4(%esp), %ecx # eax | |
4c4fd55d | 302 | movl %ecx, %ss:-4*4(%eax) |
3c88c692 PZ |
303 | |
304 | popl %ecx | |
4c4fd55d | 305 | lea -4*4(%eax), %esp |
3c88c692 PZ |
306 | popl %eax |
307 | .Lfinished_frame_\@: | |
308 | .endm | |
309 | ||
e67f1c11 | 310 | .macro SAVE_ALL pt_regs_ax=%eax switch_stacks=0 skip_gs=0 |
f0d96110 | 311 | cld |
e67f1c11 | 312 | .if \skip_gs == 0 |
ccbeed3a | 313 | PUSH_GS |
e67f1c11 | 314 | .endif |
a49976d1 | 315 | pushl %fs |
82cb8a0b | 316 | FIXUP_FRAME |
a49976d1 IM |
317 | pushl %es |
318 | pushl %ds | |
150ac78d | 319 | pushl \pt_regs_ax |
a49976d1 IM |
320 | pushl %ebp |
321 | pushl %edi | |
322 | pushl %esi | |
323 | pushl %edx | |
324 | pushl %ecx | |
325 | pushl %ebx | |
326 | movl $(__USER_DS), %edx | |
327 | movl %edx, %ds | |
328 | movl %edx, %es | |
329 | movl $(__KERNEL_PERCPU), %edx | |
330 | movl %edx, %fs | |
e67f1c11 | 331 | .if \skip_gs == 0 |
ccbeed3a | 332 | SET_KERNEL_GS %edx |
e67f1c11 | 333 | .endif |
45d7b255 JR |
334 | /* Switch to kernel stack if necessary */ |
335 | .if \switch_stacks > 0 | |
336 | SWITCH_TO_KERNEL_STACK | |
337 | .endif | |
f0d96110 | 338 | .endm |
1da177e4 | 339 | |
b65bef40 | 340 | .macro SAVE_ALL_NMI cr3_reg:req |
8b376fae | 341 | SAVE_ALL |
b65bef40 | 342 | |
97193702 JR |
343 | BUG_IF_WRONG_CR3 |
344 | ||
b65bef40 JR |
345 | /* |
346 | * Now switch the CR3 when PTI is enabled. | |
347 | * | |
348 | * We can enter with either user or kernel cr3, the code will | |
349 | * store the old cr3 in \cr3_reg and switches to the kernel cr3 | |
350 | * if necessary. | |
351 | */ | |
352 | SWITCH_TO_KERNEL_CR3 scratch_reg=\cr3_reg | |
353 | ||
354 | .Lend_\@: | |
8b376fae | 355 | .endm |
97193702 | 356 | |
f0d96110 | 357 | .macro RESTORE_INT_REGS |
a49976d1 IM |
358 | popl %ebx |
359 | popl %ecx | |
360 | popl %edx | |
361 | popl %esi | |
362 | popl %edi | |
363 | popl %ebp | |
364 | popl %eax | |
f0d96110 | 365 | .endm |
1da177e4 | 366 | |
ccbeed3a | 367 | .macro RESTORE_REGS pop=0 |
f0d96110 | 368 | RESTORE_INT_REGS |
a49976d1 IM |
369 | 1: popl %ds |
370 | 2: popl %es | |
371 | 3: popl %fs | |
ccbeed3a | 372 | POP_GS \pop |
40ad2199 | 373 | IRET_FRAME |
f0d96110 | 374 | .pushsection .fixup, "ax" |
a49976d1 IM |
375 | 4: movl $0, (%esp) |
376 | jmp 1b | |
377 | 5: movl $0, (%esp) | |
378 | jmp 2b | |
379 | 6: movl $0, (%esp) | |
380 | jmp 3b | |
f95d47ca | 381 | .popsection |
a49976d1 IM |
382 | _ASM_EXTABLE(1b, 4b) |
383 | _ASM_EXTABLE(2b, 5b) | |
384 | _ASM_EXTABLE(3b, 6b) | |
ccbeed3a | 385 | POP_GS_EX |
f0d96110 | 386 | .endm |
1da177e4 | 387 | |
b65bef40 JR |
388 | .macro RESTORE_ALL_NMI cr3_reg:req pop=0 |
389 | /* | |
390 | * Now switch the CR3 when PTI is enabled. | |
391 | * | |
392 | * We enter with kernel cr3 and switch the cr3 to the value | |
393 | * stored on \cr3_reg, which is either a user or a kernel cr3. | |
394 | */ | |
395 | ALTERNATIVE "jmp .Lswitched_\@", "", X86_FEATURE_PTI | |
396 | ||
397 | testl $PTI_SWITCH_MASK, \cr3_reg | |
398 | jz .Lswitched_\@ | |
399 | ||
400 | /* User cr3 in \cr3_reg - write it to hardware cr3 */ | |
401 | movl \cr3_reg, %cr3 | |
402 | ||
403 | .Lswitched_\@: | |
404 | ||
97193702 JR |
405 | BUG_IF_WRONG_CR3 |
406 | ||
8b376fae JR |
407 | RESTORE_REGS pop=\pop |
408 | .endm | |
409 | ||
46eabca2 JR |
410 | .macro CHECK_AND_APPLY_ESPFIX |
411 | #ifdef CONFIG_X86_ESPFIX32 | |
412 | #define GDT_ESPFIX_SS PER_CPU_VAR(gdt_page) + (GDT_ENTRY_ESPFIX_SS * 8) | |
413 | ||
414 | ALTERNATIVE "jmp .Lend_\@", "", X86_BUG_ESPFIX | |
415 | ||
416 | movl PT_EFLAGS(%esp), %eax # mix EFLAGS, SS and CS | |
417 | /* | |
418 | * Warning: PT_OLDSS(%esp) contains the wrong/random values if we | |
419 | * are returning to the kernel. | |
420 | * See comments in process.c:copy_thread() for details. | |
421 | */ | |
422 | movb PT_OLDSS(%esp), %ah | |
423 | movb PT_CS(%esp), %al | |
424 | andl $(X86_EFLAGS_VM | (SEGMENT_TI_MASK << 8) | SEGMENT_RPL_MASK), %eax | |
425 | cmpl $((SEGMENT_LDT << 8) | USER_RPL), %eax | |
426 | jne .Lend_\@ # returning to user-space with LDT SS | |
427 | ||
428 | /* | |
429 | * Setup and switch to ESPFIX stack | |
430 | * | |
431 | * We're returning to userspace with a 16 bit stack. The CPU will not | |
432 | * restore the high word of ESP for us on executing iret... This is an | |
433 | * "official" bug of all the x86-compatible CPUs, which we can work | |
434 | * around to make dosemu and wine happy. We do this by preloading the | |
435 | * high word of ESP with the high word of the userspace ESP while | |
436 | * compensating for the offset by changing to the ESPFIX segment with | |
437 | * a base address that matches for the difference. | |
438 | */ | |
439 | mov %esp, %edx /* load kernel esp */ | |
440 | mov PT_OLDESP(%esp), %eax /* load userspace esp */ | |
441 | mov %dx, %ax /* eax: new kernel esp */ | |
442 | sub %eax, %edx /* offset (low word is 0) */ | |
443 | shr $16, %edx | |
444 | mov %dl, GDT_ESPFIX_SS + 4 /* bits 16..23 */ | |
445 | mov %dh, GDT_ESPFIX_SS + 7 /* bits 24..31 */ | |
446 | pushl $__ESPFIX_SS | |
447 | pushl %eax /* new kernel esp */ | |
448 | /* | |
449 | * Disable interrupts, but do not irqtrace this section: we | |
450 | * will soon execute iret and the tracer was already set to | |
451 | * the irqstate after the IRET: | |
452 | */ | |
453 | DISABLE_INTERRUPTS(CLBR_ANY) | |
454 | lss (%esp), %esp /* switch to espfix segment */ | |
455 | .Lend_\@: | |
456 | #endif /* CONFIG_X86_ESPFIX32 */ | |
457 | .endm | |
45d7b255 | 458 | |
45d7b255 JR |
459 | /* |
460 | * Called with pt_regs fully populated and kernel segments loaded, | |
461 | * so we can access PER_CPU and use the integer registers. | |
462 | * | |
463 | * We need to be very careful here with the %esp switch, because an NMI | |
464 | * can happen everywhere. If the NMI handler finds itself on the | |
465 | * entry-stack, it will overwrite the task-stack and everything we | |
466 | * copied there. So allocate the stack-frame on the task-stack and | |
467 | * switch to it before we do any copying. | |
468 | */ | |
b92a165d | 469 | |
45d7b255 JR |
470 | .macro SWITCH_TO_KERNEL_STACK |
471 | ||
472 | ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV | |
473 | ||
97193702 JR |
474 | BUG_IF_WRONG_CR3 |
475 | ||
e464fb9f JR |
476 | SWITCH_TO_KERNEL_CR3 scratch_reg=%eax |
477 | ||
478 | /* | |
479 | * %eax now contains the entry cr3 and we carry it forward in | |
480 | * that register for the time this macro runs | |
481 | */ | |
482 | ||
45d7b255 JR |
483 | /* Are we on the entry stack? Bail out if not! */ |
484 | movl PER_CPU_VAR(cpu_entry_area), %ecx | |
485 | addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx | |
486 | subl %esp, %ecx /* ecx = (end of entry_stack) - esp */ | |
487 | cmpl $SIZEOF_entry_stack, %ecx | |
488 | jae .Lend_\@ | |
489 | ||
490 | /* Load stack pointer into %esi and %edi */ | |
491 | movl %esp, %esi | |
492 | movl %esi, %edi | |
493 | ||
494 | /* Move %edi to the top of the entry stack */ | |
495 | andl $(MASK_entry_stack), %edi | |
496 | addl $(SIZEOF_entry_stack), %edi | |
497 | ||
498 | /* Load top of task-stack into %edi */ | |
499 | movl TSS_entry2task_stack(%edi), %edi | |
500 | ||
b92a165d | 501 | /* Special case - entry from kernel mode via entry stack */ |
d5e84c21 JR |
502 | #ifdef CONFIG_VM86 |
503 | movl PT_EFLAGS(%esp), %ecx # mix EFLAGS and CS | |
504 | movb PT_CS(%esp), %cl | |
505 | andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %ecx | |
506 | #else | |
507 | movl PT_CS(%esp), %ecx | |
508 | andl $SEGMENT_RPL_MASK, %ecx | |
509 | #endif | |
510 | cmpl $USER_RPL, %ecx | |
511 | jb .Lentry_from_kernel_\@ | |
b92a165d | 512 | |
45d7b255 JR |
513 | /* Bytes to copy */ |
514 | movl $PTREGS_SIZE, %ecx | |
515 | ||
516 | #ifdef CONFIG_VM86 | |
517 | testl $X86_EFLAGS_VM, PT_EFLAGS(%esi) | |
518 | jz .Lcopy_pt_regs_\@ | |
519 | ||
520 | /* | |
521 | * Stack-frame contains 4 additional segment registers when | |
522 | * coming from VM86 mode | |
523 | */ | |
524 | addl $(4 * 4), %ecx | |
525 | ||
45d7b255 | 526 | #endif |
b92a165d | 527 | .Lcopy_pt_regs_\@: |
45d7b255 JR |
528 | |
529 | /* Allocate frame on task-stack */ | |
530 | subl %ecx, %edi | |
531 | ||
532 | /* Switch to task-stack */ | |
533 | movl %edi, %esp | |
534 | ||
535 | /* | |
536 | * We are now on the task-stack and can safely copy over the | |
537 | * stack-frame | |
538 | */ | |
539 | shrl $2, %ecx | |
540 | cld | |
541 | rep movsl | |
542 | ||
b92a165d JR |
543 | jmp .Lend_\@ |
544 | ||
545 | .Lentry_from_kernel_\@: | |
546 | ||
547 | /* | |
548 | * This handles the case when we enter the kernel from | |
549 | * kernel-mode and %esp points to the entry-stack. When this | |
550 | * happens we need to switch to the task-stack to run C code, | |
551 | * but switch back to the entry-stack again when we approach | |
552 | * iret and return to the interrupted code-path. This usually | |
553 | * happens when we hit an exception while restoring user-space | |
e464fb9f JR |
554 | * segment registers on the way back to user-space or when the |
555 | * sysenter handler runs with eflags.tf set. | |
b92a165d JR |
556 | * |
557 | * When we switch to the task-stack here, we can't trust the | |
558 | * contents of the entry-stack anymore, as the exception handler | |
559 | * might be scheduled out or moved to another CPU. Therefore we | |
560 | * copy the complete entry-stack to the task-stack and set a | |
561 | * marker in the iret-frame (bit 31 of the CS dword) to detect | |
562 | * what we've done on the iret path. | |
563 | * | |
564 | * On the iret path we copy everything back and switch to the | |
565 | * entry-stack, so that the interrupted kernel code-path | |
566 | * continues on the same stack it was interrupted with. | |
567 | * | |
568 | * Be aware that an NMI can happen anytime in this code. | |
569 | * | |
570 | * %esi: Entry-Stack pointer (same as %esp) | |
571 | * %edi: Top of the task stack | |
e464fb9f | 572 | * %eax: CR3 on kernel entry |
b92a165d JR |
573 | */ |
574 | ||
575 | /* Calculate number of bytes on the entry stack in %ecx */ | |
576 | movl %esi, %ecx | |
577 | ||
578 | /* %ecx to the top of entry-stack */ | |
579 | andl $(MASK_entry_stack), %ecx | |
580 | addl $(SIZEOF_entry_stack), %ecx | |
581 | ||
582 | /* Number of bytes on the entry stack to %ecx */ | |
583 | sub %esi, %ecx | |
584 | ||
585 | /* Mark stackframe as coming from entry stack */ | |
586 | orl $CS_FROM_ENTRY_STACK, PT_CS(%esp) | |
587 | ||
e464fb9f JR |
588 | /* |
589 | * Test the cr3 used to enter the kernel and add a marker | |
590 | * so that we can switch back to it before iret. | |
591 | */ | |
592 | testl $PTI_SWITCH_MASK, %eax | |
593 | jz .Lcopy_pt_regs_\@ | |
594 | orl $CS_FROM_USER_CR3, PT_CS(%esp) | |
595 | ||
b92a165d JR |
596 | /* |
597 | * %esi and %edi are unchanged, %ecx contains the number of | |
598 | * bytes to copy. The code at .Lcopy_pt_regs_\@ will allocate | |
599 | * the stack-frame on task-stack and copy everything over | |
600 | */ | |
601 | jmp .Lcopy_pt_regs_\@ | |
602 | ||
45d7b255 JR |
603 | .Lend_\@: |
604 | .endm | |
605 | ||
e5862d05 JR |
606 | /* |
607 | * Switch back from the kernel stack to the entry stack. | |
608 | * | |
609 | * The %esp register must point to pt_regs on the task stack. It will | |
610 | * first calculate the size of the stack-frame to copy, depending on | |
611 | * whether we return to VM86 mode or not. With that it uses 'rep movsl' | |
612 | * to copy the contents of the stack over to the entry stack. | |
613 | * | |
614 | * We must be very careful here, as we can't trust the contents of the | |
615 | * task-stack once we switched to the entry-stack. When an NMI happens | |
616 | * while on the entry-stack, the NMI handler will switch back to the top | |
617 | * of the task stack, overwriting our stack-frame we are about to copy. | |
618 | * Therefore we switch the stack only after everything is copied over. | |
619 | */ | |
620 | .macro SWITCH_TO_ENTRY_STACK | |
621 | ||
622 | ALTERNATIVE "", "jmp .Lend_\@", X86_FEATURE_XENPV | |
623 | ||
624 | /* Bytes to copy */ | |
625 | movl $PTREGS_SIZE, %ecx | |
626 | ||
627 | #ifdef CONFIG_VM86 | |
628 | testl $(X86_EFLAGS_VM), PT_EFLAGS(%esp) | |
629 | jz .Lcopy_pt_regs_\@ | |
630 | ||
631 | /* Additional 4 registers to copy when returning to VM86 mode */ | |
632 | addl $(4 * 4), %ecx | |
633 | ||
634 | .Lcopy_pt_regs_\@: | |
635 | #endif | |
636 | ||
637 | /* Initialize source and destination for movsl */ | |
638 | movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi | |
639 | subl %ecx, %edi | |
640 | movl %esp, %esi | |
641 | ||
642 | /* Save future stack pointer in %ebx */ | |
643 | movl %edi, %ebx | |
644 | ||
645 | /* Copy over the stack-frame */ | |
646 | shrl $2, %ecx | |
647 | cld | |
648 | rep movsl | |
649 | ||
650 | /* | |
651 | * Switch to entry-stack - needs to happen after everything is | |
652 | * copied because the NMI handler will overwrite the task-stack | |
653 | * when on entry-stack | |
654 | */ | |
655 | movl %ebx, %esp | |
656 | ||
657 | .Lend_\@: | |
658 | .endm | |
659 | ||
b92a165d JR |
660 | /* |
661 | * This macro handles the case when we return to kernel-mode on the iret | |
e464fb9f | 662 | * path and have to switch back to the entry stack and/or user-cr3 |
b92a165d JR |
663 | * |
664 | * See the comments below the .Lentry_from_kernel_\@ label in the | |
665 | * SWITCH_TO_KERNEL_STACK macro for more details. | |
666 | */ | |
667 | .macro PARANOID_EXIT_TO_KERNEL_MODE | |
668 | ||
669 | /* | |
670 | * Test if we entered the kernel with the entry-stack. Most | |
671 | * likely we did not, because this code only runs on the | |
672 | * return-to-kernel path. | |
673 | */ | |
674 | testl $CS_FROM_ENTRY_STACK, PT_CS(%esp) | |
675 | jz .Lend_\@ | |
676 | ||
677 | /* Unlikely slow-path */ | |
678 | ||
679 | /* Clear marker from stack-frame */ | |
680 | andl $(~CS_FROM_ENTRY_STACK), PT_CS(%esp) | |
681 | ||
682 | /* Copy the remaining task-stack contents to entry-stack */ | |
683 | movl %esp, %esi | |
684 | movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %edi | |
685 | ||
686 | /* Bytes on the task-stack to ecx */ | |
687 | movl PER_CPU_VAR(cpu_tss_rw + TSS_sp1), %ecx | |
688 | subl %esi, %ecx | |
689 | ||
690 | /* Allocate stack-frame on entry-stack */ | |
691 | subl %ecx, %edi | |
692 | ||
693 | /* | |
694 | * Save future stack-pointer, we must not switch until the | |
695 | * copy is done, otherwise the NMI handler could destroy the | |
696 | * contents of the task-stack we are about to copy. | |
697 | */ | |
698 | movl %edi, %ebx | |
699 | ||
700 | /* Do the copy */ | |
701 | shrl $2, %ecx | |
702 | cld | |
703 | rep movsl | |
704 | ||
705 | /* Safe to switch to entry-stack now */ | |
706 | movl %ebx, %esp | |
707 | ||
e464fb9f JR |
708 | /* |
709 | * We came from entry-stack and need to check if we also need to | |
710 | * switch back to user cr3. | |
711 | */ | |
712 | testl $CS_FROM_USER_CR3, PT_CS(%esp) | |
713 | jz .Lend_\@ | |
714 | ||
715 | /* Clear marker from stack-frame */ | |
716 | andl $(~CS_FROM_USER_CR3), PT_CS(%esp) | |
717 | ||
718 | SWITCH_TO_USER_CR3 scratch_reg=%eax | |
719 | ||
b92a165d JR |
720 | .Lend_\@: |
721 | .endm | |
0100301b BG |
722 | /* |
723 | * %eax: prev task | |
724 | * %edx: next task | |
725 | */ | |
726 | ENTRY(__switch_to_asm) | |
727 | /* | |
728 | * Save callee-saved registers | |
729 | * This must match the order in struct inactive_task_frame | |
730 | */ | |
731 | pushl %ebp | |
732 | pushl %ebx | |
733 | pushl %edi | |
734 | pushl %esi | |
6690e86b | 735 | pushfl |
0100301b BG |
736 | |
737 | /* switch stack */ | |
738 | movl %esp, TASK_threadsp(%eax) | |
739 | movl TASK_threadsp(%edx), %esp | |
740 | ||
050e9baa | 741 | #ifdef CONFIG_STACKPROTECTOR |
0100301b BG |
742 | movl TASK_stack_canary(%edx), %ebx |
743 | movl %ebx, PER_CPU_VAR(stack_canary)+stack_canary_offset | |
744 | #endif | |
745 | ||
c995efd5 DW |
746 | #ifdef CONFIG_RETPOLINE |
747 | /* | |
748 | * When switching from a shallower to a deeper call stack | |
749 | * the RSB may either underflow or use entries populated | |
750 | * with userspace addresses. On CPUs where those concerns | |
751 | * exist, overwrite the RSB with entries which capture | |
752 | * speculative execution to prevent attack. | |
753 | */ | |
d1c99108 | 754 | FILL_RETURN_BUFFER %ebx, RSB_CLEAR_LOOPS, X86_FEATURE_RSB_CTXSW |
c995efd5 DW |
755 | #endif |
756 | ||
0100301b | 757 | /* restore callee-saved registers */ |
6690e86b | 758 | popfl |
0100301b BG |
759 | popl %esi |
760 | popl %edi | |
761 | popl %ebx | |
762 | popl %ebp | |
763 | ||
764 | jmp __switch_to | |
765 | END(__switch_to_asm) | |
766 | ||
ebd57499 JP |
767 | /* |
768 | * The unwinder expects the last frame on the stack to always be at the same | |
769 | * offset from the end of the page, which allows it to validate the stack. | |
770 | * Calling schedule_tail() directly would break that convention because its an | |
771 | * asmlinkage function so its argument has to be pushed on the stack. This | |
772 | * wrapper creates a proper "end of stack" frame header before the call. | |
773 | */ | |
774 | ENTRY(schedule_tail_wrapper) | |
775 | FRAME_BEGIN | |
776 | ||
777 | pushl %eax | |
778 | call schedule_tail | |
779 | popl %eax | |
780 | ||
781 | FRAME_END | |
782 | ret | |
783 | ENDPROC(schedule_tail_wrapper) | |
0100301b BG |
784 | /* |
785 | * A newly forked process directly context switches into this address. | |
786 | * | |
787 | * eax: prev task we switched from | |
616d2483 BG |
788 | * ebx: kernel thread func (NULL for user thread) |
789 | * edi: kernel thread arg | |
0100301b | 790 | */ |
1da177e4 | 791 | ENTRY(ret_from_fork) |
ebd57499 | 792 | call schedule_tail_wrapper |
39e8701f | 793 | |
616d2483 BG |
794 | testl %ebx, %ebx |
795 | jnz 1f /* kernel threads are uncommon */ | |
796 | ||
797 | 2: | |
39e8701f | 798 | /* When we fork, we trace the syscall return in the child, too. */ |
ebd57499 | 799 | movl %esp, %eax |
39e8701f | 800 | call syscall_return_slowpath |
afaef01c | 801 | STACKLEAK_ERASE |
39e8701f | 802 | jmp restore_all |
39e8701f | 803 | |
616d2483 BG |
804 | /* kernel thread */ |
805 | 1: movl %edi, %eax | |
2641f08b | 806 | CALL_NOSPEC %ebx |
39e8701f | 807 | /* |
616d2483 BG |
808 | * A kernel thread is allowed to return here after successfully |
809 | * calling do_execve(). Exit to userspace to complete the execve() | |
810 | * syscall. | |
39e8701f | 811 | */ |
616d2483 BG |
812 | movl $0, PT_EAX(%esp) |
813 | jmp 2b | |
814 | END(ret_from_fork) | |
6783eaa2 | 815 | |
1da177e4 LT |
816 | /* |
817 | * Return to user mode is not as complex as all this looks, | |
818 | * but we want the default path for a system call return to | |
819 | * go as quickly as possible which is why some of this is | |
820 | * less clear than it otherwise should be. | |
821 | */ | |
822 | ||
823 | # userspace resumption stub bypassing syscall exit tracing | |
824 | ALIGN | |
825 | ret_from_exception: | |
139ec7c4 | 826 | preempt_stop(CLBR_ANY) |
1da177e4 | 827 | ret_from_intr: |
29a2e283 | 828 | #ifdef CONFIG_VM86 |
a49976d1 IM |
829 | movl PT_EFLAGS(%esp), %eax # mix EFLAGS and CS |
830 | movb PT_CS(%esp), %al | |
831 | andl $(X86_EFLAGS_VM | SEGMENT_RPL_MASK), %eax | |
29a2e283 DA |
832 | #else |
833 | /* | |
6783eaa2 | 834 | * We can be coming here from child spawned by kernel_thread(). |
29a2e283 | 835 | */ |
a49976d1 IM |
836 | movl PT_CS(%esp), %eax |
837 | andl $SEGMENT_RPL_MASK, %eax | |
29a2e283 | 838 | #endif |
a49976d1 | 839 | cmpl $USER_RPL, %eax |
5e1246ff | 840 | jb restore_all_kernel # not returning to v8086 or userspace |
f95d47ca | 841 | |
1da177e4 | 842 | ENTRY(resume_userspace) |
5d73fc70 | 843 | DISABLE_INTERRUPTS(CLBR_ANY) |
e32e58a9 | 844 | TRACE_IRQS_OFF |
5d73fc70 AL |
845 | movl %esp, %eax |
846 | call prepare_exit_to_usermode | |
a49976d1 | 847 | jmp restore_all |
47a55cd7 | 848 | END(ret_from_exception) |
1da177e4 | 849 | |
f2b37575 AL |
850 | GLOBAL(__begin_SYSENTER_singlestep_region) |
851 | /* | |
852 | * All code from here through __end_SYSENTER_singlestep_region is subject | |
853 | * to being single-stepped if a user program sets TF and executes SYSENTER. | |
854 | * There is absolutely nothing that we can do to prevent this from happening | |
855 | * (thanks Intel!). To keep our handling of this situation as simple as | |
856 | * possible, we handle TF just like AC and NT, except that our #DB handler | |
857 | * will ignore all of the single-step traps generated in this range. | |
858 | */ | |
859 | ||
28c11b0f | 860 | #ifdef CONFIG_XEN_PV |
f2b37575 AL |
861 | /* |
862 | * Xen doesn't set %esp to be precisely what the normal SYSENTER | |
863 | * entry point expects, so fix it up before using the normal path. | |
864 | */ | |
865 | ENTRY(xen_sysenter_target) | |
866 | addl $5*4, %esp /* remove xen-provided frame */ | |
1b00255f | 867 | jmp .Lsysenter_past_esp |
f2b37575 AL |
868 | #endif |
869 | ||
fda57b22 AL |
870 | /* |
871 | * 32-bit SYSENTER entry. | |
872 | * | |
873 | * 32-bit system calls through the vDSO's __kernel_vsyscall enter here | |
874 | * if X86_FEATURE_SEP is available. This is the preferred system call | |
875 | * entry on 32-bit systems. | |
876 | * | |
877 | * The SYSENTER instruction, in principle, should *only* occur in the | |
878 | * vDSO. In practice, a small number of Android devices were shipped | |
879 | * with a copy of Bionic that inlined a SYSENTER instruction. This | |
880 | * never happened in any of Google's Bionic versions -- it only happened | |
881 | * in a narrow range of Intel-provided versions. | |
882 | * | |
883 | * SYSENTER loads SS, ESP, CS, and EIP from previously programmed MSRs. | |
884 | * IF and VM in RFLAGS are cleared (IOW: interrupts are off). | |
885 | * SYSENTER does not save anything on the stack, | |
886 | * and does not save old EIP (!!!), ESP, or EFLAGS. | |
887 | * | |
888 | * To avoid losing track of EFLAGS.VM (and thus potentially corrupting | |
889 | * user and/or vm86 state), we explicitly disable the SYSENTER | |
890 | * instruction in vm86 mode by reprogramming the MSRs. | |
891 | * | |
892 | * Arguments: | |
893 | * eax system call number | |
894 | * ebx arg1 | |
895 | * ecx arg2 | |
896 | * edx arg3 | |
897 | * esi arg4 | |
898 | * edi arg5 | |
899 | * ebp user stack | |
900 | * 0(%ebp) arg6 | |
901 | */ | |
4c8cd0c5 | 902 | ENTRY(entry_SYSENTER_32) |
e464fb9f JR |
903 | /* |
904 | * On entry-stack with all userspace-regs live - save and | |
905 | * restore eflags and %eax to use it as scratch-reg for the cr3 | |
906 | * switch. | |
907 | */ | |
908 | pushfl | |
909 | pushl %eax | |
97193702 | 910 | BUG_IF_WRONG_CR3 no_user_check=1 |
e464fb9f JR |
911 | SWITCH_TO_KERNEL_CR3 scratch_reg=%eax |
912 | popl %eax | |
913 | popfl | |
914 | ||
915 | /* Stack empty again, switch to task stack */ | |
ae2e565b | 916 | movl TSS_entry2task_stack(%esp), %esp |
e464fb9f | 917 | |
1b00255f | 918 | .Lsysenter_past_esp: |
5f310f73 | 919 | pushl $__USER_DS /* pt_regs->ss */ |
30bfa7b3 | 920 | pushl %ebp /* pt_regs->sp (stashed in bp) */ |
5f310f73 AL |
921 | pushfl /* pt_regs->flags (except IF = 0) */ |
922 | orl $X86_EFLAGS_IF, (%esp) /* Fix IF */ | |
923 | pushl $__USER_CS /* pt_regs->cs */ | |
924 | pushl $0 /* pt_regs->ip = 0 (placeholder) */ | |
925 | pushl %eax /* pt_regs->orig_ax */ | |
45d7b255 | 926 | SAVE_ALL pt_regs_ax=$-ENOSYS /* save rest, stack already switched */ |
5f310f73 | 927 | |
67f590e8 | 928 | /* |
f2b37575 AL |
929 | * SYSENTER doesn't filter flags, so we need to clear NT, AC |
930 | * and TF ourselves. To save a few cycles, we can check whether | |
67f590e8 AL |
931 | * either was set instead of doing an unconditional popfq. |
932 | * This needs to happen before enabling interrupts so that | |
933 | * we don't get preempted with NT set. | |
934 | * | |
f2b37575 AL |
935 | * If TF is set, we will single-step all the way to here -- do_debug |
936 | * will ignore all the traps. (Yes, this is slow, but so is | |
937 | * single-stepping in general. This allows us to avoid having | |
938 | * a more complicated code to handle the case where a user program | |
939 | * forces us to single-step through the SYSENTER entry code.) | |
940 | * | |
67f590e8 AL |
941 | * NB.: .Lsysenter_fix_flags is a label with the code under it moved |
942 | * out-of-line as an optimization: NT is unlikely to be set in the | |
943 | * majority of the cases and instead of polluting the I$ unnecessarily, | |
944 | * we're keeping that code behind a branch which will predict as | |
945 | * not-taken and therefore its instructions won't be fetched. | |
946 | */ | |
f2b37575 | 947 | testl $X86_EFLAGS_NT|X86_EFLAGS_AC|X86_EFLAGS_TF, PT_EFLAGS(%esp) |
67f590e8 AL |
948 | jnz .Lsysenter_fix_flags |
949 | .Lsysenter_flags_fixed: | |
950 | ||
55f327fa | 951 | /* |
5f310f73 AL |
952 | * User mode is traced as though IRQs are on, and SYSENTER |
953 | * turned them off. | |
e6e5494c | 954 | */ |
55f327fa | 955 | TRACE_IRQS_OFF |
5f310f73 AL |
956 | |
957 | movl %esp, %eax | |
958 | call do_fast_syscall_32 | |
91e2eea9 BO |
959 | /* XEN PV guests always use IRET path */ |
960 | ALTERNATIVE "testl %eax, %eax; jz .Lsyscall_32_done", \ | |
961 | "jmp .Lsyscall_32_done", X86_FEATURE_XENPV | |
5f310f73 | 962 | |
afaef01c AP |
963 | STACKLEAK_ERASE |
964 | ||
5f310f73 AL |
965 | /* Opportunistic SYSEXIT */ |
966 | TRACE_IRQS_ON /* User mode traces as IRQs on. */ | |
e5862d05 JR |
967 | |
968 | /* | |
969 | * Setup entry stack - we keep the pointer in %eax and do the | |
970 | * switch after almost all user-state is restored. | |
971 | */ | |
972 | ||
973 | /* Load entry stack pointer and allocate frame for eflags/eax */ | |
974 | movl PER_CPU_VAR(cpu_tss_rw + TSS_sp0), %eax | |
975 | subl $(2*4), %eax | |
976 | ||
977 | /* Copy eflags and eax to entry stack */ | |
978 | movl PT_EFLAGS(%esp), %edi | |
979 | movl PT_EAX(%esp), %esi | |
980 | movl %edi, (%eax) | |
981 | movl %esi, 4(%eax) | |
982 | ||
983 | /* Restore user registers and segments */ | |
5f310f73 AL |
984 | movl PT_EIP(%esp), %edx /* pt_regs->ip */ |
985 | movl PT_OLDESP(%esp), %ecx /* pt_regs->sp */ | |
3bd29515 AL |
986 | 1: mov PT_FS(%esp), %fs |
987 | PTGS_TO_GS | |
e5862d05 | 988 | |
5f310f73 AL |
989 | popl %ebx /* pt_regs->bx */ |
990 | addl $2*4, %esp /* skip pt_regs->cx and pt_regs->dx */ | |
991 | popl %esi /* pt_regs->si */ | |
992 | popl %edi /* pt_regs->di */ | |
993 | popl %ebp /* pt_regs->bp */ | |
e5862d05 JR |
994 | |
995 | /* Switch to entry stack */ | |
996 | movl %eax, %esp | |
5f310f73 | 997 | |
e464fb9f JR |
998 | /* Now ready to switch the cr3 */ |
999 | SWITCH_TO_USER_CR3 scratch_reg=%eax | |
1000 | ||
c2c9b52f AL |
1001 | /* |
1002 | * Restore all flags except IF. (We restore IF separately because | |
1003 | * STI gives a one-instruction window in which we won't be interrupted, | |
1004 | * whereas POPF does not.) | |
1005 | */ | |
236f0cd2 | 1006 | btrl $X86_EFLAGS_IF_BIT, (%esp) |
97193702 | 1007 | BUG_IF_WRONG_CR3 no_user_check=1 |
c2c9b52f | 1008 | popfl |
e5862d05 | 1009 | popl %eax |
c2c9b52f | 1010 | |
5f310f73 AL |
1011 | /* |
1012 | * Return back to the vDSO, which will pop ecx and edx. | |
1013 | * Don't bother with DS and ES (they already contain __USER_DS). | |
1014 | */ | |
88c15ec9 BO |
1015 | sti |
1016 | sysexit | |
af0575bb | 1017 | |
a49976d1 IM |
1018 | .pushsection .fixup, "ax" |
1019 | 2: movl $0, PT_FS(%esp) | |
1020 | jmp 1b | |
f95d47ca | 1021 | .popsection |
a49976d1 | 1022 | _ASM_EXTABLE(1b, 2b) |
ccbeed3a | 1023 | PTGS_TO_GS_EX |
67f590e8 AL |
1024 | |
1025 | .Lsysenter_fix_flags: | |
1026 | pushl $X86_EFLAGS_FIXED | |
1027 | popfl | |
1028 | jmp .Lsysenter_flags_fixed | |
f2b37575 | 1029 | GLOBAL(__end_SYSENTER_singlestep_region) |
4c8cd0c5 | 1030 | ENDPROC(entry_SYSENTER_32) |
1da177e4 | 1031 | |
fda57b22 AL |
1032 | /* |
1033 | * 32-bit legacy system call entry. | |
1034 | * | |
1035 | * 32-bit x86 Linux system calls traditionally used the INT $0x80 | |
1036 | * instruction. INT $0x80 lands here. | |
1037 | * | |
1038 | * This entry point can be used by any 32-bit perform system calls. | |
1039 | * Instances of INT $0x80 can be found inline in various programs and | |
1040 | * libraries. It is also used by the vDSO's __kernel_vsyscall | |
1041 | * fallback for hardware that doesn't support a faster entry method. | |
1042 | * Restarted 32-bit system calls also fall back to INT $0x80 | |
1043 | * regardless of what instruction was originally used to do the system | |
1044 | * call. (64-bit programs can use INT $0x80 as well, but they can | |
1045 | * only run on 64-bit kernels and therefore land in | |
1046 | * entry_INT80_compat.) | |
1047 | * | |
1048 | * This is considered a slow path. It is not used by most libc | |
1049 | * implementations on modern hardware except during process startup. | |
1050 | * | |
1051 | * Arguments: | |
1052 | * eax system call number | |
1053 | * ebx arg1 | |
1054 | * ecx arg2 | |
1055 | * edx arg3 | |
1056 | * esi arg4 | |
1057 | * edi arg5 | |
1058 | * ebp arg6 | |
1059 | */ | |
b2502b41 | 1060 | ENTRY(entry_INT80_32) |
e59d1b0a | 1061 | ASM_CLAC |
150ac78d | 1062 | pushl %eax /* pt_regs->orig_ax */ |
45d7b255 JR |
1063 | |
1064 | SAVE_ALL pt_regs_ax=$-ENOSYS switch_stacks=1 /* save rest */ | |
150ac78d AL |
1065 | |
1066 | /* | |
a798f091 AL |
1067 | * User mode is traced as though IRQs are on, and the interrupt gate |
1068 | * turned them off. | |
150ac78d | 1069 | */ |
a798f091 | 1070 | TRACE_IRQS_OFF |
150ac78d AL |
1071 | |
1072 | movl %esp, %eax | |
a798f091 | 1073 | call do_int80_syscall_32 |
5f310f73 | 1074 | .Lsyscall_32_done: |
1da177e4 | 1075 | |
afaef01c AP |
1076 | STACKLEAK_ERASE |
1077 | ||
1da177e4 | 1078 | restore_all: |
2e04bc76 | 1079 | TRACE_IRQS_IRET |
e5862d05 | 1080 | SWITCH_TO_ENTRY_STACK |
1b00255f | 1081 | .Lrestore_all_notrace: |
46eabca2 | 1082 | CHECK_AND_APPLY_ESPFIX |
1b00255f | 1083 | .Lrestore_nocheck: |
e464fb9f JR |
1084 | /* Switch back to user CR3 */ |
1085 | SWITCH_TO_USER_CR3 scratch_reg=%eax | |
1086 | ||
97193702 JR |
1087 | BUG_IF_WRONG_CR3 |
1088 | ||
e464fb9f JR |
1089 | /* Restore user state */ |
1090 | RESTORE_REGS pop=4 # skip orig_eax/error_code | |
1b00255f | 1091 | .Lirq_return: |
10bcc80e MD |
1092 | /* |
1093 | * ARCH_HAS_MEMBARRIER_SYNC_CORE rely on IRET core serialization | |
1094 | * when returning from IPI handler and when returning from | |
1095 | * scheduler to user-space. | |
1096 | */ | |
3701d863 | 1097 | INTERRUPT_RETURN |
1b00255f | 1098 | |
0d2eb73b | 1099 | restore_all_kernel: |
48593975 | 1100 | #ifdef CONFIG_PREEMPTION |
5e1246ff PZ |
1101 | DISABLE_INTERRUPTS(CLBR_ANY) |
1102 | cmpl $0, PER_CPU_VAR(__preempt_count) | |
1103 | jnz .Lno_preempt | |
1104 | testl $X86_EFLAGS_IF, PT_EFLAGS(%esp) # interrupts off (exception path) ? | |
1105 | jz .Lno_preempt | |
1106 | call preempt_schedule_irq | |
1107 | .Lno_preempt: | |
1108 | #endif | |
0d2eb73b | 1109 | TRACE_IRQS_IRET |
b92a165d | 1110 | PARANOID_EXIT_TO_KERNEL_MODE |
97193702 | 1111 | BUG_IF_WRONG_CR3 |
0d2eb73b JR |
1112 | RESTORE_REGS 4 |
1113 | jmp .Lirq_return | |
1114 | ||
a49976d1 IM |
1115 | .section .fixup, "ax" |
1116 | ENTRY(iret_exc ) | |
1117 | pushl $0 # no error code | |
1118 | pushl $do_iret_error | |
97193702 JR |
1119 | |
1120 | #ifdef CONFIG_DEBUG_ENTRY | |
1121 | /* | |
1122 | * The stack-frame here is the one that iret faulted on, so its a | |
1123 | * return-to-user frame. We are on kernel-cr3 because we come here from | |
1124 | * the fixup code. This confuses the CR3 checker, so switch to user-cr3 | |
1125 | * as the checker expects it. | |
1126 | */ | |
1127 | pushl %eax | |
1128 | SWITCH_TO_USER_CR3 scratch_reg=%eax | |
1129 | popl %eax | |
1130 | #endif | |
1131 | ||
7252c4c3 | 1132 | jmp common_exception |
1da177e4 | 1133 | .previous |
1b00255f | 1134 | _ASM_EXTABLE(.Lirq_return, iret_exc) |
b2502b41 | 1135 | ENDPROC(entry_INT80_32) |
1da177e4 | 1136 | |
f0d96110 | 1137 | .macro FIXUP_ESPFIX_STACK |
dc4c2a0a AH |
1138 | /* |
1139 | * Switch back for ESPFIX stack to the normal zerobased stack | |
1140 | * | |
1141 | * We can't call C functions using the ESPFIX stack. This code reads | |
1142 | * the high word of the segment base from the GDT and swiches to the | |
1143 | * normal stack and adjusts ESP with the matching offset. | |
1144 | */ | |
34273f41 | 1145 | #ifdef CONFIG_X86_ESPFIX32 |
dc4c2a0a | 1146 | /* fixup the stack */ |
a49976d1 IM |
1147 | mov GDT_ESPFIX_SS + 4, %al /* bits 16..23 */ |
1148 | mov GDT_ESPFIX_SS + 7, %ah /* bits 24..31 */ | |
9b47feb7 | 1149 | shl $16, %eax |
a49976d1 IM |
1150 | addl %esp, %eax /* the adjusted stack pointer */ |
1151 | pushl $__KERNEL_DS | |
1152 | pushl %eax | |
1153 | lss (%esp), %esp /* switch to the normal stack segment */ | |
34273f41 | 1154 | #endif |
f0d96110 TH |
1155 | .endm |
1156 | .macro UNWIND_ESPFIX_STACK | |
34273f41 | 1157 | #ifdef CONFIG_X86_ESPFIX32 |
a49976d1 | 1158 | movl %ss, %eax |
f0d96110 | 1159 | /* see if on espfix stack */ |
a49976d1 IM |
1160 | cmpw $__ESPFIX_SS, %ax |
1161 | jne 27f | |
1162 | movl $__KERNEL_DS, %eax | |
1163 | movl %eax, %ds | |
1164 | movl %eax, %es | |
f0d96110 TH |
1165 | /* switch to normal stack */ |
1166 | FIXUP_ESPFIX_STACK | |
1167 | 27: | |
34273f41 | 1168 | #endif |
f0d96110 | 1169 | .endm |
1da177e4 LT |
1170 | |
1171 | /* | |
3304c9c3 DV |
1172 | * Build the entry stubs with some assembler magic. |
1173 | * We pack 1 stub into every 8-byte block. | |
1da177e4 | 1174 | */ |
3304c9c3 | 1175 | .align 8 |
1da177e4 | 1176 | ENTRY(irq_entries_start) |
3304c9c3 DV |
1177 | vector=FIRST_EXTERNAL_VECTOR |
1178 | .rept (FIRST_SYSTEM_VECTOR - FIRST_EXTERNAL_VECTOR) | |
a49976d1 | 1179 | pushl $(~vector+0x80) /* Note: always in signed byte range */ |
3304c9c3 DV |
1180 | vector=vector+1 |
1181 | jmp common_interrupt | |
3304c9c3 DV |
1182 | .align 8 |
1183 | .endr | |
47a55cd7 JB |
1184 | END(irq_entries_start) |
1185 | ||
f8a8fe61 TG |
1186 | #ifdef CONFIG_X86_LOCAL_APIC |
1187 | .align 8 | |
1188 | ENTRY(spurious_entries_start) | |
1189 | vector=FIRST_SYSTEM_VECTOR | |
1190 | .rept (NR_VECTORS - FIRST_SYSTEM_VECTOR) | |
1191 | pushl $(~vector+0x80) /* Note: always in signed byte range */ | |
1192 | vector=vector+1 | |
1193 | jmp common_spurious | |
1194 | .align 8 | |
1195 | .endr | |
1196 | END(spurious_entries_start) | |
1197 | ||
1198 | common_spurious: | |
1199 | ASM_CLAC | |
1200 | addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */ | |
1201 | SAVE_ALL switch_stacks=1 | |
1202 | ENCODE_FRAME_POINTER | |
1203 | TRACE_IRQS_OFF | |
1204 | movl %esp, %eax | |
1205 | call smp_spurious_interrupt | |
1206 | jmp ret_from_intr | |
1cbec37b | 1207 | ENDPROC(common_spurious) |
f8a8fe61 TG |
1208 | #endif |
1209 | ||
55f327fa IM |
1210 | /* |
1211 | * the CPU automatically disables interrupts when executing an IRQ vector, | |
1212 | * so IRQ-flags tracing has to follow that: | |
1213 | */ | |
b7c6244f | 1214 | .p2align CONFIG_X86_L1_CACHE_SHIFT |
1da177e4 | 1215 | common_interrupt: |
e59d1b0a | 1216 | ASM_CLAC |
a49976d1 | 1217 | addl $-0x80, (%esp) /* Adjust vector into the [-256, -1] range */ |
45d7b255 JR |
1218 | |
1219 | SAVE_ALL switch_stacks=1 | |
946c1911 | 1220 | ENCODE_FRAME_POINTER |
55f327fa | 1221 | TRACE_IRQS_OFF |
a49976d1 IM |
1222 | movl %esp, %eax |
1223 | call do_IRQ | |
1224 | jmp ret_from_intr | |
47a55cd7 | 1225 | ENDPROC(common_interrupt) |
1da177e4 | 1226 | |
45d7b255 JR |
1227 | #define BUILD_INTERRUPT3(name, nr, fn) \ |
1228 | ENTRY(name) \ | |
1229 | ASM_CLAC; \ | |
1230 | pushl $~(nr); \ | |
1231 | SAVE_ALL switch_stacks=1; \ | |
1232 | ENCODE_FRAME_POINTER; \ | |
1233 | TRACE_IRQS_OFF \ | |
1234 | movl %esp, %eax; \ | |
1235 | call fn; \ | |
1236 | jmp ret_from_intr; \ | |
47a55cd7 | 1237 | ENDPROC(name) |
1da177e4 | 1238 | |
a49976d1 IM |
1239 | #define BUILD_INTERRUPT(name, nr) \ |
1240 | BUILD_INTERRUPT3(name, nr, smp_##name); \ | |
02cf94c3 | 1241 | |
1da177e4 | 1242 | /* The include is where all of the SMP etc. interrupts come from */ |
1164dd00 | 1243 | #include <asm/entry_arch.h> |
1da177e4 | 1244 | |
1da177e4 | 1245 | ENTRY(coprocessor_error) |
e59d1b0a | 1246 | ASM_CLAC |
a49976d1 IM |
1247 | pushl $0 |
1248 | pushl $do_coprocessor_error | |
7252c4c3 | 1249 | jmp common_exception |
47a55cd7 | 1250 | END(coprocessor_error) |
1da177e4 LT |
1251 | |
1252 | ENTRY(simd_coprocessor_error) | |
e59d1b0a | 1253 | ASM_CLAC |
a49976d1 | 1254 | pushl $0 |
40d2e763 BG |
1255 | #ifdef CONFIG_X86_INVD_BUG |
1256 | /* AMD 486 bug: invd from userspace calls exception 19 instead of #GP */ | |
a49976d1 IM |
1257 | ALTERNATIVE "pushl $do_general_protection", \ |
1258 | "pushl $do_simd_coprocessor_error", \ | |
8e65f6e0 | 1259 | X86_FEATURE_XMM |
40d2e763 | 1260 | #else |
a49976d1 | 1261 | pushl $do_simd_coprocessor_error |
40d2e763 | 1262 | #endif |
7252c4c3 | 1263 | jmp common_exception |
47a55cd7 | 1264 | END(simd_coprocessor_error) |
1da177e4 LT |
1265 | |
1266 | ENTRY(device_not_available) | |
e59d1b0a | 1267 | ASM_CLAC |
a49976d1 IM |
1268 | pushl $-1 # mark this as an int |
1269 | pushl $do_device_not_available | |
7252c4c3 | 1270 | jmp common_exception |
47a55cd7 | 1271 | END(device_not_available) |
1da177e4 | 1272 | |
d3561b7f RR |
1273 | #ifdef CONFIG_PARAVIRT |
1274 | ENTRY(native_iret) | |
3701d863 | 1275 | iret |
6837a54d | 1276 | _ASM_EXTABLE(native_iret, iret_exc) |
47a55cd7 | 1277 | END(native_iret) |
d3561b7f RR |
1278 | #endif |
1279 | ||
1da177e4 | 1280 | ENTRY(overflow) |
e59d1b0a | 1281 | ASM_CLAC |
a49976d1 IM |
1282 | pushl $0 |
1283 | pushl $do_overflow | |
7252c4c3 | 1284 | jmp common_exception |
47a55cd7 | 1285 | END(overflow) |
1da177e4 LT |
1286 | |
1287 | ENTRY(bounds) | |
e59d1b0a | 1288 | ASM_CLAC |
a49976d1 IM |
1289 | pushl $0 |
1290 | pushl $do_bounds | |
7252c4c3 | 1291 | jmp common_exception |
47a55cd7 | 1292 | END(bounds) |
1da177e4 LT |
1293 | |
1294 | ENTRY(invalid_op) | |
e59d1b0a | 1295 | ASM_CLAC |
a49976d1 IM |
1296 | pushl $0 |
1297 | pushl $do_invalid_op | |
7252c4c3 | 1298 | jmp common_exception |
47a55cd7 | 1299 | END(invalid_op) |
1da177e4 LT |
1300 | |
1301 | ENTRY(coprocessor_segment_overrun) | |
e59d1b0a | 1302 | ASM_CLAC |
a49976d1 IM |
1303 | pushl $0 |
1304 | pushl $do_coprocessor_segment_overrun | |
7252c4c3 | 1305 | jmp common_exception |
47a55cd7 | 1306 | END(coprocessor_segment_overrun) |
1da177e4 LT |
1307 | |
1308 | ENTRY(invalid_TSS) | |
e59d1b0a | 1309 | ASM_CLAC |
a49976d1 | 1310 | pushl $do_invalid_TSS |
7252c4c3 | 1311 | jmp common_exception |
47a55cd7 | 1312 | END(invalid_TSS) |
1da177e4 LT |
1313 | |
1314 | ENTRY(segment_not_present) | |
e59d1b0a | 1315 | ASM_CLAC |
a49976d1 | 1316 | pushl $do_segment_not_present |
7252c4c3 | 1317 | jmp common_exception |
47a55cd7 | 1318 | END(segment_not_present) |
1da177e4 LT |
1319 | |
1320 | ENTRY(stack_segment) | |
e59d1b0a | 1321 | ASM_CLAC |
a49976d1 | 1322 | pushl $do_stack_segment |
7252c4c3 | 1323 | jmp common_exception |
47a55cd7 | 1324 | END(stack_segment) |
1da177e4 | 1325 | |
1da177e4 | 1326 | ENTRY(alignment_check) |
e59d1b0a | 1327 | ASM_CLAC |
a49976d1 | 1328 | pushl $do_alignment_check |
7252c4c3 | 1329 | jmp common_exception |
47a55cd7 | 1330 | END(alignment_check) |
1da177e4 | 1331 | |
d28c4393 | 1332 | ENTRY(divide_error) |
e59d1b0a | 1333 | ASM_CLAC |
a49976d1 IM |
1334 | pushl $0 # no error code |
1335 | pushl $do_divide_error | |
7252c4c3 | 1336 | jmp common_exception |
47a55cd7 | 1337 | END(divide_error) |
1da177e4 LT |
1338 | |
1339 | #ifdef CONFIG_X86_MCE | |
1340 | ENTRY(machine_check) | |
e59d1b0a | 1341 | ASM_CLAC |
a49976d1 IM |
1342 | pushl $0 |
1343 | pushl machine_check_vector | |
7252c4c3 | 1344 | jmp common_exception |
47a55cd7 | 1345 | END(machine_check) |
1da177e4 LT |
1346 | #endif |
1347 | ||
1348 | ENTRY(spurious_interrupt_bug) | |
e59d1b0a | 1349 | ASM_CLAC |
a49976d1 IM |
1350 | pushl $0 |
1351 | pushl $do_spurious_interrupt_bug | |
7252c4c3 | 1352 | jmp common_exception |
47a55cd7 | 1353 | END(spurious_interrupt_bug) |
1da177e4 | 1354 | |
28c11b0f | 1355 | #ifdef CONFIG_XEN_PV |
5ead97c8 | 1356 | ENTRY(xen_hypervisor_callback) |
a49976d1 IM |
1357 | /* |
1358 | * Check to see if we got the event in the critical | |
1359 | * region in xen_iret_direct, after we've reenabled | |
1360 | * events and checked for pending events. This simulates | |
1361 | * iret instruction's behaviour where it delivers a | |
1362 | * pending interrupt when enabling interrupts: | |
1363 | */ | |
29b810f5 | 1364 | cmpl $xen_iret_start_crit, (%esp) |
a49976d1 | 1365 | jb 1f |
29b810f5 | 1366 | cmpl $xen_iret_end_crit, (%esp) |
a49976d1 | 1367 | jae 1f |
29b810f5 JB |
1368 | call xen_iret_crit_fixup |
1369 | 1: | |
1370 | pushl $-1 /* orig_ax = -1 => not a system call */ | |
1371 | SAVE_ALL | |
1372 | ENCODE_FRAME_POINTER | |
1373 | TRACE_IRQS_OFF | |
1374 | mov %esp, %eax | |
a49976d1 | 1375 | call xen_evtchn_do_upcall |
48593975 | 1376 | #ifndef CONFIG_PREEMPTION |
a49976d1 | 1377 | call xen_maybe_preempt_hcall |
fdfd811d | 1378 | #endif |
a49976d1 | 1379 | jmp ret_from_intr |
5ead97c8 JF |
1380 | ENDPROC(xen_hypervisor_callback) |
1381 | ||
a49976d1 IM |
1382 | /* |
1383 | * Hypervisor uses this for application faults while it executes. | |
1384 | * We get here for two reasons: | |
1385 | * 1. Fault while reloading DS, ES, FS or GS | |
1386 | * 2. Fault while executing IRET | |
1387 | * Category 1 we fix up by reattempting the load, and zeroing the segment | |
1388 | * register if the load fails. | |
1389 | * Category 2 we fix up by jumping to do_iret_error. We cannot use the | |
1390 | * normal Linux return path in this case because if we use the IRET hypercall | |
1391 | * to pop the stack frame we end up in an infinite loop of failsafe callbacks. | |
1392 | * We distinguish between categories by maintaining a status value in EAX. | |
1393 | */ | |
5ead97c8 | 1394 | ENTRY(xen_failsafe_callback) |
a49976d1 IM |
1395 | pushl %eax |
1396 | movl $1, %eax | |
1397 | 1: mov 4(%esp), %ds | |
1398 | 2: mov 8(%esp), %es | |
1399 | 3: mov 12(%esp), %fs | |
1400 | 4: mov 16(%esp), %gs | |
a349e23d DV |
1401 | /* EAX == 0 => Category 1 (Bad segment) |
1402 | EAX != 0 => Category 2 (Bad IRET) */ | |
a49976d1 IM |
1403 | testl %eax, %eax |
1404 | popl %eax | |
1405 | lea 16(%esp), %esp | |
1406 | jz 5f | |
1407 | jmp iret_exc | |
1408 | 5: pushl $-1 /* orig_ax = -1 => not a system call */ | |
5ead97c8 | 1409 | SAVE_ALL |
946c1911 | 1410 | ENCODE_FRAME_POINTER |
a49976d1 IM |
1411 | jmp ret_from_exception |
1412 | ||
1413 | .section .fixup, "ax" | |
1414 | 6: xorl %eax, %eax | |
1415 | movl %eax, 4(%esp) | |
1416 | jmp 1b | |
1417 | 7: xorl %eax, %eax | |
1418 | movl %eax, 8(%esp) | |
1419 | jmp 2b | |
1420 | 8: xorl %eax, %eax | |
1421 | movl %eax, 12(%esp) | |
1422 | jmp 3b | |
1423 | 9: xorl %eax, %eax | |
1424 | movl %eax, 16(%esp) | |
1425 | jmp 4b | |
5ead97c8 | 1426 | .previous |
a49976d1 IM |
1427 | _ASM_EXTABLE(1b, 6b) |
1428 | _ASM_EXTABLE(2b, 7b) | |
1429 | _ASM_EXTABLE(3b, 8b) | |
1430 | _ASM_EXTABLE(4b, 9b) | |
5ead97c8 | 1431 | ENDPROC(xen_failsafe_callback) |
28c11b0f | 1432 | #endif /* CONFIG_XEN_PV */ |
5ead97c8 | 1433 | |
28c11b0f | 1434 | #ifdef CONFIG_XEN_PVHVM |
bc2b0331 | 1435 | BUILD_INTERRUPT3(xen_hvm_callback_vector, HYPERVISOR_CALLBACK_VECTOR, |
4b9a8dca | 1436 | xen_evtchn_do_upcall) |
28c11b0f | 1437 | #endif |
38e20b07 | 1438 | |
bc2b0331 S |
1439 | |
1440 | #if IS_ENABLED(CONFIG_HYPERV) | |
1441 | ||
1442 | BUILD_INTERRUPT3(hyperv_callback_vector, HYPERVISOR_CALLBACK_VECTOR, | |
4b9a8dca | 1443 | hyperv_vector_handler) |
bc2b0331 | 1444 | |
93286261 VK |
1445 | BUILD_INTERRUPT3(hyperv_reenlightenment_vector, HYPERV_REENLIGHTENMENT_VECTOR, |
1446 | hyperv_reenlightenment_intr) | |
1447 | ||
248e742a MK |
1448 | BUILD_INTERRUPT3(hv_stimer0_callback_vector, HYPERV_STIMER0_VECTOR, |
1449 | hv_stimer0_vector_handler) | |
1450 | ||
bc2b0331 | 1451 | #endif /* CONFIG_HYPERV */ |
5ead97c8 | 1452 | |
d211af05 | 1453 | ENTRY(page_fault) |
e59d1b0a | 1454 | ASM_CLAC |
b8f70953 MM |
1455 | pushl $do_page_fault |
1456 | jmp common_exception_read_cr2 | |
1457 | END(page_fault) | |
a0d14b89 | 1458 | |
b8f70953 MM |
1459 | common_exception_read_cr2: |
1460 | /* the function address is in %gs's slot on the stack */ | |
a0d14b89 PZ |
1461 | SAVE_ALL switch_stacks=1 skip_gs=1 |
1462 | ||
1463 | ENCODE_FRAME_POINTER | |
1464 | UNWIND_ESPFIX_STACK | |
1465 | ||
1466 | /* fixup %gs */ | |
1467 | GS_TO_REG %ecx | |
b8f70953 | 1468 | movl PT_GS(%esp), %edi |
a0d14b89 PZ |
1469 | REG_TO_PTGS %ecx |
1470 | SET_KERNEL_GS %ecx | |
1471 | ||
1472 | GET_CR2_INTO(%ecx) # might clobber %eax | |
1473 | ||
1474 | /* fixup orig %eax */ | |
1475 | movl PT_ORIG_EAX(%esp), %edx # get the error code | |
1476 | movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart | |
1477 | ||
1478 | TRACE_IRQS_OFF | |
1479 | movl %esp, %eax # pt_regs pointer | |
b8f70953 | 1480 | CALL_NOSPEC %edi |
a0d14b89 | 1481 | jmp ret_from_exception |
b8f70953 | 1482 | END(common_exception_read_cr2) |
7252c4c3 JP |
1483 | |
1484 | common_exception: | |
ccbeed3a | 1485 | /* the function address is in %gs's slot on the stack */ |
e67f1c11 | 1486 | SAVE_ALL switch_stacks=1 skip_gs=1 |
946c1911 | 1487 | ENCODE_FRAME_POINTER |
d211af05 | 1488 | UNWIND_ESPFIX_STACK |
e67f1c11 PZ |
1489 | |
1490 | /* fixup %gs */ | |
ccbeed3a | 1491 | GS_TO_REG %ecx |
a49976d1 | 1492 | movl PT_GS(%esp), %edi # get the function address |
ccbeed3a TH |
1493 | REG_TO_PTGS %ecx |
1494 | SET_KERNEL_GS %ecx | |
e67f1c11 PZ |
1495 | |
1496 | /* fixup orig %eax */ | |
1497 | movl PT_ORIG_EAX(%esp), %edx # get the error code | |
1498 | movl $-1, PT_ORIG_EAX(%esp) # no syscall to restart | |
1499 | ||
d211af05 | 1500 | TRACE_IRQS_OFF |
a49976d1 | 1501 | movl %esp, %eax # pt_regs pointer |
2641f08b | 1502 | CALL_NOSPEC %edi |
a49976d1 | 1503 | jmp ret_from_exception |
7252c4c3 | 1504 | END(common_exception) |
d211af05 | 1505 | |
d211af05 | 1506 | ENTRY(debug) |
7536656f | 1507 | /* |
929b44eb | 1508 | * Entry from sysenter is now handled in common_exception |
7536656f | 1509 | */ |
e59d1b0a | 1510 | ASM_CLAC |
a49976d1 | 1511 | pushl $-1 # mark this as an int |
929b44eb JR |
1512 | pushl $do_debug |
1513 | jmp common_exception | |
d211af05 AH |
1514 | END(debug) |
1515 | ||
1516 | /* | |
7536656f AL |
1517 | * NMI is doubly nasty. It can happen on the first instruction of |
1518 | * entry_SYSENTER_32 (just like #DB), but it can also interrupt the beginning | |
1519 | * of the #DB handler even if that #DB in turn hit before entry_SYSENTER_32 | |
1520 | * switched stacks. We handle both conditions by simply checking whether we | |
1521 | * interrupted kernel code running on the SYSENTER stack. | |
d211af05 AH |
1522 | */ |
1523 | ENTRY(nmi) | |
e59d1b0a | 1524 | ASM_CLAC |
45d7b255 | 1525 | |
34273f41 | 1526 | #ifdef CONFIG_X86_ESPFIX32 |
a49976d1 IM |
1527 | pushl %eax |
1528 | movl %ss, %eax | |
1529 | cmpw $__ESPFIX_SS, %ax | |
1530 | popl %eax | |
1b00255f | 1531 | je .Lnmi_espfix_stack |
34273f41 | 1532 | #endif |
7536656f AL |
1533 | |
1534 | pushl %eax # pt_regs->orig_ax | |
b65bef40 | 1535 | SAVE_ALL_NMI cr3_reg=%edi |
946c1911 | 1536 | ENCODE_FRAME_POINTER |
a49976d1 IM |
1537 | xorl %edx, %edx # zero error code |
1538 | movl %esp, %eax # pt_regs pointer | |
7536656f AL |
1539 | |
1540 | /* Are we currently on the SYSENTER stack? */ | |
72f5e08d | 1541 | movl PER_CPU_VAR(cpu_entry_area), %ecx |
4fe2d8b1 DH |
1542 | addl $CPU_ENTRY_AREA_entry_stack + SIZEOF_entry_stack, %ecx |
1543 | subl %eax, %ecx /* ecx = (end of entry_stack) - esp */ | |
1544 | cmpl $SIZEOF_entry_stack, %ecx | |
7536656f AL |
1545 | jb .Lnmi_from_sysenter_stack |
1546 | ||
1547 | /* Not on SYSENTER stack. */ | |
a49976d1 | 1548 | call do_nmi |
8e676ced | 1549 | jmp .Lnmi_return |
d211af05 | 1550 | |
7536656f AL |
1551 | .Lnmi_from_sysenter_stack: |
1552 | /* | |
1553 | * We're on the SYSENTER stack. Switch off. No one (not even debug) | |
1554 | * is using the thread stack right now, so it's safe for us to use it. | |
1555 | */ | |
946c1911 | 1556 | movl %esp, %ebx |
7536656f AL |
1557 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esp |
1558 | call do_nmi | |
946c1911 | 1559 | movl %ebx, %esp |
8e676ced JR |
1560 | |
1561 | .Lnmi_return: | |
1562 | CHECK_AND_APPLY_ESPFIX | |
b65bef40 | 1563 | RESTORE_ALL_NMI cr3_reg=%edi pop=4 |
8e676ced | 1564 | jmp .Lirq_return |
d211af05 | 1565 | |
34273f41 | 1566 | #ifdef CONFIG_X86_ESPFIX32 |
1b00255f | 1567 | .Lnmi_espfix_stack: |
131484c8 | 1568 | /* |
d211af05 AH |
1569 | * create the pointer to lss back |
1570 | */ | |
a49976d1 IM |
1571 | pushl %ss |
1572 | pushl %esp | |
1573 | addl $4, (%esp) | |
d211af05 AH |
1574 | /* copy the iret frame of 12 bytes */ |
1575 | .rept 3 | |
a49976d1 | 1576 | pushl 16(%esp) |
d211af05 | 1577 | .endr |
a49976d1 | 1578 | pushl %eax |
b65bef40 | 1579 | SAVE_ALL_NMI cr3_reg=%edi |
946c1911 | 1580 | ENCODE_FRAME_POINTER |
a49976d1 IM |
1581 | FIXUP_ESPFIX_STACK # %eax == %esp |
1582 | xorl %edx, %edx # zero error code | |
1583 | call do_nmi | |
b65bef40 | 1584 | RESTORE_ALL_NMI cr3_reg=%edi |
a49976d1 | 1585 | lss 12+4(%esp), %esp # back to espfix stack |
1b00255f | 1586 | jmp .Lirq_return |
34273f41 | 1587 | #endif |
d211af05 AH |
1588 | END(nmi) |
1589 | ||
1590 | ENTRY(int3) | |
e59d1b0a | 1591 | ASM_CLAC |
a49976d1 | 1592 | pushl $-1 # mark this as an int |
45d7b255 JR |
1593 | |
1594 | SAVE_ALL switch_stacks=1 | |
946c1911 | 1595 | ENCODE_FRAME_POINTER |
d211af05 | 1596 | TRACE_IRQS_OFF |
a49976d1 IM |
1597 | xorl %edx, %edx # zero error code |
1598 | movl %esp, %eax # pt_regs pointer | |
1599 | call do_int3 | |
1600 | jmp ret_from_exception | |
d211af05 AH |
1601 | END(int3) |
1602 | ||
1603 | ENTRY(general_protection) | |
a49976d1 | 1604 | pushl $do_general_protection |
7252c4c3 | 1605 | jmp common_exception |
d211af05 AH |
1606 | END(general_protection) |
1607 | ||
631bc487 GN |
1608 | #ifdef CONFIG_KVM_GUEST |
1609 | ENTRY(async_page_fault) | |
e59d1b0a | 1610 | ASM_CLAC |
a49976d1 | 1611 | pushl $do_async_page_fault |
b8f70953 | 1612 | jmp common_exception_read_cr2 |
2ae9d293 | 1613 | END(async_page_fault) |
631bc487 | 1614 | #endif |
2deb4be2 AL |
1615 | |
1616 | ENTRY(rewind_stack_do_exit) | |
1617 | /* Prevent any naive code from trying to unwind to our caller. */ | |
1618 | xorl %ebp, %ebp | |
1619 | ||
1620 | movl PER_CPU_VAR(cpu_current_top_of_stack), %esi | |
1621 | leal -TOP_OF_KERNEL_STACK_PADDING-PTREGS_SIZE(%esi), %esp | |
1622 | ||
1623 | call do_exit | |
1624 | 1: jmp 1b | |
1625 | END(rewind_stack_do_exit) |