[linux-2.6-block.git] / arch / x86 / boot / cpucheck.c

/* -*- linux-c -*- ------------------------------------------------------- *
 *
 *   Copyright (C) 1991, 1992 Linus Torvalds
 *   Copyright 2007 rPath, Inc. - All Rights Reserved
 *
 *   This file is part of the Linux kernel, and is made available under
 *   the terms of the GNU General Public License version 2.
 *
 * ----------------------------------------------------------------------- */

/*
 * Check for obligatory CPU features and abort if the features are not
 * present.  This code should be compilable as 16-, 32- or 64-bit
 * code, so be very careful with types and inline assembly.
 *
 * This code should not contain any messages; that requires an
 * additional wrapper.
 *
 * As written, this code is not safe for inclusion into the kernel
 * proper (after FPU initialization, in particular).
 */

#ifdef _SETUP
# include "boot.h"
# include "bitops.h"
#endif
#include <linux/types.h>
#include <asm/cpufeature.h>
#include <asm/processor-flags.h>
#include <asm/required-features.h>
#include <asm/msr-index.h>

struct cpu_features {
	int level;		/* Family, or 64 for x86-64 */
	int model;
	u32 flags[NCAPINTS];
};

static struct cpu_features cpu;
static u32 cpu_vendor[3];
static u32 err_flags[NCAPINTS];

static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;

static const u32 req_flags[NCAPINTS] =
{
	REQUIRED_MASK0,
	REQUIRED_MASK1,
	REQUIRED_MASK2,
	REQUIRED_MASK3,
	REQUIRED_MASK4,
	REQUIRED_MASK5,
	REQUIRED_MASK6,
	REQUIRED_MASK7,
};

#define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))

static int is_amd(void)
{
	return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
	       cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
	       cpu_vendor[2] == A32('c', 'A', 'M', 'D');
}

static int is_centaur(void)
{
	return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
	       cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
	       cpu_vendor[2] == A32('a', 'u', 'l', 's');
}

static int is_transmeta(void)
{
	return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
	       cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
	       cpu_vendor[2] == A32('M', 'x', '8', '6');
}

static int has_fpu(void)
{
	u16 fcw = -1, fsw = -1;
	u32 cr0;

	asm("movl %%cr0,%0" : "=r" (cr0));
	if (cr0 & (X86_CR0_EM|X86_CR0_TS)) {
		cr0 &= ~(X86_CR0_EM|X86_CR0_TS);
		asm volatile("movl %0,%%cr0" : : "r" (cr0));
	}

	asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
		     : "+m" (fsw), "+m" (fcw));

	return fsw == 0 && (fcw & 0x103f) == 0x003f;
}

static int has_eflag(u32 mask)
{
	u32 f0, f1;

	asm("pushfl ; "
	    "pushfl ; "
	    "popl %0 ; "
	    "movl %0,%1 ; "
	    "xorl %2,%1 ; "
	    "pushl %1 ; "
	    "popfl ; "
	    "pushfl ; "
	    "popl %1 ; "
	    "popfl"
	    : "=&r" (f0), "=&r" (f1)
	    : "ri" (mask));

	return !!((f0^f1) & mask);
}

static void get_flags(void)
{
	u32 max_intel_level, max_amd_level;
	u32 tfms;

	if (has_fpu())
		set_bit(X86_FEATURE_FPU, cpu.flags);

	if (has_eflag(X86_EFLAGS_ID)) {
		asm("cpuid"
		    : "=a" (max_intel_level),
		      "=b" (cpu_vendor[0]),
		      "=d" (cpu_vendor[1]),
		      "=c" (cpu_vendor[2])
		    : "a" (0));

		if (max_intel_level >= 0x00000001 &&
		    max_intel_level <= 0x0000ffff) {
			asm("cpuid"
			    : "=a" (tfms),
			      "=c" (cpu.flags[4]),
			      "=d" (cpu.flags[0])
			    : "a" (0x00000001)
			    : "ebx");
			cpu.level = (tfms >> 8) & 15;
			cpu.model = (tfms >> 4) & 15;
			if (cpu.level >= 6)
				cpu.model += ((tfms >> 16) & 0xf) << 4;
		}

		asm("cpuid"
		    : "=a" (max_amd_level)
		    : "a" (0x80000000)
		    : "ebx", "ecx", "edx");

		if (max_amd_level >= 0x80000001 &&
		    max_amd_level <= 0x8000ffff) {
			u32 eax = 0x80000001;
			asm("cpuid"
			    : "+a" (eax),
			      "=c" (cpu.flags[6]),
			      "=d" (cpu.flags[1])
			    : : "ebx");
		}
	}
}

/* Returns a bitmask of which words we have error bits in */
static int check_flags(void)
{
	u32 err;
	int i;

	err = 0;
	for (i = 0; i < NCAPINTS; i++) {
		err_flags[i] = req_flags[i] & ~cpu.flags[i];
		if (err_flags[i])
			err |= 1 << i;
	}

	return err;
}

/*
 * Returns -1 on error.
 *
 * *cpu_level is set to the current CPU level; *req_level to the required
 * level.  x86-64 is considered level 64 for this purpose.
 *
 * *err_flags_ptr is set to the flags error array if there are flags missing.
 */
int check_cpu(int *cpu_level_ptr, int *req_level_ptr, u32 **err_flags_ptr)
{
	int err;

	memset(&cpu.flags, 0, sizeof cpu.flags);
	cpu.level = 3;

	if (has_eflag(X86_EFLAGS_AC))
		cpu.level = 4;

	get_flags();
	err = check_flags();

	if (test_bit(X86_FEATURE_LM, cpu.flags))
		cpu.level = 64;

	if (err == 0x01 &&
	    !(err_flags[0] &
	      ~((1 << X86_FEATURE_XMM)|(1 << X86_FEATURE_XMM2))) &&
	    is_amd()) {
		/* If this is an AMD and we're only missing SSE+SSE2, try to
		   turn them on */

		u32 ecx = MSR_K7_HWCR;
		u32 eax, edx;

		asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
		eax &= ~(1 << 15);
		asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));

		get_flags();	/* Make sure it really did something */
		err = check_flags();
	} else if (err == 0x01 &&
		   !(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
		   is_centaur() && cpu.model >= 6) {
		/* If this is a VIA C3, we might have to enable CX8
		   explicitly */

		u32 ecx = MSR_VIA_FCR;
		u32 eax, edx;

		asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
		eax |= (1<<1)|(1<<7);
		asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));

		set_bit(X86_FEATURE_CX8, cpu.flags);
		err = check_flags();
	} else if (err == 0x01 && is_transmeta()) {
		/* Transmeta might have masked feature bits in word 0 */

		u32 ecx = 0x80860004;
		u32 eax, edx;
		u32 level = 1;

		asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
		asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
		asm("cpuid"
		    : "+a" (level), "=d" (cpu.flags[0])
		    : : "ecx", "ebx");
		asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));

		err = check_flags();
	}

	if (err_flags_ptr)
		*err_flags_ptr = err ? err_flags : NULL;
	if (cpu_level_ptr)
		*cpu_level_ptr = cpu.level;
	if (req_level_ptr)
		*req_level_ptr = req_level;

	return (cpu.level < req_level || err) ? -1 : 0;
}
Commit	Line	Data
31b54f40 PA	1	/* -- linux-c -- ------------------------------------------------------- *
	2	*
	3	* Copyright (C) 1991, 1992 Linus Torvalds
	4	* Copyright 2007 rPath, Inc. - All Rights Reserved
	5	*
	6	* This file is part of the Linux kernel, and is made available under
	7	* the terms of the GNU General Public License version 2.
	8	*
	9	* ----------------------------------------------------------------------- */
	10
	11	/*
31b54f40 PA	12	* Check for obligatory CPU features and abort if the features are not
	13	* present. This code should be compilable as 16-, 32- or 64-bit
	14	* code, so be very careful with types and inline assembly.
	15	*
	16	* This code should not contain any messages; that requires an
	17	* additional wrapper.
	18	*
	19	* As written, this code is not safe for inclusion into the kernel
	20	* proper (after FPU initialization, in particular).
	21	*/
	22
	23	#ifdef _SETUP
	24	# include "boot.h"
	25	# include "bitops.h"
	26	#endif
	27	#include <linux/types.h>
	28	#include <asm/cpufeature.h>
	29	#include <asm/processor-flags.h>
	30	#include <asm/required-features.h>
	31	#include <asm/msr-index.h>
	32
	33	struct cpu_features {
	34	int level; /* Family, or 64 for x86-64 */
	35	int model;
	36	u32 flags[NCAPINTS];
	37	};
	38
	39	static struct cpu_features cpu;
	40	static u32 cpu_vendor[3];
	41	static u32 err_flags[NCAPINTS];
	42
31b54f40	43	static const int req_level = CONFIG_X86_MINIMUM_CPU_FAMILY;
31b54f40 PA	44
	45	static const u32 req_flags[NCAPINTS] =
	46	{
	47	REQUIRED_MASK0,
	48	REQUIRED_MASK1,
	49	REQUIRED_MASK2,
	50	REQUIRED_MASK3,
	51	REQUIRED_MASK4,
	52	REQUIRED_MASK5,
	53	REQUIRED_MASK6,
	54	REQUIRED_MASK7,
	55	};
	56
7030760a	57	#define A32(a, b, c, d) (((d) << 24)+((c) << 16)+((b) << 8)+(a))
31b54f40 PA	58
	59	static int is_amd(void)
	60	{
7030760a PC	61	return cpu_vendor[0] == A32('A', 'u', 't', 'h') &&
	62	cpu_vendor[1] == A32('e', 'n', 't', 'i') &&
	63	cpu_vendor[2] == A32('c', 'A', 'M', 'D');
31b54f40 PA	64	}
	65
	66	static int is_centaur(void)
	67	{
7030760a PC	68	return cpu_vendor[0] == A32('C', 'e', 'n', 't') &&
	69	cpu_vendor[1] == A32('a', 'u', 'r', 'H') &&
	70	cpu_vendor[2] == A32('a', 'u', 'l', 's');
31b54f40 PA	71	}
	72
	73	static int is_transmeta(void)
	74	{
7030760a PC	75	return cpu_vendor[0] == A32('G', 'e', 'n', 'u') &&
	76	cpu_vendor[1] == A32('i', 'n', 'e', 'T') &&
	77	cpu_vendor[2] == A32('M', 'x', '8', '6');
31b54f40 PA	78	}
	79
	80	static int has_fpu(void)
	81	{
	82	u16 fcw = -1, fsw = -1;
	83	u32 cr0;
	84
	85	asm("movl %%cr0,%0" : "=r" (cr0));
	86	if (cr0 & (X86_CR0_EM\|X86_CR0_TS)) {
	87	cr0 &= ~(X86_CR0_EM\|X86_CR0_TS);
	88	asm volatile("movl %0,%%cr0" : : "r" (cr0));
	89	}
	90
b015124e PA	91	asm volatile("fninit ; fnstsw %0 ; fnstcw %1"
b015124e PA	92	: "+m" (fsw), "+m" (fcw));
31b54f40 PA	93
	94	return fsw == 0 && (fcw & 0x103f) == 0x003f;
	95	}
	96
	97	static int has_eflag(u32 mask)
	98	{
	99	u32 f0, f1;
	100
	101	asm("pushfl ; "
	102	"pushfl ; "
	103	"popl %0 ; "
	104	"movl %0,%1 ; "
	105	"xorl %2,%1 ; "
	106	"pushl %1 ; "
	107	"popfl ; "
	108	"pushfl ; "
	109	"popl %1 ; "
	110	"popfl"
5593eaa8 PA	111	: "=&r" (f0), "=&r" (f1)
5593eaa8 PA	112	: "ri" (mask));
31b54f40 PA	113
	114	return !!((f0^f1) & mask);
	115	}
	116
	117	static void get_flags(void)
	118	{
	119	u32 max_intel_level, max_amd_level;
	120	u32 tfms;
	121
	122	if (has_fpu())
	123	set_bit(X86_FEATURE_FPU, cpu.flags);
	124
	125	if (has_eflag(X86_EFLAGS_ID)) {
	126	asm("cpuid"
	127	: "=a" (max_intel_level),
	128	"=b" (cpu_vendor[0]),
	129	"=d" (cpu_vendor[1]),
	130	"=c" (cpu_vendor[2])
	131	: "a" (0));
	132
	133	if (max_intel_level >= 0x00000001 &&
	134	max_intel_level <= 0x0000ffff) {
	135	asm("cpuid"
	136	: "=a" (tfms),
	137	"=c" (cpu.flags[4]),
	138	"=d" (cpu.flags[0])
	139	: "a" (0x00000001)
	140	: "ebx");
	141	cpu.level = (tfms >> 8) & 15;
	142	cpu.model = (tfms >> 4) & 15;
	143	if (cpu.level >= 6)
	144	cpu.model += ((tfms >> 16) & 0xf) << 4;
	145	}
	146
	147	asm("cpuid"
	148	: "=a" (max_amd_level)
	149	: "a" (0x80000000)
	150	: "ebx", "ecx", "edx");
	151
	152	if (max_amd_level >= 0x80000001 &&
	153	max_amd_level <= 0x8000ffff) {
	154	u32 eax = 0x80000001;
	155	asm("cpuid"
	156	: "+a" (eax),
	157	"=c" (cpu.flags[6]),
	158	"=d" (cpu.flags[1])
	159	: : "ebx");
	160	}
	161	}
	162	}
	163
	164	/* Returns a bitmask of which words we have error bits in */
	165	static int check_flags(void)
	166	{
	167	u32 err;
	168	int i;
	169
	170	err = 0;
	171	for (i = 0; i < NCAPINTS; i++) {
	172	err_flags[i] = req_flags[i] & ~cpu.flags[i];
	173	if (err_flags[i])
	174	err \|= 1 << i;
	175	}
	176
177	return err;
178	}
179
180	/*
181	* Returns -1 on error.
182	*
183	* cpu_level is set to the current CPU level; req_level to the required
184	* level. x86-64 is considered level 64 for this purpose.
185	*
186	* *err_flags_ptr is set to the flags error array if there are flags missing.
187	*/
188	int check_cpu(int cpu_level_ptr, int req_level_ptr, u32 **err_flags_ptr)
189	{
190	int err;
191
192	memset(&cpu.flags, 0, sizeof cpu.flags);
193	cpu.level = 3;
194
195	if (has_eflag(X86_EFLAGS_AC))
196	cpu.level = 4;
197
198	get_flags();
199	err = check_flags();
200
201	if (test_bit(X86_FEATURE_LM, cpu.flags))
202	cpu.level = 64;
203
204	if (err == 0x01 &&
205	!(err_flags[0] &
206	~((1 << X86_FEATURE_XMM)\|(1 << X86_FEATURE_XMM2))) &&
207	is_amd()) {
208	/* If this is an AMD and we're only missing SSE+SSE2, try to
209	turn them on */
210
211	u32 ecx = MSR_K7_HWCR;
212	u32 eax, edx;
213
214	asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
215	eax &= ~(1 << 15);
216	asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
217
218	get_flags(); /* Make sure it really did something */
219	err = check_flags();
220	} else if (err == 0x01 &&
221	!(err_flags[0] & ~(1 << X86_FEATURE_CX8)) &&
222	is_centaur() && cpu.model >= 6) {
223	/* If this is a VIA C3, we might have to enable CX8
224	explicitly */
225
226	u32 ecx = MSR_VIA_FCR;
227	u32 eax, edx;
228
229	asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
230	eax \|= (1<<1)\|(1<<7);
231	asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
232
233	set_bit(X86_FEATURE_CX8, cpu.flags);
234	err = check_flags();
235	} else if (err == 0x01 && is_transmeta()) {
236	/* Transmeta might have masked feature bits in word 0 */
237
238	u32 ecx = 0x80860004;
239	u32 eax, edx;
240	u32 level = 1;
241
242	asm("rdmsr" : "=a" (eax), "=d" (edx) : "c" (ecx));
243	asm("wrmsr" : : "a" (~0), "d" (edx), "c" (ecx));
244	asm("cpuid"
245	: "+a" (level), "=d" (cpu.flags[0])
246	: : "ecx", "ebx");
247	asm("wrmsr" : : "a" (eax), "d" (edx), "c" (ecx));
248
249	err = check_flags();
250	}
251
252	if (err_flags_ptr)
253	*err_flags_ptr = err ? err_flags : NULL;
254	if (cpu_level_ptr)
255	*cpu_level_ptr = cpu.level;
256	if (req_level_ptr)
257	*req_level_ptr = req_level;
258
259	return (cpu.level < req_level \|\| err) ? -1 : 0;
260	}