[linux-2.6-block.git] / arch / x86 / Kconfig.cpu

# Put here option for CPU selection and depending optimization
if !X86_ELAN

choice
	prompt "Processor family"
	default M686 if X86_32
	default GENERIC_CPU if X86_64

config M386
	bool "386"
	depends on X86_32 && !UML
	---help---
	  This is the processor type of your CPU. This information is used for
	  optimizing purposes. In order to compile a kernel that can run on
	  all x86 CPU types (albeit not optimally fast), you can specify
	  "386" here.

	  The kernel will not necessarily run on earlier architectures than
	  the one you have chosen, e.g. a Pentium optimized kernel will run on
	  a PPro, but not necessarily on a i486.

	  Here are the settings recommended for greatest speed:
	  - "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
	  486DLC/DLC2, and UMC 486SX-S.  Only "386" kernels will run on a 386
	  class machine.
	  - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
	  SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
	  - "586" for generic Pentium CPUs lacking the TSC
	  (time stamp counter) register.
	  - "Pentium-Classic" for the Intel Pentium.
	  - "Pentium-MMX" for the Intel Pentium MMX.
	  - "Pentium-Pro" for the Intel Pentium Pro.
	  - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
	  - "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
	  - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
	  - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
	  - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
	  - "Crusoe" for the Transmeta Crusoe series.
	  - "Efficeon" for the Transmeta Efficeon series.
	  - "Winchip-C6" for original IDT Winchip.
	  - "Winchip-2" for IDT Winchips with 3dNow! capabilities.
	  - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
	  - "Geode GX/LX" For AMD Geode GX and LX processors.
	  - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
	  - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
	  - "VIA C7" for VIA C7.

	  If you don't know what to do, choose "386".

config M486
	bool "486"
	depends on X86_32
	help
	  Select this for a 486 series processor, either Intel or one of the
	  compatible processors from AMD, Cyrix, IBM, or Intel.  Includes DX,
	  DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
	  U5S.

config M586
	bool "586/K5/5x86/6x86/6x86MX"
	depends on X86_32
	help
	  Select this for an 586 or 686 series processor such as the AMD K5,
	  the Cyrix 5x86, 6x86 and 6x86MX.  This choice does not
	  assume the RDTSC (Read Time Stamp Counter) instruction.

config M586TSC
	bool "Pentium-Classic"
	depends on X86_32
	help
	  Select this for a Pentium Classic processor with the RDTSC (Read
	  Time Stamp Counter) instruction for benchmarking.

config M586MMX
	bool "Pentium-MMX"
	depends on X86_32
	help
	  Select this for a Pentium with the MMX graphics/multimedia
	  extended instructions.

config M686
	bool "Pentium-Pro"
	depends on X86_32
	help
	  Select this for Intel Pentium Pro chips.  This enables the use of
	  Pentium Pro extended instructions, and disables the init-time guard
	  against the f00f bug found in earlier Pentiums.

config MPENTIUMII
	bool "Pentium-II/Celeron(pre-Coppermine)"
	depends on X86_32
	help
	  Select this for Intel chips based on the Pentium-II and
	  pre-Coppermine Celeron core.  This option enables an unaligned
	  copy optimization, compiles the kernel with optimization flags
	  tailored for the chip, and applies any applicable Pentium Pro
	  optimizations.

config MPENTIUMIII
	bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
	depends on X86_32
	help
	  Select this for Intel chips based on the Pentium-III and
	  Celeron-Coppermine core.  This option enables use of some
	  extended prefetch instructions in addition to the Pentium II
	  extensions.

config MPENTIUMM
	bool "Pentium M"
	depends on X86_32
	help
	  Select this for Intel Pentium M (not Pentium-4 M)
	  notebook chips.

config MPENTIUM4
	bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
	depends on X86_32
	help
	  Select this for Intel Pentium 4 chips.  This includes the
	  Pentium 4, Pentium D, P4-based Celeron and Xeon, and
	  Pentium-4 M (not Pentium M) chips.  This option enables compile
	  flags optimized for the chip, uses the correct cache line size, and
	  applies any applicable optimizations.

	  CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )

	  Select this for:
	    Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
		-Willamette
		-Northwood
		-Mobile Pentium 4
		-Mobile Pentium 4 M
		-Extreme Edition (Gallatin)
		-Prescott
		-Prescott 2M
		-Cedar Mill
		-Presler
		-Smithfiled
	    Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
		-Foster
		-Prestonia
		-Gallatin
		-Nocona
		-Irwindale
		-Cranford
		-Potomac
		-Paxville
		-Dempsey


config MK6
	bool "K6/K6-II/K6-III"
	depends on X86_32
	help
	  Select this for an AMD K6-family processor.  Enables use of
	  some extended instructions, and passes appropriate optimization
	  flags to GCC.

config MK7
	bool "Athlon/Duron/K7"
	depends on X86_32
	help
	  Select this for an AMD Athlon K7-family processor.  Enables use of
	  some extended instructions, and passes appropriate optimization
	  flags to GCC.

config MK8
	bool "Opteron/Athlon64/Hammer/K8"
	help
	  Select this for an AMD Opteron or Athlon64 Hammer-family processor.
	  Enables use of some extended instructions, and passes appropriate
	  optimization flags to GCC.

config MCRUSOE
	bool "Crusoe"
	depends on X86_32
	help
	  Select this for a Transmeta Crusoe processor.  Treats the processor
	  like a 586 with TSC, and sets some GCC optimization flags (like a
	  Pentium Pro with no alignment requirements).

config MEFFICEON
	bool "Efficeon"
	depends on X86_32
	help
	  Select this for a Transmeta Efficeon processor.

config MWINCHIPC6
	bool "Winchip-C6"
	depends on X86_32
	help
	  Select this for an IDT Winchip C6 chip.  Linux and GCC
	  treat this chip as a 586TSC with some extended instructions
	  and alignment requirements.

config MWINCHIP3D
	bool "Winchip-2/Winchip-2A/Winchip-3"
	depends on X86_32
	help
	  Select this for an IDT Winchip-2, 2A or 3.  Linux and GCC
	  treat this chip as a 586TSC with some extended instructions
	  and alignment requirements.  Also enable out of order memory
	  stores for this CPU, which can increase performance of some
	  operations.

config MGEODEGX1
	bool "GeodeGX1"
	depends on X86_32
	help
	  Select this for a Geode GX1 (Cyrix MediaGX) chip.

config MGEODE_LX
	bool "Geode GX/LX"
	depends on X86_32
	help
	  Select this for AMD Geode GX and LX processors.

config MCYRIXIII
	bool "CyrixIII/VIA-C3"
	depends on X86_32
	help
	  Select this for a Cyrix III or C3 chip.  Presently Linux and GCC
	  treat this chip as a generic 586. Whilst the CPU is 686 class,
	  it lacks the cmov extension which gcc assumes is present when
	  generating 686 code.
	  Note that Nehemiah (Model 9) and above will not boot with this
	  kernel due to them lacking the 3DNow! instructions used in earlier
	  incarnations of the CPU.

config MVIAC3_2
	bool "VIA C3-2 (Nehemiah)"
	depends on X86_32
	help
	  Select this for a VIA C3 "Nehemiah". Selecting this enables usage
	  of SSE and tells gcc to treat the CPU as a 686.
	  Note, this kernel will not boot on older (pre model 9) C3s.

config MVIAC7
	bool "VIA C7"
	depends on X86_32
	help
	  Select this for a VIA C7.  Selecting this uses the correct cache
	  shift and tells gcc to treat the CPU as a 686.

config MPSC
	bool "Intel P4 / older Netburst based Xeon"
	depends on X86_64
	help
	  Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
	  Xeon CPUs with Intel 64bit which is compatible with x86-64.
	  Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
	  Netburst core and shouldn't use this option. You can distinguish them
	  using the cpu family field
	  in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.

config MCORE2
	bool "Core 2/newer Xeon"
	help

	  Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
	  53xx) CPUs. You can distinguish newer from older Xeons by the CPU
	  family in /proc/cpuinfo. Newer ones have 6 and older ones 15
	  (not a typo)

config GENERIC_CPU
	bool "Generic-x86-64"
	depends on X86_64
	help
	  Generic x86-64 CPU.
	  Run equally well on all x86-64 CPUs.

endchoice

config X86_GENERIC
	bool "Generic x86 support"
	depends on X86_32
	help
	  Instead of just including optimizations for the selected
	  x86 variant (e.g. PII, Crusoe or Athlon), include some more
	  generic optimizations as well. This will make the kernel
	  perform better on x86 CPUs other than that selected.

	  This is really intended for distributors who need more
	  generic optimizations.

endif

config X86_CPU
	def_bool y
	select GENERIC_FIND_FIRST_BIT
	select GENERIC_FIND_NEXT_BIT

#
# Define implied options from the CPU selection here
config X86_L1_CACHE_BYTES
	int
	default "128" if GENERIC_CPU || MPSC
	default "64" if MK8 || MCORE2
	depends on X86_64

config X86_INTERNODE_CACHE_BYTES
	int
	default "4096" if X86_VSMP
	default X86_L1_CACHE_BYTES if !X86_VSMP
	depends on X86_64

config X86_CMPXCHG
	def_bool X86_64 || (X86_32 && !M386)

config X86_L1_CACHE_SHIFT
	int
	default "7" if MPENTIUM4 || X86_GENERIC || GENERIC_CPU || MPSC
	default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
	default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
	default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7

config X86_XADD
	def_bool y
	depends on X86_32 && !M386

config X86_PPRO_FENCE
	bool "PentiumPro memory ordering errata workaround"
	depends on M686 || M586MMX || M586TSC || M586 || M486 || M386 || MGEODEGX1
	help
	  Old PentiumPro multiprocessor systems had errata that could cause
	  memory operations to violate the x86 ordering standard in rare cases.
	  Enabling this option will attempt to work around some (but not all)
	  occurances of this problem, at the cost of much heavier spinlock and
	  memory barrier operations.

	  If unsure, say n here. Even distro kernels should think twice before
	  enabling this: there are few systems, and an unlikely bug.

config X86_F00F_BUG
	def_bool y
	depends on M586MMX || M586TSC || M586 || M486 || M386

config X86_WP_WORKS_OK
	def_bool y
	depends on !M386

config X86_INVLPG
	def_bool y
	depends on X86_32 && !M386

config X86_BSWAP
	def_bool y
	depends on X86_32 && !M386

config X86_POPAD_OK
	def_bool y
	depends on X86_32 && !M386

config X86_ALIGNMENT_16
	def_bool y
	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || X86_ELAN || MK6 || M586MMX || M586TSC || M586 || M486 || MVIAC3_2 || MGEODEGX1

config X86_INTEL_USERCOPY
	def_bool y
	depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2

config X86_USE_PPRO_CHECKSUM
	def_bool y
	depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2

config X86_USE_3DNOW
	def_bool y
	depends on (MCYRIXIII || MK7 || MGEODE_LX) && !UML

config X86_OOSTORE
	def_bool y
	depends on (MWINCHIP3D || MWINCHIPC6) && MTRR

#
# P6_NOPs are a relatively minor optimization that require a family >=
# 6 processor, except that it is broken on certain VIA chips.
# Furthermore, AMD chips prefer a totally different sequence of NOPs
# (which work on all CPUs).  In addition, it looks like Virtual PC
# does not understand them.
#
# As a result, disallow these if we're not compiling for X86_64 (these
# NOPs do work on all x86-64 capable chips); the list of processors in
# the right-hand clause are the cores that benefit from this optimization.
#
config X86_P6_NOP
	def_bool y
	depends on X86_64
	depends on (MCORE2 || MPENTIUM4 || MPSC)

config X86_TSC
	def_bool y
	depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64

config X86_CMPXCHG64
	def_bool y
	depends on X86_PAE || X86_64

# this should be set for all -march=.. options where the compiler
# generates cmov.
config X86_CMOV
	def_bool y
	depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64)

config X86_MINIMUM_CPU_FAMILY
	int
	default "64" if X86_64
	default "6" if X86_32 && X86_P6_NOP
	default "4" if X86_32 && (X86_XADD || X86_CMPXCHG || X86_BSWAP || X86_WP_WORKS_OK)
	default "3"

config X86_DEBUGCTLMSR
	def_bool y
	depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486 || M386) && !UML

menuconfig PROCESSOR_SELECT
	bool "Supported processor vendors" if EMBEDDED
	help
	  This lets you choose what x86 vendor support code your kernel
	  will include.

config CPU_SUP_INTEL
	default y
	bool "Support Intel processors" if PROCESSOR_SELECT
	help
	  This enables detection, tunings and quirks for Intel processors

	  You need this enabled if you want your kernel to run on an
	  Intel CPU. Disabling this option on other types of CPUs
	  makes the kernel a tiny bit smaller. Disabling it on an Intel
	  CPU might render the kernel unbootable.

	  If unsure, say N.

config CPU_SUP_CYRIX_32
	default y
	bool "Support Cyrix processors" if PROCESSOR_SELECT
	depends on !64BIT
	help
	  This enables detection, tunings and quirks for Cyrix processors

	  You need this enabled if you want your kernel to run on a
	  Cyrix CPU. Disabling this option on other types of CPUs
	  makes the kernel a tiny bit smaller. Disabling it on a Cyrix
	  CPU might render the kernel unbootable.

	  If unsure, say N.

config CPU_SUP_AMD
	default y
	bool "Support AMD processors" if PROCESSOR_SELECT
	help
	  This enables detection, tunings and quirks for AMD processors

	  You need this enabled if you want your kernel to run on an
	  AMD CPU. Disabling this option on other types of CPUs
	  makes the kernel a tiny bit smaller. Disabling it on an AMD
	  CPU might render the kernel unbootable.

	  If unsure, say N.

config CPU_SUP_CENTAUR_32
	default y
	bool "Support Centaur processors" if PROCESSOR_SELECT
	depends on !64BIT
	help
	  This enables detection, tunings and quirks for Centaur processors

	  You need this enabled if you want your kernel to run on a
	  Centaur CPU. Disabling this option on other types of CPUs
	  makes the kernel a tiny bit smaller. Disabling it on a Centaur
	  CPU might render the kernel unbootable.

	  If unsure, say N.

config CPU_SUP_CENTAUR_64
	default y
	bool "Support Centaur processors" if PROCESSOR_SELECT
	depends on 64BIT
	help
	  This enables detection, tunings and quirks for Centaur processors

	  You need this enabled if you want your kernel to run on a
	  Centaur CPU. Disabling this option on other types of CPUs
	  makes the kernel a tiny bit smaller. Disabling it on a Centaur
	  CPU might render the kernel unbootable.

	  If unsure, say N.

config CPU_SUP_TRANSMETA_32
	default y
	bool "Support Transmeta processors" if PROCESSOR_SELECT
	depends on !64BIT
	help
	  This enables detection, tunings and quirks for Transmeta processors

	  You need this enabled if you want your kernel to run on a
	  Transmeta CPU. Disabling this option on other types of CPUs
	  makes the kernel a tiny bit smaller. Disabling it on a Transmeta
	  CPU might render the kernel unbootable.

	  If unsure, say N.

config CPU_SUP_UMC_32
	default y
	bool "Support UMC processors" if PROCESSOR_SELECT
	depends on !64BIT
	help
	  This enables detection, tunings and quirks for UMC processors

	  You need this enabled if you want your kernel to run on a
	  UMC CPU. Disabling this option on other types of CPUs
	  makes the kernel a tiny bit smaller. Disabling it on a UMC
	  CPU might render the kernel unbootable.

	  If unsure, say N.

config X86_DS
	def_bool X86_PTRACE_BTS
	depends on X86_DEBUGCTLMSR
	select HAVE_HW_BRANCH_TRACER

config X86_PTRACE_BTS
	bool "Branch Trace Store"
	default y
	depends on X86_DEBUGCTLMSR
	help
	  This adds a ptrace interface to the hardware's branch trace store.

	  Debuggers may use it to collect an execution trace of the debugged
	  application in order to answer the question 'how did I get here?'.
	  Debuggers may trace user mode as well as kernel mode.

	  Say Y unless there is no application development on this machine
	  and you want to save a small amount of code size.
Commit	Line	Data
96d55b88 PBG	1	# Put here option for CPU selection and depending optimization
	2	if !X86_ELAN
	3
	4	choice
	5	prompt "Processor family"
1032c0ba SR	6	default M686 if X86_32
1032c0ba SR	7	default GENERIC_CPU if X86_64
96d55b88 PBG	8
	9	config M386
	10	bool "386"
1032c0ba	11	depends on X86_32 && !UML
96d55b88 PBG	12	---help---
	13	This is the processor type of your CPU. This information is used for
	14	optimizing purposes. In order to compile a kernel that can run on
	15	all x86 CPU types (albeit not optimally fast), you can specify
	16	"386" here.
	17
	18	The kernel will not necessarily run on earlier architectures than
	19	the one you have chosen, e.g. a Pentium optimized kernel will run on
	20	a PPro, but not necessarily on a i486.
	21
	22	Here are the settings recommended for greatest speed:
	23	- "386" for the AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI
f7f17a67 DV	24	486DLC/DLC2, and UMC 486SX-S. Only "386" kernels will run on a 386
f7f17a67 DV	25	class machine.
96d55b88 PBG	26	- "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or
	27	SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S.
	28	- "586" for generic Pentium CPUs lacking the TSC
	29	(time stamp counter) register.
	30	- "Pentium-Classic" for the Intel Pentium.
	31	- "Pentium-MMX" for the Intel Pentium MMX.
	32	- "Pentium-Pro" for the Intel Pentium Pro.
	33	- "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron.
	34	- "Pentium-III" for the Intel Pentium III or Coppermine Celeron.
	35	- "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
	36	- "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
	37	- "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
	38	- "Crusoe" for the Transmeta Crusoe series.
	39	- "Efficeon" for the Transmeta Efficeon series.
	40	- "Winchip-C6" for original IDT Winchip.
69d45dd1	41	- "Winchip-2" for IDT Winchips with 3dNow! capabilities.
96d55b88	42	- "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
f90b8116	43	- "Geode GX/LX" For AMD Geode GX and LX processors.
96d55b88	44	- "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
48a1204c	45	- "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
0949be35	46	- "VIA C7" for VIA C7.
96d55b88 PBG	47
	48	If you don't know what to do, choose "386".
	49
	50	config M486
	51	bool "486"
1032c0ba	52	depends on X86_32
96d55b88 PBG	53	help
	54	Select this for a 486 series processor, either Intel or one of the
	55	compatible processors from AMD, Cyrix, IBM, or Intel. Includes DX,
	56	DX2, and DX4 variants; also SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or
	57	U5S.
	58
	59	config M586
	60	bool "586/K5/5x86/6x86/6x86MX"
1032c0ba	61	depends on X86_32
96d55b88 PBG	62	help
	63	Select this for an 586 or 686 series processor such as the AMD K5,
	64	the Cyrix 5x86, 6x86 and 6x86MX. This choice does not
	65	assume the RDTSC (Read Time Stamp Counter) instruction.
	66
	67	config M586TSC
	68	bool "Pentium-Classic"
1032c0ba	69	depends on X86_32
96d55b88 PBG	70	help
	71	Select this for a Pentium Classic processor with the RDTSC (Read
	72	Time Stamp Counter) instruction for benchmarking.
	73
	74	config M586MMX
	75	bool "Pentium-MMX"
1032c0ba	76	depends on X86_32
96d55b88 PBG	77	help
	78	Select this for a Pentium with the MMX graphics/multimedia
	79	extended instructions.
	80
	81	config M686
	82	bool "Pentium-Pro"
1032c0ba	83	depends on X86_32
96d55b88 PBG	84	help
	85	Select this for Intel Pentium Pro chips. This enables the use of
	86	Pentium Pro extended instructions, and disables the init-time guard
	87	against the f00f bug found in earlier Pentiums.
	88
	89	config MPENTIUMII
	90	bool "Pentium-II/Celeron(pre-Coppermine)"
1032c0ba	91	depends on X86_32
96d55b88 PBG	92	help
	93	Select this for Intel chips based on the Pentium-II and
	94	pre-Coppermine Celeron core. This option enables an unaligned
	95	copy optimization, compiles the kernel with optimization flags
	96	tailored for the chip, and applies any applicable Pentium Pro
	97	optimizations.
	98
	99	config MPENTIUMIII
	100	bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon"
1032c0ba	101	depends on X86_32
96d55b88 PBG	102	help
	103	Select this for Intel chips based on the Pentium-III and
	104	Celeron-Coppermine core. This option enables use of some
	105	extended prefetch instructions in addition to the Pentium II
	106	extensions.
	107
	108	config MPENTIUMM
	109	bool "Pentium M"
1032c0ba	110	depends on X86_32
96d55b88 PBG	111	help
	112	Select this for Intel Pentium M (not Pentium-4 M)
	113	notebook chips.
	114
	115	config MPENTIUM4
c55d92d1	116	bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
1032c0ba	117	depends on X86_32
96d55b88 PBG	118	help
96d55b88 PBG	119	Select this for Intel Pentium 4 chips. This includes the
75e3808b OP	120	Pentium 4, Pentium D, P4-based Celeron and Xeon, and
	121	Pentium-4 M (not Pentium M) chips. This option enables compile
	122	flags optimized for the chip, uses the correct cache line size, and
	123	applies any applicable optimizations.
	124
	125	CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 )
	126
	127	Select this for:
	128	Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename:
	129	-Willamette
	130	-Northwood
	131	-Mobile Pentium 4
	132	-Mobile Pentium 4 M
	133	-Extreme Edition (Gallatin)
	134	-Prescott
	135	-Prescott 2M
	136	-Cedar Mill
	137	-Presler
	138	-Smithfiled
	139	Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
	140	-Foster
	141	-Prestonia
	142	-Gallatin
	143	-Nocona
	144	-Irwindale
	145	-Cranford
	146	-Potomac
	147	-Paxville
	148	-Dempsey
	149
96d55b88 PBG	150
	151	config MK6
	152	bool "K6/K6-II/K6-III"
1032c0ba	153	depends on X86_32
96d55b88 PBG	154	help
	155	Select this for an AMD K6-family processor. Enables use of
	156	some extended instructions, and passes appropriate optimization
	157	flags to GCC.
	158
	159	config MK7
	160	bool "Athlon/Duron/K7"
1032c0ba	161	depends on X86_32
96d55b88 PBG	162	help
	163	Select this for an AMD Athlon K7-family processor. Enables use of
	164	some extended instructions, and passes appropriate optimization
	165	flags to GCC.
	166
	167	config MK8
	168	bool "Opteron/Athlon64/Hammer/K8"
	169	help
36723bfe BP	170	Select this for an AMD Opteron or Athlon64 Hammer-family processor.
	171	Enables use of some extended instructions, and passes appropriate
	172	optimization flags to GCC.
96d55b88 PBG	173
	174	config MCRUSOE
	175	bool "Crusoe"
1032c0ba	176	depends on X86_32
96d55b88 PBG	177	help
	178	Select this for a Transmeta Crusoe processor. Treats the processor
	179	like a 586 with TSC, and sets some GCC optimization flags (like a
	180	Pentium Pro with no alignment requirements).
	181
	182	config MEFFICEON
	183	bool "Efficeon"
1032c0ba	184	depends on X86_32
96d55b88 PBG	185	help
	186	Select this for a Transmeta Efficeon processor.
	187
	188	config MWINCHIPC6
	189	bool "Winchip-C6"
1032c0ba	190	depends on X86_32
96d55b88 PBG	191	help
	192	Select this for an IDT Winchip C6 chip. Linux and GCC
	193	treat this chip as a 586TSC with some extended instructions
	194	and alignment requirements.
	195
96d55b88	196	config MWINCHIP3D
69d45dd1	197	bool "Winchip-2/Winchip-2A/Winchip-3"
1032c0ba	198	depends on X86_32
96d55b88	199	help
69d45dd1	200	Select this for an IDT Winchip-2, 2A or 3. Linux and GCC
96d55b88	201	treat this chip as a 586TSC with some extended instructions
3dde6ad8	202	and alignment requirements. Also enable out of order memory
96d55b88 PBG	203	stores for this CPU, which can increase performance of some
	204	operations.
	205
	206	config MGEODEGX1
	207	bool "GeodeGX1"
1032c0ba	208	depends on X86_32
96d55b88 PBG	209	help
	210	Select this for a Geode GX1 (Cyrix MediaGX) chip.
	211
f90b8116	212	config MGEODE_LX
96daa8cd	213	bool "Geode GX/LX"
1032c0ba	214	depends on X86_32
96daa8cd HH	215	help
96daa8cd HH	216	Select this for AMD Geode GX and LX processors.
f90b8116	217
96d55b88 PBG	218	config MCYRIXIII
96d55b88 PBG	219	bool "CyrixIII/VIA-C3"
1032c0ba	220	depends on X86_32
96d55b88 PBG	221	help
	222	Select this for a Cyrix III or C3 chip. Presently Linux and GCC
	223	treat this chip as a generic 586. Whilst the CPU is 686 class,
	224	it lacks the cmov extension which gcc assumes is present when
	225	generating 686 code.
	226	Note that Nehemiah (Model 9) and above will not boot with this
	227	kernel due to them lacking the 3DNow! instructions used in earlier
	228	incarnations of the CPU.
	229
	230	config MVIAC3_2
	231	bool "VIA C3-2 (Nehemiah)"
1032c0ba	232	depends on X86_32
96d55b88 PBG	233	help
	234	Select this for a VIA C3 "Nehemiah". Selecting this enables usage
	235	of SSE and tells gcc to treat the CPU as a 686.
	236	Note, this kernel will not boot on older (pre model 9) C3s.
	237
0949be35 SA	238	config MVIAC7
0949be35 SA	239	bool "VIA C7"
1032c0ba	240	depends on X86_32
0949be35 SA	241	help
	242	Select this for a VIA C7. Selecting this uses the correct cache
	243	shift and tells gcc to treat the CPU as a 686.
	244
1032c0ba SR	245	config MPSC
	246	bool "Intel P4 / older Netburst based Xeon"
	247	depends on X86_64
	248	help
	249	Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
	250	Xeon CPUs with Intel 64bit which is compatible with x86-64.
	251	Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
96daa8cd	252	Netburst core and shouldn't use this option. You can distinguish them
1032c0ba SR	253	using the cpu family field
	254	in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
	255
	256	config MCORE2
	257	bool "Core 2/newer Xeon"
	258	help
36723bfe BP	259
	260	Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
	261	53xx) CPUs. You can distinguish newer from older Xeons by the CPU
	262	family in /proc/cpuinfo. Newer ones have 6 and older ones 15
	263	(not a typo)
1032c0ba SR	264
	265	config GENERIC_CPU
	266	bool "Generic-x86-64"
	267	depends on X86_64
	268	help
	269	Generic x86-64 CPU.
	270	Run equally well on all x86-64 CPUs.
	271
96d55b88 PBG	272	endchoice
	273
	274	config X86_GENERIC
1032c0ba SR	275	bool "Generic x86 support"
	276	depends on X86_32
	277	help
96d55b88 PBG	278	Instead of just including optimizations for the selected
	279	x86 variant (e.g. PII, Crusoe or Athlon), include some more
	280	generic optimizations as well. This will make the kernel
	281	perform better on x86 CPUs other than that selected.
	282
	283	This is really intended for distributors who need more
	284	generic optimizations.
	285
	286	endif
	287
acbaa93e IM	288	config X86_CPU
	289	def_bool y
	290	select GENERIC_FIND_FIRST_BIT
	291	select GENERIC_FIND_NEXT_BIT
	292
96d55b88 PBG	293	#
96d55b88 PBG	294	# Define implied options from the CPU selection here
1032c0ba SR	295	config X86_L1_CACHE_BYTES
	296	int
	297	default "128" if GENERIC_CPU \|\| MPSC
	298	default "64" if MK8 \|\| MCORE2
	299	depends on X86_64
	300
	301	config X86_INTERNODE_CACHE_BYTES
	302	int
	303	default "4096" if X86_VSMP
	304	default X86_L1_CACHE_BYTES if !X86_VSMP
	305	depends on X86_64
	306
96d55b88	307	config X86_CMPXCHG
1032c0ba	308	def_bool X86_64 \|\| (X86_32 && !M386)
96d55b88	309
96d55b88 PBG	310	config X86_L1_CACHE_SHIFT
96d55b88 PBG	311	int
1032c0ba	312	default "7" if MPENTIUM4 \|\| X86_GENERIC \|\| GENERIC_CPU \|\| MPSC
f90b8116	313	default "4" if X86_ELAN \|\| M486 \|\| M386 \|\| MGEODEGX1
69d45dd1	314	default "5" if MWINCHIP3D \|\| MWINCHIPC6 \|\| MCRUSOE \|\| MEFFICEON \|\| MCYRIXIII \|\| MK6 \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M686 \|\| M586MMX \|\| M586TSC \|\| M586 \|\| MVIAC3_2 \|\| MGEODE_LX
0949be35	315	default "6" if MK7 \|\| MK8 \|\| MPENTIUMM \|\| MCORE2 \|\| MVIAC7
96d55b88	316
c7f81c94	317	config X86_XADD
96daa8cd	318	def_bool y
1032c0ba	319	depends on X86_32 && !M386
96d55b88 PBG	320
96d55b88 PBG	321	config X86_PPRO_FENCE
fb0328e2	322	bool "PentiumPro memory ordering errata workaround"
96d55b88	323	depends on M686 \|\| M586MMX \|\| M586TSC \|\| M586 \|\| M486 \|\| M386 \|\| MGEODEGX1
fb0328e2	324	help
36723bfe BP	325	Old PentiumPro multiprocessor systems had errata that could cause
	326	memory operations to violate the x86 ordering standard in rare cases.
	327	Enabling this option will attempt to work around some (but not all)
	328	occurances of this problem, at the cost of much heavier spinlock and
	329	memory barrier operations.
	330
	331	If unsure, say n here. Even distro kernels should think twice before
	332	enabling this: there are few systems, and an unlikely bug.
96d55b88 PBG	333
96d55b88 PBG	334	config X86_F00F_BUG
96daa8cd	335	def_bool y
96d55b88	336	depends on M586MMX \|\| M586TSC \|\| M586 \|\| M486 \|\| M386
96d55b88 PBG	337
96d55b88 PBG	338	config X86_WP_WORKS_OK
96daa8cd	339	def_bool y
293e6a25	340	depends on !M386
96d55b88 PBG	341
96d55b88 PBG	342	config X86_INVLPG
96daa8cd	343	def_bool y
1032c0ba	344	depends on X86_32 && !M386
96d55b88 PBG	345
96d55b88 PBG	346	config X86_BSWAP
96daa8cd	347	def_bool y
1032c0ba	348	depends on X86_32 && !M386
96d55b88 PBG	349
96d55b88 PBG	350	config X86_POPAD_OK
96daa8cd	351	def_bool y
1032c0ba	352	depends on X86_32 && !M386
96d55b88	353
96d55b88	354	config X86_ALIGNMENT_16
96daa8cd	355	def_bool y
69d45dd1	356	depends on MWINCHIP3D \|\| MWINCHIPC6 \|\| MCYRIXIII \|\| X86_ELAN \|\| MK6 \|\| M586MMX \|\| M586TSC \|\| M586 \|\| M486 \|\| MVIAC3_2 \|\| MGEODEGX1
96d55b88	357
96d55b88	358	config X86_INTEL_USERCOPY
96daa8cd	359	def_bool y
c55d92d1	360	depends on MPENTIUM4 \|\| MPENTIUMM \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M586MMX \|\| X86_GENERIC \|\| MK8 \|\| MK7 \|\| MEFFICEON \|\| MCORE2
96d55b88 PBG	361
96d55b88 PBG	362	config X86_USE_PPRO_CHECKSUM
96daa8cd	363	def_bool y
69d45dd1	364	depends on MWINCHIP3D \|\| MWINCHIPC6 \|\| MCYRIXIII \|\| MK7 \|\| MK6 \|\| MPENTIUM4 \|\| MPENTIUMM \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M686 \|\| MK8 \|\| MVIAC3_2 \|\| MEFFICEON \|\| MGEODE_LX \|\| MCORE2
96d55b88 PBG	365
96d55b88 PBG	366	config X86_USE_3DNOW
96daa8cd	367	def_bool y
1b4ad242	368	depends on (MCYRIXIII \|\| MK7 \|\| MGEODE_LX) && !UML
96d55b88 PBG	369
96d55b88 PBG	370	config X86_OOSTORE
96daa8cd	371	def_bool y
69d45dd1	372	depends on (MWINCHIP3D \|\| MWINCHIPC6) && MTRR
96d55b88	373
959b3be6 PA	374	#
	375	# P6_NOPs are a relatively minor optimization that require a family >=
	376	# 6 processor, except that it is broken on certain VIA chips.
	377	# Furthermore, AMD chips prefer a totally different sequence of NOPs
14469a8d LT	378	# (which work on all CPUs). In addition, it looks like Virtual PC
	379	# does not understand them.
	380	#
	381	# As a result, disallow these if we're not compiling for X86_64 (these
	382	# NOPs do work on all x86-64 capable chips); the list of processors in
	383	# the right-hand clause are the cores that benefit from this optimization.
959b3be6	384	#
7343b3b3 PA	385	config X86_P6_NOP
7343b3b3 PA	386	def_bool y
14469a8d LT	387	depends on X86_64
14469a8d LT	388	depends on (MCORE2 \|\| MPENTIUM4 \|\| MPSC)
7343b3b3	389
96d55b88	390	config X86_TSC
96daa8cd	391	def_bool y
69d45dd1	392	depends on ((MWINCHIP3D \|\| MCRUSOE \|\| MEFFICEON \|\| MCYRIXIII \|\| MK7 \|\| MK6 \|\| MPENTIUM4 \|\| MPENTIUMM \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M686 \|\| M586MMX \|\| M586TSC \|\| MK8 \|\| MVIAC3_2 \|\| MVIAC7 \|\| MGEODEGX1 \|\| MGEODE_LX \|\| MCORE2) && !X86_NUMAQ) \|\| X86_64
c7f81c94	393
f8096f92 JB	394	config X86_CMPXCHG64
	395	def_bool y
	396	depends on X86_PAE \|\| X86_64
	397
c7f81c94 AK	398	# this should be set for all -march=.. options where the compiler
	399	# generates cmov.
	400	config X86_CMOV
96daa8cd	401	def_bool y
79aa10dd	402	depends on (MK8 \|\| MK7 \|\| MCORE2 \|\| MPENTIUM4 \|\| MPENTIUMM \|\| MPENTIUMIII \|\| MPENTIUMII \|\| M686 \|\| MVIAC3_2 \|\| MVIAC7 \|\| MCRUSOE \|\| MEFFICEON \|\| X86_64)
c7f81c94	403
de32e041	404	config X86_MINIMUM_CPU_FAMILY
c7f81c94	405	int
1032c0ba	406	default "64" if X86_64
7343b3b3	407	default "6" if X86_32 && X86_P6_NOP
1032c0ba	408	default "4" if X86_32 && (X86_XADD \|\| X86_CMPXCHG \|\| X86_BSWAP \|\| X86_WP_WORKS_OK)
de32e041	409	default "3"
c7f81c94	410
0a049bb0	411	config X86_DEBUGCTLMSR
96daa8cd	412	def_bool y
5641f1fd	413	depends on !(MK6 \|\| MWINCHIPC6 \|\| MWINCHIP3D \|\| MCYRIXIII \|\| M586MMX \|\| M586TSC \|\| M586 \|\| M486 \|\| M386) && !UML
8d02c211 TP	414
8d02c211 TP	415	menuconfig PROCESSOR_SELECT
8d02c211 TP	416	bool "Supported processor vendors" if EMBEDDED
	417	help
	418	This lets you choose what x86 vendor support code your kernel
	419	will include.
	420
879d792b	421	config CPU_SUP_INTEL
8d02c211 TP	422	default y
8d02c211 TP	423	bool "Support Intel processors" if PROCESSOR_SELECT
8d02c211	424	help
b7b3a425 IM	425	This enables detection, tunings and quirks for Intel processors
	426
	427	You need this enabled if you want your kernel to run on an
	428	Intel CPU. Disabling this option on other types of CPUs
	429	makes the kernel a tiny bit smaller. Disabling it on an Intel
	430	CPU might render the kernel unbootable.
	431
	432	If unsure, say N.
8d02c211 TP	433
	434	config CPU_SUP_CYRIX_32
	435	default y
	436	bool "Support Cyrix processors" if PROCESSOR_SELECT
	437	depends on !64BIT
	438	help
b7b3a425 IM	439	This enables detection, tunings and quirks for Cyrix processors
	440
	441	You need this enabled if you want your kernel to run on a
	442	Cyrix CPU. Disabling this option on other types of CPUs
	443	makes the kernel a tiny bit smaller. Disabling it on a Cyrix
	444	CPU might render the kernel unbootable.
	445
	446	If unsure, say N.
8d02c211	447
ff73152c	448	config CPU_SUP_AMD
8d02c211 TP	449	default y
8d02c211 TP	450	bool "Support AMD processors" if PROCESSOR_SELECT
8d02c211	451	help
b7b3a425 IM	452	This enables detection, tunings and quirks for AMD processors
	453
	454	You need this enabled if you want your kernel to run on an
	455	AMD CPU. Disabling this option on other types of CPUs
	456	makes the kernel a tiny bit smaller. Disabling it on an AMD
	457	CPU might render the kernel unbootable.
	458
	459	If unsure, say N.
8d02c211 TP	460
	461	config CPU_SUP_CENTAUR_32
	462	default y
	463	bool "Support Centaur processors" if PROCESSOR_SELECT
	464	depends on !64BIT
	465	help
b7b3a425 IM	466	This enables detection, tunings and quirks for Centaur processors
	467
	468	You need this enabled if you want your kernel to run on a
	469	Centaur CPU. Disabling this option on other types of CPUs
	470	makes the kernel a tiny bit smaller. Disabling it on a Centaur
	471	CPU might render the kernel unbootable.
	472
	473	If unsure, say N.
8d02c211 TP	474
	475	config CPU_SUP_CENTAUR_64
	476	default y
	477	bool "Support Centaur processors" if PROCESSOR_SELECT
	478	depends on 64BIT
	479	help
b7b3a425 IM	480	This enables detection, tunings and quirks for Centaur processors
	481
	482	You need this enabled if you want your kernel to run on a
	483	Centaur CPU. Disabling this option on other types of CPUs
	484	makes the kernel a tiny bit smaller. Disabling it on a Centaur
	485	CPU might render the kernel unbootable.
	486
	487	If unsure, say N.
8d02c211 TP	488
	489	config CPU_SUP_TRANSMETA_32
	490	default y
	491	bool "Support Transmeta processors" if PROCESSOR_SELECT
	492	depends on !64BIT
	493	help
b7b3a425 IM	494	This enables detection, tunings and quirks for Transmeta processors
	495
	496	You need this enabled if you want your kernel to run on a
	497	Transmeta CPU. Disabling this option on other types of CPUs
	498	makes the kernel a tiny bit smaller. Disabling it on a Transmeta
	499	CPU might render the kernel unbootable.
	500
	501	If unsure, say N.
8d02c211 TP	502
	503	config CPU_SUP_UMC_32
	504	default y
	505	bool "Support UMC processors" if PROCESSOR_SELECT
	506	depends on !64BIT
	507	help
b7b3a425 IM	508	This enables detection, tunings and quirks for UMC processors
	509
	510	You need this enabled if you want your kernel to run on a
	511	UMC CPU. Disabling this option on other types of CPUs
	512	makes the kernel a tiny bit smaller. Disabling it on a UMC
	513	CPU might render the kernel unbootable.
	514
	515	If unsure, say N.
81faaae4	516
93fa7636	517	config X86_DS
531f6ed7 MM	518	def_bool X86_PTRACE_BTS
531f6ed7 MM	519	depends on X86_DEBUGCTLMSR
1e9b51c2	520	select HAVE_HW_BRANCH_TRACER
93fa7636 MM	521
93fa7636 MM	522	config X86_PTRACE_BTS
531f6ed7	523	bool "Branch Trace Store"
93fa7636	524	default y
531f6ed7	525	depends on X86_DEBUGCTLMSR
93fa7636	526	help
531f6ed7 MM	527	This adds a ptrace interface to the hardware's branch trace store.
	528
	529	Debuggers may use it to collect an execution trace of the debugged
	530	application in order to answer the question 'how did I get here?'.
	531	Debuggers may trace user mode as well as kernel mode.
	532
	533	Say Y unless there is no application development on this machine
	534	and you want to save a small amount of code size.