Commit | Line | Data |
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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
96d55b88 | 2 | # Put here option for CPU selection and depending optimization |
96d55b88 PBG |
3 | choice |
4 | prompt "Processor family" | |
1032c0ba SR |
5 | default M686 if X86_32 |
6 | default GENERIC_CPU if X86_64 | |
a7f7f624 | 7 | help |
eb068e78 PA |
8 | This is the processor type of your CPU. This information is |
9 | used for optimizing purposes. In order to compile a kernel | |
10 | that can run on all supported x86 CPU types (albeit not | |
11 | optimally fast), you can specify "486" here. | |
12 | ||
13 | Note that the 386 is no longer supported, this includes | |
14 | AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI 486DLC/DLC2, | |
11af32b6 | 15 | UMC 486SX-S and the NexGen Nx586. |
96d55b88 PBG |
16 | |
17 | The kernel will not necessarily run on earlier architectures than | |
18 | the one you have chosen, e.g. a Pentium optimized kernel will run on | |
19 | a PPro, but not necessarily on a i486. | |
20 | ||
21 | Here are the settings recommended for greatest speed: | |
96d55b88 | 22 | - "486" for the AMD/Cyrix/IBM/Intel 486DX/DX2/DX4 or |
221836e9 | 23 | SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5D or U5S. |
96d55b88 | 24 | - "586" for generic Pentium CPUs lacking the TSC |
221836e9 | 25 | (time stamp counter) register. |
96d55b88 PBG |
26 | - "Pentium-Classic" for the Intel Pentium. |
27 | - "Pentium-MMX" for the Intel Pentium MMX. | |
28 | - "Pentium-Pro" for the Intel Pentium Pro. | |
29 | - "Pentium-II" for the Intel Pentium II or pre-Coppermine Celeron. | |
30 | - "Pentium-III" for the Intel Pentium III or Coppermine Celeron. | |
31 | - "Pentium-4" for the Intel Pentium 4 or P4-based Celeron. | |
32 | - "K6" for the AMD K6, K6-II and K6-III (aka K6-3D). | |
33 | - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird). | |
221836e9 | 34 | - "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs. |
96d55b88 PBG |
35 | - "Crusoe" for the Transmeta Crusoe series. |
36 | - "Efficeon" for the Transmeta Efficeon series. | |
37 | - "Winchip-C6" for original IDT Winchip. | |
69d45dd1 | 38 | - "Winchip-2" for IDT Winchips with 3dNow! capabilities. |
221836e9 | 39 | - "AMD Elan" for the 32-bit AMD Elan embedded CPU. |
96d55b88 | 40 | - "GeodeGX1" for Geode GX1 (Cyrix MediaGX). |
f90b8116 | 41 | - "Geode GX/LX" For AMD Geode GX and LX processors. |
96d55b88 | 42 | - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3. |
48a1204c | 43 | - "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above). |
0949be35 | 44 | - "VIA C7" for VIA C7. |
221836e9 BP |
45 | - "Intel P4" for the Pentium 4/Netburst microarchitecture. |
46 | - "Core 2/newer Xeon" for all core2 and newer Intel CPUs. | |
47 | - "Intel Atom" for the Atom-microarchitecture CPUs. | |
48 | - "Generic-x86-64" for a kernel which runs on any x86-64 CPU. | |
49 | ||
50 | See each option's help text for additional details. If you don't know | |
51 | what to do, choose "486". | |
96d55b88 | 52 | |
87d6021b AB |
53 | config M486SX |
54 | bool "486SX" | |
55 | depends on X86_32 | |
a7f7f624 | 56 | help |
87d6021b AB |
57 | Select this for an 486-class CPU without an FPU such as |
58 | AMD/Cyrix/IBM/Intel SL/SLC/SLC2/SLC3/SX/SX2 and UMC U5S. | |
59 | ||
221836e9 | 60 | config M486 |
87d6021b | 61 | bool "486DX" |
221836e9 | 62 | depends on X86_32 |
a7f7f624 | 63 | help |
221836e9 | 64 | Select this for an 486-class CPU such as AMD/Cyrix/IBM/Intel |
87d6021b | 65 | 486DX/DX2/DX4 and UMC U5D. |
96d55b88 PBG |
66 | |
67 | config M586 | |
68 | bool "586/K5/5x86/6x86/6x86MX" | |
1032c0ba | 69 | depends on X86_32 |
a7f7f624 | 70 | help |
96d55b88 PBG |
71 | Select this for an 586 or 686 series processor such as the AMD K5, |
72 | the Cyrix 5x86, 6x86 and 6x86MX. This choice does not | |
73 | assume the RDTSC (Read Time Stamp Counter) instruction. | |
74 | ||
75 | config M586TSC | |
76 | bool "Pentium-Classic" | |
1032c0ba | 77 | depends on X86_32 |
a7f7f624 | 78 | help |
96d55b88 PBG |
79 | Select this for a Pentium Classic processor with the RDTSC (Read |
80 | Time Stamp Counter) instruction for benchmarking. | |
81 | ||
82 | config M586MMX | |
83 | bool "Pentium-MMX" | |
1032c0ba | 84 | depends on X86_32 |
a7f7f624 | 85 | help |
96d55b88 PBG |
86 | Select this for a Pentium with the MMX graphics/multimedia |
87 | extended instructions. | |
88 | ||
89 | config M686 | |
90 | bool "Pentium-Pro" | |
1032c0ba | 91 | depends on X86_32 |
a7f7f624 | 92 | help |
96d55b88 PBG |
93 | Select this for Intel Pentium Pro chips. This enables the use of |
94 | Pentium Pro extended instructions, and disables the init-time guard | |
95 | against the f00f bug found in earlier Pentiums. | |
96 | ||
97 | config MPENTIUMII | |
98 | bool "Pentium-II/Celeron(pre-Coppermine)" | |
1032c0ba | 99 | depends on X86_32 |
a7f7f624 | 100 | help |
96d55b88 PBG |
101 | Select this for Intel chips based on the Pentium-II and |
102 | pre-Coppermine Celeron core. This option enables an unaligned | |
103 | copy optimization, compiles the kernel with optimization flags | |
104 | tailored for the chip, and applies any applicable Pentium Pro | |
105 | optimizations. | |
106 | ||
107 | config MPENTIUMIII | |
108 | bool "Pentium-III/Celeron(Coppermine)/Pentium-III Xeon" | |
1032c0ba | 109 | depends on X86_32 |
a7f7f624 | 110 | help |
96d55b88 PBG |
111 | Select this for Intel chips based on the Pentium-III and |
112 | Celeron-Coppermine core. This option enables use of some | |
113 | extended prefetch instructions in addition to the Pentium II | |
114 | extensions. | |
115 | ||
116 | config MPENTIUMM | |
117 | bool "Pentium M" | |
1032c0ba | 118 | depends on X86_32 |
a7f7f624 | 119 | help |
96d55b88 PBG |
120 | Select this for Intel Pentium M (not Pentium-4 M) |
121 | notebook chips. | |
122 | ||
123 | config MPENTIUM4 | |
c55d92d1 | 124 | bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon" |
1032c0ba | 125 | depends on X86_32 |
a7f7f624 | 126 | help |
96d55b88 | 127 | Select this for Intel Pentium 4 chips. This includes the |
75e3808b OP |
128 | Pentium 4, Pentium D, P4-based Celeron and Xeon, and |
129 | Pentium-4 M (not Pentium M) chips. This option enables compile | |
130 | flags optimized for the chip, uses the correct cache line size, and | |
131 | applies any applicable optimizations. | |
132 | ||
133 | CPUIDs: F[0-6][1-A] (in /proc/cpuinfo show = cpu family : 15 ) | |
134 | ||
135 | Select this for: | |
136 | Pentiums (Pentium 4, Pentium D, Celeron, Celeron D) corename: | |
137 | -Willamette | |
138 | -Northwood | |
139 | -Mobile Pentium 4 | |
140 | -Mobile Pentium 4 M | |
141 | -Extreme Edition (Gallatin) | |
142 | -Prescott | |
143 | -Prescott 2M | |
144 | -Cedar Mill | |
145 | -Presler | |
146 | -Smithfiled | |
147 | Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename: | |
148 | -Foster | |
149 | -Prestonia | |
150 | -Gallatin | |
151 | -Nocona | |
152 | -Irwindale | |
153 | -Cranford | |
154 | -Potomac | |
155 | -Paxville | |
156 | -Dempsey | |
157 | ||
96d55b88 PBG |
158 | |
159 | config MK6 | |
160 | bool "K6/K6-II/K6-III" | |
1032c0ba | 161 | depends on X86_32 |
a7f7f624 | 162 | help |
96d55b88 PBG |
163 | Select this for an AMD K6-family processor. Enables use of |
164 | some extended instructions, and passes appropriate optimization | |
165 | flags to GCC. | |
166 | ||
167 | config MK7 | |
168 | bool "Athlon/Duron/K7" | |
1032c0ba | 169 | depends on X86_32 |
a7f7f624 | 170 | help |
96d55b88 PBG |
171 | Select this for an AMD Athlon K7-family processor. Enables use of |
172 | some extended instructions, and passes appropriate optimization | |
173 | flags to GCC. | |
174 | ||
175 | config MK8 | |
176 | bool "Opteron/Athlon64/Hammer/K8" | |
a7f7f624 | 177 | help |
36723bfe BP |
178 | Select this for an AMD Opteron or Athlon64 Hammer-family processor. |
179 | Enables use of some extended instructions, and passes appropriate | |
180 | optimization flags to GCC. | |
96d55b88 PBG |
181 | |
182 | config MCRUSOE | |
183 | bool "Crusoe" | |
1032c0ba | 184 | depends on X86_32 |
a7f7f624 | 185 | help |
96d55b88 PBG |
186 | Select this for a Transmeta Crusoe processor. Treats the processor |
187 | like a 586 with TSC, and sets some GCC optimization flags (like a | |
188 | Pentium Pro with no alignment requirements). | |
189 | ||
190 | config MEFFICEON | |
191 | bool "Efficeon" | |
1032c0ba | 192 | depends on X86_32 |
a7f7f624 | 193 | help |
96d55b88 PBG |
194 | Select this for a Transmeta Efficeon processor. |
195 | ||
196 | config MWINCHIPC6 | |
197 | bool "Winchip-C6" | |
1032c0ba | 198 | depends on X86_32 |
a7f7f624 | 199 | help |
96d55b88 PBG |
200 | Select this for an IDT Winchip C6 chip. Linux and GCC |
201 | treat this chip as a 586TSC with some extended instructions | |
202 | and alignment requirements. | |
203 | ||
96d55b88 | 204 | config MWINCHIP3D |
69d45dd1 | 205 | bool "Winchip-2/Winchip-2A/Winchip-3" |
1032c0ba | 206 | depends on X86_32 |
a7f7f624 | 207 | help |
69d45dd1 | 208 | Select this for an IDT Winchip-2, 2A or 3. Linux and GCC |
96d55b88 | 209 | treat this chip as a 586TSC with some extended instructions |
3dde6ad8 | 210 | and alignment requirements. Also enable out of order memory |
96d55b88 PBG |
211 | stores for this CPU, which can increase performance of some |
212 | operations. | |
213 | ||
ce9c99af IC |
214 | config MELAN |
215 | bool "AMD Elan" | |
216 | depends on X86_32 | |
a7f7f624 | 217 | help |
ce9c99af IC |
218 | Select this for an AMD Elan processor. |
219 | ||
220 | Do not use this option for K6/Athlon/Opteron processors! | |
221 | ||
96d55b88 PBG |
222 | config MGEODEGX1 |
223 | bool "GeodeGX1" | |
1032c0ba | 224 | depends on X86_32 |
a7f7f624 | 225 | help |
96d55b88 PBG |
226 | Select this for a Geode GX1 (Cyrix MediaGX) chip. |
227 | ||
f90b8116 | 228 | config MGEODE_LX |
96daa8cd | 229 | bool "Geode GX/LX" |
1032c0ba | 230 | depends on X86_32 |
a7f7f624 | 231 | help |
96daa8cd | 232 | Select this for AMD Geode GX and LX processors. |
f90b8116 | 233 | |
96d55b88 PBG |
234 | config MCYRIXIII |
235 | bool "CyrixIII/VIA-C3" | |
1032c0ba | 236 | depends on X86_32 |
a7f7f624 | 237 | help |
96d55b88 PBG |
238 | Select this for a Cyrix III or C3 chip. Presently Linux and GCC |
239 | treat this chip as a generic 586. Whilst the CPU is 686 class, | |
240 | it lacks the cmov extension which gcc assumes is present when | |
241 | generating 686 code. | |
242 | Note that Nehemiah (Model 9) and above will not boot with this | |
243 | kernel due to them lacking the 3DNow! instructions used in earlier | |
244 | incarnations of the CPU. | |
245 | ||
246 | config MVIAC3_2 | |
247 | bool "VIA C3-2 (Nehemiah)" | |
1032c0ba | 248 | depends on X86_32 |
a7f7f624 | 249 | help |
96d55b88 PBG |
250 | Select this for a VIA C3 "Nehemiah". Selecting this enables usage |
251 | of SSE and tells gcc to treat the CPU as a 686. | |
252 | Note, this kernel will not boot on older (pre model 9) C3s. | |
253 | ||
0949be35 SA |
254 | config MVIAC7 |
255 | bool "VIA C7" | |
1032c0ba | 256 | depends on X86_32 |
a7f7f624 | 257 | help |
0949be35 SA |
258 | Select this for a VIA C7. Selecting this uses the correct cache |
259 | shift and tells gcc to treat the CPU as a 686. | |
260 | ||
1032c0ba SR |
261 | config MPSC |
262 | bool "Intel P4 / older Netburst based Xeon" | |
263 | depends on X86_64 | |
a7f7f624 | 264 | help |
1032c0ba SR |
265 | Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey |
266 | Xeon CPUs with Intel 64bit which is compatible with x86-64. | |
267 | Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the | |
96daa8cd | 268 | Netburst core and shouldn't use this option. You can distinguish them |
1032c0ba SR |
269 | using the cpu family field |
270 | in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one. | |
271 | ||
272 | config MCORE2 | |
273 | bool "Core 2/newer Xeon" | |
a7f7f624 | 274 | help |
36723bfe BP |
275 | |
276 | Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and | |
277 | 53xx) CPUs. You can distinguish newer from older Xeons by the CPU | |
278 | family in /proc/cpuinfo. Newer ones have 6 and older ones 15 | |
279 | (not a typo) | |
1032c0ba | 280 | |
366d19e1 TD |
281 | config MATOM |
282 | bool "Intel Atom" | |
a7f7f624 | 283 | help |
366d19e1 TD |
284 | |
285 | Select this for the Intel Atom platform. Intel Atom CPUs have an | |
286 | in-order pipelining architecture and thus can benefit from | |
287 | accordingly optimized code. Use a recent GCC with specific Atom | |
288 | support in order to fully benefit from selecting this option. | |
289 | ||
1032c0ba SR |
290 | config GENERIC_CPU |
291 | bool "Generic-x86-64" | |
292 | depends on X86_64 | |
a7f7f624 | 293 | help |
1032c0ba SR |
294 | Generic x86-64 CPU. |
295 | Run equally well on all x86-64 CPUs. | |
296 | ||
96d55b88 PBG |
297 | endchoice |
298 | ||
299 | config X86_GENERIC | |
1032c0ba SR |
300 | bool "Generic x86 support" |
301 | depends on X86_32 | |
a7f7f624 | 302 | help |
96d55b88 PBG |
303 | Instead of just including optimizations for the selected |
304 | x86 variant (e.g. PII, Crusoe or Athlon), include some more | |
305 | generic optimizations as well. This will make the kernel | |
306 | perform better on x86 CPUs other than that selected. | |
307 | ||
308 | This is really intended for distributors who need more | |
309 | generic optimizations. | |
310 | ||
96d55b88 PBG |
311 | # |
312 | # Define implied options from the CPU selection here | |
350f8f56 | 313 | config X86_INTERNODE_CACHE_SHIFT |
1032c0ba | 314 | int |
350f8f56 | 315 | default "12" if X86_VSMP |
350f8f56 | 316 | default X86_L1_CACHE_SHIFT |
1032c0ba | 317 | |
96d55b88 PBG |
318 | config X86_L1_CACHE_SHIFT |
319 | int | |
0a2a18b7 | 320 | default "7" if MPENTIUM4 || MPSC |
350f8f56 | 321 | default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU |
87d6021b | 322 | default "4" if MELAN || M486SX || M486 || MGEODEGX1 |
69d45dd1 | 323 | default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX |
96d55b88 | 324 | |
96d55b88 | 325 | config X86_F00F_BUG |
96daa8cd | 326 | def_bool y |
87d6021b | 327 | depends on M586MMX || M586TSC || M586 || M486SX || M486 |
96d55b88 | 328 | |
40d2e763 BG |
329 | config X86_INVD_BUG |
330 | def_bool y | |
87d6021b | 331 | depends on M486SX || M486 |
40d2e763 | 332 | |
96d55b88 | 333 | config X86_ALIGNMENT_16 |
96daa8cd | 334 | def_bool y |
87d6021b | 335 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MELAN || MK6 || M586MMX || M586TSC || M586 || M486SX || M486 || MVIAC3_2 || MGEODEGX1 |
96d55b88 | 336 | |
96d55b88 | 337 | config X86_INTEL_USERCOPY |
96daa8cd | 338 | def_bool y |
c55d92d1 | 339 | depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2 |
96d55b88 PBG |
340 | |
341 | config X86_USE_PPRO_CHECKSUM | |
96daa8cd | 342 | def_bool y |
1eda75c1 | 343 | depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM |
96d55b88 | 344 | |
959b3be6 PA |
345 | # |
346 | # P6_NOPs are a relatively minor optimization that require a family >= | |
347 | # 6 processor, except that it is broken on certain VIA chips. | |
348 | # Furthermore, AMD chips prefer a totally different sequence of NOPs | |
14469a8d LT |
349 | # (which work on all CPUs). In addition, it looks like Virtual PC |
350 | # does not understand them. | |
351 | # | |
352 | # As a result, disallow these if we're not compiling for X86_64 (these | |
353 | # NOPs do work on all x86-64 capable chips); the list of processors in | |
354 | # the right-hand clause are the cores that benefit from this optimization. | |
959b3be6 | 355 | # |
7343b3b3 PA |
356 | config X86_P6_NOP |
357 | def_bool y | |
14469a8d LT |
358 | depends on X86_64 |
359 | depends on (MCORE2 || MPENTIUM4 || MPSC) | |
7343b3b3 | 360 | |
96d55b88 | 361 | config X86_TSC |
96daa8cd | 362 | def_bool y |
b5660ba7 | 363 | depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64 |
c7f81c94 | 364 | |
88a2b4ed AB |
365 | config X86_HAVE_PAE |
366 | def_bool y | |
367 | depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC7 || MCORE2 || MATOM || X86_64 | |
368 | ||
f8096f92 JB |
369 | config X86_CMPXCHG64 |
370 | def_bool y | |
88a2b4ed | 371 | depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 |
f8096f92 | 372 | |
c7f81c94 AK |
373 | # this should be set for all -march=.. options where the compiler |
374 | # generates cmov. | |
375 | config X86_CMOV | |
96daa8cd | 376 | def_bool y |
98059e34 | 377 | depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX) |
c7f81c94 | 378 | |
de32e041 | 379 | config X86_MINIMUM_CPU_FAMILY |
c7f81c94 | 380 | int |
1032c0ba | 381 | default "64" if X86_64 |
f6a18925 | 382 | default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCORE2 || MK7 || MK8) |
982d007a | 383 | default "5" if X86_32 && X86_CMPXCHG64 |
eb068e78 | 384 | default "4" |
c7f81c94 | 385 | |
0a049bb0 | 386 | config X86_DEBUGCTLMSR |
96daa8cd | 387 | def_bool y |
87d6021b | 388 | depends on !(MK6 || MWINCHIPC6 || MWINCHIP3D || MCYRIXIII || M586MMX || M586TSC || M586 || M486SX || M486) && !UML |
8d02c211 | 389 | |
1db2a6e1 SC |
390 | config IA32_FEAT_CTL |
391 | def_bool y | |
7d37953b | 392 | depends on CPU_SUP_INTEL || CPU_SUP_CENTAUR || CPU_SUP_ZHAOXIN |
1db2a6e1 | 393 | |
b47ce1fe SC |
394 | config X86_VMX_FEATURE_NAMES |
395 | def_bool y | |
7583e8fb | 396 | depends on IA32_FEAT_CTL |
b47ce1fe | 397 | |
8d02c211 | 398 | menuconfig PROCESSOR_SELECT |
6a108a14 | 399 | bool "Supported processor vendors" if EXPERT |
a7f7f624 | 400 | help |
8d02c211 TP |
401 | This lets you choose what x86 vendor support code your kernel |
402 | will include. | |
403 | ||
879d792b | 404 | config CPU_SUP_INTEL |
8d02c211 TP |
405 | default y |
406 | bool "Support Intel processors" if PROCESSOR_SELECT | |
a7f7f624 | 407 | help |
b7b3a425 IM |
408 | This enables detection, tunings and quirks for Intel processors |
409 | ||
410 | You need this enabled if you want your kernel to run on an | |
411 | Intel CPU. Disabling this option on other types of CPUs | |
412 | makes the kernel a tiny bit smaller. Disabling it on an Intel | |
413 | CPU might render the kernel unbootable. | |
414 | ||
415 | If unsure, say N. | |
8d02c211 TP |
416 | |
417 | config CPU_SUP_CYRIX_32 | |
418 | default y | |
419 | bool "Support Cyrix processors" if PROCESSOR_SELECT | |
87d6021b | 420 | depends on M486SX || M486 || M586 || M586TSC || M586MMX || (EXPERT && !64BIT) |
a7f7f624 | 421 | help |
b7b3a425 IM |
422 | This enables detection, tunings and quirks for Cyrix processors |
423 | ||
424 | You need this enabled if you want your kernel to run on a | |
425 | Cyrix CPU. Disabling this option on other types of CPUs | |
426 | makes the kernel a tiny bit smaller. Disabling it on a Cyrix | |
427 | CPU might render the kernel unbootable. | |
428 | ||
429 | If unsure, say N. | |
8d02c211 | 430 | |
ff73152c | 431 | config CPU_SUP_AMD |
8d02c211 TP |
432 | default y |
433 | bool "Support AMD processors" if PROCESSOR_SELECT | |
a7f7f624 | 434 | help |
b7b3a425 IM |
435 | This enables detection, tunings and quirks for AMD processors |
436 | ||
437 | You need this enabled if you want your kernel to run on an | |
438 | AMD CPU. Disabling this option on other types of CPUs | |
439 | makes the kernel a tiny bit smaller. Disabling it on an AMD | |
440 | CPU might render the kernel unbootable. | |
441 | ||
442 | If unsure, say N. | |
8d02c211 | 443 | |
c9661c1e PW |
444 | config CPU_SUP_HYGON |
445 | default y | |
446 | bool "Support Hygon processors" if PROCESSOR_SELECT | |
447 | select CPU_SUP_AMD | |
448 | help | |
449 | This enables detection, tunings and quirks for Hygon processors | |
450 | ||
451 | You need this enabled if you want your kernel to run on an | |
452 | Hygon CPU. Disabling this option on other types of CPUs | |
453 | makes the kernel a tiny bit smaller. Disabling it on an Hygon | |
454 | CPU might render the kernel unbootable. | |
455 | ||
456 | If unsure, say N. | |
457 | ||
48f4c485 | 458 | config CPU_SUP_CENTAUR |
8d02c211 TP |
459 | default y |
460 | bool "Support Centaur processors" if PROCESSOR_SELECT | |
a7f7f624 | 461 | help |
b7b3a425 IM |
462 | This enables detection, tunings and quirks for Centaur processors |
463 | ||
464 | You need this enabled if you want your kernel to run on a | |
465 | Centaur CPU. Disabling this option on other types of CPUs | |
466 | makes the kernel a tiny bit smaller. Disabling it on a Centaur | |
467 | CPU might render the kernel unbootable. | |
468 | ||
469 | If unsure, say N. | |
8d02c211 TP |
470 | |
471 | config CPU_SUP_TRANSMETA_32 | |
472 | default y | |
473 | bool "Support Transmeta processors" if PROCESSOR_SELECT | |
474 | depends on !64BIT | |
a7f7f624 | 475 | help |
b7b3a425 IM |
476 | This enables detection, tunings and quirks for Transmeta processors |
477 | ||
478 | You need this enabled if you want your kernel to run on a | |
479 | Transmeta CPU. Disabling this option on other types of CPUs | |
480 | makes the kernel a tiny bit smaller. Disabling it on a Transmeta | |
481 | CPU might render the kernel unbootable. | |
482 | ||
483 | If unsure, say N. | |
8d02c211 TP |
484 | |
485 | config CPU_SUP_UMC_32 | |
486 | default y | |
487 | bool "Support UMC processors" if PROCESSOR_SELECT | |
87d6021b | 488 | depends on M486SX || M486 || (EXPERT && !64BIT) |
a7f7f624 | 489 | help |
b7b3a425 IM |
490 | This enables detection, tunings and quirks for UMC processors |
491 | ||
492 | You need this enabled if you want your kernel to run on a | |
493 | UMC CPU. Disabling this option on other types of CPUs | |
494 | makes the kernel a tiny bit smaller. Disabling it on a UMC | |
495 | CPU might render the kernel unbootable. | |
496 | ||
497 | If unsure, say N. | |
761fdd5e TW |
498 | |
499 | config CPU_SUP_ZHAOXIN | |
500 | default y | |
501 | bool "Support Zhaoxin processors" if PROCESSOR_SELECT | |
502 | help | |
503 | This enables detection, tunings and quirks for Zhaoxin processors | |
504 | ||
505 | You need this enabled if you want your kernel to run on a | |
506 | Zhaoxin CPU. Disabling this option on other types of CPUs | |
507 | makes the kernel a tiny bit smaller. Disabling it on a Zhaoxin | |
508 | CPU might render the kernel unbootable. | |
509 | ||
510 | If unsure, say N. | |
639475d4 MDSV |
511 | |
512 | config CPU_SUP_VORTEX_32 | |
513 | default y | |
514 | bool "Support Vortex processors" if PROCESSOR_SELECT | |
515 | depends on X86_32 | |
516 | help | |
517 | This enables detection, tunings and quirks for Vortex processors | |
518 | ||
519 | You need this enabled if you want your kernel to run on a | |
520 | Vortex CPU. Disabling this option on other types of CPUs | |
521 | makes the kernel a tiny bit smaller. | |
522 | ||
523 | If unsure, say N. |