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b2441318 | 1 | # SPDX-License-Identifier: GPL-2.0 |
b50f1704 G |
2 | comment "Processor Type" |
3 | ||
4 | # Select CPU types depending on the architecture selected. This selects | |
5 | # which CPUs we support in the kernel image, and the compiler instruction | |
6 | # optimiser behaviour. | |
7 | ||
8 | config CPU_UCV2 | |
9 | def_bool y | |
10 | ||
11 | comment "Processor Features" | |
12 | ||
13 | config CPU_ICACHE_DISABLE | |
14 | bool "Disable I-Cache (I-bit)" | |
15 | help | |
16 | Say Y here to disable the processor instruction cache. Unless | |
17 | you have a reason not to or are unsure, say N. | |
18 | ||
19 | config CPU_DCACHE_DISABLE | |
20 | bool "Disable D-Cache (D-bit)" | |
21 | help | |
22 | Say Y here to disable the processor data cache. Unless | |
23 | you have a reason not to or are unsure, say N. | |
24 | ||
25 | config CPU_DCACHE_WRITETHROUGH | |
26 | bool "Force write through D-cache" | |
27 | help | |
28 | Say Y here to use the data cache in writethrough mode. Unless you | |
29 | specifically require this or are unsure, say N. | |
30 | ||
31 | config CPU_DCACHE_LINE_DISABLE | |
32 | bool "Disable D-cache line ops" | |
33 | default y | |
34 | help | |
35 | Say Y here to disable the data cache line operations. | |
36 | ||
37 | config CPU_TLB_SINGLE_ENTRY_DISABLE | |
38 | bool "Disable TLB single entry ops" | |
39 | default y | |
40 | help | |
41 | Say Y here to disable the TLB single entry operations. | |
42 | ||
43 | config SWIOTLB | |
44 | def_bool y | |
45 | ||
46 | config IOMMU_HELPER | |
47 | def_bool SWIOTLB | |
48 | ||
49 | config NEED_SG_DMA_LENGTH | |
50 | def_bool SWIOTLB | |
51 |