[linux-2.6-block.git] / arch / unicore32 / kernel / irq.c

/*
 * linux/arch/unicore32/kernel/irq.c
 *
 * Code specific to PKUnity SoC and UniCore ISA
 *
 * Copyright (C) 2001-2010 GUAN Xue-tao
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/kernel_stat.h>
#include <linux/module.h>
#include <linux/signal.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/random.h>
#include <linux/smp.h>
#include <linux/init.h>
#include <linux/seq_file.h>
#include <linux/errno.h>
#include <linux/list.h>
#include <linux/kallsyms.h>
#include <linux/proc_fs.h>
#include <linux/syscore_ops.h>
#include <linux/gpio.h>

#include <mach/hardware.h>

#include "setup.h"

/*
 * PKUnity GPIO edge detection for IRQs:
 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
 * Use this instead of directly setting GRER/GFER.
 */
static int GPIO_IRQ_rising_edge;
static int GPIO_IRQ_falling_edge;
static int GPIO_IRQ_mask = 0;

#define GPIO_MASK(irq)		(1 << (irq - IRQ_GPIO0))

static int puv3_gpio_type(struct irq_data *d, unsigned int type)
{
	unsigned int mask;

	if (d->irq < IRQ_GPIOHIGH)
		mask = 1 << d->irq;
	else
		mask = GPIO_MASK(d->irq);

	if (type == IRQ_TYPE_PROBE) {
		if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
			return 0;
		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	if (type & IRQ_TYPE_EDGE_RISING)
		GPIO_IRQ_rising_edge |= mask;
	else
		GPIO_IRQ_rising_edge &= ~mask;
	if (type & IRQ_TYPE_EDGE_FALLING)
		GPIO_IRQ_falling_edge |= mask;
	else
		GPIO_IRQ_falling_edge &= ~mask;

	writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
	writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);

	return 0;
}

/*
 * GPIO IRQs must be acknowledged.  This is for IRQs from 0 to 7.
 */
static void puv3_low_gpio_ack(struct irq_data *d)
{
	writel((1 << d->irq), GPIO_GEDR);
}

static void puv3_low_gpio_mask(struct irq_data *d)
{
	writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
}

static void puv3_low_gpio_unmask(struct irq_data *d)
{
	writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR);
}

static int puv3_low_gpio_wake(struct irq_data *d, unsigned int on)
{
	if (on)
		writel(readl(PM_PWER) | (1 << d->irq), PM_PWER);
	else
		writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER);
	return 0;
}

static struct irq_chip puv3_low_gpio_chip = {
	.name		= "GPIO-low",
	.irq_ack	= puv3_low_gpio_ack,
	.irq_mask	= puv3_low_gpio_mask,
	.irq_unmask	= puv3_low_gpio_unmask,
	.irq_set_type	= puv3_gpio_type,
	.irq_set_wake	= puv3_low_gpio_wake,
};

/*
 * IRQ8 (GPIO0 through 27) handler.  We enter here with the
 * irq_controller_lock held, and IRQs disabled.  Decode the IRQ
 * and call the handler.
 */
static void
puv3_gpio_handler(unsigned int irq, struct irq_desc *desc)
{
	unsigned int mask;

	mask = readl(GPIO_GEDR);
	do {
		/*
		 * clear down all currently active IRQ sources.
		 * We will be processing them all.
		 */
		writel(mask, GPIO_GEDR);

		irq = IRQ_GPIO0;
		do {
			if (mask & 1)
				generic_handle_irq(irq);
			mask >>= 1;
			irq++;
		} while (mask);
		mask = readl(GPIO_GEDR);
	} while (mask);
}

/*
 * GPIO0-27 edge IRQs need to be handled specially.
 * In addition, the IRQs are all collected up into one bit in the
 * interrupt controller registers.
 */
static void puv3_high_gpio_ack(struct irq_data *d)
{
	unsigned int mask = GPIO_MASK(d->irq);

	writel(mask, GPIO_GEDR);
}

static void puv3_high_gpio_mask(struct irq_data *d)
{
	unsigned int mask = GPIO_MASK(d->irq);

	GPIO_IRQ_mask &= ~mask;

	writel(readl(GPIO_GRER) & ~mask, GPIO_GRER);
	writel(readl(GPIO_GFER) & ~mask, GPIO_GFER);
}

static void puv3_high_gpio_unmask(struct irq_data *d)
{
	unsigned int mask = GPIO_MASK(d->irq);

	GPIO_IRQ_mask |= mask;

	writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
	writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
}

static int puv3_high_gpio_wake(struct irq_data *d, unsigned int on)
{
	if (on)
		writel(readl(PM_PWER) | PM_PWER_GPIOHIGH, PM_PWER);
	else
		writel(readl(PM_PWER) & ~PM_PWER_GPIOHIGH, PM_PWER);
	return 0;
}

static struct irq_chip puv3_high_gpio_chip = {
	.name		= "GPIO-high",
	.irq_ack	= puv3_high_gpio_ack,
	.irq_mask	= puv3_high_gpio_mask,
	.irq_unmask	= puv3_high_gpio_unmask,
	.irq_set_type	= puv3_gpio_type,
	.irq_set_wake	= puv3_high_gpio_wake,
};

/*
 * We don't need to ACK IRQs on the PKUnity unless they're GPIOs
 * this is for internal IRQs i.e. from 8 to 31.
 */
static void puv3_mask_irq(struct irq_data *d)
{
	writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
}

static void puv3_unmask_irq(struct irq_data *d)
{
	writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR);
}

/*
 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
 */
static int puv3_set_wake(struct irq_data *d, unsigned int on)
{
	if (d->irq == IRQ_RTCAlarm) {
		if (on)
			writel(readl(PM_PWER) | PM_PWER_RTC, PM_PWER);
		else
			writel(readl(PM_PWER) & ~PM_PWER_RTC, PM_PWER);
		return 0;
	}
	return -EINVAL;
}

static struct irq_chip puv3_normal_chip = {
	.name		= "PKUnity-v3",
	.irq_ack	= puv3_mask_irq,
	.irq_mask	= puv3_mask_irq,
	.irq_unmask	= puv3_unmask_irq,
	.irq_set_wake	= puv3_set_wake,
};

static struct resource irq_resource = {
	.name	= "irqs",
	.start	= io_v2p(PKUNITY_INTC_BASE),
	.end	= io_v2p(PKUNITY_INTC_BASE) + 0xFFFFF,
};

static struct puv3_irq_state {
	unsigned int	saved;
	unsigned int	icmr;
	unsigned int	iclr;
	unsigned int	iccr;
} puv3_irq_state;

static int puv3_irq_suspend(void)
{
	struct puv3_irq_state *st = &puv3_irq_state;

	st->saved = 1;
	st->icmr = readl(INTC_ICMR);
	st->iclr = readl(INTC_ICLR);
	st->iccr = readl(INTC_ICCR);

	/*
	 * Disable all GPIO-based interrupts.
	 */
	writel(readl(INTC_ICMR) & ~(0x1ff), INTC_ICMR);

	/*
	 * Set the appropriate edges for wakeup.
	 */
	writel(readl(PM_PWER) & GPIO_IRQ_rising_edge, GPIO_GRER);
	writel(readl(PM_PWER) & GPIO_IRQ_falling_edge, GPIO_GFER);

	/*
	 * Clear any pending GPIO interrupts.
	 */
	writel(readl(GPIO_GEDR), GPIO_GEDR);

	return 0;
}

static void puv3_irq_resume(void)
{
	struct puv3_irq_state *st = &puv3_irq_state;

	if (st->saved) {
		writel(st->iccr, INTC_ICCR);
		writel(st->iclr, INTC_ICLR);

		writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
		writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);

		writel(st->icmr, INTC_ICMR);
	}
}

static struct syscore_ops puv3_irq_syscore_ops = {
	.suspend	= puv3_irq_suspend,
	.resume		= puv3_irq_resume,
};

static int __init puv3_irq_init_syscore(void)
{
	register_syscore_ops(&puv3_irq_syscore_ops);
	return 0;
}

device_initcall(puv3_irq_init_syscore);

void __init init_IRQ(void)
{
	unsigned int irq;

	request_resource(&iomem_resource, &irq_resource);

	/* disable all IRQs */
	writel(0, INTC_ICMR);

	/* all IRQs are IRQ, not REAL */
	writel(0, INTC_ICLR);

	/* clear all GPIO edge detects */
	writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR);
	writel(0, GPIO_GFER);
	writel(0, GPIO_GRER);
	writel(0x0FFFFFFF, GPIO_GEDR);

	writel(1, INTC_ICCR);

	for (irq = 0; irq < IRQ_GPIOHIGH; irq++) {
		irq_set_chip(irq, &puv3_low_gpio_chip);
		irq_set_handler(irq, handle_edge_irq);
		irq_modify_status(irq,
			IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
			0);
	}

	for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) {
		irq_set_chip(irq, &puv3_normal_chip);
		irq_set_handler(irq, handle_level_irq);
		irq_modify_status(irq,
			IRQ_NOREQUEST | IRQ_NOAUTOEN,
			IRQ_NOPROBE);
	}

	for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) {
		irq_set_chip(irq, &puv3_high_gpio_chip);
		irq_set_handler(irq, handle_edge_irq);
		irq_modify_status(irq,
			IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
			0);
	}

	/*
	 * Install handler for GPIO 0-27 edge detect interrupts
	 */
	irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
	irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);

#ifdef CONFIG_PUV3_GPIO
	puv3_init_gpio();
#endif
}

/*
 * do_IRQ handles all hardware IRQ's.  Decoded IRQs should not
 * come via this function.  Instead, they should provide their
 * own 'handler'
 */
asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
{
	struct pt_regs *old_regs = set_irq_regs(regs);

	irq_enter();

	/*
	 * Some hardware gives randomly wrong interrupts.  Rather
	 * than crashing, do something sensible.
	 */
	if (unlikely(irq >= nr_irqs)) {
		if (printk_ratelimit())
			printk(KERN_WARNING "Bad IRQ%u\n", irq);
		ack_bad_irq(irq);
	} else {
		generic_handle_irq(irq);
	}

	irq_exit();
	set_irq_regs(old_regs);
}
Commit	Line	Data
752bcb4d G	1	/*
	2	* linux/arch/unicore32/kernel/irq.c
	3	*
	4	* Code specific to PKUnity SoC and UniCore ISA
	5	*
	6	* Copyright (C) 2001-2010 GUAN Xue-tao
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <linux/kernel_stat.h>
	13	#include <linux/module.h>
	14	#include <linux/signal.h>
	15	#include <linux/ioport.h>
	16	#include <linux/interrupt.h>
	17	#include <linux/irq.h>
	18	#include <linux/random.h>
	19	#include <linux/smp.h>
	20	#include <linux/init.h>
	21	#include <linux/seq_file.h>
	22	#include <linux/errno.h>
	23	#include <linux/list.h>
	24	#include <linux/kallsyms.h>
	25	#include <linux/proc_fs.h>
f98bf4aa	26	#include <linux/syscore_ops.h>
752bcb4d G	27	#include <linux/gpio.h>
752bcb4d G	28
752bcb4d G	29	#include <mach/hardware.h>
	30
	31	#include "setup.h"
	32
	33	/*
	34	* PKUnity GPIO edge detection for IRQs:
	35	* IRQs are generated on Falling-Edge, Rising-Edge, or both.
	36	* Use this instead of directly setting GRER/GFER.
	37	*/
	38	static int GPIO_IRQ_rising_edge;
	39	static int GPIO_IRQ_falling_edge;
	40	static int GPIO_IRQ_mask = 0;
	41
	42	#define GPIO_MASK(irq) (1 << (irq - IRQ_GPIO0))
	43
36a8b8c3	44	static int puv3_gpio_type(struct irq_data *d, unsigned int type)
752bcb4d G	45	{
	46	unsigned int mask;
	47
36a8b8c3 G	48	if (d->irq < IRQ_GPIOHIGH)
36a8b8c3 G	49	mask = 1 << d->irq;
752bcb4d	50	else
36a8b8c3	51	mask = GPIO_MASK(d->irq);
752bcb4d G	52
	53	if (type == IRQ_TYPE_PROBE) {
	54	if ((GPIO_IRQ_rising_edge \| GPIO_IRQ_falling_edge) & mask)
	55	return 0;
	56	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
	57	}
	58
	59	if (type & IRQ_TYPE_EDGE_RISING)
	60	GPIO_IRQ_rising_edge \|= mask;
	61	else
	62	GPIO_IRQ_rising_edge &= ~mask;
	63	if (type & IRQ_TYPE_EDGE_FALLING)
	64	GPIO_IRQ_falling_edge \|= mask;
	65	else
	66	GPIO_IRQ_falling_edge &= ~mask;
	67
e5abf78b G	68	writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
e5abf78b G	69	writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
752bcb4d G	70
	71	return 0;
	72	}
	73
	74	/*
	75	* GPIO IRQs must be acknowledged. This is for IRQs from 0 to 7.
	76	*/
36a8b8c3	77	static void puv3_low_gpio_ack(struct irq_data *d)
752bcb4d	78	{
e5abf78b	79	writel((1 << d->irq), GPIO_GEDR);
752bcb4d G	80	}
752bcb4d G	81
36a8b8c3	82	static void puv3_low_gpio_mask(struct irq_data *d)
752bcb4d	83	{
e5abf78b	84	writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
752bcb4d G	85	}
752bcb4d G	86
36a8b8c3	87	static void puv3_low_gpio_unmask(struct irq_data *d)
752bcb4d	88	{
e5abf78b	89	writel(readl(INTC_ICMR) \| (1 << d->irq), INTC_ICMR);
752bcb4d G	90	}
752bcb4d G	91
36a8b8c3	92	static int puv3_low_gpio_wake(struct irq_data *d, unsigned int on)
752bcb4d G	93	{
752bcb4d G	94	if (on)
e5abf78b	95	writel(readl(PM_PWER) \| (1 << d->irq), PM_PWER);
752bcb4d	96	else
e5abf78b	97	writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER);
752bcb4d G	98	return 0;
	99	}
	100
	101	static struct irq_chip puv3_low_gpio_chip = {
	102	.name = "GPIO-low",
36a8b8c3 G	103	.irq_ack = puv3_low_gpio_ack,
	104	.irq_mask = puv3_low_gpio_mask,
	105	.irq_unmask = puv3_low_gpio_unmask,
	106	.irq_set_type = puv3_gpio_type,
	107	.irq_set_wake = puv3_low_gpio_wake,
752bcb4d G	108	};
	109
	110	/*
	111	* IRQ8 (GPIO0 through 27) handler. We enter here with the
	112	* irq_controller_lock held, and IRQs disabled. Decode the IRQ
	113	* and call the handler.
	114	*/
	115	static void
	116	puv3_gpio_handler(unsigned int irq, struct irq_desc *desc)
	117	{
	118	unsigned int mask;
	119
e5abf78b	120	mask = readl(GPIO_GEDR);
752bcb4d G	121	do {
	122	/*
	123	* clear down all currently active IRQ sources.
	124	* We will be processing them all.
	125	*/
e5abf78b	126	writel(mask, GPIO_GEDR);
752bcb4d G	127
	128	irq = IRQ_GPIO0;
	129	do {
	130	if (mask & 1)
	131	generic_handle_irq(irq);
	132	mask >>= 1;
	133	irq++;
	134	} while (mask);
e5abf78b	135	mask = readl(GPIO_GEDR);
752bcb4d G	136	} while (mask);
	137	}
	138
	139	/*
	140	* GPIO0-27 edge IRQs need to be handled specially.
	141	* In addition, the IRQs are all collected up into one bit in the
	142	* interrupt controller registers.
	143	*/
36a8b8c3	144	static void puv3_high_gpio_ack(struct irq_data *d)
752bcb4d	145	{
36a8b8c3	146	unsigned int mask = GPIO_MASK(d->irq);
752bcb4d	147
e5abf78b	148	writel(mask, GPIO_GEDR);
752bcb4d G	149	}
752bcb4d G	150
36a8b8c3	151	static void puv3_high_gpio_mask(struct irq_data *d)
752bcb4d	152	{
36a8b8c3	153	unsigned int mask = GPIO_MASK(d->irq);
752bcb4d G	154
	155	GPIO_IRQ_mask &= ~mask;
	156
e5abf78b G	157	writel(readl(GPIO_GRER) & ~mask, GPIO_GRER);
e5abf78b G	158	writel(readl(GPIO_GFER) & ~mask, GPIO_GFER);
752bcb4d G	159	}
752bcb4d G	160
36a8b8c3	161	static void puv3_high_gpio_unmask(struct irq_data *d)
752bcb4d	162	{
36a8b8c3	163	unsigned int mask = GPIO_MASK(d->irq);
752bcb4d G	164
	165	GPIO_IRQ_mask \|= mask;
	166
e5abf78b G	167	writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
e5abf78b G	168	writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
752bcb4d G	169	}
752bcb4d G	170
36a8b8c3	171	static int puv3_high_gpio_wake(struct irq_data *d, unsigned int on)
752bcb4d G	172	{
752bcb4d G	173	if (on)
e5abf78b	174	writel(readl(PM_PWER) \| PM_PWER_GPIOHIGH, PM_PWER);
752bcb4d	175	else
e5abf78b	176	writel(readl(PM_PWER) & ~PM_PWER_GPIOHIGH, PM_PWER);
752bcb4d G	177	return 0;
	178	}
	179
	180	static struct irq_chip puv3_high_gpio_chip = {
	181	.name = "GPIO-high",
36a8b8c3 G	182	.irq_ack = puv3_high_gpio_ack,
	183	.irq_mask = puv3_high_gpio_mask,
	184	.irq_unmask = puv3_high_gpio_unmask,
	185	.irq_set_type = puv3_gpio_type,
	186	.irq_set_wake = puv3_high_gpio_wake,
752bcb4d G	187	};
	188
	189	/*
	190	* We don't need to ACK IRQs on the PKUnity unless they're GPIOs
	191	* this is for internal IRQs i.e. from 8 to 31.
	192	*/
36a8b8c3	193	static void puv3_mask_irq(struct irq_data *d)
752bcb4d	194	{
e5abf78b	195	writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR);
752bcb4d G	196	}
752bcb4d G	197
36a8b8c3	198	static void puv3_unmask_irq(struct irq_data *d)
752bcb4d	199	{
e5abf78b	200	writel(readl(INTC_ICMR) \| (1 << d->irq), INTC_ICMR);
752bcb4d G	201	}
	202
	203	/*
	204	* Apart form GPIOs, only the RTC alarm can be a wakeup event.
	205	*/
36a8b8c3	206	static int puv3_set_wake(struct irq_data *d, unsigned int on)
752bcb4d	207	{
36a8b8c3	208	if (d->irq == IRQ_RTCAlarm) {
752bcb4d	209	if (on)
e5abf78b	210	writel(readl(PM_PWER) \| PM_PWER_RTC, PM_PWER);
752bcb4d	211	else
e5abf78b	212	writel(readl(PM_PWER) & ~PM_PWER_RTC, PM_PWER);
752bcb4d G	213	return 0;
	214	}
	215	return -EINVAL;
	216	}
	217
	218	static struct irq_chip puv3_normal_chip = {
	219	.name = "PKUnity-v3",
36a8b8c3 G	220	.irq_ack = puv3_mask_irq,
	221	.irq_mask = puv3_mask_irq,
	222	.irq_unmask = puv3_unmask_irq,
	223	.irq_set_wake = puv3_set_wake,
752bcb4d G	224	};
	225
	226	static struct resource irq_resource = {
	227	.name = "irqs",
1cf46c42 G	228	.start = io_v2p(PKUNITY_INTC_BASE),
1cf46c42 G	229	.end = io_v2p(PKUNITY_INTC_BASE) + 0xFFFFF,
752bcb4d G	230	};
	231
	232	static struct puv3_irq_state {
	233	unsigned int saved;
	234	unsigned int icmr;
	235	unsigned int iclr;
	236	unsigned int iccr;
	237	} puv3_irq_state;
	238
f98bf4aa	239	static int puv3_irq_suspend(void)
752bcb4d G	240	{
	241	struct puv3_irq_state *st = &puv3_irq_state;
	242
	243	st->saved = 1;
e5abf78b G	244	st->icmr = readl(INTC_ICMR);
	245	st->iclr = readl(INTC_ICLR);
	246	st->iccr = readl(INTC_ICCR);
752bcb4d G	247
	248	/*
	249	* Disable all GPIO-based interrupts.
	250	*/
e5abf78b	251	writel(readl(INTC_ICMR) & ~(0x1ff), INTC_ICMR);
752bcb4d G	252
	253	/*
	254	* Set the appropriate edges for wakeup.
	255	*/
e5abf78b G	256	writel(readl(PM_PWER) & GPIO_IRQ_rising_edge, GPIO_GRER);
e5abf78b G	257	writel(readl(PM_PWER) & GPIO_IRQ_falling_edge, GPIO_GFER);
752bcb4d G	258
	259	/*
	260	* Clear any pending GPIO interrupts.
	261	*/
e5abf78b	262	writel(readl(GPIO_GEDR), GPIO_GEDR);
752bcb4d G	263
	264	return 0;
	265	}
	266
f98bf4aa	267	static void puv3_irq_resume(void)
752bcb4d G	268	{
	269	struct puv3_irq_state *st = &puv3_irq_state;
	270
	271	if (st->saved) {
e5abf78b G	272	writel(st->iccr, INTC_ICCR);
e5abf78b G	273	writel(st->iclr, INTC_ICLR);
752bcb4d	274
e5abf78b G	275	writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER);
e5abf78b G	276	writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER);
752bcb4d	277
e5abf78b	278	writel(st->icmr, INTC_ICMR);
752bcb4d	279	}
752bcb4d G	280	}
752bcb4d G	281
f98bf4aa	282	static struct syscore_ops puv3_irq_syscore_ops = {
752bcb4d G	283	.suspend = puv3_irq_suspend,
	284	.resume = puv3_irq_resume,
	285	};
	286
f98bf4aa	287	static int __init puv3_irq_init_syscore(void)
752bcb4d	288	{
f98bf4aa RW	289	register_syscore_ops(&puv3_irq_syscore_ops);
f98bf4aa RW	290	return 0;
752bcb4d G	291	}
752bcb4d G	292
f98bf4aa	293	device_initcall(puv3_irq_init_syscore);
752bcb4d G	294
	295	void __init init_IRQ(void)
	296	{
	297	unsigned int irq;
	298
	299	request_resource(&iomem_resource, &irq_resource);
	300
	301	/* disable all IRQs */
e5abf78b	302	writel(0, INTC_ICMR);
752bcb4d G	303
752bcb4d G	304	/* all IRQs are IRQ, not REAL */
e5abf78b	305	writel(0, INTC_ICLR);
752bcb4d G	306
752bcb4d G	307	/* clear all GPIO edge detects */
e5abf78b G	308	writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR);
	309	writel(0, GPIO_GFER);
	310	writel(0, GPIO_GRER);
	311	writel(0x0FFFFFFF, GPIO_GEDR);
752bcb4d	312
e5abf78b	313	writel(1, INTC_ICCR);
752bcb4d G	314
752bcb4d G	315	for (irq = 0; irq < IRQ_GPIOHIGH; irq++) {
e1f5ce81 TG	316	irq_set_chip(irq, &puv3_low_gpio_chip);
e1f5ce81 TG	317	irq_set_handler(irq, handle_edge_irq);
752bcb4d G	318	irq_modify_status(irq,
	319	IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN,
	320	0);
	321	}
	322
	323	for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) {
e1f5ce81 TG	324	irq_set_chip(irq, &puv3_normal_chip);
e1f5ce81 TG	325	irq_set_handler(irq, handle_level_irq);
752bcb4d G	326	irq_modify_status(irq,
	327	IRQ_NOREQUEST \| IRQ_NOAUTOEN,
	328	IRQ_NOPROBE);
	329	}
	330
	331	for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) {
e1f5ce81 TG	332	irq_set_chip(irq, &puv3_high_gpio_chip);
e1f5ce81 TG	333	irq_set_handler(irq, handle_edge_irq);
752bcb4d G	334	irq_modify_status(irq,
	335	IRQ_NOREQUEST \| IRQ_NOPROBE \| IRQ_NOAUTOEN,
	336	0);
	337	}
	338
	339	/*
	340	* Install handler for GPIO 0-27 edge detect interrupts
	341	*/
e1f5ce81 TG	342	irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
e1f5ce81 TG	343	irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);
752bcb4d G	344
	345	#ifdef CONFIG_PUV3_GPIO
	346	puv3_init_gpio();
	347	#endif
	348	}
	349
752bcb4d G	350	/*
	351	* do_IRQ handles all hardware IRQ's. Decoded IRQs should not
	352	* come via this function. Instead, they should provide their
	353	* own 'handler'
	354	*/
	355	asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
	356	{
	357	struct pt_regs *old_regs = set_irq_regs(regs);
	358
	359	irq_enter();
	360
	361	/*
	362	* Some hardware gives randomly wrong interrupts. Rather
	363	* than crashing, do something sensible.
	364	*/
	365	if (unlikely(irq >= nr_irqs)) {
	366	if (printk_ratelimit())
	367	printk(KERN_WARNING "Bad IRQ%u\n", irq);
	368	ack_bad_irq(irq);
	369	} else {
	370	generic_handle_irq(irq);
	371	}
	372
	373	irq_exit();
	374	set_irq_regs(old_regs);
	375	}
	376