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1da177e4 LT |
1 | /* |
2 | * This file contains miscellaneous low-level functions. | |
3 | * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org) | |
4 | * | |
5 | * Largely rewritten by Cort Dougan (cort@cs.nmt.edu) | |
6 | * and Paul Mackerras. | |
7 | * | |
8 | * A couple of functions stolen from arch/ppc/kernel/misc.S for UML | |
9 | * by Chris Emerson. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License | |
13 | * as published by the Free Software Foundation; either version | |
14 | * 2 of the License, or (at your option) any later version. | |
15 | * | |
16 | */ | |
17 | ||
1da177e4 LT |
18 | #include <asm/processor.h> |
19 | #include "ppc_asm.h" | |
20 | ||
21 | #if defined(CONFIG_4xx) || defined(CONFIG_8xx) | |
22 | #define CACHE_LINE_SIZE 16 | |
23 | #define LG_CACHE_LINE_SIZE 4 | |
24 | #define MAX_COPY_PREFETCH 1 | |
227318bb | 25 | #else |
1da177e4 LT |
26 | #define CACHE_LINE_SIZE 32 |
27 | #define LG_CACHE_LINE_SIZE 5 | |
28 | #define MAX_COPY_PREFETCH 4 | |
1da177e4 LT |
29 | #endif /* CONFIG_4xx || CONFIG_8xx */ |
30 | ||
31 | .text | |
32 | ||
33 | /* | |
34 | * Clear a page using the dcbz instruction, which doesn't cause any | |
35 | * memory traffic (except to write out any cache lines which get | |
36 | * displaced). This only works on cacheable memory. | |
37 | */ | |
38 | _GLOBAL(clear_page) | |
39 | li r0,4096/CACHE_LINE_SIZE | |
40 | mtctr r0 | |
41 | #ifdef CONFIG_8xx | |
42 | li r4, 0 | |
43 | 1: stw r4, 0(r3) | |
44 | stw r4, 4(r3) | |
45 | stw r4, 8(r3) | |
46 | stw r4, 12(r3) | |
47 | #else | |
48 | 1: dcbz 0,r3 | |
49 | #endif | |
50 | addi r3,r3,CACHE_LINE_SIZE | |
51 | bdnz 1b | |
52 | blr | |
53 | ||
54 | /* | |
55 | * Copy a whole page. We use the dcbz instruction on the destination | |
56 | * to reduce memory traffic (it eliminates the unnecessary reads of | |
57 | * the destination into cache). This requires that the destination | |
58 | * is cacheable. | |
59 | */ | |
60 | #define COPY_16_BYTES \ | |
61 | lwz r6,4(r4); \ | |
62 | lwz r7,8(r4); \ | |
63 | lwz r8,12(r4); \ | |
64 | lwzu r9,16(r4); \ | |
65 | stw r6,4(r3); \ | |
66 | stw r7,8(r3); \ | |
67 | stw r8,12(r3); \ | |
68 | stwu r9,16(r3) | |
69 | ||
70 | _GLOBAL(copy_page) | |
71 | addi r3,r3,-4 | |
72 | addi r4,r4,-4 | |
73 | li r5,4 | |
74 | ||
75 | #ifndef CONFIG_8xx | |
76 | #if MAX_COPY_PREFETCH > 1 | |
77 | li r0,MAX_COPY_PREFETCH | |
78 | li r11,4 | |
79 | mtctr r0 | |
80 | 11: dcbt r11,r4 | |
81 | addi r11,r11,CACHE_LINE_SIZE | |
82 | bdnz 11b | |
83 | #else /* MAX_COPY_PREFETCH == 1 */ | |
84 | dcbt r5,r4 | |
85 | li r11,CACHE_LINE_SIZE+4 | |
86 | #endif /* MAX_COPY_PREFETCH */ | |
87 | #endif /* CONFIG_8xx */ | |
88 | ||
89 | li r0,4096/CACHE_LINE_SIZE | |
90 | mtctr r0 | |
91 | 1: | |
92 | #ifndef CONFIG_8xx | |
93 | dcbt r11,r4 | |
94 | dcbz r5,r3 | |
95 | #endif | |
96 | COPY_16_BYTES | |
97 | #if CACHE_LINE_SIZE >= 32 | |
98 | COPY_16_BYTES | |
99 | #if CACHE_LINE_SIZE >= 64 | |
100 | COPY_16_BYTES | |
101 | COPY_16_BYTES | |
102 | #if CACHE_LINE_SIZE >= 128 | |
103 | COPY_16_BYTES | |
104 | COPY_16_BYTES | |
105 | COPY_16_BYTES | |
106 | COPY_16_BYTES | |
107 | #endif | |
108 | #endif | |
109 | #endif | |
110 | bdnz 1b | |
111 | blr |