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f02cbbe6 | 1 | /* |
398fa5a9 | 2 | * Copyright 2011 Tilera Corporation. All Rights Reserved. |
f02cbbe6 CM |
3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * as published by the Free Software Foundation, version 2. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, but | |
9 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
11 | * NON INFRINGEMENT. See the GNU General Public License for | |
12 | * more details. | |
13 | */ | |
14 | ||
15 | #include <linux/kernel.h> | |
16 | #include <linux/pci.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/string.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/capability.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/bootmem.h> | |
24 | #include <linux/irq.h> | |
25 | #include <linux/io.h> | |
26 | #include <linux/uaccess.h> | |
3989efb7 | 27 | #include <linux/export.h> |
f02cbbe6 CM |
28 | |
29 | #include <asm/processor.h> | |
30 | #include <asm/sections.h> | |
31 | #include <asm/byteorder.h> | |
32 | #include <asm/hv_driver.h> | |
33 | #include <hv/drv_pcie_rc_intf.h> | |
34 | ||
35 | ||
36 | /* | |
37 | * Initialization flow and process | |
38 | * ------------------------------- | |
39 | * | |
25985edc | 40 | * This files contains the routines to search for PCI buses, |
f02cbbe6 CM |
41 | * enumerate the buses, and configure any attached devices. |
42 | * | |
43 | * There are two entry points here: | |
44 | * 1) tile_pci_init | |
45 | * This sets up the pci_controller structs, and opens the | |
46 | * FDs to the hypervisor. This is called from setup_arch() early | |
47 | * in the boot process. | |
48 | * 2) pcibios_init | |
49 | * This probes the PCI bus(es) for any attached hardware. It's | |
50 | * called by subsys_initcall. All of the real work is done by the | |
51 | * generic Linux PCI layer. | |
52 | * | |
53 | */ | |
54 | ||
55 | /* | |
56 | * This flag tells if the platform is TILEmpower that needs | |
57 | * special configuration for the PLX switch chip. | |
58 | */ | |
59 | int __write_once tile_plx_gen1; | |
60 | ||
61 | static struct pci_controller controllers[TILE_NUM_PCIE]; | |
62 | static int num_controllers; | |
398fa5a9 | 63 | static int pci_scan_flags[TILE_NUM_PCIE]; |
f02cbbe6 CM |
64 | |
65 | static struct pci_ops tile_cfg_ops; | |
66 | ||
67 | ||
68 | /* | |
69 | * We don't need to worry about the alignment of resources. | |
70 | */ | |
71 | resource_size_t pcibios_align_resource(void *data, const struct resource *res, | |
72 | resource_size_t size, resource_size_t align) | |
73 | { | |
74 | return res->start; | |
75 | } | |
76 | EXPORT_SYMBOL(pcibios_align_resource); | |
77 | ||
78 | /* | |
79 | * Open a FD to the hypervisor PCI device. | |
80 | * | |
81 | * controller_id is the controller number, config type is 0 or 1 for | |
82 | * config0 or config1 operations. | |
83 | */ | |
398fa5a9 | 84 | static int __devinit tile_pcie_open(int controller_id, int config_type) |
f02cbbe6 CM |
85 | { |
86 | char filename[32]; | |
87 | int fd; | |
88 | ||
89 | sprintf(filename, "pcie/%d/config%d", controller_id, config_type); | |
90 | ||
91 | fd = hv_dev_open((HV_VirtAddr)filename, 0); | |
92 | ||
93 | return fd; | |
94 | } | |
95 | ||
96 | ||
97 | /* | |
98 | * Get the IRQ numbers from the HV and set up the handlers for them. | |
99 | */ | |
398fa5a9 | 100 | static int __devinit tile_init_irqs(int controller_id, |
f02cbbe6 CM |
101 | struct pci_controller *controller) |
102 | { | |
103 | char filename[32]; | |
104 | int fd; | |
105 | int ret; | |
106 | int x; | |
107 | struct pcie_rc_config rc_config; | |
108 | ||
109 | sprintf(filename, "pcie/%d/ctl", controller_id); | |
110 | fd = hv_dev_open((HV_VirtAddr)filename, 0); | |
111 | if (fd < 0) { | |
112 | pr_err("PCI: hv_dev_open(%s) failed\n", filename); | |
113 | return -1; | |
114 | } | |
115 | ret = hv_dev_pread(fd, 0, (HV_VirtAddr)(&rc_config), | |
116 | sizeof(rc_config), PCIE_RC_CONFIG_MASK_OFF); | |
117 | hv_dev_close(fd); | |
118 | if (ret != sizeof(rc_config)) { | |
119 | pr_err("PCI: wanted %zd bytes, got %d\n", | |
120 | sizeof(rc_config), ret); | |
121 | return -1; | |
122 | } | |
123 | /* Record irq_base so that we can map INTx to IRQ # later. */ | |
124 | controller->irq_base = rc_config.intr; | |
125 | ||
126 | for (x = 0; x < 4; x++) | |
127 | tile_irq_activate(rc_config.intr + x, | |
128 | TILE_IRQ_HW_CLEAR); | |
129 | ||
130 | if (rc_config.plx_gen1) | |
131 | controller->plx_gen1 = 1; | |
132 | ||
133 | return 0; | |
134 | } | |
135 | ||
136 | /* | |
137 | * First initialization entry point, called from setup_arch(). | |
138 | * | |
139 | * Find valid controllers and fill in pci_controller structs for each | |
140 | * of them. | |
141 | * | |
142 | * Returns the number of controllers discovered. | |
143 | */ | |
05ef1b79 | 144 | int __init tile_pci_init(void) |
f02cbbe6 CM |
145 | { |
146 | int i; | |
147 | ||
148 | pr_info("PCI: Searching for controllers...\n"); | |
149 | ||
398fa5a9 CM |
150 | /* Re-init number of PCIe controllers to support hot-plug feature. */ |
151 | num_controllers = 0; | |
152 | ||
f02cbbe6 CM |
153 | /* Do any configuration we need before using the PCIe */ |
154 | ||
155 | for (i = 0; i < TILE_NUM_PCIE; i++) { | |
f02cbbe6 | 156 | /* |
398fa5a9 CM |
157 | * To see whether we need a real config op based on |
158 | * the results of pcibios_init(), to support PCIe hot-plug. | |
f02cbbe6 | 159 | */ |
398fa5a9 CM |
160 | if (pci_scan_flags[i] == 0) { |
161 | int hv_cfg_fd0 = -1; | |
162 | int hv_cfg_fd1 = -1; | |
163 | int hv_mem_fd = -1; | |
164 | char name[32]; | |
165 | struct pci_controller *controller; | |
166 | ||
167 | /* | |
168 | * Open the fd to the HV. If it fails then this | |
169 | * device doesn't exist. | |
170 | */ | |
171 | hv_cfg_fd0 = tile_pcie_open(i, 0); | |
172 | if (hv_cfg_fd0 < 0) | |
173 | continue; | |
174 | hv_cfg_fd1 = tile_pcie_open(i, 1); | |
175 | if (hv_cfg_fd1 < 0) { | |
176 | pr_err("PCI: Couldn't open config fd to HV " | |
177 | "for controller %d\n", i); | |
178 | goto err_cont; | |
179 | } | |
f02cbbe6 | 180 | |
398fa5a9 CM |
181 | sprintf(name, "pcie/%d/mem", i); |
182 | hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0); | |
183 | if (hv_mem_fd < 0) { | |
184 | pr_err("PCI: Could not open mem fd to HV!\n"); | |
185 | goto err_cont; | |
186 | } | |
f02cbbe6 | 187 | |
398fa5a9 | 188 | pr_info("PCI: Found PCI controller #%d\n", i); |
f02cbbe6 | 189 | |
398fa5a9 | 190 | controller = &controllers[i]; |
f02cbbe6 | 191 | |
398fa5a9 CM |
192 | controller->index = i; |
193 | controller->hv_cfg_fd[0] = hv_cfg_fd0; | |
194 | controller->hv_cfg_fd[1] = hv_cfg_fd1; | |
195 | controller->hv_mem_fd = hv_mem_fd; | |
196 | controller->first_busno = 0; | |
197 | controller->last_busno = 0xff; | |
198 | controller->ops = &tile_cfg_ops; | |
f02cbbe6 | 199 | |
398fa5a9 CM |
200 | num_controllers++; |
201 | continue; | |
f02cbbe6 CM |
202 | |
203 | err_cont: | |
398fa5a9 CM |
204 | if (hv_cfg_fd0 >= 0) |
205 | hv_dev_close(hv_cfg_fd0); | |
206 | if (hv_cfg_fd1 >= 0) | |
207 | hv_dev_close(hv_cfg_fd1); | |
208 | if (hv_mem_fd >= 0) | |
209 | hv_dev_close(hv_mem_fd); | |
210 | continue; | |
211 | } | |
f02cbbe6 CM |
212 | } |
213 | ||
214 | /* | |
215 | * Before using the PCIe, see if we need to do any platform-specific | |
216 | * configuration, such as the PLX switch Gen 1 issue on TILEmpower. | |
217 | */ | |
218 | for (i = 0; i < num_controllers; i++) { | |
219 | struct pci_controller *controller = &controllers[i]; | |
220 | ||
221 | if (controller->plx_gen1) | |
222 | tile_plx_gen1 = 1; | |
223 | } | |
224 | ||
225 | return num_controllers; | |
226 | } | |
227 | ||
228 | /* | |
229 | * (pin - 1) converts from the PCI standard's [1:4] convention to | |
230 | * a normal [0:3] range. | |
231 | */ | |
d5341942 | 232 | static int tile_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
f02cbbe6 CM |
233 | { |
234 | struct pci_controller *controller = | |
235 | (struct pci_controller *)dev->sysdata; | |
236 | return (pin - 1) + controller->irq_base; | |
237 | } | |
238 | ||
239 | ||
398fa5a9 | 240 | static void __devinit fixup_read_and_payload_sizes(void) |
f02cbbe6 CM |
241 | { |
242 | struct pci_dev *dev = NULL; | |
243 | int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */ | |
244 | int max_read_size = 0x2; /* Limit to 512 byte reads. */ | |
245 | u16 new_values; | |
246 | ||
247 | /* Scan for the smallest maximum payload size. */ | |
248 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
249 | int pcie_caps_offset; | |
250 | u32 devcap; | |
251 | int max_payload; | |
252 | ||
253 | pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
254 | if (pcie_caps_offset == 0) | |
255 | continue; | |
256 | ||
257 | pci_read_config_dword(dev, pcie_caps_offset + PCI_EXP_DEVCAP, | |
258 | &devcap); | |
259 | max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD; | |
260 | if (max_payload < smallest_max_payload) | |
261 | smallest_max_payload = max_payload; | |
262 | } | |
263 | ||
264 | /* Now, set the max_payload_size for all devices to that value. */ | |
265 | new_values = (max_read_size << 12) | (smallest_max_payload << 5); | |
266 | while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { | |
267 | int pcie_caps_offset; | |
268 | u16 devctl; | |
269 | ||
270 | pcie_caps_offset = pci_find_capability(dev, PCI_CAP_ID_EXP); | |
271 | if (pcie_caps_offset == 0) | |
272 | continue; | |
273 | ||
274 | pci_read_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL, | |
275 | &devctl); | |
276 | devctl &= ~(PCI_EXP_DEVCTL_PAYLOAD | PCI_EXP_DEVCTL_READRQ); | |
277 | devctl |= new_values; | |
278 | pci_write_config_word(dev, pcie_caps_offset + PCI_EXP_DEVCTL, | |
279 | devctl); | |
280 | } | |
281 | } | |
282 | ||
283 | ||
284 | /* | |
285 | * Second PCI initialization entry point, called by subsys_initcall. | |
286 | * | |
287 | * The controllers have been set up by the time we get here, by a call to | |
288 | * tile_pci_init. | |
289 | */ | |
05ef1b79 | 290 | int __init pcibios_init(void) |
f02cbbe6 CM |
291 | { |
292 | int i; | |
293 | ||
294 | pr_info("PCI: Probing PCI hardware\n"); | |
295 | ||
296 | /* | |
297 | * Delay a bit in case devices aren't ready. Some devices are | |
298 | * known to require at least 20ms here, but we use a more | |
299 | * conservative value. | |
300 | */ | |
301 | mdelay(250); | |
302 | ||
303 | /* Scan all of the recorded PCI controllers. */ | |
398fa5a9 | 304 | for (i = 0; i < TILE_NUM_PCIE; i++) { |
f02cbbe6 | 305 | /* |
398fa5a9 CM |
306 | * Do real pcibios init ops if the controller is initialized |
307 | * by tile_pci_init() successfully and not initialized by | |
308 | * pcibios_init() yet to support PCIe hot-plug. | |
f02cbbe6 | 309 | */ |
398fa5a9 CM |
310 | if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) { |
311 | struct pci_controller *controller = &controllers[i]; | |
312 | struct pci_bus *bus; | |
313 | ||
f4de51de CM |
314 | if (tile_init_irqs(i, controller)) { |
315 | pr_err("PCI: Could not initialize IRQs\n"); | |
316 | continue; | |
317 | } | |
318 | ||
398fa5a9 CM |
319 | pr_info("PCI: initializing controller #%d\n", i); |
320 | ||
321 | /* | |
322 | * This comes from the generic Linux PCI driver. | |
323 | * | |
324 | * It reads the PCI tree for this bus into the Linux | |
325 | * data structures. | |
326 | * | |
327 | * This is inlined in linux/pci.h and calls into | |
328 | * pci_scan_bus_parented() in probe.c. | |
329 | */ | |
330 | bus = pci_scan_bus(0, controller->ops, controller); | |
331 | controller->root_bus = bus; | |
b918c62e | 332 | controller->last_busno = bus->busn_res.end; |
398fa5a9 | 333 | } |
f02cbbe6 CM |
334 | } |
335 | ||
336 | /* Do machine dependent PCI interrupt routing */ | |
337 | pci_fixup_irqs(pci_common_swizzle, tile_map_irq); | |
338 | ||
339 | /* | |
340 | * This comes from the generic Linux PCI driver. | |
341 | * | |
342 | * It allocates all of the resources (I/O memory, etc) | |
343 | * associated with the devices read in above. | |
344 | */ | |
f02cbbe6 CM |
345 | pci_assign_unassigned_resources(); |
346 | ||
347 | /* Configure the max_read_size and max_payload_size values. */ | |
348 | fixup_read_and_payload_sizes(); | |
349 | ||
350 | /* Record the I/O resources in the PCI controller structure. */ | |
398fa5a9 CM |
351 | for (i = 0; i < TILE_NUM_PCIE; i++) { |
352 | /* | |
353 | * Do real pcibios init ops if the controller is initialized | |
354 | * by tile_pci_init() successfully and not initialized by | |
355 | * pcibios_init() yet to support PCIe hot-plug. | |
356 | */ | |
357 | if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) { | |
358 | struct pci_bus *root_bus = controllers[i].root_bus; | |
359 | struct pci_bus *next_bus; | |
360 | struct pci_dev *dev; | |
361 | ||
362 | list_for_each_entry(dev, &root_bus->devices, bus_list) { | |
363 | /* | |
364 | * Find the PCI host controller, ie. the 1st | |
365 | * bridge. | |
366 | */ | |
367 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && | |
368 | (PCI_SLOT(dev->devfn) == 0)) { | |
b918c62e | 369 | next_bus = dev->busn_res.end; |
398fa5a9 CM |
370 | controllers[i].mem_resources[0] = |
371 | *next_bus->resource[0]; | |
372 | controllers[i].mem_resources[1] = | |
373 | *next_bus->resource[1]; | |
374 | controllers[i].mem_resources[2] = | |
375 | *next_bus->resource[2]; | |
376 | ||
377 | /* Setup flags. */ | |
378 | pci_scan_flags[i] = 1; | |
379 | ||
380 | break; | |
381 | } | |
f02cbbe6 CM |
382 | } |
383 | } | |
f02cbbe6 CM |
384 | } |
385 | ||
386 | return 0; | |
387 | } | |
388 | subsys_initcall(pcibios_init); | |
389 | ||
390 | /* | |
391 | * No bus fixups needed. | |
392 | */ | |
393 | void __devinit pcibios_fixup_bus(struct pci_bus *bus) | |
394 | { | |
395 | /* Nothing needs to be done. */ | |
396 | } | |
397 | ||
cf1c5230 MS |
398 | void pcibios_set_master(struct pci_dev *dev) |
399 | { | |
400 | /* No special bus mastering setup handling. */ | |
401 | } | |
402 | ||
f02cbbe6 CM |
403 | /* |
404 | * This can be called from the generic PCI layer, but doesn't need to | |
405 | * do anything. | |
406 | */ | |
407 | char __devinit *pcibios_setup(char *str) | |
408 | { | |
409 | /* Nothing needs to be done. */ | |
410 | return str; | |
411 | } | |
412 | ||
413 | /* | |
414 | * This is called from the generic Linux layer. | |
415 | */ | |
398fa5a9 | 416 | void __devinit pcibios_update_irq(struct pci_dev *dev, int irq) |
f02cbbe6 CM |
417 | { |
418 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); | |
419 | } | |
420 | ||
421 | /* | |
422 | * Enable memory and/or address decoding, as appropriate, for the | |
423 | * device described by the 'dev' struct. | |
424 | * | |
425 | * This is called from the generic PCI layer, and can be called | |
426 | * for bridges or endpoints. | |
427 | */ | |
428 | int pcibios_enable_device(struct pci_dev *dev, int mask) | |
429 | { | |
430 | u16 cmd, old_cmd; | |
431 | u8 header_type; | |
432 | int i; | |
433 | struct resource *r; | |
434 | ||
435 | pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); | |
436 | ||
437 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
438 | old_cmd = cmd; | |
439 | if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) { | |
440 | /* | |
441 | * For bridges, we enable both memory and I/O decoding | |
442 | * in call cases. | |
443 | */ | |
444 | cmd |= PCI_COMMAND_IO; | |
445 | cmd |= PCI_COMMAND_MEMORY; | |
446 | } else { | |
447 | /* | |
448 | * For endpoints, we enable memory and/or I/O decoding | |
449 | * only if they have a memory resource of that type. | |
450 | */ | |
451 | for (i = 0; i < 6; i++) { | |
452 | r = &dev->resource[i]; | |
453 | if (r->flags & IORESOURCE_UNSET) { | |
454 | pr_err("PCI: Device %s not available " | |
455 | "because of resource collisions\n", | |
456 | pci_name(dev)); | |
457 | return -EINVAL; | |
458 | } | |
459 | if (r->flags & IORESOURCE_IO) | |
460 | cmd |= PCI_COMMAND_IO; | |
461 | if (r->flags & IORESOURCE_MEM) | |
462 | cmd |= PCI_COMMAND_MEMORY; | |
463 | } | |
464 | } | |
465 | ||
466 | /* | |
467 | * We only write the command if it changed. | |
468 | */ | |
469 | if (cmd != old_cmd) | |
470 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
471 | return 0; | |
472 | } | |
473 | ||
f02cbbe6 CM |
474 | /**************************************************************** |
475 | * | |
476 | * Tile PCI config space read/write routines | |
477 | * | |
478 | ****************************************************************/ | |
479 | ||
480 | /* | |
481 | * These are the normal read and write ops | |
482 | * These are expanded with macros from pci_bus_read_config_byte() etc. | |
483 | * | |
484 | * devfn is the combined PCI slot & function. | |
485 | * | |
486 | * offset is in bytes, from the start of config space for the | |
487 | * specified bus & slot. | |
488 | */ | |
489 | ||
490 | static int __devinit tile_cfg_read(struct pci_bus *bus, | |
491 | unsigned int devfn, | |
492 | int offset, | |
493 | int size, | |
494 | u32 *val) | |
495 | { | |
496 | struct pci_controller *controller = bus->sysdata; | |
497 | int busnum = bus->number & 0xff; | |
498 | int slot = (devfn >> 3) & 0x1f; | |
499 | int function = devfn & 0x7; | |
500 | u32 addr; | |
501 | int config_mode = 1; | |
502 | ||
503 | /* | |
504 | * There is no bridge between the Tile and bus 0, so we | |
505 | * use config0 to talk to bus 0. | |
506 | * | |
507 | * If we're talking to a bus other than zero then we | |
508 | * must have found a bridge. | |
509 | */ | |
510 | if (busnum == 0) { | |
511 | /* | |
512 | * We fake an empty slot for (busnum == 0) && (slot > 0), | |
513 | * since there is only one slot on bus 0. | |
514 | */ | |
515 | if (slot) { | |
516 | *val = 0xFFFFFFFF; | |
517 | return 0; | |
518 | } | |
519 | config_mode = 0; | |
520 | } | |
521 | ||
522 | addr = busnum << 20; /* Bus in 27:20 */ | |
523 | addr |= slot << 15; /* Slot (device) in 19:15 */ | |
524 | addr |= function << 12; /* Function is in 14:12 */ | |
525 | addr |= (offset & 0xFFF); /* byte address in 0:11 */ | |
526 | ||
527 | return hv_dev_pread(controller->hv_cfg_fd[config_mode], 0, | |
528 | (HV_VirtAddr)(val), size, addr); | |
529 | } | |
530 | ||
531 | ||
532 | /* | |
25985edc | 533 | * See tile_cfg_read() for relevant comments. |
f02cbbe6 CM |
534 | * Note that "val" is the value to write, not a pointer to that value. |
535 | */ | |
536 | static int __devinit tile_cfg_write(struct pci_bus *bus, | |
537 | unsigned int devfn, | |
538 | int offset, | |
539 | int size, | |
540 | u32 val) | |
541 | { | |
542 | struct pci_controller *controller = bus->sysdata; | |
543 | int busnum = bus->number & 0xff; | |
544 | int slot = (devfn >> 3) & 0x1f; | |
545 | int function = devfn & 0x7; | |
546 | u32 addr; | |
547 | int config_mode = 1; | |
548 | HV_VirtAddr valp = (HV_VirtAddr)&val; | |
549 | ||
550 | /* | |
551 | * For bus 0 slot 0 we use config 0 accesses. | |
552 | */ | |
553 | if (busnum == 0) { | |
554 | /* | |
555 | * We fake an empty slot for (busnum == 0) && (slot > 0), | |
556 | * since there is only one slot on bus 0. | |
557 | */ | |
558 | if (slot) | |
559 | return 0; | |
560 | config_mode = 0; | |
561 | } | |
562 | ||
563 | addr = busnum << 20; /* Bus in 27:20 */ | |
564 | addr |= slot << 15; /* Slot (device) in 19:15 */ | |
565 | addr |= function << 12; /* Function is in 14:12 */ | |
566 | addr |= (offset & 0xFFF); /* byte address in 0:11 */ | |
567 | ||
568 | #ifdef __BIG_ENDIAN | |
569 | /* Point to the correct part of the 32-bit "val". */ | |
570 | valp += 4 - size; | |
571 | #endif | |
572 | ||
573 | return hv_dev_pwrite(controller->hv_cfg_fd[config_mode], 0, | |
574 | valp, size, addr); | |
575 | } | |
576 | ||
577 | ||
578 | static struct pci_ops tile_cfg_ops = { | |
579 | .read = tile_cfg_read, | |
580 | .write = tile_cfg_write, | |
581 | }; | |
582 | ||
583 | ||
584 | /* | |
585 | * In the following, each PCI controller's mem_resources[1] | |
586 | * represents its (non-prefetchable) PCI memory resource. | |
587 | * mem_resources[0] and mem_resources[2] refer to its PCI I/O and | |
588 | * prefetchable PCI memory resources, respectively. | |
589 | * For more details, see pci_setup_bridge() in setup-bus.c. | |
590 | * By comparing the target PCI memory address against the | |
591 | * end address of controller 0, we can determine the controller | |
592 | * that should accept the PCI memory access. | |
593 | */ | |
594 | #define TILE_READ(size, type) \ | |
595 | type _tile_read##size(unsigned long addr) \ | |
596 | { \ | |
597 | type val; \ | |
598 | int idx = 0; \ | |
599 | if (addr > controllers[0].mem_resources[1].end && \ | |
600 | addr > controllers[0].mem_resources[2].end) \ | |
601 | idx = 1; \ | |
602 | if (hv_dev_pread(controllers[idx].hv_mem_fd, 0, \ | |
603 | (HV_VirtAddr)(&val), sizeof(type), addr)) \ | |
604 | pr_err("PCI: read %zd bytes at 0x%lX failed\n", \ | |
605 | sizeof(type), addr); \ | |
606 | return val; \ | |
607 | } \ | |
608 | EXPORT_SYMBOL(_tile_read##size) | |
609 | ||
610 | TILE_READ(b, u8); | |
611 | TILE_READ(w, u16); | |
612 | TILE_READ(l, u32); | |
613 | TILE_READ(q, u64); | |
614 | ||
615 | #define TILE_WRITE(size, type) \ | |
616 | void _tile_write##size(type val, unsigned long addr) \ | |
617 | { \ | |
618 | int idx = 0; \ | |
619 | if (addr > controllers[0].mem_resources[1].end && \ | |
620 | addr > controllers[0].mem_resources[2].end) \ | |
621 | idx = 1; \ | |
622 | if (hv_dev_pwrite(controllers[idx].hv_mem_fd, 0, \ | |
623 | (HV_VirtAddr)(&val), sizeof(type), addr)) \ | |
624 | pr_err("PCI: write %zd bytes at 0x%lX failed\n", \ | |
625 | sizeof(type), addr); \ | |
626 | } \ | |
627 | EXPORT_SYMBOL(_tile_write##size) | |
628 | ||
629 | TILE_WRITE(b, u8); | |
630 | TILE_WRITE(w, u16); | |
631 | TILE_WRITE(l, u32); | |
632 | TILE_WRITE(q, u64); |