[linux-2.6-block.git] / arch / tile / include / asm / processor.h

/*
 * Copyright 2010 Tilera Corporation. All Rights Reserved.
 *
 *   This program is free software; you can redistribute it and/or
 *   modify it under the terms of the GNU General Public License
 *   as published by the Free Software Foundation, version 2.
 *
 *   This program is distributed in the hope that it will be useful, but
 *   WITHOUT ANY WARRANTY; without even the implied warranty of
 *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *   NON INFRINGEMENT.  See the GNU General Public License for
 *   more details.
 */

#ifndef _ASM_TILE_PROCESSOR_H
#define _ASM_TILE_PROCESSOR_H

#include <arch/chip.h>

#ifndef __ASSEMBLY__

/*
 * NOTE: we don't include <linux/ptrace.h> or <linux/percpu.h> as one
 * normally would, due to #include dependencies.
 */
#include <linux/types.h>
#include <asm/ptrace.h>
#include <asm/percpu.h>

#include <arch/spr_def.h>

struct task_struct;
struct thread_struct;

typedef struct {
	unsigned long seg;
} mm_segment_t;

/*
 * Default implementation of macro that returns current
 * instruction pointer ("program counter").
 */
void *current_text_addr(void);

#if CHIP_HAS_TILE_DMA()
/* Capture the state of a suspended DMA. */
struct tile_dma_state {
	int enabled;
	unsigned long src;
	unsigned long dest;
	unsigned long strides;
	unsigned long chunk_size;
	unsigned long src_chunk;
	unsigned long dest_chunk;
	unsigned long byte;
	unsigned long status;
};

/*
 * A mask of the DMA status register for selecting only the 'running'
 * and 'done' bits.
 */
#define DMA_STATUS_MASK \
  (SPR_DMA_STATUS__RUNNING_MASK | SPR_DMA_STATUS__DONE_MASK)
#endif

/*
 * Track asynchronous TLB events (faults and access violations)
 * that occur while we are in kernel mode from DMA or the SN processor.
 */
struct async_tlb {
	short fault_num;         /* original fault number; 0 if none */
	char is_fault;           /* was it a fault (vs an access violation) */
	char is_write;           /* for fault: was it caused by a write? */
	unsigned long address;   /* what address faulted? */
};

#ifdef CONFIG_HARDWALL
struct hardwall_info;
struct hardwall_task {
	/* Which hardwall is this task tied to? (or NULL if none) */
	struct hardwall_info *info;
	/* Chains this task into the list at info->task_head. */
	struct list_head list;
};
#ifdef __tilepro__
#define HARDWALL_TYPES 1   /* udn */
#else
#define HARDWALL_TYPES 3   /* udn, idn, and ipi */
#endif
#endif

struct thread_struct {
	/* kernel stack pointer */
	unsigned long  ksp;
	/* kernel PC */
	unsigned long  pc;
	/* starting user stack pointer (for page migration) */
	unsigned long  usp0;
	/* pid of process that created this one */
	pid_t creator_pid;
#if CHIP_HAS_TILE_DMA()
	/* DMA info for suspended threads (byte == 0 means no DMA state) */
	struct tile_dma_state tile_dma_state;
#endif
	/* User EX_CONTEXT registers */
	unsigned long ex_context[2];
	/* User SYSTEM_SAVE registers */
	unsigned long system_save[4];
	/* User interrupt mask */
	unsigned long long interrupt_mask;
	/* User interrupt-control 0 state */
	unsigned long intctrl_0;
	/* Any other miscellaneous processor state bits */
	unsigned long proc_status;
#if !CHIP_HAS_FIXED_INTVEC_BASE()
	/* Interrupt base for PL0 interrupts */
	unsigned long interrupt_vector_base;
#endif
	/* Tile cache retry fifo high-water mark */
	unsigned long tile_rtf_hwm;
#if CHIP_HAS_DSTREAM_PF()
	/* Data stream prefetch control */
	unsigned long dstream_pf;
#endif
#ifdef CONFIG_HARDWALL
	/* Hardwall information for various resources. */
	struct hardwall_task hardwall[HARDWALL_TYPES];
#endif
#if CHIP_HAS_TILE_DMA()
	/* Async DMA TLB fault information */
	struct async_tlb dma_async_tlb;
#endif
};

#endif /* !__ASSEMBLY__ */

/*
 * Start with "sp" this many bytes below the top of the kernel stack.
 * This allows us to be cache-aware when handling the initial save
 * of the pt_regs value to the stack.
 */
#define STACK_TOP_DELTA 64

/*
 * When entering the kernel via a fault, start with the top of the
 * pt_regs structure this many bytes below the top of the page.
 * This aligns the pt_regs structure optimally for cache-line access.
 */
#ifdef __tilegx__
#define KSTK_PTREGS_GAP  48
#else
#define KSTK_PTREGS_GAP  56
#endif

#ifndef __ASSEMBLY__

#ifdef __tilegx__
#define TASK_SIZE_MAX		(_AC(1, UL) << (MAX_VA_WIDTH - 1))
#else
#define TASK_SIZE_MAX		PAGE_OFFSET
#endif

/* TASK_SIZE and related variables are always checked in "current" context. */
#ifdef CONFIG_COMPAT
#define COMPAT_TASK_SIZE	(1UL << 31)
#define TASK_SIZE		((current_thread_info()->status & TS_COMPAT) ?\
				 COMPAT_TASK_SIZE : TASK_SIZE_MAX)
#else
#define TASK_SIZE		TASK_SIZE_MAX
#endif

#define VDSO_BASE	((unsigned long)current->active_mm->context.vdso_base)
#define VDSO_SYM(x)	(VDSO_BASE + (unsigned long)(x))

#define STACK_TOP		TASK_SIZE

/* STACK_TOP_MAX is used temporarily in execve and should not check COMPAT. */
#define STACK_TOP_MAX		TASK_SIZE_MAX

/*
 * This decides where the kernel will search for a free chunk of vm
 * space during mmap's, if it is using bottom-up mapping.
 */
#define TASK_UNMAPPED_BASE	(PAGE_ALIGN(TASK_SIZE / 3))

#define HAVE_ARCH_PICK_MMAP_LAYOUT

#define INIT_THREAD {                                                   \
	.ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \
	.interrupt_mask = -1ULL                                         \
}

/* Kernel stack top for the task that first boots on this cpu. */
DECLARE_PER_CPU(unsigned long, boot_sp);

/* PC to boot from on this cpu. */
DECLARE_PER_CPU(unsigned long, boot_pc);

/* Do necessary setup to start up a newly executed thread. */
static inline void start_thread(struct pt_regs *regs,
				unsigned long pc, unsigned long usp)
{
	regs->pc = pc;
	regs->sp = usp;
	single_step_execve();
}

/* Free all resources held by a thread. */
static inline void release_thread(struct task_struct *dead_task)
{
	/* Nothing for now */
}

extern void prepare_exit_to_usermode(struct pt_regs *regs, u32 flags);


/*
 * Return saved (kernel) PC of a blocked thread.
 * Only used in a printk() in kernel/sched/core.c, so don't work too hard.
 */
#define thread_saved_pc(t)   ((t)->thread.pc)

unsigned long get_wchan(struct task_struct *p);

/* Return initial ksp value for given task. */
#define task_ksp0(task) \
	((unsigned long)(task)->stack + THREAD_SIZE - STACK_TOP_DELTA)

/* Return some info about the user process TASK. */
#define task_pt_regs(task) \
	((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1)
#define current_pt_regs()                                   \
	((struct pt_regs *)((stack_pointer | (THREAD_SIZE - 1)) - \
			    STACK_TOP_DELTA - (KSTK_PTREGS_GAP - 1)) - 1)
#define task_sp(task)	(task_pt_regs(task)->sp)
#define task_pc(task)	(task_pt_regs(task)->pc)
/* Aliases for pc and sp (used in fs/proc/array.c) */
#define KSTK_EIP(task)	task_pc(task)
#define KSTK_ESP(task)	task_sp(task)

/* Fine-grained unaligned JIT support */
#define GET_UNALIGN_CTL(tsk, adr)	get_unalign_ctl((tsk), (adr))
#define SET_UNALIGN_CTL(tsk, val)	set_unalign_ctl((tsk), (val))

extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);

/* Standard format for printing registers and other word-size data. */
#ifdef __tilegx__
# define REGFMT "0x%016lx"
#else
# define REGFMT "0x%08lx"
#endif

/*
 * Do some slow action (e.g. read a slow SPR).
 * Note that this must also have compiler-barrier semantics since
 * it may be used in a busy loop reading memory.
 */
static inline void cpu_relax(void)
{
	__insn_mfspr(SPR_PASS);
	barrier();
}

#define cpu_relax_lowlatency() cpu_relax()

/* Info on this processor (see fs/proc/cpuinfo.c) */
struct seq_operations;
extern const struct seq_operations cpuinfo_op;

/* Provide information about the chip model. */
extern char chip_model[64];

/* Data on which physical memory controller corresponds to which NUMA node. */
extern int node_controller[];

/* Does the heap allocator return hash-for-home pages by default? */
extern int hash_default;

/* Should kernel stack pages be hash-for-home? */
extern int kstack_hash;

/* Does MAP_ANONYMOUS return hash-for-home pages by default? */
#define uheap_hash hash_default


/* Are we using huge pages in the TLB for kernel data? */
extern int kdata_huge;

/* Support standard Linux prefetching. */
#define ARCH_HAS_PREFETCH
#define prefetch(x) __builtin_prefetch(x)
#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()

/* Bring a value into the L1D, faulting the TLB if necessary. */
#ifdef __tilegx__
#define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x))
#else
#define prefetch_L1(x) __insn_prefetch_L1((void *)(x))
#endif

#else /* __ASSEMBLY__ */

/* Do some slow action (e.g. read a slow SPR). */
#define CPU_RELAX       mfspr zero, SPR_PASS

#endif /* !__ASSEMBLY__ */

/* Assembly code assumes that the PL is in the low bits. */
#if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0
# error Fix assembly assumptions about PL
#endif

/* We sometimes use these macros for EX_CONTEXT_0_1 as well. */
#if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT || \
    SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK || \
    SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT || \
    SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK
# error Fix assumptions that EX1 macros work for both PL0 and PL1
#endif

/* Allow pulling apart and recombining the PL and ICS bits in EX_CONTEXT. */
#define EX1_PL(ex1) \
  (((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
#define EX1_ICS(ex1) \
  (((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
#define PL_ICS_EX1(pl, ics) \
  (((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) | \
   ((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))

/*
 * Provide symbolic constants for PLs.
 */
#define USER_PL 0
#if CONFIG_KERNEL_PL == 2
#define GUEST_PL 1
#endif
#define KERNEL_PL CONFIG_KERNEL_PL

/* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */
#ifdef __tilegx__
#define CPU_SHIFT 48
#if CHIP_VA_WIDTH() > CPU_SHIFT
# error Too many VA bits!
#endif
#define MAX_CPU_ID ((1 << (64 - CPU_SHIFT)) - 1)
#define raw_smp_processor_id() \
	((int)(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) >> CPU_SHIFT))
#define get_current_ksp0() \
	((unsigned long)(((long)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) << \
			  (64 - CPU_SHIFT)) >> (64 - CPU_SHIFT)))
#define next_current_ksp0(task) ({ \
	unsigned long __ksp0 = task_ksp0(task) & ((1UL << CPU_SHIFT) - 1); \
	unsigned long __cpu = (long)raw_smp_processor_id() << CPU_SHIFT; \
	__ksp0 | __cpu; \
})
#else
#define LOG2_NR_CPU_IDS 6
#define MAX_CPU_ID ((1 << LOG2_NR_CPU_IDS) - 1)
#define raw_smp_processor_id() \
	((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & MAX_CPU_ID)
#define get_current_ksp0() \
	(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~MAX_CPU_ID)
#define next_current_ksp0(task) ({ \
	unsigned long __ksp0 = task_ksp0(task); \
	int __cpu = raw_smp_processor_id(); \
	BUG_ON(__ksp0 & MAX_CPU_ID); \
	__ksp0 | __cpu; \
})
#endif
#if CONFIG_NR_CPUS > (MAX_CPU_ID + 1)
# error Too many cpus!
#endif

#endif /* _ASM_TILE_PROCESSOR_H */
Commit	Line	Data
867e359b CM	1	/*
	2	* Copyright 2010 Tilera Corporation. All Rights Reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or
	5	* modify it under the terms of the GNU General Public License
	6	* as published by the Free Software Foundation, version 2.
	7	*
	8	* This program is distributed in the hope that it will be useful, but
	9	* WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	11	* NON INFRINGEMENT. See the GNU General Public License for
	12	* more details.
	13	*/
	14
	15	#ifndef _ASM_TILE_PROCESSOR_H
	16	#define _ASM_TILE_PROCESSOR_H
	17
051168df CM	18	#include <arch/chip.h>
051168df CM	19
867e359b CM	20	#ifndef __ASSEMBLY__
	21
	22	/*
	23	* NOTE: we don't include <linux/ptrace.h> or <linux/percpu.h> as one
	24	* normally would, due to #include dependencies.
	25	*/
9f9c0382	26	#include <linux/types.h>
867e359b CM	27	#include <asm/ptrace.h>
	28	#include <asm/percpu.h>
	29
867e359b CM	30	#include <arch/spr_def.h>
	31
	32	struct task_struct;
	33	struct thread_struct;
867e359b CM	34
	35	typedef struct {
	36	unsigned long seg;
	37	} mm_segment_t;
	38
	39	/*
	40	* Default implementation of macro that returns current
	41	* instruction pointer ("program counter").
	42	*/
	43	void *current_text_addr(void);
	44
	45	#if CHIP_HAS_TILE_DMA()
	46	/* Capture the state of a suspended DMA. */
	47	struct tile_dma_state {
	48	int enabled;
	49	unsigned long src;
	50	unsigned long dest;
	51	unsigned long strides;
	52	unsigned long chunk_size;
	53	unsigned long src_chunk;
	54	unsigned long dest_chunk;
	55	unsigned long byte;
	56	unsigned long status;
	57	};
	58
	59	/*
	60	* A mask of the DMA status register for selecting only the 'running'
	61	* and 'done' bits.
	62	*/
	63	#define DMA_STATUS_MASK \
	64	(SPR_DMA_STATUS__RUNNING_MASK \| SPR_DMA_STATUS__DONE_MASK)
	65	#endif
	66
	67	/*
	68	* Track asynchronous TLB events (faults and access violations)
	69	* that occur while we are in kernel mode from DMA or the SN processor.
	70	*/
	71	struct async_tlb {
	72	short fault_num; /* original fault number; 0 if none */
	73	char is_fault; /* was it a fault (vs an access violation) */
	74	char is_write; /* for fault: was it caused by a write? */
	75	unsigned long address; /* what address faulted? */
	76	};
	77
9f9c0382 CM	78	#ifdef CONFIG_HARDWALL
9f9c0382 CM	79	struct hardwall_info;
b8ace083 CM	80	struct hardwall_task {
	81	/* Which hardwall is this task tied to? (or NULL if none) */
	82	struct hardwall_info *info;
	83	/* Chains this task into the list at info->task_head. */
	84	struct list_head list;
	85	};
	86	#ifdef __tilepro__
	87	#define HARDWALL_TYPES 1 /* udn */
	88	#else
	89	#define HARDWALL_TYPES 3 /* udn, idn, and ipi */
	90	#endif
9f9c0382	91	#endif
867e359b CM	92
	93	struct thread_struct {
	94	/* kernel stack pointer */
	95	unsigned long ksp;
	96	/* kernel PC */
	97	unsigned long pc;
	98	/* starting user stack pointer (for page migration) */
	99	unsigned long usp0;
	100	/* pid of process that created this one */
	101	pid_t creator_pid;
	102	#if CHIP_HAS_TILE_DMA()
	103	/* DMA info for suspended threads (byte == 0 means no DMA state) */
	104	struct tile_dma_state tile_dma_state;
	105	#endif
	106	/* User EX_CONTEXT registers */
	107	unsigned long ex_context[2];
	108	/* User SYSTEM_SAVE registers */
	109	unsigned long system_save[4];
	110	/* User interrupt mask */
	111	unsigned long long interrupt_mask;
	112	/* User interrupt-control 0 state */
	113	unsigned long intctrl_0;
867e359b CM	114	/* Any other miscellaneous processor state bits */
867e359b CM	115	unsigned long proc_status;
a802fc68 CM	116	#if !CHIP_HAS_FIXED_INTVEC_BASE()
	117	/* Interrupt base for PL0 interrupts */
	118	unsigned long interrupt_vector_base;
	119	#endif
a802fc68 CM	120	/* Tile cache retry fifo high-water mark */
a802fc68 CM	121	unsigned long tile_rtf_hwm;
a802fc68 CM	122	#if CHIP_HAS_DSTREAM_PF()
	123	/* Data stream prefetch control */
	124	unsigned long dstream_pf;
	125	#endif
9f9c0382	126	#ifdef CONFIG_HARDWALL
b8ace083 CM	127	/* Hardwall information for various resources. */
b8ace083 CM	128	struct hardwall_task hardwall[HARDWALL_TYPES];
9f9c0382	129	#endif
867e359b CM	130	#if CHIP_HAS_TILE_DMA()
	131	/* Async DMA TLB fault information */
	132	struct async_tlb dma_async_tlb;
	133	#endif
867e359b CM	134	};
	135
	136	#endif /* !__ASSEMBLY__ */
	137
	138	/*
	139	* Start with "sp" this many bytes below the top of the kernel stack.
35f05976 CM	140	* This allows us to be cache-aware when handling the initial save
35f05976 CM	141	* of the pt_regs value to the stack.
867e359b	142	*/
35f05976	143	#define STACK_TOP_DELTA 64
867e359b CM	144
	145	/*
	146	* When entering the kernel via a fault, start with the top of the
	147	* pt_regs structure this many bytes below the top of the page.
	148	* This aligns the pt_regs structure optimally for cache-line access.
	149	*/
	150	#ifdef __tilegx__
	151	#define KSTK_PTREGS_GAP 48
	152	#else
	153	#define KSTK_PTREGS_GAP 56
	154	#endif
	155
	156	#ifndef __ASSEMBLY__
	157
	158	#ifdef __tilegx__
acbde1db	159	#define TASK_SIZE_MAX (_AC(1, UL) << (MAX_VA_WIDTH - 1))
867e359b CM	160	#else
	161	#define TASK_SIZE_MAX PAGE_OFFSET
	162	#endif
	163
	164	/* TASK_SIZE and related variables are always checked in "current" context. */
	165	#ifdef CONFIG_COMPAT
	166	#define COMPAT_TASK_SIZE (1UL << 31)
	167	#define TASK_SIZE ((current_thread_info()->status & TS_COMPAT) ?\
	168	COMPAT_TASK_SIZE : TASK_SIZE_MAX)
	169	#else
	170	#define TASK_SIZE TASK_SIZE_MAX
	171	#endif
	172
4a556f4f CM	173	#define VDSO_BASE ((unsigned long)current->active_mm->context.vdso_base)
4a556f4f CM	174	#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
867e359b	175
4a556f4f	176	#define STACK_TOP TASK_SIZE
867e359b CM	177
	178	/* STACK_TOP_MAX is used temporarily in execve and should not check COMPAT. */
	179	#define STACK_TOP_MAX TASK_SIZE_MAX
	180
	181	/*
	182	* This decides where the kernel will search for a free chunk of vm
	183	* space during mmap's, if it is using bottom-up mapping.
	184	*/
	185	#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 3))
	186
	187	#define HAVE_ARCH_PICK_MMAP_LAYOUT
	188
	189	#define INIT_THREAD { \
	190	.ksp = (unsigned long)init_stack + THREAD_SIZE - STACK_TOP_DELTA, \
	191	.interrupt_mask = -1ULL \
	192	}
	193
	194	/* Kernel stack top for the task that first boots on this cpu. */
	195	DECLARE_PER_CPU(unsigned long, boot_sp);
	196
	197	/* PC to boot from on this cpu. */
	198	DECLARE_PER_CPU(unsigned long, boot_pc);
	199
	200	/* Do necessary setup to start up a newly executed thread. */
	201	static inline void start_thread(struct pt_regs *regs,
	202	unsigned long pc, unsigned long usp)
	203	{
	204	regs->pc = pc;
	205	regs->sp = usp;
53055065	206	single_step_execve();
867e359b CM	207	}
	208
	209	/* Free all resources held by a thread. */
	210	static inline void release_thread(struct task_struct *dead_task)
	211	{
	212	/* Nothing for now */
	213	}
	214
583b24a2	215	extern void prepare_exit_to_usermode(struct pt_regs *regs, u32 flags);
313ce674	216
867e359b CM	217
	218	/*
	219	* Return saved (kernel) PC of a blocked thread.
0a0fca9d	220	* Only used in a printk() in kernel/sched/core.c, so don't work too hard.
867e359b CM	221	*/
	222	#define thread_saved_pc(t) ((t)->thread.pc)
	223
	224	unsigned long get_wchan(struct task_struct *p);
	225
	226	/* Return initial ksp value for given task. */
35f05976 CM	227	#define task_ksp0(task) \
35f05976 CM	228	((unsigned long)(task)->stack + THREAD_SIZE - STACK_TOP_DELTA)
867e359b CM	229
867e359b CM	230	/* Return some info about the user process TASK. */
867e359b	231	#define task_pt_regs(task) \
35f05976	232	((struct pt_regs *)(task_ksp0(task) - KSTK_PTREGS_GAP) - 1)
733deca1	233	#define current_pt_regs() \
35f05976 CM	234	((struct pt_regs *)((stack_pointer \| (THREAD_SIZE - 1)) - \
35f05976 CM	235	STACK_TOP_DELTA - (KSTK_PTREGS_GAP - 1)) - 1)
867e359b CM	236	#define task_sp(task) (task_pt_regs(task)->sp)
	237	#define task_pc(task) (task_pt_regs(task)->pc)
	238	/* Aliases for pc and sp (used in fs/proc/array.c) */
	239	#define KSTK_EIP(task) task_pc(task)
	240	#define KSTK_ESP(task) task_sp(task)
	241
2f9ac29e CM	242	/* Fine-grained unaligned JIT support */
	243	#define GET_UNALIGN_CTL(tsk, adr) get_unalign_ctl((tsk), (adr))
	244	#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
	245
	246	extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
	247	extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
	248
867e359b CM	249	/* Standard format for printing registers and other word-size data. */
	250	#ifdef __tilegx__
	251	# define REGFMT "0x%016lx"
	252	#else
	253	# define REGFMT "0x%08lx"
	254	#endif
	255
	256	/*
	257	* Do some slow action (e.g. read a slow SPR).
	258	* Note that this must also have compiler-barrier semantics since
	259	* it may be used in a busy loop reading memory.
	260	*/
	261	static inline void cpu_relax(void)
	262	{
	263	__insn_mfspr(SPR_PASS);
	264	barrier();
	265	}
	266
3a6bfbc9 DB	267	#define cpu_relax_lowlatency() cpu_relax()
3a6bfbc9 DB	268
9f9c0382 CM	269	/* Info on this processor (see fs/proc/cpuinfo.c) */
	270	struct seq_operations;
	271	extern const struct seq_operations cpuinfo_op;
	272
867e359b CM	273	/* Provide information about the chip model. */
	274	extern char chip_model[64];
	275
	276	/* Data on which physical memory controller corresponds to which NUMA node. */
	277	extern int node_controller[];
	278
867e359b CM	279	/* Does the heap allocator return hash-for-home pages by default? */
	280	extern int hash_default;
	281
	282	/* Should kernel stack pages be hash-for-home? */
	283	extern int kstack_hash;
ef06f55a CM	284
	285	/* Does MAP_ANONYMOUS return hash-for-home pages by default? */
	286	#define uheap_hash hash_default
	287
867e359b CM	288
	289	/* Are we using huge pages in the TLB for kernel data? */
	290	extern int kdata_huge;
	291
e5a06939 CM	292	/* Support standard Linux prefetching. */
	293	#define ARCH_HAS_PREFETCH
	294	#define prefetch(x) __builtin_prefetch(x)
ef06f55a	295	#define PREFETCH_STRIDE CHIP_L2_LINE_SIZE()
867e359b	296
e5a06939 CM	297	/* Bring a value into the L1D, faulting the TLB if necessary. */
	298	#ifdef __tilegx__
	299	#define prefetch_L1(x) __insn_prefetch_l1_fault((void *)(x))
	300	#else
	301	#define prefetch_L1(x) __insn_prefetch_L1((void *)(x))
	302	#endif
	303
867e359b CM	304	#else /* __ASSEMBLY__ */
	305
	306	/* Do some slow action (e.g. read a slow SPR). */
	307	#define CPU_RELAX mfspr zero, SPR_PASS
	308
	309	#endif /* !__ASSEMBLY__ */
	310
	311	/* Assembly code assumes that the PL is in the low bits. */
	312	#if SPR_EX_CONTEXT_1_1__PL_SHIFT != 0
	313	# error Fix assembly assumptions about PL
	314	#endif
	315
	316	/* We sometimes use these macros for EX_CONTEXT_0_1 as well. */
	317	#if SPR_EX_CONTEXT_1_1__PL_SHIFT != SPR_EX_CONTEXT_0_1__PL_SHIFT \|\| \
	318	SPR_EX_CONTEXT_1_1__PL_RMASK != SPR_EX_CONTEXT_0_1__PL_RMASK \|\| \
	319	SPR_EX_CONTEXT_1_1__ICS_SHIFT != SPR_EX_CONTEXT_0_1__ICS_SHIFT \|\| \
	320	SPR_EX_CONTEXT_1_1__ICS_RMASK != SPR_EX_CONTEXT_0_1__ICS_RMASK
	321	# error Fix assumptions that EX1 macros work for both PL0 and PL1
	322	#endif
	323
	324	/* Allow pulling apart and recombining the PL and ICS bits in EX_CONTEXT. */
	325	#define EX1_PL(ex1) \
	326	(((ex1) >> SPR_EX_CONTEXT_1_1__PL_SHIFT) & SPR_EX_CONTEXT_1_1__PL_RMASK)
	327	#define EX1_ICS(ex1) \
	328	(((ex1) >> SPR_EX_CONTEXT_1_1__ICS_SHIFT) & SPR_EX_CONTEXT_1_1__ICS_RMASK)
	329	#define PL_ICS_EX1(pl, ics) \
	330	(((pl) << SPR_EX_CONTEXT_1_1__PL_SHIFT) \| \
	331	((ics) << SPR_EX_CONTEXT_1_1__ICS_SHIFT))
	332
	333	/*
	334	* Provide symbolic constants for PLs.
867e359b CM	335	*/
867e359b CM	336	#define USER_PL 0
a78c942d CM	337	#if CONFIG_KERNEL_PL == 2
	338	#define GUEST_PL 1
	339	#endif
	340	#define KERNEL_PL CONFIG_KERNEL_PL
867e359b	341
a78c942d	342	/* SYSTEM_SAVE_K_0 holds the current cpu number ORed with ksp0. */
35f05976 CM	343	#ifdef __tilegx__
	344	#define CPU_SHIFT 48
	345	#if CHIP_VA_WIDTH() > CPU_SHIFT
	346	# error Too many VA bits!
867e359b	347	#endif
35f05976	348	#define MAX_CPU_ID ((1 << (64 - CPU_SHIFT)) - 1)
867e359b	349	#define raw_smp_processor_id() \
35f05976	350	((int)(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) >> CPU_SHIFT))
867e359b	351	#define get_current_ksp0() \
35f05976 CM	352	((unsigned long)(((long)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) << \
	353	(64 - CPU_SHIFT)) >> (64 - CPU_SHIFT)))
	354	#define next_current_ksp0(task) ({ \
	355	unsigned long __ksp0 = task_ksp0(task) & ((1UL << CPU_SHIFT) - 1); \
	356	unsigned long __cpu = (long)raw_smp_processor_id() << CPU_SHIFT; \
	357	__ksp0 \| __cpu; \
	358	})
	359	#else
	360	#define LOG2_NR_CPU_IDS 6
	361	#define MAX_CPU_ID ((1 << LOG2_NR_CPU_IDS) - 1)
	362	#define raw_smp_processor_id() \
	363	((int)__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & MAX_CPU_ID)
	364	#define get_current_ksp0() \
	365	(__insn_mfspr(SPR_SYSTEM_SAVE_K_0) & ~MAX_CPU_ID)
867e359b CM	366	#define next_current_ksp0(task) ({ \
	367	unsigned long __ksp0 = task_ksp0(task); \
	368	int __cpu = raw_smp_processor_id(); \
35f05976	369	BUG_ON(__ksp0 & MAX_CPU_ID); \
867e359b CM	370	__ksp0 \| __cpu; \
867e359b CM	371	})
35f05976 CM	372	#endif
	373	#if CONFIG_NR_CPUS > (MAX_CPU_ID + 1)
	374	# error Too many cpus!
	375	#endif
867e359b CM	376
867e359b CM	377	#endif /* _ASM_TILE_PROCESSOR_H */