Commit | Line | Data |
---|---|---|
b00dc837 | 1 | /* |
1da177e4 LT |
2 | * arch/sparc64/mm/init.c |
3 | * | |
4 | * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
c4bce90e | 8 | #include <linux/module.h> |
1da177e4 LT |
9 | #include <linux/kernel.h> |
10 | #include <linux/sched.h> | |
11 | #include <linux/string.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/hugetlb.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/initrd.h> | |
18 | #include <linux/swap.h> | |
19 | #include <linux/pagemap.h> | |
c9cf5528 | 20 | #include <linux/poison.h> |
1da177e4 LT |
21 | #include <linux/fs.h> |
22 | #include <linux/seq_file.h> | |
05e14cb3 | 23 | #include <linux/kprobes.h> |
1ac4f5eb | 24 | #include <linux/cache.h> |
13edad7a | 25 | #include <linux/sort.h> |
5cbc3073 | 26 | #include <linux/percpu.h> |
3b2a7e23 | 27 | #include <linux/lmb.h> |
919ee677 | 28 | #include <linux/mmzone.h> |
1da177e4 LT |
29 | |
30 | #include <asm/head.h> | |
31 | #include <asm/system.h> | |
32 | #include <asm/page.h> | |
33 | #include <asm/pgalloc.h> | |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/oplib.h> | |
36 | #include <asm/iommu.h> | |
37 | #include <asm/io.h> | |
38 | #include <asm/uaccess.h> | |
39 | #include <asm/mmu_context.h> | |
40 | #include <asm/tlbflush.h> | |
41 | #include <asm/dma.h> | |
42 | #include <asm/starfire.h> | |
43 | #include <asm/tlb.h> | |
44 | #include <asm/spitfire.h> | |
45 | #include <asm/sections.h> | |
517af332 | 46 | #include <asm/tsb.h> |
481295f9 | 47 | #include <asm/hypervisor.h> |
372b07bb | 48 | #include <asm/prom.h> |
5cbc3073 | 49 | #include <asm/mdesc.h> |
3d5ae6b6 | 50 | #include <asm/cpudata.h> |
4f70f7a9 | 51 | #include <asm/irq.h> |
1da177e4 | 52 | |
af1ee569 | 53 | #include "init.h" |
9cc3a1ac DM |
54 | |
55 | unsigned long kern_linear_pte_xor[2] __read_mostly; | |
56 | ||
57 | /* A bitmap, one bit for every 256MB of physical memory. If the bit | |
58 | * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else | |
59 | * if set we should use a 256MB page (via kern_linear_pte_xor[1]). | |
60 | */ | |
61 | unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)]; | |
62 | ||
d1acb421 | 63 | #ifndef CONFIG_DEBUG_PAGEALLOC |
2d9e2763 DM |
64 | /* A special kernel TSB for 4MB and 256MB linear mappings. |
65 | * Space is allocated for this right after the trap table | |
66 | * in arch/sparc64/kernel/head.S | |
67 | */ | |
68 | extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; | |
d1acb421 | 69 | #endif |
d7744a09 | 70 | |
13edad7a DM |
71 | #define MAX_BANKS 32 |
72 | ||
73 | static struct linux_prom64_registers pavail[MAX_BANKS] __initdata; | |
13edad7a | 74 | static int pavail_ents __initdata; |
13edad7a DM |
75 | |
76 | static int cmp_p64(const void *a, const void *b) | |
77 | { | |
78 | const struct linux_prom64_registers *x = a, *y = b; | |
79 | ||
80 | if (x->phys_addr > y->phys_addr) | |
81 | return 1; | |
82 | if (x->phys_addr < y->phys_addr) | |
83 | return -1; | |
84 | return 0; | |
85 | } | |
86 | ||
87 | static void __init read_obp_memory(const char *property, | |
88 | struct linux_prom64_registers *regs, | |
89 | int *num_ents) | |
90 | { | |
91 | int node = prom_finddevice("/memory"); | |
92 | int prop_size = prom_getproplen(node, property); | |
93 | int ents, ret, i; | |
94 | ||
95 | ents = prop_size / sizeof(struct linux_prom64_registers); | |
96 | if (ents > MAX_BANKS) { | |
97 | prom_printf("The machine has more %s property entries than " | |
98 | "this kernel can support (%d).\n", | |
99 | property, MAX_BANKS); | |
100 | prom_halt(); | |
101 | } | |
102 | ||
103 | ret = prom_getproperty(node, property, (char *) regs, prop_size); | |
104 | if (ret == -1) { | |
105 | prom_printf("Couldn't get %s property from /memory.\n"); | |
106 | prom_halt(); | |
107 | } | |
108 | ||
13edad7a DM |
109 | /* Sanitize what we got from the firmware, by page aligning |
110 | * everything. | |
111 | */ | |
112 | for (i = 0; i < ents; i++) { | |
113 | unsigned long base, size; | |
114 | ||
115 | base = regs[i].phys_addr; | |
116 | size = regs[i].reg_size; | |
10147570 | 117 | |
13edad7a DM |
118 | size &= PAGE_MASK; |
119 | if (base & ~PAGE_MASK) { | |
120 | unsigned long new_base = PAGE_ALIGN(base); | |
121 | ||
122 | size -= new_base - base; | |
123 | if ((long) size < 0L) | |
124 | size = 0UL; | |
125 | base = new_base; | |
126 | } | |
0015d3d6 DM |
127 | if (size == 0UL) { |
128 | /* If it is empty, simply get rid of it. | |
129 | * This simplifies the logic of the other | |
130 | * functions that process these arrays. | |
131 | */ | |
132 | memmove(®s[i], ®s[i + 1], | |
133 | (ents - i - 1) * sizeof(regs[0])); | |
486ad10a | 134 | i--; |
0015d3d6 DM |
135 | ents--; |
136 | continue; | |
486ad10a | 137 | } |
0015d3d6 DM |
138 | regs[i].phys_addr = base; |
139 | regs[i].reg_size = size; | |
486ad10a DM |
140 | } |
141 | ||
142 | *num_ents = ents; | |
143 | ||
c9c10830 | 144 | sort(regs, ents, sizeof(struct linux_prom64_registers), |
13edad7a DM |
145 | cmp_p64, NULL); |
146 | } | |
1da177e4 | 147 | |
2bdb3cb2 | 148 | unsigned long *sparc64_valid_addr_bitmap __read_mostly; |
1da177e4 | 149 | |
d1112018 | 150 | /* Kernel physical address base and size in bytes. */ |
1ac4f5eb DM |
151 | unsigned long kern_base __read_mostly; |
152 | unsigned long kern_size __read_mostly; | |
1da177e4 | 153 | |
1da177e4 LT |
154 | /* Initial ramdisk setup */ |
155 | extern unsigned long sparc_ramdisk_image64; | |
156 | extern unsigned int sparc_ramdisk_image; | |
157 | extern unsigned int sparc_ramdisk_size; | |
158 | ||
1ac4f5eb | 159 | struct page *mem_map_zero __read_mostly; |
35802c0b | 160 | EXPORT_SYMBOL(mem_map_zero); |
1da177e4 | 161 | |
0835ae0f DM |
162 | unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; |
163 | ||
164 | unsigned long sparc64_kern_pri_context __read_mostly; | |
165 | unsigned long sparc64_kern_pri_nuc_bits __read_mostly; | |
166 | unsigned long sparc64_kern_sec_context __read_mostly; | |
167 | ||
64658743 | 168 | int num_kernel_image_mappings; |
1da177e4 | 169 | |
1da177e4 LT |
170 | #ifdef CONFIG_DEBUG_DCFLUSH |
171 | atomic_t dcpage_flushes = ATOMIC_INIT(0); | |
172 | #ifdef CONFIG_SMP | |
173 | atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); | |
174 | #endif | |
175 | #endif | |
176 | ||
7a591cfe | 177 | inline void flush_dcache_page_impl(struct page *page) |
1da177e4 | 178 | { |
7a591cfe | 179 | BUG_ON(tlb_type == hypervisor); |
1da177e4 LT |
180 | #ifdef CONFIG_DEBUG_DCFLUSH |
181 | atomic_inc(&dcpage_flushes); | |
182 | #endif | |
183 | ||
184 | #ifdef DCACHE_ALIASING_POSSIBLE | |
185 | __flush_dcache_page(page_address(page), | |
186 | ((tlb_type == spitfire) && | |
187 | page_mapping(page) != NULL)); | |
188 | #else | |
189 | if (page_mapping(page) != NULL && | |
190 | tlb_type == spitfire) | |
191 | __flush_icache_page(__pa(page_address(page))); | |
192 | #endif | |
193 | } | |
194 | ||
195 | #define PG_dcache_dirty PG_arch_1 | |
22adb358 DM |
196 | #define PG_dcache_cpu_shift 32UL |
197 | #define PG_dcache_cpu_mask \ | |
198 | ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) | |
1da177e4 LT |
199 | |
200 | #define dcache_dirty_cpu(page) \ | |
48b0e548 | 201 | (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) |
1da177e4 | 202 | |
d979f179 | 203 | static inline void set_dcache_dirty(struct page *page, int this_cpu) |
1da177e4 LT |
204 | { |
205 | unsigned long mask = this_cpu; | |
48b0e548 DM |
206 | unsigned long non_cpu_bits; |
207 | ||
208 | non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); | |
209 | mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); | |
210 | ||
1da177e4 LT |
211 | __asm__ __volatile__("1:\n\t" |
212 | "ldx [%2], %%g7\n\t" | |
213 | "and %%g7, %1, %%g1\n\t" | |
214 | "or %%g1, %0, %%g1\n\t" | |
215 | "casx [%2], %%g7, %%g1\n\t" | |
216 | "cmp %%g7, %%g1\n\t" | |
b445e26c | 217 | "membar #StoreLoad | #StoreStore\n\t" |
1da177e4 | 218 | "bne,pn %%xcc, 1b\n\t" |
b445e26c | 219 | " nop" |
1da177e4 LT |
220 | : /* no outputs */ |
221 | : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) | |
222 | : "g1", "g7"); | |
223 | } | |
224 | ||
d979f179 | 225 | static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) |
1da177e4 LT |
226 | { |
227 | unsigned long mask = (1UL << PG_dcache_dirty); | |
228 | ||
229 | __asm__ __volatile__("! test_and_clear_dcache_dirty\n" | |
230 | "1:\n\t" | |
231 | "ldx [%2], %%g7\n\t" | |
48b0e548 | 232 | "srlx %%g7, %4, %%g1\n\t" |
1da177e4 LT |
233 | "and %%g1, %3, %%g1\n\t" |
234 | "cmp %%g1, %0\n\t" | |
235 | "bne,pn %%icc, 2f\n\t" | |
236 | " andn %%g7, %1, %%g1\n\t" | |
237 | "casx [%2], %%g7, %%g1\n\t" | |
238 | "cmp %%g7, %%g1\n\t" | |
b445e26c | 239 | "membar #StoreLoad | #StoreStore\n\t" |
1da177e4 | 240 | "bne,pn %%xcc, 1b\n\t" |
b445e26c | 241 | " nop\n" |
1da177e4 LT |
242 | "2:" |
243 | : /* no outputs */ | |
244 | : "r" (cpu), "r" (mask), "r" (&page->flags), | |
48b0e548 DM |
245 | "i" (PG_dcache_cpu_mask), |
246 | "i" (PG_dcache_cpu_shift) | |
1da177e4 LT |
247 | : "g1", "g7"); |
248 | } | |
249 | ||
517af332 DM |
250 | static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) |
251 | { | |
252 | unsigned long tsb_addr = (unsigned long) ent; | |
253 | ||
3b3ab2eb | 254 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) |
517af332 DM |
255 | tsb_addr = __pa(tsb_addr); |
256 | ||
257 | __tsb_insert(tsb_addr, tag, pte); | |
258 | } | |
259 | ||
c4bce90e DM |
260 | unsigned long _PAGE_ALL_SZ_BITS __read_mostly; |
261 | unsigned long _PAGE_SZBITS __read_mostly; | |
262 | ||
1da177e4 LT |
263 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) |
264 | { | |
bd40791e | 265 | struct mm_struct *mm; |
74ae9987 | 266 | struct tsb *tsb; |
7a1ac526 | 267 | unsigned long tag, flags; |
dcc1e8dd | 268 | unsigned long tsb_index, tsb_hash_shift; |
7a591cfe DM |
269 | |
270 | if (tlb_type != hypervisor) { | |
271 | unsigned long pfn = pte_pfn(pte); | |
272 | unsigned long pg_flags; | |
273 | struct page *page; | |
274 | ||
275 | if (pfn_valid(pfn) && | |
276 | (page = pfn_to_page(pfn), page_mapping(page)) && | |
277 | ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) { | |
278 | int cpu = ((pg_flags >> PG_dcache_cpu_shift) & | |
279 | PG_dcache_cpu_mask); | |
280 | int this_cpu = get_cpu(); | |
281 | ||
282 | /* This is just to optimize away some function calls | |
283 | * in the SMP case. | |
284 | */ | |
285 | if (cpu == this_cpu) | |
286 | flush_dcache_page_impl(page); | |
287 | else | |
288 | smp_flush_dcache_page_impl(page, cpu); | |
289 | ||
290 | clear_dcache_dirty_cpu(page, cpu); | |
291 | ||
292 | put_cpu(); | |
293 | } | |
1da177e4 | 294 | } |
bd40791e DM |
295 | |
296 | mm = vma->vm_mm; | |
7a1ac526 | 297 | |
dcc1e8dd DM |
298 | tsb_index = MM_TSB_BASE; |
299 | tsb_hash_shift = PAGE_SHIFT; | |
300 | ||
7a1ac526 DM |
301 | spin_lock_irqsave(&mm->context.lock, flags); |
302 | ||
dcc1e8dd DM |
303 | #ifdef CONFIG_HUGETLB_PAGE |
304 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) { | |
305 | if ((tlb_type == hypervisor && | |
306 | (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) || | |
307 | (tlb_type != hypervisor && | |
308 | (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) { | |
309 | tsb_index = MM_TSB_HUGE; | |
310 | tsb_hash_shift = HPAGE_SHIFT; | |
311 | } | |
312 | } | |
313 | #endif | |
314 | ||
315 | tsb = mm->context.tsb_block[tsb_index].tsb; | |
316 | tsb += ((address >> tsb_hash_shift) & | |
317 | (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); | |
74ae9987 DM |
318 | tag = (address >> 22UL); |
319 | tsb_insert(tsb, tag, pte_val(pte)); | |
7a1ac526 DM |
320 | |
321 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
1da177e4 LT |
322 | } |
323 | ||
324 | void flush_dcache_page(struct page *page) | |
325 | { | |
a9546f59 DM |
326 | struct address_space *mapping; |
327 | int this_cpu; | |
1da177e4 | 328 | |
7a591cfe DM |
329 | if (tlb_type == hypervisor) |
330 | return; | |
331 | ||
a9546f59 DM |
332 | /* Do not bother with the expensive D-cache flush if it |
333 | * is merely the zero page. The 'bigcore' testcase in GDB | |
334 | * causes this case to run millions of times. | |
335 | */ | |
336 | if (page == ZERO_PAGE(0)) | |
337 | return; | |
338 | ||
339 | this_cpu = get_cpu(); | |
340 | ||
341 | mapping = page_mapping(page); | |
1da177e4 | 342 | if (mapping && !mapping_mapped(mapping)) { |
a9546f59 | 343 | int dirty = test_bit(PG_dcache_dirty, &page->flags); |
1da177e4 | 344 | if (dirty) { |
a9546f59 DM |
345 | int dirty_cpu = dcache_dirty_cpu(page); |
346 | ||
1da177e4 LT |
347 | if (dirty_cpu == this_cpu) |
348 | goto out; | |
349 | smp_flush_dcache_page_impl(page, dirty_cpu); | |
350 | } | |
351 | set_dcache_dirty(page, this_cpu); | |
352 | } else { | |
353 | /* We could delay the flush for the !page_mapping | |
354 | * case too. But that case is for exec env/arg | |
355 | * pages and those are %99 certainly going to get | |
356 | * faulted into the tlb (and thus flushed) anyways. | |
357 | */ | |
358 | flush_dcache_page_impl(page); | |
359 | } | |
360 | ||
361 | out: | |
362 | put_cpu(); | |
363 | } | |
364 | ||
05e14cb3 | 365 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 366 | { |
a43fe0e7 | 367 | /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ |
1da177e4 LT |
368 | if (tlb_type == spitfire) { |
369 | unsigned long kaddr; | |
370 | ||
a94aa253 DM |
371 | /* This code only runs on Spitfire cpus so this is |
372 | * why we can assume _PAGE_PADDR_4U. | |
373 | */ | |
374 | for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { | |
375 | unsigned long paddr, mask = _PAGE_PADDR_4U; | |
376 | ||
377 | if (kaddr >= PAGE_OFFSET) | |
378 | paddr = kaddr & mask; | |
379 | else { | |
380 | pgd_t *pgdp = pgd_offset_k(kaddr); | |
381 | pud_t *pudp = pud_offset(pgdp, kaddr); | |
382 | pmd_t *pmdp = pmd_offset(pudp, kaddr); | |
383 | pte_t *ptep = pte_offset_kernel(pmdp, kaddr); | |
384 | ||
385 | paddr = pte_val(*ptep) & mask; | |
386 | } | |
387 | __flush_icache_page(paddr); | |
388 | } | |
1da177e4 LT |
389 | } |
390 | } | |
391 | ||
1da177e4 LT |
392 | void mmu_info(struct seq_file *m) |
393 | { | |
394 | if (tlb_type == cheetah) | |
395 | seq_printf(m, "MMU Type\t: Cheetah\n"); | |
396 | else if (tlb_type == cheetah_plus) | |
397 | seq_printf(m, "MMU Type\t: Cheetah+\n"); | |
398 | else if (tlb_type == spitfire) | |
399 | seq_printf(m, "MMU Type\t: Spitfire\n"); | |
a43fe0e7 DM |
400 | else if (tlb_type == hypervisor) |
401 | seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); | |
1da177e4 LT |
402 | else |
403 | seq_printf(m, "MMU Type\t: ???\n"); | |
404 | ||
405 | #ifdef CONFIG_DEBUG_DCFLUSH | |
406 | seq_printf(m, "DCPageFlushes\t: %d\n", | |
407 | atomic_read(&dcpage_flushes)); | |
408 | #ifdef CONFIG_SMP | |
409 | seq_printf(m, "DCPageFlushesXC\t: %d\n", | |
410 | atomic_read(&dcpage_flushes_xcall)); | |
411 | #endif /* CONFIG_SMP */ | |
412 | #endif /* CONFIG_DEBUG_DCFLUSH */ | |
413 | } | |
414 | ||
a94aa253 DM |
415 | struct linux_prom_translation prom_trans[512] __read_mostly; |
416 | unsigned int prom_trans_ents __read_mostly; | |
417 | ||
1da177e4 LT |
418 | unsigned long kern_locked_tte_data; |
419 | ||
c9c10830 DM |
420 | /* The obp translations are saved based on 8k pagesize, since obp can |
421 | * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> | |
74bf4312 | 422 | * HI_OBP_ADDRESS range are handled in ktlb.S. |
c9c10830 | 423 | */ |
5085b4a5 DM |
424 | static inline int in_obp_range(unsigned long vaddr) |
425 | { | |
426 | return (vaddr >= LOW_OBP_ADDRESS && | |
427 | vaddr < HI_OBP_ADDRESS); | |
428 | } | |
429 | ||
c9c10830 | 430 | static int cmp_ptrans(const void *a, const void *b) |
405599bd | 431 | { |
c9c10830 | 432 | const struct linux_prom_translation *x = a, *y = b; |
405599bd | 433 | |
c9c10830 DM |
434 | if (x->virt > y->virt) |
435 | return 1; | |
436 | if (x->virt < y->virt) | |
437 | return -1; | |
438 | return 0; | |
405599bd DM |
439 | } |
440 | ||
c9c10830 | 441 | /* Read OBP translations property into 'prom_trans[]'. */ |
9ad98c5b | 442 | static void __init read_obp_translations(void) |
405599bd | 443 | { |
c9c10830 | 444 | int n, node, ents, first, last, i; |
1da177e4 LT |
445 | |
446 | node = prom_finddevice("/virtual-memory"); | |
447 | n = prom_getproplen(node, "translations"); | |
405599bd | 448 | if (unlikely(n == 0 || n == -1)) { |
b206fc4c | 449 | prom_printf("prom_mappings: Couldn't get size.\n"); |
1da177e4 LT |
450 | prom_halt(); |
451 | } | |
405599bd DM |
452 | if (unlikely(n > sizeof(prom_trans))) { |
453 | prom_printf("prom_mappings: Size %Zd is too big.\n", n); | |
1da177e4 LT |
454 | prom_halt(); |
455 | } | |
405599bd | 456 | |
b206fc4c | 457 | if ((n = prom_getproperty(node, "translations", |
405599bd DM |
458 | (char *)&prom_trans[0], |
459 | sizeof(prom_trans))) == -1) { | |
b206fc4c | 460 | prom_printf("prom_mappings: Couldn't get property.\n"); |
1da177e4 LT |
461 | prom_halt(); |
462 | } | |
9ad98c5b | 463 | |
b206fc4c | 464 | n = n / sizeof(struct linux_prom_translation); |
9ad98c5b | 465 | |
c9c10830 DM |
466 | ents = n; |
467 | ||
468 | sort(prom_trans, ents, sizeof(struct linux_prom_translation), | |
469 | cmp_ptrans, NULL); | |
470 | ||
471 | /* Now kick out all the non-OBP entries. */ | |
472 | for (i = 0; i < ents; i++) { | |
473 | if (in_obp_range(prom_trans[i].virt)) | |
474 | break; | |
475 | } | |
476 | first = i; | |
477 | for (; i < ents; i++) { | |
478 | if (!in_obp_range(prom_trans[i].virt)) | |
479 | break; | |
480 | } | |
481 | last = i; | |
482 | ||
483 | for (i = 0; i < (last - first); i++) { | |
484 | struct linux_prom_translation *src = &prom_trans[i + first]; | |
485 | struct linux_prom_translation *dest = &prom_trans[i]; | |
486 | ||
487 | *dest = *src; | |
488 | } | |
489 | for (; i < ents; i++) { | |
490 | struct linux_prom_translation *dest = &prom_trans[i]; | |
491 | dest->virt = dest->size = dest->data = 0x0UL; | |
492 | } | |
493 | ||
494 | prom_trans_ents = last - first; | |
495 | ||
496 | if (tlb_type == spitfire) { | |
497 | /* Clear diag TTE bits. */ | |
498 | for (i = 0; i < prom_trans_ents; i++) | |
499 | prom_trans[i].data &= ~0x0003fe0000000000UL; | |
500 | } | |
405599bd | 501 | } |
1da177e4 | 502 | |
d82ace7d DM |
503 | static void __init hypervisor_tlb_lock(unsigned long vaddr, |
504 | unsigned long pte, | |
505 | unsigned long mmu) | |
506 | { | |
7db35f31 DM |
507 | unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); |
508 | ||
509 | if (ret != 0) { | |
12e126ad | 510 | prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: " |
7db35f31 | 511 | "errors with %lx\n", vaddr, 0, pte, mmu, ret); |
12e126ad DM |
512 | prom_halt(); |
513 | } | |
d82ace7d DM |
514 | } |
515 | ||
c4bce90e DM |
516 | static unsigned long kern_large_tte(unsigned long paddr); |
517 | ||
898cf0ec | 518 | static void __init remap_kernel(void) |
405599bd DM |
519 | { |
520 | unsigned long phys_page, tte_vaddr, tte_data; | |
64658743 | 521 | int i, tlb_ent = sparc64_highest_locked_tlbent(); |
405599bd | 522 | |
1da177e4 | 523 | tte_vaddr = (unsigned long) KERNBASE; |
bff06d55 | 524 | phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL; |
c4bce90e | 525 | tte_data = kern_large_tte(phys_page); |
1da177e4 LT |
526 | |
527 | kern_locked_tte_data = tte_data; | |
528 | ||
d82ace7d DM |
529 | /* Now lock us into the TLBs via Hypervisor or OBP. */ |
530 | if (tlb_type == hypervisor) { | |
64658743 | 531 | for (i = 0; i < num_kernel_image_mappings; i++) { |
d82ace7d DM |
532 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); |
533 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); | |
64658743 DM |
534 | tte_vaddr += 0x400000; |
535 | tte_data += 0x400000; | |
d82ace7d DM |
536 | } |
537 | } else { | |
64658743 DM |
538 | for (i = 0; i < num_kernel_image_mappings; i++) { |
539 | prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
540 | prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
541 | tte_vaddr += 0x400000; | |
542 | tte_data += 0x400000; | |
d82ace7d | 543 | } |
64658743 | 544 | sparc64_highest_unlocked_tlb_ent = tlb_ent - i; |
1da177e4 | 545 | } |
0835ae0f DM |
546 | if (tlb_type == cheetah_plus) { |
547 | sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | | |
548 | CTX_CHEETAH_PLUS_NUC); | |
549 | sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; | |
550 | sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; | |
551 | } | |
405599bd | 552 | } |
1da177e4 | 553 | |
405599bd | 554 | |
c9c10830 | 555 | static void __init inherit_prom_mappings(void) |
9ad98c5b | 556 | { |
405599bd | 557 | /* Now fixup OBP's idea about where we really are mapped. */ |
3c62a2d3 | 558 | printk("Remapping the kernel... "); |
405599bd | 559 | remap_kernel(); |
3c62a2d3 | 560 | printk("done.\n"); |
1da177e4 LT |
561 | } |
562 | ||
1da177e4 LT |
563 | void prom_world(int enter) |
564 | { | |
1da177e4 LT |
565 | if (!enter) |
566 | set_fs((mm_segment_t) { get_thread_current_ds() }); | |
567 | ||
3487d1d4 | 568 | __asm__ __volatile__("flushw"); |
1da177e4 LT |
569 | } |
570 | ||
1da177e4 LT |
571 | void __flush_dcache_range(unsigned long start, unsigned long end) |
572 | { | |
573 | unsigned long va; | |
574 | ||
575 | if (tlb_type == spitfire) { | |
576 | int n = 0; | |
577 | ||
578 | for (va = start; va < end; va += 32) { | |
579 | spitfire_put_dcache_tag(va & 0x3fe0, 0x0); | |
580 | if (++n >= 512) | |
581 | break; | |
582 | } | |
a43fe0e7 | 583 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
584 | start = __pa(start); |
585 | end = __pa(end); | |
586 | for (va = start; va < end; va += 32) | |
587 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
588 | "membar #Sync" | |
589 | : /* no outputs */ | |
590 | : "r" (va), | |
591 | "i" (ASI_DCACHE_INVALIDATE)); | |
592 | } | |
593 | } | |
1da177e4 | 594 | |
85f1e1f6 DM |
595 | /* get_new_mmu_context() uses "cache + 1". */ |
596 | DEFINE_SPINLOCK(ctx_alloc_lock); | |
597 | unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; | |
598 | #define MAX_CTX_NR (1UL << CTX_NR_BITS) | |
599 | #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) | |
600 | DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); | |
601 | ||
1da177e4 LT |
602 | /* Caller does TLB context flushing on local CPU if necessary. |
603 | * The caller also ensures that CTX_VALID(mm->context) is false. | |
604 | * | |
605 | * We must be careful about boundary cases so that we never | |
606 | * let the user have CTX 0 (nucleus) or we ever use a CTX | |
607 | * version of zero (and thus NO_CONTEXT would not be caught | |
608 | * by version mis-match tests in mmu_context.h). | |
a0663a79 DM |
609 | * |
610 | * Always invoked with interrupts disabled. | |
1da177e4 LT |
611 | */ |
612 | void get_new_mmu_context(struct mm_struct *mm) | |
613 | { | |
614 | unsigned long ctx, new_ctx; | |
615 | unsigned long orig_pgsz_bits; | |
a77754b4 | 616 | unsigned long flags; |
a0663a79 | 617 | int new_version; |
1da177e4 | 618 | |
a77754b4 | 619 | spin_lock_irqsave(&ctx_alloc_lock, flags); |
1da177e4 LT |
620 | orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); |
621 | ctx = (tlb_context_cache + 1) & CTX_NR_MASK; | |
622 | new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); | |
a0663a79 | 623 | new_version = 0; |
1da177e4 LT |
624 | if (new_ctx >= (1 << CTX_NR_BITS)) { |
625 | new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); | |
626 | if (new_ctx >= ctx) { | |
627 | int i; | |
628 | new_ctx = (tlb_context_cache & CTX_VERSION_MASK) + | |
629 | CTX_FIRST_VERSION; | |
630 | if (new_ctx == 1) | |
631 | new_ctx = CTX_FIRST_VERSION; | |
632 | ||
633 | /* Don't call memset, for 16 entries that's just | |
634 | * plain silly... | |
635 | */ | |
636 | mmu_context_bmap[0] = 3; | |
637 | mmu_context_bmap[1] = 0; | |
638 | mmu_context_bmap[2] = 0; | |
639 | mmu_context_bmap[3] = 0; | |
640 | for (i = 4; i < CTX_BMAP_SLOTS; i += 4) { | |
641 | mmu_context_bmap[i + 0] = 0; | |
642 | mmu_context_bmap[i + 1] = 0; | |
643 | mmu_context_bmap[i + 2] = 0; | |
644 | mmu_context_bmap[i + 3] = 0; | |
645 | } | |
a0663a79 | 646 | new_version = 1; |
1da177e4 LT |
647 | goto out; |
648 | } | |
649 | } | |
650 | mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); | |
651 | new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); | |
652 | out: | |
653 | tlb_context_cache = new_ctx; | |
654 | mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; | |
a77754b4 | 655 | spin_unlock_irqrestore(&ctx_alloc_lock, flags); |
a0663a79 DM |
656 | |
657 | if (unlikely(new_version)) | |
658 | smp_new_mmu_context_version(); | |
1da177e4 LT |
659 | } |
660 | ||
919ee677 DM |
661 | static int numa_enabled = 1; |
662 | static int numa_debug; | |
663 | ||
664 | static int __init early_numa(char *p) | |
1da177e4 | 665 | { |
919ee677 DM |
666 | if (!p) |
667 | return 0; | |
668 | ||
669 | if (strstr(p, "off")) | |
670 | numa_enabled = 0; | |
d1112018 | 671 | |
919ee677 DM |
672 | if (strstr(p, "debug")) |
673 | numa_debug = 1; | |
d1112018 | 674 | |
919ee677 | 675 | return 0; |
d1112018 | 676 | } |
919ee677 DM |
677 | early_param("numa", early_numa); |
678 | ||
679 | #define numadbg(f, a...) \ | |
680 | do { if (numa_debug) \ | |
681 | printk(KERN_INFO f, ## a); \ | |
682 | } while (0) | |
d1112018 | 683 | |
4e82c9a6 DM |
684 | static void __init find_ramdisk(unsigned long phys_base) |
685 | { | |
686 | #ifdef CONFIG_BLK_DEV_INITRD | |
687 | if (sparc_ramdisk_image || sparc_ramdisk_image64) { | |
688 | unsigned long ramdisk_image; | |
689 | ||
690 | /* Older versions of the bootloader only supported a | |
691 | * 32-bit physical address for the ramdisk image | |
692 | * location, stored at sparc_ramdisk_image. Newer | |
693 | * SILO versions set sparc_ramdisk_image to zero and | |
694 | * provide a full 64-bit physical address at | |
695 | * sparc_ramdisk_image64. | |
696 | */ | |
697 | ramdisk_image = sparc_ramdisk_image; | |
698 | if (!ramdisk_image) | |
699 | ramdisk_image = sparc_ramdisk_image64; | |
700 | ||
701 | /* Another bootloader quirk. The bootloader normalizes | |
702 | * the physical address to KERNBASE, so we have to | |
703 | * factor that back out and add in the lowest valid | |
704 | * physical page address to get the true physical address. | |
705 | */ | |
706 | ramdisk_image -= KERNBASE; | |
707 | ramdisk_image += phys_base; | |
708 | ||
919ee677 DM |
709 | numadbg("Found ramdisk at physical address 0x%lx, size %u\n", |
710 | ramdisk_image, sparc_ramdisk_size); | |
711 | ||
4e82c9a6 DM |
712 | initrd_start = ramdisk_image; |
713 | initrd_end = ramdisk_image + sparc_ramdisk_size; | |
3b2a7e23 | 714 | |
7047901e | 715 | lmb_reserve(initrd_start, sparc_ramdisk_size); |
d45100f7 DM |
716 | |
717 | initrd_start += PAGE_OFFSET; | |
718 | initrd_end += PAGE_OFFSET; | |
4e82c9a6 DM |
719 | } |
720 | #endif | |
721 | } | |
722 | ||
919ee677 DM |
723 | struct node_mem_mask { |
724 | unsigned long mask; | |
725 | unsigned long val; | |
726 | unsigned long bootmem_paddr; | |
727 | }; | |
728 | static struct node_mem_mask node_masks[MAX_NUMNODES]; | |
729 | static int num_node_masks; | |
730 | ||
731 | int numa_cpu_lookup_table[NR_CPUS]; | |
732 | cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; | |
733 | ||
734 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
919ee677 DM |
735 | |
736 | struct mdesc_mblock { | |
737 | u64 base; | |
738 | u64 size; | |
739 | u64 offset; /* RA-to-PA */ | |
740 | }; | |
741 | static struct mdesc_mblock *mblocks; | |
742 | static int num_mblocks; | |
743 | ||
744 | static unsigned long ra_to_pa(unsigned long addr) | |
745 | { | |
746 | int i; | |
747 | ||
748 | for (i = 0; i < num_mblocks; i++) { | |
749 | struct mdesc_mblock *m = &mblocks[i]; | |
750 | ||
751 | if (addr >= m->base && | |
752 | addr < (m->base + m->size)) { | |
753 | addr += m->offset; | |
754 | break; | |
755 | } | |
756 | } | |
757 | return addr; | |
758 | } | |
759 | ||
760 | static int find_node(unsigned long addr) | |
761 | { | |
762 | int i; | |
763 | ||
764 | addr = ra_to_pa(addr); | |
765 | for (i = 0; i < num_node_masks; i++) { | |
766 | struct node_mem_mask *p = &node_masks[i]; | |
767 | ||
768 | if ((addr & p->mask) == p->val) | |
769 | return i; | |
770 | } | |
771 | return -1; | |
772 | } | |
773 | ||
774 | static unsigned long nid_range(unsigned long start, unsigned long end, | |
775 | int *nid) | |
776 | { | |
777 | *nid = find_node(start); | |
778 | start += PAGE_SIZE; | |
779 | while (start < end) { | |
780 | int n = find_node(start); | |
781 | ||
782 | if (n != *nid) | |
783 | break; | |
784 | start += PAGE_SIZE; | |
785 | } | |
786 | ||
c918dcce DM |
787 | if (start > end) |
788 | start = end; | |
789 | ||
919ee677 DM |
790 | return start; |
791 | } | |
792 | #else | |
793 | static unsigned long nid_range(unsigned long start, unsigned long end, | |
794 | int *nid) | |
795 | { | |
796 | *nid = 0; | |
797 | return end; | |
798 | } | |
799 | #endif | |
800 | ||
801 | /* This must be invoked after performing all of the necessary | |
802 | * add_active_range() calls for 'nid'. We need to be able to get | |
803 | * correct data from get_pfn_range_for_nid(). | |
f1cfdb55 | 804 | */ |
919ee677 DM |
805 | static void __init allocate_node_data(int nid) |
806 | { | |
807 | unsigned long paddr, num_pages, start_pfn, end_pfn; | |
808 | struct pglist_data *p; | |
809 | ||
810 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
811 | paddr = lmb_alloc_nid(sizeof(struct pglist_data), | |
812 | SMP_CACHE_BYTES, nid, nid_range); | |
813 | if (!paddr) { | |
814 | prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); | |
815 | prom_halt(); | |
816 | } | |
817 | NODE_DATA(nid) = __va(paddr); | |
818 | memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); | |
819 | ||
b61bfa3c | 820 | NODE_DATA(nid)->bdata = &bootmem_node_data[nid]; |
919ee677 DM |
821 | #endif |
822 | ||
823 | p = NODE_DATA(nid); | |
824 | ||
825 | get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); | |
826 | p->node_start_pfn = start_pfn; | |
827 | p->node_spanned_pages = end_pfn - start_pfn; | |
828 | ||
829 | if (p->node_spanned_pages) { | |
830 | num_pages = bootmem_bootmap_pages(p->node_spanned_pages); | |
831 | ||
832 | paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid, | |
833 | nid_range); | |
834 | if (!paddr) { | |
835 | prom_printf("Cannot allocate bootmap for nid[%d]\n", | |
836 | nid); | |
837 | prom_halt(); | |
838 | } | |
839 | node_masks[nid].bootmem_paddr = paddr; | |
840 | } | |
841 | } | |
842 | ||
843 | static void init_node_masks_nonnuma(void) | |
d1112018 | 844 | { |
1da177e4 LT |
845 | int i; |
846 | ||
919ee677 | 847 | numadbg("Initializing tables for non-numa.\n"); |
6fc5bae7 | 848 | |
919ee677 DM |
849 | node_masks[0].mask = node_masks[0].val = 0; |
850 | num_node_masks = 1; | |
d1112018 | 851 | |
919ee677 DM |
852 | for (i = 0; i < NR_CPUS; i++) |
853 | numa_cpu_lookup_table[i] = 0; | |
1da177e4 | 854 | |
919ee677 DM |
855 | numa_cpumask_lookup_table[0] = CPU_MASK_ALL; |
856 | } | |
857 | ||
858 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
859 | struct pglist_data *node_data[MAX_NUMNODES]; | |
860 | ||
861 | EXPORT_SYMBOL(numa_cpu_lookup_table); | |
862 | EXPORT_SYMBOL(numa_cpumask_lookup_table); | |
863 | EXPORT_SYMBOL(node_data); | |
864 | ||
865 | struct mdesc_mlgroup { | |
866 | u64 node; | |
867 | u64 latency; | |
868 | u64 match; | |
869 | u64 mask; | |
870 | }; | |
871 | static struct mdesc_mlgroup *mlgroups; | |
872 | static int num_mlgroups; | |
873 | ||
874 | static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, | |
875 | u32 cfg_handle) | |
876 | { | |
877 | u64 arc; | |
878 | ||
879 | mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { | |
880 | u64 target = mdesc_arc_target(md, arc); | |
881 | const u64 *val; | |
882 | ||
883 | val = mdesc_get_property(md, target, | |
884 | "cfg-handle", NULL); | |
885 | if (val && *val == cfg_handle) | |
886 | return 0; | |
887 | } | |
888 | return -ENODEV; | |
889 | } | |
890 | ||
891 | static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, | |
892 | u32 cfg_handle) | |
893 | { | |
894 | u64 arc, candidate, best_latency = ~(u64)0; | |
895 | ||
896 | candidate = MDESC_NODE_NULL; | |
897 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
898 | u64 target = mdesc_arc_target(md, arc); | |
899 | const char *name = mdesc_node_name(md, target); | |
900 | const u64 *val; | |
901 | ||
902 | if (strcmp(name, "pio-latency-group")) | |
903 | continue; | |
904 | ||
905 | val = mdesc_get_property(md, target, "latency", NULL); | |
906 | if (!val) | |
907 | continue; | |
908 | ||
909 | if (*val < best_latency) { | |
910 | candidate = target; | |
911 | best_latency = *val; | |
912 | } | |
913 | } | |
914 | ||
915 | if (candidate == MDESC_NODE_NULL) | |
916 | return -ENODEV; | |
917 | ||
918 | return scan_pio_for_cfg_handle(md, candidate, cfg_handle); | |
919 | } | |
920 | ||
921 | int of_node_to_nid(struct device_node *dp) | |
922 | { | |
923 | const struct linux_prom64_registers *regs; | |
924 | struct mdesc_handle *md; | |
925 | u32 cfg_handle; | |
926 | int count, nid; | |
927 | u64 grp; | |
928 | ||
072bd413 DM |
929 | /* This is the right thing to do on currently supported |
930 | * SUN4U NUMA platforms as well, as the PCI controller does | |
931 | * not sit behind any particular memory controller. | |
932 | */ | |
919ee677 DM |
933 | if (!mlgroups) |
934 | return -1; | |
935 | ||
936 | regs = of_get_property(dp, "reg", NULL); | |
937 | if (!regs) | |
938 | return -1; | |
939 | ||
940 | cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; | |
941 | ||
942 | md = mdesc_grab(); | |
943 | ||
944 | count = 0; | |
945 | nid = -1; | |
946 | mdesc_for_each_node_by_name(md, grp, "group") { | |
947 | if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { | |
948 | nid = count; | |
949 | break; | |
950 | } | |
951 | count++; | |
952 | } | |
953 | ||
954 | mdesc_release(md); | |
955 | ||
956 | return nid; | |
957 | } | |
958 | ||
8c29890a | 959 | static void __init add_node_ranges(void) |
919ee677 DM |
960 | { |
961 | int i; | |
962 | ||
963 | for (i = 0; i < lmb.memory.cnt; i++) { | |
964 | unsigned long size = lmb_size_bytes(&lmb.memory, i); | |
965 | unsigned long start, end; | |
966 | ||
967 | start = lmb.memory.region[i].base; | |
968 | end = start + size; | |
969 | while (start < end) { | |
970 | unsigned long this_end; | |
971 | int nid; | |
972 | ||
973 | this_end = nid_range(start, end, &nid); | |
974 | ||
975 | numadbg("Adding active range nid[%d] " | |
976 | "start[%lx] end[%lx]\n", | |
977 | nid, start, this_end); | |
978 | ||
979 | add_active_range(nid, | |
980 | start >> PAGE_SHIFT, | |
981 | this_end >> PAGE_SHIFT); | |
982 | ||
983 | start = this_end; | |
984 | } | |
985 | } | |
986 | } | |
987 | ||
988 | static int __init grab_mlgroups(struct mdesc_handle *md) | |
989 | { | |
990 | unsigned long paddr; | |
991 | int count = 0; | |
992 | u64 node; | |
993 | ||
994 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") | |
995 | count++; | |
996 | if (!count) | |
997 | return -ENOENT; | |
998 | ||
999 | paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup), | |
1000 | SMP_CACHE_BYTES); | |
1001 | if (!paddr) | |
1002 | return -ENOMEM; | |
1003 | ||
1004 | mlgroups = __va(paddr); | |
1005 | num_mlgroups = count; | |
1006 | ||
1007 | count = 0; | |
1008 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") { | |
1009 | struct mdesc_mlgroup *m = &mlgroups[count++]; | |
1010 | const u64 *val; | |
1011 | ||
1012 | m->node = node; | |
1013 | ||
1014 | val = mdesc_get_property(md, node, "latency", NULL); | |
1015 | m->latency = *val; | |
1016 | val = mdesc_get_property(md, node, "address-match", NULL); | |
1017 | m->match = *val; | |
1018 | val = mdesc_get_property(md, node, "address-mask", NULL); | |
1019 | m->mask = *val; | |
1020 | ||
1021 | numadbg("MLGROUP[%d]: node[%lx] latency[%lx] " | |
1022 | "match[%lx] mask[%lx]\n", | |
1023 | count - 1, m->node, m->latency, m->match, m->mask); | |
1024 | } | |
1025 | ||
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | static int __init grab_mblocks(struct mdesc_handle *md) | |
1030 | { | |
1031 | unsigned long paddr; | |
1032 | int count = 0; | |
1033 | u64 node; | |
1034 | ||
1035 | mdesc_for_each_node_by_name(md, node, "mblock") | |
1036 | count++; | |
1037 | if (!count) | |
1038 | return -ENOENT; | |
1039 | ||
1040 | paddr = lmb_alloc(count * sizeof(struct mdesc_mblock), | |
1041 | SMP_CACHE_BYTES); | |
1042 | if (!paddr) | |
1043 | return -ENOMEM; | |
1044 | ||
1045 | mblocks = __va(paddr); | |
1046 | num_mblocks = count; | |
1047 | ||
1048 | count = 0; | |
1049 | mdesc_for_each_node_by_name(md, node, "mblock") { | |
1050 | struct mdesc_mblock *m = &mblocks[count++]; | |
1051 | const u64 *val; | |
1052 | ||
1053 | val = mdesc_get_property(md, node, "base", NULL); | |
1054 | m->base = *val; | |
1055 | val = mdesc_get_property(md, node, "size", NULL); | |
1056 | m->size = *val; | |
1057 | val = mdesc_get_property(md, node, | |
1058 | "address-congruence-offset", NULL); | |
1059 | m->offset = *val; | |
1060 | ||
1061 | numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n", | |
1062 | count - 1, m->base, m->size, m->offset); | |
1063 | } | |
1064 | ||
1065 | return 0; | |
1066 | } | |
1067 | ||
1068 | static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, | |
1069 | u64 grp, cpumask_t *mask) | |
1070 | { | |
1071 | u64 arc; | |
1072 | ||
1073 | cpus_clear(*mask); | |
1074 | ||
1075 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { | |
1076 | u64 target = mdesc_arc_target(md, arc); | |
1077 | const char *name = mdesc_node_name(md, target); | |
1078 | const u64 *id; | |
1079 | ||
1080 | if (strcmp(name, "cpu")) | |
1081 | continue; | |
1082 | id = mdesc_get_property(md, target, "id", NULL); | |
1083 | if (*id < NR_CPUS) | |
1084 | cpu_set(*id, *mask); | |
1085 | } | |
1086 | } | |
1087 | ||
1088 | static struct mdesc_mlgroup * __init find_mlgroup(u64 node) | |
1089 | { | |
1090 | int i; | |
1091 | ||
1092 | for (i = 0; i < num_mlgroups; i++) { | |
1093 | struct mdesc_mlgroup *m = &mlgroups[i]; | |
1094 | if (m->node == node) | |
1095 | return m; | |
1096 | } | |
1097 | return NULL; | |
1098 | } | |
1099 | ||
1100 | static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, | |
1101 | int index) | |
1102 | { | |
1103 | struct mdesc_mlgroup *candidate = NULL; | |
1104 | u64 arc, best_latency = ~(u64)0; | |
1105 | struct node_mem_mask *n; | |
1106 | ||
1107 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
1108 | u64 target = mdesc_arc_target(md, arc); | |
1109 | struct mdesc_mlgroup *m = find_mlgroup(target); | |
1110 | if (!m) | |
1111 | continue; | |
1112 | if (m->latency < best_latency) { | |
1113 | candidate = m; | |
1114 | best_latency = m->latency; | |
1115 | } | |
1116 | } | |
1117 | if (!candidate) | |
1118 | return -ENOENT; | |
1119 | ||
1120 | if (num_node_masks != index) { | |
1121 | printk(KERN_ERR "Inconsistent NUMA state, " | |
1122 | "index[%d] != num_node_masks[%d]\n", | |
1123 | index, num_node_masks); | |
1124 | return -EINVAL; | |
1125 | } | |
1126 | ||
1127 | n = &node_masks[num_node_masks++]; | |
1128 | ||
1129 | n->mask = candidate->mask; | |
1130 | n->val = candidate->match; | |
1da177e4 | 1131 | |
919ee677 DM |
1132 | numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n", |
1133 | index, n->mask, n->val, candidate->latency); | |
1da177e4 | 1134 | |
919ee677 DM |
1135 | return 0; |
1136 | } | |
1137 | ||
1138 | static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, | |
1139 | int index) | |
1140 | { | |
1141 | cpumask_t mask; | |
1142 | int cpu; | |
1143 | ||
1144 | numa_parse_mdesc_group_cpus(md, grp, &mask); | |
1145 | ||
1146 | for_each_cpu_mask(cpu, mask) | |
1147 | numa_cpu_lookup_table[cpu] = index; | |
1148 | numa_cpumask_lookup_table[index] = mask; | |
1149 | ||
1150 | if (numa_debug) { | |
1151 | printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); | |
1152 | for_each_cpu_mask(cpu, mask) | |
1153 | printk("%d ", cpu); | |
1154 | printk("]\n"); | |
1155 | } | |
1156 | ||
1157 | return numa_attach_mlgroup(md, grp, index); | |
1158 | } | |
1159 | ||
1160 | static int __init numa_parse_mdesc(void) | |
1161 | { | |
1162 | struct mdesc_handle *md = mdesc_grab(); | |
1163 | int i, err, count; | |
1164 | u64 node; | |
1165 | ||
1166 | node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); | |
1167 | if (node == MDESC_NODE_NULL) { | |
1168 | mdesc_release(md); | |
1169 | return -ENOENT; | |
1170 | } | |
1171 | ||
1172 | err = grab_mblocks(md); | |
1173 | if (err < 0) | |
1174 | goto out; | |
1175 | ||
1176 | err = grab_mlgroups(md); | |
1177 | if (err < 0) | |
1178 | goto out; | |
1179 | ||
1180 | count = 0; | |
1181 | mdesc_for_each_node_by_name(md, node, "group") { | |
1182 | err = numa_parse_mdesc_group(md, node, count); | |
1183 | if (err < 0) | |
1184 | break; | |
1185 | count++; | |
1186 | } | |
1187 | ||
1188 | add_node_ranges(); | |
1189 | ||
1190 | for (i = 0; i < num_node_masks; i++) { | |
1191 | allocate_node_data(i); | |
1192 | node_set_online(i); | |
1193 | } | |
1194 | ||
1195 | err = 0; | |
1196 | out: | |
1197 | mdesc_release(md); | |
1198 | return err; | |
1199 | } | |
1200 | ||
072bd413 DM |
1201 | static int __init numa_parse_jbus(void) |
1202 | { | |
1203 | unsigned long cpu, index; | |
1204 | ||
1205 | /* NUMA node id is encoded in bits 36 and higher, and there is | |
1206 | * a 1-to-1 mapping from CPU ID to NUMA node ID. | |
1207 | */ | |
1208 | index = 0; | |
1209 | for_each_present_cpu(cpu) { | |
1210 | numa_cpu_lookup_table[cpu] = index; | |
1211 | numa_cpumask_lookup_table[index] = cpumask_of_cpu(cpu); | |
1212 | node_masks[index].mask = ~((1UL << 36UL) - 1UL); | |
1213 | node_masks[index].val = cpu << 36UL; | |
1214 | ||
1215 | index++; | |
1216 | } | |
1217 | num_node_masks = index; | |
1218 | ||
1219 | add_node_ranges(); | |
1220 | ||
1221 | for (index = 0; index < num_node_masks; index++) { | |
1222 | allocate_node_data(index); | |
1223 | node_set_online(index); | |
1224 | } | |
1225 | ||
1226 | return 0; | |
1227 | } | |
1228 | ||
919ee677 DM |
1229 | static int __init numa_parse_sun4u(void) |
1230 | { | |
072bd413 DM |
1231 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1232 | unsigned long ver; | |
1233 | ||
1234 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
1235 | if ((ver >> 32UL) == __JALAPENO_ID || | |
1236 | (ver >> 32UL) == __SERRANO_ID) | |
1237 | return numa_parse_jbus(); | |
1238 | } | |
919ee677 DM |
1239 | return -1; |
1240 | } | |
1241 | ||
1242 | static int __init bootmem_init_numa(void) | |
1243 | { | |
1244 | int err = -1; | |
1245 | ||
1246 | numadbg("bootmem_init_numa()\n"); | |
1247 | ||
1248 | if (numa_enabled) { | |
1249 | if (tlb_type == hypervisor) | |
1250 | err = numa_parse_mdesc(); | |
1251 | else | |
1252 | err = numa_parse_sun4u(); | |
1253 | } | |
1254 | return err; | |
1255 | } | |
1256 | ||
1257 | #else | |
1da177e4 | 1258 | |
919ee677 DM |
1259 | static int bootmem_init_numa(void) |
1260 | { | |
1261 | return -1; | |
1262 | } | |
1263 | ||
1264 | #endif | |
1265 | ||
1266 | static void __init bootmem_init_nonnuma(void) | |
1267 | { | |
1268 | unsigned long top_of_ram = lmb_end_of_DRAM(); | |
1269 | unsigned long total_ram = lmb_phys_mem_size(); | |
1270 | unsigned int i; | |
1271 | ||
1272 | numadbg("bootmem_init_nonnuma()\n"); | |
1273 | ||
1274 | printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", | |
1275 | top_of_ram, total_ram); | |
1276 | printk(KERN_INFO "Memory hole size: %ldMB\n", | |
1277 | (top_of_ram - total_ram) >> 20); | |
1278 | ||
1279 | init_node_masks_nonnuma(); | |
1280 | ||
1281 | for (i = 0; i < lmb.memory.cnt; i++) { | |
1282 | unsigned long size = lmb_size_bytes(&lmb.memory, i); | |
1283 | unsigned long start_pfn, end_pfn; | |
1284 | ||
1285 | if (!size) | |
1286 | continue; | |
1da177e4 | 1287 | |
9422273b | 1288 | start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT; |
919ee677 DM |
1289 | end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i); |
1290 | add_active_range(0, start_pfn, end_pfn); | |
1291 | } | |
d1112018 | 1292 | |
919ee677 DM |
1293 | allocate_node_data(0); |
1294 | ||
1295 | node_set_online(0); | |
1296 | } | |
1297 | ||
1298 | static void __init reserve_range_in_node(int nid, unsigned long start, | |
1299 | unsigned long end) | |
1300 | { | |
1301 | numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n", | |
1302 | nid, start, end); | |
1303 | while (start < end) { | |
1304 | unsigned long this_end; | |
1305 | int n; | |
1306 | ||
1307 | this_end = nid_range(start, end, &n); | |
1308 | if (n == nid) { | |
1309 | numadbg(" MATCH reserving range [%lx:%lx]\n", | |
1310 | start, this_end); | |
1311 | reserve_bootmem_node(NODE_DATA(nid), start, | |
1312 | (this_end - start), BOOTMEM_DEFAULT); | |
1313 | } else | |
1314 | numadbg(" NO MATCH, advancing start to %lx\n", | |
1315 | this_end); | |
1316 | ||
1317 | start = this_end; | |
d1112018 | 1318 | } |
919ee677 DM |
1319 | } |
1320 | ||
1321 | static void __init trim_reserved_in_node(int nid) | |
1322 | { | |
1323 | int i; | |
1324 | ||
1325 | numadbg(" trim_reserved_in_node(%d)\n", nid); | |
1326 | ||
1327 | for (i = 0; i < lmb.reserved.cnt; i++) { | |
1328 | unsigned long start = lmb.reserved.region[i].base; | |
1329 | unsigned long size = lmb_size_bytes(&lmb.reserved, i); | |
1330 | unsigned long end = start + size; | |
1331 | ||
1332 | reserve_range_in_node(nid, start, end); | |
1333 | } | |
1334 | } | |
1335 | ||
1336 | static void __init bootmem_init_one_node(int nid) | |
1337 | { | |
1338 | struct pglist_data *p; | |
1339 | ||
1340 | numadbg("bootmem_init_one_node(%d)\n", nid); | |
1341 | ||
1342 | p = NODE_DATA(nid); | |
1343 | ||
1344 | if (p->node_spanned_pages) { | |
1345 | unsigned long paddr = node_masks[nid].bootmem_paddr; | |
1346 | unsigned long end_pfn; | |
1347 | ||
1348 | end_pfn = p->node_start_pfn + p->node_spanned_pages; | |
1349 | ||
1350 | numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n", | |
1351 | nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn); | |
1352 | ||
1353 | init_bootmem_node(p, paddr >> PAGE_SHIFT, | |
1354 | p->node_start_pfn, end_pfn); | |
1355 | ||
1356 | numadbg(" free_bootmem_with_active_regions(%d, %lx)\n", | |
1357 | nid, end_pfn); | |
1358 | free_bootmem_with_active_regions(nid, end_pfn); | |
1359 | ||
1360 | trim_reserved_in_node(nid); | |
1361 | ||
1362 | numadbg(" sparse_memory_present_with_active_regions(%d)\n", | |
1363 | nid); | |
1364 | sparse_memory_present_with_active_regions(nid); | |
1365 | } | |
1366 | } | |
1367 | ||
1368 | static unsigned long __init bootmem_init(unsigned long phys_base) | |
1369 | { | |
1370 | unsigned long end_pfn; | |
1371 | int nid; | |
1372 | ||
1373 | end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT; | |
1374 | max_pfn = max_low_pfn = end_pfn; | |
1375 | min_low_pfn = (phys_base >> PAGE_SHIFT); | |
1376 | ||
1377 | if (bootmem_init_numa() < 0) | |
1378 | bootmem_init_nonnuma(); | |
1379 | ||
1380 | /* XXX cpu notifier XXX */ | |
1381 | ||
1382 | for_each_online_node(nid) | |
1383 | bootmem_init_one_node(nid); | |
d1112018 DM |
1384 | |
1385 | sparse_init(); | |
1386 | ||
1da177e4 LT |
1387 | return end_pfn; |
1388 | } | |
1389 | ||
9cc3a1ac DM |
1390 | static struct linux_prom64_registers pall[MAX_BANKS] __initdata; |
1391 | static int pall_ents __initdata; | |
1392 | ||
56425306 | 1393 | #ifdef CONFIG_DEBUG_PAGEALLOC |
896aef43 SR |
1394 | static unsigned long __ref kernel_map_range(unsigned long pstart, |
1395 | unsigned long pend, pgprot_t prot) | |
56425306 DM |
1396 | { |
1397 | unsigned long vstart = PAGE_OFFSET + pstart; | |
1398 | unsigned long vend = PAGE_OFFSET + pend; | |
1399 | unsigned long alloc_bytes = 0UL; | |
1400 | ||
1401 | if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { | |
13edad7a | 1402 | prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", |
56425306 DM |
1403 | vstart, vend); |
1404 | prom_halt(); | |
1405 | } | |
1406 | ||
1407 | while (vstart < vend) { | |
1408 | unsigned long this_end, paddr = __pa(vstart); | |
1409 | pgd_t *pgd = pgd_offset_k(vstart); | |
1410 | pud_t *pud; | |
1411 | pmd_t *pmd; | |
1412 | pte_t *pte; | |
1413 | ||
1414 | pud = pud_offset(pgd, vstart); | |
1415 | if (pud_none(*pud)) { | |
1416 | pmd_t *new; | |
1417 | ||
1418 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1419 | alloc_bytes += PAGE_SIZE; | |
1420 | pud_populate(&init_mm, pud, new); | |
1421 | } | |
1422 | ||
1423 | pmd = pmd_offset(pud, vstart); | |
1424 | if (!pmd_present(*pmd)) { | |
1425 | pte_t *new; | |
1426 | ||
1427 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1428 | alloc_bytes += PAGE_SIZE; | |
1429 | pmd_populate_kernel(&init_mm, pmd, new); | |
1430 | } | |
1431 | ||
1432 | pte = pte_offset_kernel(pmd, vstart); | |
1433 | this_end = (vstart + PMD_SIZE) & PMD_MASK; | |
1434 | if (this_end > vend) | |
1435 | this_end = vend; | |
1436 | ||
1437 | while (vstart < this_end) { | |
1438 | pte_val(*pte) = (paddr | pgprot_val(prot)); | |
1439 | ||
1440 | vstart += PAGE_SIZE; | |
1441 | paddr += PAGE_SIZE; | |
1442 | pte++; | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | return alloc_bytes; | |
1447 | } | |
1448 | ||
56425306 | 1449 | extern unsigned int kvmap_linear_patch[1]; |
9cc3a1ac DM |
1450 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1451 | ||
1452 | static void __init mark_kpte_bitmap(unsigned long start, unsigned long end) | |
1453 | { | |
1454 | const unsigned long shift_256MB = 28; | |
1455 | const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL); | |
1456 | const unsigned long size_256MB = (1UL << shift_256MB); | |
1457 | ||
1458 | while (start < end) { | |
1459 | long remains; | |
1460 | ||
f7c00338 DM |
1461 | remains = end - start; |
1462 | if (remains < size_256MB) | |
1463 | break; | |
1464 | ||
9cc3a1ac DM |
1465 | if (start & mask_256MB) { |
1466 | start = (start + size_256MB) & ~mask_256MB; | |
1467 | continue; | |
1468 | } | |
1469 | ||
9cc3a1ac DM |
1470 | while (remains >= size_256MB) { |
1471 | unsigned long index = start >> shift_256MB; | |
1472 | ||
1473 | __set_bit(index, kpte_linear_bitmap); | |
1474 | ||
1475 | start += size_256MB; | |
1476 | remains -= size_256MB; | |
1477 | } | |
1478 | } | |
1479 | } | |
56425306 | 1480 | |
8f361453 | 1481 | static void __init init_kpte_bitmap(void) |
56425306 | 1482 | { |
9cc3a1ac | 1483 | unsigned long i; |
13edad7a DM |
1484 | |
1485 | for (i = 0; i < pall_ents; i++) { | |
56425306 DM |
1486 | unsigned long phys_start, phys_end; |
1487 | ||
13edad7a DM |
1488 | phys_start = pall[i].phys_addr; |
1489 | phys_end = phys_start + pall[i].reg_size; | |
9cc3a1ac DM |
1490 | |
1491 | mark_kpte_bitmap(phys_start, phys_end); | |
8f361453 DM |
1492 | } |
1493 | } | |
9cc3a1ac | 1494 | |
8f361453 DM |
1495 | static void __init kernel_physical_mapping_init(void) |
1496 | { | |
9cc3a1ac | 1497 | #ifdef CONFIG_DEBUG_PAGEALLOC |
8f361453 DM |
1498 | unsigned long i, mem_alloced = 0UL; |
1499 | ||
1500 | for (i = 0; i < pall_ents; i++) { | |
1501 | unsigned long phys_start, phys_end; | |
1502 | ||
1503 | phys_start = pall[i].phys_addr; | |
1504 | phys_end = phys_start + pall[i].reg_size; | |
1505 | ||
56425306 DM |
1506 | mem_alloced += kernel_map_range(phys_start, phys_end, |
1507 | PAGE_KERNEL); | |
56425306 DM |
1508 | } |
1509 | ||
1510 | printk("Allocated %ld bytes for kernel page tables.\n", | |
1511 | mem_alloced); | |
1512 | ||
1513 | kvmap_linear_patch[0] = 0x01000000; /* nop */ | |
1514 | flushi(&kvmap_linear_patch[0]); | |
1515 | ||
1516 | __flush_tlb_all(); | |
9cc3a1ac | 1517 | #endif |
56425306 DM |
1518 | } |
1519 | ||
9cc3a1ac | 1520 | #ifdef CONFIG_DEBUG_PAGEALLOC |
56425306 DM |
1521 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1522 | { | |
1523 | unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; | |
1524 | unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); | |
1525 | ||
1526 | kernel_map_range(phys_start, phys_end, | |
1527 | (enable ? PAGE_KERNEL : __pgprot(0))); | |
1528 | ||
74bf4312 DM |
1529 | flush_tsb_kernel_range(PAGE_OFFSET + phys_start, |
1530 | PAGE_OFFSET + phys_end); | |
1531 | ||
56425306 DM |
1532 | /* we should perform an IPI and flush all tlbs, |
1533 | * but that can deadlock->flush only current cpu. | |
1534 | */ | |
1535 | __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, | |
1536 | PAGE_OFFSET + phys_end); | |
1537 | } | |
1538 | #endif | |
1539 | ||
10147570 DM |
1540 | unsigned long __init find_ecache_flush_span(unsigned long size) |
1541 | { | |
0836a0eb DM |
1542 | int i; |
1543 | ||
13edad7a DM |
1544 | for (i = 0; i < pavail_ents; i++) { |
1545 | if (pavail[i].reg_size >= size) | |
1546 | return pavail[i].phys_addr; | |
0836a0eb DM |
1547 | } |
1548 | ||
13edad7a | 1549 | return ~0UL; |
0836a0eb DM |
1550 | } |
1551 | ||
517af332 DM |
1552 | static void __init tsb_phys_patch(void) |
1553 | { | |
d257d5da | 1554 | struct tsb_ldquad_phys_patch_entry *pquad; |
517af332 DM |
1555 | struct tsb_phys_patch_entry *p; |
1556 | ||
d257d5da DM |
1557 | pquad = &__tsb_ldquad_phys_patch; |
1558 | while (pquad < &__tsb_ldquad_phys_patch_end) { | |
1559 | unsigned long addr = pquad->addr; | |
1560 | ||
1561 | if (tlb_type == hypervisor) | |
1562 | *(unsigned int *) addr = pquad->sun4v_insn; | |
1563 | else | |
1564 | *(unsigned int *) addr = pquad->sun4u_insn; | |
1565 | wmb(); | |
1566 | __asm__ __volatile__("flush %0" | |
1567 | : /* no outputs */ | |
1568 | : "r" (addr)); | |
1569 | ||
1570 | pquad++; | |
1571 | } | |
1572 | ||
517af332 DM |
1573 | p = &__tsb_phys_patch; |
1574 | while (p < &__tsb_phys_patch_end) { | |
1575 | unsigned long addr = p->addr; | |
1576 | ||
1577 | *(unsigned int *) addr = p->insn; | |
1578 | wmb(); | |
1579 | __asm__ __volatile__("flush %0" | |
1580 | : /* no outputs */ | |
1581 | : "r" (addr)); | |
1582 | ||
1583 | p++; | |
1584 | } | |
1585 | } | |
1586 | ||
490384e7 | 1587 | /* Don't mark as init, we give this to the Hypervisor. */ |
d1acb421 DM |
1588 | #ifndef CONFIG_DEBUG_PAGEALLOC |
1589 | #define NUM_KTSB_DESCR 2 | |
1590 | #else | |
1591 | #define NUM_KTSB_DESCR 1 | |
1592 | #endif | |
1593 | static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; | |
490384e7 DM |
1594 | extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; |
1595 | ||
1596 | static void __init sun4v_ktsb_init(void) | |
1597 | { | |
1598 | unsigned long ktsb_pa; | |
1599 | ||
d7744a09 | 1600 | /* First KTSB for PAGE_SIZE mappings. */ |
490384e7 DM |
1601 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); |
1602 | ||
1603 | switch (PAGE_SIZE) { | |
1604 | case 8 * 1024: | |
1605 | default: | |
1606 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; | |
1607 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; | |
1608 | break; | |
1609 | ||
1610 | case 64 * 1024: | |
1611 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; | |
1612 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; | |
1613 | break; | |
1614 | ||
1615 | case 512 * 1024: | |
1616 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; | |
1617 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; | |
1618 | break; | |
1619 | ||
1620 | case 4 * 1024 * 1024: | |
1621 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1622 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; | |
1623 | break; | |
1624 | }; | |
1625 | ||
3f19a84e | 1626 | ktsb_descr[0].assoc = 1; |
490384e7 DM |
1627 | ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; |
1628 | ktsb_descr[0].ctx_idx = 0; | |
1629 | ktsb_descr[0].tsb_base = ktsb_pa; | |
1630 | ktsb_descr[0].resv = 0; | |
1631 | ||
d1acb421 | 1632 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 DM |
1633 | /* Second KTSB for 4MB/256MB mappings. */ |
1634 | ktsb_pa = (kern_base + | |
1635 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
1636 | ||
1637 | ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1638 | ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB | | |
1639 | HV_PGSZ_MASK_256MB); | |
1640 | ktsb_descr[1].assoc = 1; | |
1641 | ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; | |
1642 | ktsb_descr[1].ctx_idx = 0; | |
1643 | ktsb_descr[1].tsb_base = ktsb_pa; | |
1644 | ktsb_descr[1].resv = 0; | |
d1acb421 | 1645 | #endif |
490384e7 DM |
1646 | } |
1647 | ||
1648 | void __cpuinit sun4v_ktsb_register(void) | |
1649 | { | |
7db35f31 | 1650 | unsigned long pa, ret; |
490384e7 DM |
1651 | |
1652 | pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); | |
1653 | ||
7db35f31 DM |
1654 | ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); |
1655 | if (ret != 0) { | |
1656 | prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " | |
1657 | "errors with %lx\n", pa, ret); | |
1658 | prom_halt(); | |
1659 | } | |
490384e7 DM |
1660 | } |
1661 | ||
1da177e4 LT |
1662 | /* paging_init() sets up the page tables */ |
1663 | ||
1da177e4 | 1664 | static unsigned long last_valid_pfn; |
56425306 | 1665 | pgd_t swapper_pg_dir[2048]; |
1da177e4 | 1666 | |
c4bce90e DM |
1667 | static void sun4u_pgprot_init(void); |
1668 | static void sun4v_pgprot_init(void); | |
1669 | ||
3afc6202 | 1670 | /* Dummy function */ |
1671 | void __init setup_per_cpu_areas(void) | |
1672 | { | |
1673 | } | |
1674 | ||
1da177e4 LT |
1675 | void __init paging_init(void) |
1676 | { | |
919ee677 | 1677 | unsigned long end_pfn, shift, phys_base; |
0836a0eb DM |
1678 | unsigned long real_end, i; |
1679 | ||
22adb358 DM |
1680 | /* These build time checkes make sure that the dcache_dirty_cpu() |
1681 | * page->flags usage will work. | |
1682 | * | |
1683 | * When a page gets marked as dcache-dirty, we store the | |
1684 | * cpu number starting at bit 32 in the page->flags. Also, | |
1685 | * functions like clear_dcache_dirty_cpu use the cpu mask | |
1686 | * in 13-bit signed-immediate instruction fields. | |
1687 | */ | |
9223b419 CL |
1688 | |
1689 | /* | |
1690 | * Page flags must not reach into upper 32 bits that are used | |
1691 | * for the cpu number | |
1692 | */ | |
1693 | BUILD_BUG_ON(NR_PAGEFLAGS > 32); | |
1694 | ||
1695 | /* | |
1696 | * The bit fields placed in the high range must not reach below | |
1697 | * the 32 bit boundary. Otherwise we cannot place the cpu field | |
1698 | * at the 32 bit boundary. | |
1699 | */ | |
22adb358 | 1700 | BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + |
9223b419 CL |
1701 | ilog2(roundup_pow_of_two(NR_CPUS)) > 32); |
1702 | ||
22adb358 DM |
1703 | BUILD_BUG_ON(NR_CPUS > 4096); |
1704 | ||
481295f9 DM |
1705 | kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL; |
1706 | kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; | |
1707 | ||
d7744a09 | 1708 | /* Invalidate both kernel TSBs. */ |
8b234274 | 1709 | memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); |
d1acb421 | 1710 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 | 1711 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); |
d1acb421 | 1712 | #endif |
8b234274 | 1713 | |
c4bce90e DM |
1714 | if (tlb_type == hypervisor) |
1715 | sun4v_pgprot_init(); | |
1716 | else | |
1717 | sun4u_pgprot_init(); | |
1718 | ||
d257d5da DM |
1719 | if (tlb_type == cheetah_plus || |
1720 | tlb_type == hypervisor) | |
517af332 DM |
1721 | tsb_phys_patch(); |
1722 | ||
490384e7 | 1723 | if (tlb_type == hypervisor) { |
d257d5da | 1724 | sun4v_patch_tlb_handlers(); |
490384e7 DM |
1725 | sun4v_ktsb_init(); |
1726 | } | |
d257d5da | 1727 | |
3b2a7e23 DM |
1728 | lmb_init(); |
1729 | ||
a94a172d DM |
1730 | /* Find available physical memory... |
1731 | * | |
1732 | * Read it twice in order to work around a bug in openfirmware. | |
1733 | * The call to grab this table itself can cause openfirmware to | |
1734 | * allocate memory, which in turn can take away some space from | |
1735 | * the list of available memory. Reading it twice makes sure | |
1736 | * we really do get the final value. | |
1737 | */ | |
1738 | read_obp_translations(); | |
1739 | read_obp_memory("reg", &pall[0], &pall_ents); | |
1740 | read_obp_memory("available", &pavail[0], &pavail_ents); | |
13edad7a | 1741 | read_obp_memory("available", &pavail[0], &pavail_ents); |
0836a0eb DM |
1742 | |
1743 | phys_base = 0xffffffffffffffffUL; | |
3b2a7e23 | 1744 | for (i = 0; i < pavail_ents; i++) { |
13edad7a | 1745 | phys_base = min(phys_base, pavail[i].phys_addr); |
3b2a7e23 DM |
1746 | lmb_add(pavail[i].phys_addr, pavail[i].reg_size); |
1747 | } | |
1748 | ||
1749 | lmb_reserve(kern_base, kern_size); | |
0836a0eb | 1750 | |
4e82c9a6 DM |
1751 | find_ramdisk(phys_base); |
1752 | ||
f2b60794 | 1753 | lmb_enforce_memory_limit(cmdline_memory_size); |
25b0c659 | 1754 | |
3b2a7e23 DM |
1755 | lmb_analyze(); |
1756 | lmb_dump_all(); | |
1757 | ||
1da177e4 LT |
1758 | set_bit(0, mmu_context_bmap); |
1759 | ||
2bdb3cb2 DM |
1760 | shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); |
1761 | ||
1da177e4 | 1762 | real_end = (unsigned long)_end; |
64658743 DM |
1763 | num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22); |
1764 | printk("Kernel: Using %d locked TLB entries for main kernel image.\n", | |
1765 | num_kernel_image_mappings); | |
2bdb3cb2 DM |
1766 | |
1767 | /* Set kernel pgd to upper alias so physical page computations | |
1da177e4 LT |
1768 | * work. |
1769 | */ | |
1770 | init_mm.pgd += ((shift) / (sizeof(pgd_t))); | |
1771 | ||
56425306 | 1772 | memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir)); |
1da177e4 LT |
1773 | |
1774 | /* Now can init the kernel/bad page tables. */ | |
1775 | pud_set(pud_offset(&swapper_pg_dir[0], 0), | |
56425306 | 1776 | swapper_low_pmd_dir + (shift / sizeof(pgd_t))); |
1da177e4 | 1777 | |
c9c10830 | 1778 | inherit_prom_mappings(); |
5085b4a5 | 1779 | |
8f361453 DM |
1780 | init_kpte_bitmap(); |
1781 | ||
a8b900d8 DM |
1782 | /* Ok, we can use our TLB miss and window trap handlers safely. */ |
1783 | setup_tba(); | |
1da177e4 | 1784 | |
c9c10830 | 1785 | __flush_tlb_all(); |
9ad98c5b | 1786 | |
490384e7 DM |
1787 | if (tlb_type == hypervisor) |
1788 | sun4v_ktsb_register(); | |
1789 | ||
b9709456 DM |
1790 | /* We must setup the per-cpu areas before we pull in the |
1791 | * PROM and the MDESC. The code there fills in cpu and | |
1792 | * other information into per-cpu data structures. | |
1793 | */ | |
1794 | real_setup_per_cpu_areas(); | |
1795 | ||
ad072004 DM |
1796 | prom_build_devicetree(); |
1797 | ||
4a283339 DM |
1798 | if (tlb_type == hypervisor) |
1799 | sun4v_mdesc_init(); | |
1800 | ||
4f70f7a9 DM |
1801 | /* Once the OF device tree and MDESC have been setup, we know |
1802 | * the list of possible cpus. Therefore we can allocate the | |
1803 | * IRQ stacks. | |
1804 | */ | |
1805 | for_each_possible_cpu(i) { | |
1806 | /* XXX Use node local allocations... XXX */ | |
1807 | softirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); | |
1808 | hardirq_stack[i] = __va(lmb_alloc(THREAD_SIZE, THREAD_SIZE)); | |
1809 | } | |
1810 | ||
2bdb3cb2 | 1811 | /* Setup bootmem... */ |
919ee677 | 1812 | last_valid_pfn = end_pfn = bootmem_init(phys_base); |
d1112018 | 1813 | |
919ee677 | 1814 | #ifndef CONFIG_NEED_MULTIPLE_NODES |
17b0e199 | 1815 | max_mapnr = last_valid_pfn; |
919ee677 | 1816 | #endif |
56425306 | 1817 | kernel_physical_mapping_init(); |
56425306 | 1818 | |
1da177e4 | 1819 | { |
919ee677 | 1820 | unsigned long max_zone_pfns[MAX_NR_ZONES]; |
1da177e4 | 1821 | |
919ee677 | 1822 | memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); |
1da177e4 | 1823 | |
919ee677 | 1824 | max_zone_pfns[ZONE_NORMAL] = end_pfn; |
1da177e4 | 1825 | |
919ee677 | 1826 | free_area_init_nodes(max_zone_pfns); |
1da177e4 LT |
1827 | } |
1828 | ||
3c62a2d3 | 1829 | printk("Booting Linux...\n"); |
1da177e4 LT |
1830 | } |
1831 | ||
919ee677 DM |
1832 | int __init page_in_phys_avail(unsigned long paddr) |
1833 | { | |
1834 | int i; | |
1835 | ||
1836 | paddr &= PAGE_MASK; | |
1837 | ||
1838 | for (i = 0; i < pavail_ents; i++) { | |
1839 | unsigned long start, end; | |
1840 | ||
1841 | start = pavail[i].phys_addr; | |
1842 | end = start + pavail[i].reg_size; | |
1843 | ||
1844 | if (paddr >= start && paddr < end) | |
1845 | return 1; | |
1846 | } | |
1847 | if (paddr >= kern_base && paddr < (kern_base + kern_size)) | |
1848 | return 1; | |
1849 | #ifdef CONFIG_BLK_DEV_INITRD | |
1850 | if (paddr >= __pa(initrd_start) && | |
1851 | paddr < __pa(PAGE_ALIGN(initrd_end))) | |
1852 | return 1; | |
1853 | #endif | |
1854 | ||
1855 | return 0; | |
1856 | } | |
1857 | ||
1858 | static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata; | |
1859 | static int pavail_rescan_ents __initdata; | |
1860 | ||
1861 | /* Certain OBP calls, such as fetching "available" properties, can | |
1862 | * claim physical memory. So, along with initializing the valid | |
1863 | * address bitmap, what we do here is refetch the physical available | |
1864 | * memory list again, and make sure it provides at least as much | |
1865 | * memory as 'pavail' does. | |
1866 | */ | |
dbb8c35d | 1867 | static void __init setup_valid_addr_bitmap_from_pavail(void) |
1da177e4 | 1868 | { |
1da177e4 LT |
1869 | int i; |
1870 | ||
13edad7a | 1871 | read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents); |
1da177e4 | 1872 | |
13edad7a | 1873 | for (i = 0; i < pavail_ents; i++) { |
1da177e4 LT |
1874 | unsigned long old_start, old_end; |
1875 | ||
13edad7a | 1876 | old_start = pavail[i].phys_addr; |
919ee677 | 1877 | old_end = old_start + pavail[i].reg_size; |
1da177e4 LT |
1878 | while (old_start < old_end) { |
1879 | int n; | |
1880 | ||
c2a5a46b | 1881 | for (n = 0; n < pavail_rescan_ents; n++) { |
1da177e4 LT |
1882 | unsigned long new_start, new_end; |
1883 | ||
13edad7a DM |
1884 | new_start = pavail_rescan[n].phys_addr; |
1885 | new_end = new_start + | |
1886 | pavail_rescan[n].reg_size; | |
1da177e4 LT |
1887 | |
1888 | if (new_start <= old_start && | |
1889 | new_end >= (old_start + PAGE_SIZE)) { | |
13edad7a DM |
1890 | set_bit(old_start >> 22, |
1891 | sparc64_valid_addr_bitmap); | |
1da177e4 LT |
1892 | goto do_next_page; |
1893 | } | |
1894 | } | |
919ee677 DM |
1895 | |
1896 | prom_printf("mem_init: Lost memory in pavail\n"); | |
1897 | prom_printf("mem_init: OLD start[%lx] size[%lx]\n", | |
1898 | pavail[i].phys_addr, | |
1899 | pavail[i].reg_size); | |
1900 | prom_printf("mem_init: NEW start[%lx] size[%lx]\n", | |
1901 | pavail_rescan[i].phys_addr, | |
1902 | pavail_rescan[i].reg_size); | |
1903 | prom_printf("mem_init: Cannot continue, aborting.\n"); | |
1904 | prom_halt(); | |
1da177e4 LT |
1905 | |
1906 | do_next_page: | |
1907 | old_start += PAGE_SIZE; | |
1908 | } | |
1909 | } | |
1910 | } | |
1911 | ||
1912 | void __init mem_init(void) | |
1913 | { | |
1914 | unsigned long codepages, datapages, initpages; | |
1915 | unsigned long addr, last; | |
1916 | int i; | |
1917 | ||
1918 | i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6); | |
1919 | i += 1; | |
2bdb3cb2 | 1920 | sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3); |
1da177e4 LT |
1921 | if (sparc64_valid_addr_bitmap == NULL) { |
1922 | prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n"); | |
1923 | prom_halt(); | |
1924 | } | |
1925 | memset(sparc64_valid_addr_bitmap, 0, i << 3); | |
1926 | ||
1927 | addr = PAGE_OFFSET + kern_base; | |
1928 | last = PAGE_ALIGN(kern_size) + addr; | |
1929 | while (addr < last) { | |
1930 | set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap); | |
1931 | addr += PAGE_SIZE; | |
1932 | } | |
1933 | ||
919ee677 | 1934 | setup_valid_addr_bitmap_from_pavail(); |
1da177e4 | 1935 | |
1da177e4 LT |
1936 | high_memory = __va(last_valid_pfn << PAGE_SHIFT); |
1937 | ||
919ee677 DM |
1938 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
1939 | for_each_online_node(i) { | |
1940 | if (NODE_DATA(i)->node_spanned_pages != 0) { | |
1941 | totalram_pages += | |
1942 | free_all_bootmem_node(NODE_DATA(i)); | |
1943 | } | |
1944 | } | |
1945 | #else | |
1946 | totalram_pages = free_all_bootmem(); | |
1947 | #endif | |
1948 | ||
f1cfdb55 DM |
1949 | /* We subtract one to account for the mem_map_zero page |
1950 | * allocated below. | |
1951 | */ | |
919ee677 DM |
1952 | totalram_pages -= 1; |
1953 | num_physpages = totalram_pages; | |
1da177e4 LT |
1954 | |
1955 | /* | |
1956 | * Set up the zero page, mark it reserved, so that page count | |
1957 | * is not manipulated when freeing the page from user ptes. | |
1958 | */ | |
1959 | mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); | |
1960 | if (mem_map_zero == NULL) { | |
1961 | prom_printf("paging_init: Cannot alloc zero page.\n"); | |
1962 | prom_halt(); | |
1963 | } | |
1964 | SetPageReserved(mem_map_zero); | |
1965 | ||
1966 | codepages = (((unsigned long) _etext) - ((unsigned long) _start)); | |
1967 | codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT; | |
1968 | datapages = (((unsigned long) _edata) - ((unsigned long) _etext)); | |
1969 | datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT; | |
1970 | initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin)); | |
1971 | initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT; | |
1972 | ||
96177299 | 1973 | printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n", |
1da177e4 LT |
1974 | nr_free_pages() << (PAGE_SHIFT-10), |
1975 | codepages << (PAGE_SHIFT-10), | |
1976 | datapages << (PAGE_SHIFT-10), | |
1977 | initpages << (PAGE_SHIFT-10), | |
1978 | PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT)); | |
1979 | ||
1980 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
1981 | cheetah_ecache_flush_init(); | |
1982 | } | |
1983 | ||
898cf0ec | 1984 | void free_initmem(void) |
1da177e4 LT |
1985 | { |
1986 | unsigned long addr, initend; | |
f2b60794 DM |
1987 | int do_free = 1; |
1988 | ||
1989 | /* If the physical memory maps were trimmed by kernel command | |
1990 | * line options, don't even try freeing this initmem stuff up. | |
1991 | * The kernel image could have been in the trimmed out region | |
1992 | * and if so the freeing below will free invalid page structs. | |
1993 | */ | |
1994 | if (cmdline_memory_size) | |
1995 | do_free = 0; | |
1da177e4 LT |
1996 | |
1997 | /* | |
1998 | * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. | |
1999 | */ | |
2000 | addr = PAGE_ALIGN((unsigned long)(__init_begin)); | |
2001 | initend = (unsigned long)(__init_end) & PAGE_MASK; | |
2002 | for (; addr < initend; addr += PAGE_SIZE) { | |
2003 | unsigned long page; | |
2004 | struct page *p; | |
2005 | ||
2006 | page = (addr + | |
2007 | ((unsigned long) __va(kern_base)) - | |
2008 | ((unsigned long) KERNBASE)); | |
c9cf5528 | 2009 | memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); |
1da177e4 | 2010 | |
f2b60794 DM |
2011 | if (do_free) { |
2012 | p = virt_to_page(page); | |
2013 | ||
2014 | ClearPageReserved(p); | |
2015 | init_page_count(p); | |
2016 | __free_page(p); | |
2017 | num_physpages++; | |
2018 | totalram_pages++; | |
2019 | } | |
1da177e4 LT |
2020 | } |
2021 | } | |
2022 | ||
2023 | #ifdef CONFIG_BLK_DEV_INITRD | |
2024 | void free_initrd_mem(unsigned long start, unsigned long end) | |
2025 | { | |
2026 | if (start < end) | |
2027 | printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); | |
2028 | for (; start < end; start += PAGE_SIZE) { | |
2029 | struct page *p = virt_to_page(start); | |
2030 | ||
2031 | ClearPageReserved(p); | |
7835e98b | 2032 | init_page_count(p); |
1da177e4 LT |
2033 | __free_page(p); |
2034 | num_physpages++; | |
2035 | totalram_pages++; | |
2036 | } | |
2037 | } | |
2038 | #endif | |
c4bce90e | 2039 | |
c4bce90e DM |
2040 | #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) |
2041 | #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) | |
2042 | #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) | |
2043 | #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) | |
2044 | #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) | |
2045 | #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) | |
2046 | ||
2047 | pgprot_t PAGE_KERNEL __read_mostly; | |
2048 | EXPORT_SYMBOL(PAGE_KERNEL); | |
2049 | ||
2050 | pgprot_t PAGE_KERNEL_LOCKED __read_mostly; | |
2051 | pgprot_t PAGE_COPY __read_mostly; | |
0f15952a DM |
2052 | |
2053 | pgprot_t PAGE_SHARED __read_mostly; | |
2054 | EXPORT_SYMBOL(PAGE_SHARED); | |
2055 | ||
c4bce90e DM |
2056 | unsigned long pg_iobits __read_mostly; |
2057 | ||
2058 | unsigned long _PAGE_IE __read_mostly; | |
987c74fc | 2059 | EXPORT_SYMBOL(_PAGE_IE); |
b2bef442 | 2060 | |
c4bce90e | 2061 | unsigned long _PAGE_E __read_mostly; |
b2bef442 DM |
2062 | EXPORT_SYMBOL(_PAGE_E); |
2063 | ||
c4bce90e | 2064 | unsigned long _PAGE_CACHE __read_mostly; |
b2bef442 | 2065 | EXPORT_SYMBOL(_PAGE_CACHE); |
c4bce90e | 2066 | |
46644c24 | 2067 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
46644c24 DM |
2068 | unsigned long vmemmap_table[VMEMMAP_SIZE]; |
2069 | ||
2070 | int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node) | |
2071 | { | |
2072 | unsigned long vstart = (unsigned long) start; | |
2073 | unsigned long vend = (unsigned long) (start + nr); | |
2074 | unsigned long phys_start = (vstart - VMEMMAP_BASE); | |
2075 | unsigned long phys_end = (vend - VMEMMAP_BASE); | |
2076 | unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK; | |
2077 | unsigned long end = VMEMMAP_ALIGN(phys_end); | |
2078 | unsigned long pte_base; | |
2079 | ||
2080 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2081 | _PAGE_CP_4U | _PAGE_CV_4U | | |
2082 | _PAGE_P_4U | _PAGE_W_4U); | |
2083 | if (tlb_type == hypervisor) | |
2084 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
2085 | _PAGE_CP_4V | _PAGE_CV_4V | | |
2086 | _PAGE_P_4V | _PAGE_W_4V); | |
2087 | ||
2088 | for (; addr < end; addr += VMEMMAP_CHUNK) { | |
2089 | unsigned long *vmem_pp = | |
2090 | vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT); | |
2091 | void *block; | |
2092 | ||
2093 | if (!(*vmem_pp & _PAGE_VALID)) { | |
2094 | block = vmemmap_alloc_block(1UL << 22, node); | |
2095 | if (!block) | |
2096 | return -ENOMEM; | |
2097 | ||
2098 | *vmem_pp = pte_base | __pa(block); | |
2099 | ||
2100 | printk(KERN_INFO "[%p-%p] page_structs=%lu " | |
2101 | "node=%d entry=%lu/%lu\n", start, block, nr, | |
2102 | node, | |
2103 | addr >> VMEMMAP_CHUNK_SHIFT, | |
2104 | VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT); | |
2105 | } | |
2106 | } | |
2107 | return 0; | |
2108 | } | |
2109 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
2110 | ||
c4bce90e DM |
2111 | static void prot_init_common(unsigned long page_none, |
2112 | unsigned long page_shared, | |
2113 | unsigned long page_copy, | |
2114 | unsigned long page_readonly, | |
2115 | unsigned long page_exec_bit) | |
2116 | { | |
2117 | PAGE_COPY = __pgprot(page_copy); | |
0f15952a | 2118 | PAGE_SHARED = __pgprot(page_shared); |
c4bce90e DM |
2119 | |
2120 | protection_map[0x0] = __pgprot(page_none); | |
2121 | protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); | |
2122 | protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); | |
2123 | protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); | |
2124 | protection_map[0x4] = __pgprot(page_readonly); | |
2125 | protection_map[0x5] = __pgprot(page_readonly); | |
2126 | protection_map[0x6] = __pgprot(page_copy); | |
2127 | protection_map[0x7] = __pgprot(page_copy); | |
2128 | protection_map[0x8] = __pgprot(page_none); | |
2129 | protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); | |
2130 | protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); | |
2131 | protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); | |
2132 | protection_map[0xc] = __pgprot(page_readonly); | |
2133 | protection_map[0xd] = __pgprot(page_readonly); | |
2134 | protection_map[0xe] = __pgprot(page_shared); | |
2135 | protection_map[0xf] = __pgprot(page_shared); | |
2136 | } | |
2137 | ||
2138 | static void __init sun4u_pgprot_init(void) | |
2139 | { | |
2140 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2141 | unsigned long page_exec_bit; | |
2142 | ||
2143 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2144 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2145 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2146 | _PAGE_EXEC_4U); | |
2147 | PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2148 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2149 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2150 | _PAGE_EXEC_4U | _PAGE_L_4U); | |
c4bce90e DM |
2151 | |
2152 | _PAGE_IE = _PAGE_IE_4U; | |
2153 | _PAGE_E = _PAGE_E_4U; | |
2154 | _PAGE_CACHE = _PAGE_CACHE_4U; | |
2155 | ||
2156 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | | |
2157 | __ACCESS_BITS_4U | _PAGE_E_4U); | |
2158 | ||
d1acb421 DM |
2159 | #ifdef CONFIG_DEBUG_PAGEALLOC |
2160 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^ | |
af1ee569 | 2161 | 0xfffff80000000000UL; |
d1acb421 | 2162 | #else |
9cc3a1ac | 2163 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ |
af1ee569 | 2164 | 0xfffff80000000000UL; |
d1acb421 | 2165 | #endif |
9cc3a1ac DM |
2166 | kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | |
2167 | _PAGE_P_4U | _PAGE_W_4U); | |
2168 | ||
2169 | /* XXX Should use 256MB on Panther. XXX */ | |
2170 | kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; | |
c4bce90e DM |
2171 | |
2172 | _PAGE_SZBITS = _PAGE_SZBITS_4U; | |
2173 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | | |
2174 | _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | | |
2175 | _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); | |
2176 | ||
2177 | ||
2178 | page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; | |
2179 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2180 | __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); | |
2181 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2182 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2183 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2184 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2185 | ||
2186 | page_exec_bit = _PAGE_EXEC_4U; | |
2187 | ||
2188 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2189 | page_exec_bit); | |
2190 | } | |
2191 | ||
2192 | static void __init sun4v_pgprot_init(void) | |
2193 | { | |
2194 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2195 | unsigned long page_exec_bit; | |
2196 | ||
2197 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | | |
2198 | _PAGE_CACHE_4V | _PAGE_P_4V | | |
2199 | __ACCESS_BITS_4V | __DIRTY_BITS_4V | | |
2200 | _PAGE_EXEC_4V); | |
2201 | PAGE_KERNEL_LOCKED = PAGE_KERNEL; | |
c4bce90e DM |
2202 | |
2203 | _PAGE_IE = _PAGE_IE_4V; | |
2204 | _PAGE_E = _PAGE_E_4V; | |
2205 | _PAGE_CACHE = _PAGE_CACHE_4V; | |
2206 | ||
d1acb421 DM |
2207 | #ifdef CONFIG_DEBUG_PAGEALLOC |
2208 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ | |
af1ee569 | 2209 | 0xfffff80000000000UL; |
d1acb421 | 2210 | #else |
9cc3a1ac | 2211 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ |
af1ee569 | 2212 | 0xfffff80000000000UL; |
d1acb421 | 2213 | #endif |
9cc3a1ac DM |
2214 | kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
2215 | _PAGE_P_4V | _PAGE_W_4V); | |
2216 | ||
d1acb421 DM |
2217 | #ifdef CONFIG_DEBUG_PAGEALLOC |
2218 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ | |
af1ee569 | 2219 | 0xfffff80000000000UL; |
d1acb421 | 2220 | #else |
9cc3a1ac | 2221 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ |
af1ee569 | 2222 | 0xfffff80000000000UL; |
d1acb421 | 2223 | #endif |
9cc3a1ac DM |
2224 | kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
2225 | _PAGE_P_4V | _PAGE_W_4V); | |
c4bce90e DM |
2226 | |
2227 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | | |
2228 | __ACCESS_BITS_4V | _PAGE_E_4V); | |
2229 | ||
2230 | _PAGE_SZBITS = _PAGE_SZBITS_4V; | |
2231 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | | |
2232 | _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | | |
2233 | _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | | |
2234 | _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); | |
2235 | ||
2236 | page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V; | |
2237 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2238 | __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); | |
2239 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2240 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
2241 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2242 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
2243 | ||
2244 | page_exec_bit = _PAGE_EXEC_4V; | |
2245 | ||
2246 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2247 | page_exec_bit); | |
2248 | } | |
2249 | ||
2250 | unsigned long pte_sz_bits(unsigned long sz) | |
2251 | { | |
2252 | if (tlb_type == hypervisor) { | |
2253 | switch (sz) { | |
2254 | case 8 * 1024: | |
2255 | default: | |
2256 | return _PAGE_SZ8K_4V; | |
2257 | case 64 * 1024: | |
2258 | return _PAGE_SZ64K_4V; | |
2259 | case 512 * 1024: | |
2260 | return _PAGE_SZ512K_4V; | |
2261 | case 4 * 1024 * 1024: | |
2262 | return _PAGE_SZ4MB_4V; | |
2263 | }; | |
2264 | } else { | |
2265 | switch (sz) { | |
2266 | case 8 * 1024: | |
2267 | default: | |
2268 | return _PAGE_SZ8K_4U; | |
2269 | case 64 * 1024: | |
2270 | return _PAGE_SZ64K_4U; | |
2271 | case 512 * 1024: | |
2272 | return _PAGE_SZ512K_4U; | |
2273 | case 4 * 1024 * 1024: | |
2274 | return _PAGE_SZ4MB_4U; | |
2275 | }; | |
2276 | } | |
2277 | } | |
2278 | ||
2279 | pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) | |
2280 | { | |
2281 | pte_t pte; | |
cf627156 DM |
2282 | |
2283 | pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); | |
c4bce90e DM |
2284 | pte_val(pte) |= (((unsigned long)space) << 32); |
2285 | pte_val(pte) |= pte_sz_bits(page_size); | |
c4bce90e | 2286 | |
cf627156 | 2287 | return pte; |
c4bce90e DM |
2288 | } |
2289 | ||
2290 | static unsigned long kern_large_tte(unsigned long paddr) | |
2291 | { | |
2292 | unsigned long val; | |
2293 | ||
2294 | val = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2295 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | | |
2296 | _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); | |
2297 | if (tlb_type == hypervisor) | |
2298 | val = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
2299 | _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V | | |
2300 | _PAGE_EXEC_4V | _PAGE_W_4V); | |
2301 | ||
2302 | return val | paddr; | |
2303 | } | |
2304 | ||
c4bce90e DM |
2305 | /* If not locked, zap it. */ |
2306 | void __flush_tlb_all(void) | |
2307 | { | |
2308 | unsigned long pstate; | |
2309 | int i; | |
2310 | ||
2311 | __asm__ __volatile__("flushw\n\t" | |
2312 | "rdpr %%pstate, %0\n\t" | |
2313 | "wrpr %0, %1, %%pstate" | |
2314 | : "=r" (pstate) | |
2315 | : "i" (PSTATE_IE)); | |
8f361453 DM |
2316 | if (tlb_type == hypervisor) { |
2317 | sun4v_mmu_demap_all(); | |
2318 | } else if (tlb_type == spitfire) { | |
c4bce90e DM |
2319 | for (i = 0; i < 64; i++) { |
2320 | /* Spitfire Errata #32 workaround */ | |
2321 | /* NOTE: Always runs on spitfire, so no | |
2322 | * cheetah+ page size encodings. | |
2323 | */ | |
2324 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2325 | "flush %%g6" | |
2326 | : /* No outputs */ | |
2327 | : "r" (0), | |
2328 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2329 | ||
2330 | if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { | |
2331 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2332 | "membar #Sync" | |
2333 | : /* no outputs */ | |
2334 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); | |
2335 | spitfire_put_dtlb_data(i, 0x0UL); | |
2336 | } | |
2337 | ||
2338 | /* Spitfire Errata #32 workaround */ | |
2339 | /* NOTE: Always runs on spitfire, so no | |
2340 | * cheetah+ page size encodings. | |
2341 | */ | |
2342 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2343 | "flush %%g6" | |
2344 | : /* No outputs */ | |
2345 | : "r" (0), | |
2346 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2347 | ||
2348 | if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { | |
2349 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2350 | "membar #Sync" | |
2351 | : /* no outputs */ | |
2352 | : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); | |
2353 | spitfire_put_itlb_data(i, 0x0UL); | |
2354 | } | |
2355 | } | |
2356 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
2357 | cheetah_flush_dtlb_all(); | |
2358 | cheetah_flush_itlb_all(); | |
2359 | } | |
2360 | __asm__ __volatile__("wrpr %0, 0, %%pstate" | |
2361 | : : "r" (pstate)); | |
2362 | } |