Commit | Line | Data |
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1da177e4 LT |
1 | /* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $ |
2 | * arch/sparc64/mm/init.c | |
3 | * | |
4 | * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
c4bce90e | 8 | #include <linux/module.h> |
1da177e4 LT |
9 | #include <linux/kernel.h> |
10 | #include <linux/sched.h> | |
11 | #include <linux/string.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/bootmem.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/hugetlb.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/initrd.h> | |
18 | #include <linux/swap.h> | |
19 | #include <linux/pagemap.h> | |
c9cf5528 | 20 | #include <linux/poison.h> |
1da177e4 LT |
21 | #include <linux/fs.h> |
22 | #include <linux/seq_file.h> | |
05e14cb3 | 23 | #include <linux/kprobes.h> |
1ac4f5eb | 24 | #include <linux/cache.h> |
13edad7a | 25 | #include <linux/sort.h> |
5cbc3073 | 26 | #include <linux/percpu.h> |
3b2a7e23 | 27 | #include <linux/lmb.h> |
919ee677 | 28 | #include <linux/mmzone.h> |
1da177e4 LT |
29 | |
30 | #include <asm/head.h> | |
31 | #include <asm/system.h> | |
32 | #include <asm/page.h> | |
33 | #include <asm/pgalloc.h> | |
34 | #include <asm/pgtable.h> | |
35 | #include <asm/oplib.h> | |
36 | #include <asm/iommu.h> | |
37 | #include <asm/io.h> | |
38 | #include <asm/uaccess.h> | |
39 | #include <asm/mmu_context.h> | |
40 | #include <asm/tlbflush.h> | |
41 | #include <asm/dma.h> | |
42 | #include <asm/starfire.h> | |
43 | #include <asm/tlb.h> | |
44 | #include <asm/spitfire.h> | |
45 | #include <asm/sections.h> | |
517af332 | 46 | #include <asm/tsb.h> |
481295f9 | 47 | #include <asm/hypervisor.h> |
372b07bb | 48 | #include <asm/prom.h> |
22d6a1cb | 49 | #include <asm/sstate.h> |
5cbc3073 | 50 | #include <asm/mdesc.h> |
3d5ae6b6 | 51 | #include <asm/cpudata.h> |
1da177e4 | 52 | |
9cc3a1ac DM |
53 | #define MAX_PHYS_ADDRESS (1UL << 42UL) |
54 | #define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL) | |
55 | #define KPTE_BITMAP_BYTES \ | |
56 | ((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 8) | |
57 | ||
58 | unsigned long kern_linear_pte_xor[2] __read_mostly; | |
59 | ||
60 | /* A bitmap, one bit for every 256MB of physical memory. If the bit | |
61 | * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else | |
62 | * if set we should use a 256MB page (via kern_linear_pte_xor[1]). | |
63 | */ | |
64 | unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)]; | |
65 | ||
d1acb421 | 66 | #ifndef CONFIG_DEBUG_PAGEALLOC |
2d9e2763 DM |
67 | /* A special kernel TSB for 4MB and 256MB linear mappings. |
68 | * Space is allocated for this right after the trap table | |
69 | * in arch/sparc64/kernel/head.S | |
70 | */ | |
71 | extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; | |
d1acb421 | 72 | #endif |
d7744a09 | 73 | |
13edad7a DM |
74 | #define MAX_BANKS 32 |
75 | ||
76 | static struct linux_prom64_registers pavail[MAX_BANKS] __initdata; | |
13edad7a | 77 | static int pavail_ents __initdata; |
13edad7a DM |
78 | |
79 | static int cmp_p64(const void *a, const void *b) | |
80 | { | |
81 | const struct linux_prom64_registers *x = a, *y = b; | |
82 | ||
83 | if (x->phys_addr > y->phys_addr) | |
84 | return 1; | |
85 | if (x->phys_addr < y->phys_addr) | |
86 | return -1; | |
87 | return 0; | |
88 | } | |
89 | ||
90 | static void __init read_obp_memory(const char *property, | |
91 | struct linux_prom64_registers *regs, | |
92 | int *num_ents) | |
93 | { | |
94 | int node = prom_finddevice("/memory"); | |
95 | int prop_size = prom_getproplen(node, property); | |
96 | int ents, ret, i; | |
97 | ||
98 | ents = prop_size / sizeof(struct linux_prom64_registers); | |
99 | if (ents > MAX_BANKS) { | |
100 | prom_printf("The machine has more %s property entries than " | |
101 | "this kernel can support (%d).\n", | |
102 | property, MAX_BANKS); | |
103 | prom_halt(); | |
104 | } | |
105 | ||
106 | ret = prom_getproperty(node, property, (char *) regs, prop_size); | |
107 | if (ret == -1) { | |
108 | prom_printf("Couldn't get %s property from /memory.\n"); | |
109 | prom_halt(); | |
110 | } | |
111 | ||
13edad7a DM |
112 | /* Sanitize what we got from the firmware, by page aligning |
113 | * everything. | |
114 | */ | |
115 | for (i = 0; i < ents; i++) { | |
116 | unsigned long base, size; | |
117 | ||
118 | base = regs[i].phys_addr; | |
119 | size = regs[i].reg_size; | |
10147570 | 120 | |
13edad7a DM |
121 | size &= PAGE_MASK; |
122 | if (base & ~PAGE_MASK) { | |
123 | unsigned long new_base = PAGE_ALIGN(base); | |
124 | ||
125 | size -= new_base - base; | |
126 | if ((long) size < 0L) | |
127 | size = 0UL; | |
128 | base = new_base; | |
129 | } | |
0015d3d6 DM |
130 | if (size == 0UL) { |
131 | /* If it is empty, simply get rid of it. | |
132 | * This simplifies the logic of the other | |
133 | * functions that process these arrays. | |
134 | */ | |
135 | memmove(®s[i], ®s[i + 1], | |
136 | (ents - i - 1) * sizeof(regs[0])); | |
486ad10a | 137 | i--; |
0015d3d6 DM |
138 | ents--; |
139 | continue; | |
486ad10a | 140 | } |
0015d3d6 DM |
141 | regs[i].phys_addr = base; |
142 | regs[i].reg_size = size; | |
486ad10a DM |
143 | } |
144 | ||
145 | *num_ents = ents; | |
146 | ||
c9c10830 | 147 | sort(regs, ents, sizeof(struct linux_prom64_registers), |
13edad7a DM |
148 | cmp_p64, NULL); |
149 | } | |
1da177e4 | 150 | |
2bdb3cb2 | 151 | unsigned long *sparc64_valid_addr_bitmap __read_mostly; |
1da177e4 | 152 | |
d1112018 | 153 | /* Kernel physical address base and size in bytes. */ |
1ac4f5eb DM |
154 | unsigned long kern_base __read_mostly; |
155 | unsigned long kern_size __read_mostly; | |
1da177e4 | 156 | |
1da177e4 LT |
157 | /* Initial ramdisk setup */ |
158 | extern unsigned long sparc_ramdisk_image64; | |
159 | extern unsigned int sparc_ramdisk_image; | |
160 | extern unsigned int sparc_ramdisk_size; | |
161 | ||
1ac4f5eb | 162 | struct page *mem_map_zero __read_mostly; |
35802c0b | 163 | EXPORT_SYMBOL(mem_map_zero); |
1da177e4 | 164 | |
0835ae0f DM |
165 | unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; |
166 | ||
167 | unsigned long sparc64_kern_pri_context __read_mostly; | |
168 | unsigned long sparc64_kern_pri_nuc_bits __read_mostly; | |
169 | unsigned long sparc64_kern_sec_context __read_mostly; | |
170 | ||
64658743 | 171 | int num_kernel_image_mappings; |
1da177e4 | 172 | |
1da177e4 LT |
173 | #ifdef CONFIG_DEBUG_DCFLUSH |
174 | atomic_t dcpage_flushes = ATOMIC_INIT(0); | |
175 | #ifdef CONFIG_SMP | |
176 | atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); | |
177 | #endif | |
178 | #endif | |
179 | ||
7a591cfe | 180 | inline void flush_dcache_page_impl(struct page *page) |
1da177e4 | 181 | { |
7a591cfe | 182 | BUG_ON(tlb_type == hypervisor); |
1da177e4 LT |
183 | #ifdef CONFIG_DEBUG_DCFLUSH |
184 | atomic_inc(&dcpage_flushes); | |
185 | #endif | |
186 | ||
187 | #ifdef DCACHE_ALIASING_POSSIBLE | |
188 | __flush_dcache_page(page_address(page), | |
189 | ((tlb_type == spitfire) && | |
190 | page_mapping(page) != NULL)); | |
191 | #else | |
192 | if (page_mapping(page) != NULL && | |
193 | tlb_type == spitfire) | |
194 | __flush_icache_page(__pa(page_address(page))); | |
195 | #endif | |
196 | } | |
197 | ||
198 | #define PG_dcache_dirty PG_arch_1 | |
22adb358 DM |
199 | #define PG_dcache_cpu_shift 32UL |
200 | #define PG_dcache_cpu_mask \ | |
201 | ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) | |
1da177e4 LT |
202 | |
203 | #define dcache_dirty_cpu(page) \ | |
48b0e548 | 204 | (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) |
1da177e4 | 205 | |
d979f179 | 206 | static inline void set_dcache_dirty(struct page *page, int this_cpu) |
1da177e4 LT |
207 | { |
208 | unsigned long mask = this_cpu; | |
48b0e548 DM |
209 | unsigned long non_cpu_bits; |
210 | ||
211 | non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); | |
212 | mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); | |
213 | ||
1da177e4 LT |
214 | __asm__ __volatile__("1:\n\t" |
215 | "ldx [%2], %%g7\n\t" | |
216 | "and %%g7, %1, %%g1\n\t" | |
217 | "or %%g1, %0, %%g1\n\t" | |
218 | "casx [%2], %%g7, %%g1\n\t" | |
219 | "cmp %%g7, %%g1\n\t" | |
b445e26c | 220 | "membar #StoreLoad | #StoreStore\n\t" |
1da177e4 | 221 | "bne,pn %%xcc, 1b\n\t" |
b445e26c | 222 | " nop" |
1da177e4 LT |
223 | : /* no outputs */ |
224 | : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) | |
225 | : "g1", "g7"); | |
226 | } | |
227 | ||
d979f179 | 228 | static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) |
1da177e4 LT |
229 | { |
230 | unsigned long mask = (1UL << PG_dcache_dirty); | |
231 | ||
232 | __asm__ __volatile__("! test_and_clear_dcache_dirty\n" | |
233 | "1:\n\t" | |
234 | "ldx [%2], %%g7\n\t" | |
48b0e548 | 235 | "srlx %%g7, %4, %%g1\n\t" |
1da177e4 LT |
236 | "and %%g1, %3, %%g1\n\t" |
237 | "cmp %%g1, %0\n\t" | |
238 | "bne,pn %%icc, 2f\n\t" | |
239 | " andn %%g7, %1, %%g1\n\t" | |
240 | "casx [%2], %%g7, %%g1\n\t" | |
241 | "cmp %%g7, %%g1\n\t" | |
b445e26c | 242 | "membar #StoreLoad | #StoreStore\n\t" |
1da177e4 | 243 | "bne,pn %%xcc, 1b\n\t" |
b445e26c | 244 | " nop\n" |
1da177e4 LT |
245 | "2:" |
246 | : /* no outputs */ | |
247 | : "r" (cpu), "r" (mask), "r" (&page->flags), | |
48b0e548 DM |
248 | "i" (PG_dcache_cpu_mask), |
249 | "i" (PG_dcache_cpu_shift) | |
1da177e4 LT |
250 | : "g1", "g7"); |
251 | } | |
252 | ||
517af332 DM |
253 | static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) |
254 | { | |
255 | unsigned long tsb_addr = (unsigned long) ent; | |
256 | ||
3b3ab2eb | 257 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) |
517af332 DM |
258 | tsb_addr = __pa(tsb_addr); |
259 | ||
260 | __tsb_insert(tsb_addr, tag, pte); | |
261 | } | |
262 | ||
c4bce90e DM |
263 | unsigned long _PAGE_ALL_SZ_BITS __read_mostly; |
264 | unsigned long _PAGE_SZBITS __read_mostly; | |
265 | ||
1da177e4 LT |
266 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte) |
267 | { | |
bd40791e | 268 | struct mm_struct *mm; |
74ae9987 | 269 | struct tsb *tsb; |
7a1ac526 | 270 | unsigned long tag, flags; |
dcc1e8dd | 271 | unsigned long tsb_index, tsb_hash_shift; |
7a591cfe DM |
272 | |
273 | if (tlb_type != hypervisor) { | |
274 | unsigned long pfn = pte_pfn(pte); | |
275 | unsigned long pg_flags; | |
276 | struct page *page; | |
277 | ||
278 | if (pfn_valid(pfn) && | |
279 | (page = pfn_to_page(pfn), page_mapping(page)) && | |
280 | ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) { | |
281 | int cpu = ((pg_flags >> PG_dcache_cpu_shift) & | |
282 | PG_dcache_cpu_mask); | |
283 | int this_cpu = get_cpu(); | |
284 | ||
285 | /* This is just to optimize away some function calls | |
286 | * in the SMP case. | |
287 | */ | |
288 | if (cpu == this_cpu) | |
289 | flush_dcache_page_impl(page); | |
290 | else | |
291 | smp_flush_dcache_page_impl(page, cpu); | |
292 | ||
293 | clear_dcache_dirty_cpu(page, cpu); | |
294 | ||
295 | put_cpu(); | |
296 | } | |
1da177e4 | 297 | } |
bd40791e DM |
298 | |
299 | mm = vma->vm_mm; | |
7a1ac526 | 300 | |
dcc1e8dd DM |
301 | tsb_index = MM_TSB_BASE; |
302 | tsb_hash_shift = PAGE_SHIFT; | |
303 | ||
7a1ac526 DM |
304 | spin_lock_irqsave(&mm->context.lock, flags); |
305 | ||
dcc1e8dd DM |
306 | #ifdef CONFIG_HUGETLB_PAGE |
307 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) { | |
308 | if ((tlb_type == hypervisor && | |
309 | (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) || | |
310 | (tlb_type != hypervisor && | |
311 | (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) { | |
312 | tsb_index = MM_TSB_HUGE; | |
313 | tsb_hash_shift = HPAGE_SHIFT; | |
314 | } | |
315 | } | |
316 | #endif | |
317 | ||
318 | tsb = mm->context.tsb_block[tsb_index].tsb; | |
319 | tsb += ((address >> tsb_hash_shift) & | |
320 | (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); | |
74ae9987 DM |
321 | tag = (address >> 22UL); |
322 | tsb_insert(tsb, tag, pte_val(pte)); | |
7a1ac526 DM |
323 | |
324 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
1da177e4 LT |
325 | } |
326 | ||
327 | void flush_dcache_page(struct page *page) | |
328 | { | |
a9546f59 DM |
329 | struct address_space *mapping; |
330 | int this_cpu; | |
1da177e4 | 331 | |
7a591cfe DM |
332 | if (tlb_type == hypervisor) |
333 | return; | |
334 | ||
a9546f59 DM |
335 | /* Do not bother with the expensive D-cache flush if it |
336 | * is merely the zero page. The 'bigcore' testcase in GDB | |
337 | * causes this case to run millions of times. | |
338 | */ | |
339 | if (page == ZERO_PAGE(0)) | |
340 | return; | |
341 | ||
342 | this_cpu = get_cpu(); | |
343 | ||
344 | mapping = page_mapping(page); | |
1da177e4 | 345 | if (mapping && !mapping_mapped(mapping)) { |
a9546f59 | 346 | int dirty = test_bit(PG_dcache_dirty, &page->flags); |
1da177e4 | 347 | if (dirty) { |
a9546f59 DM |
348 | int dirty_cpu = dcache_dirty_cpu(page); |
349 | ||
1da177e4 LT |
350 | if (dirty_cpu == this_cpu) |
351 | goto out; | |
352 | smp_flush_dcache_page_impl(page, dirty_cpu); | |
353 | } | |
354 | set_dcache_dirty(page, this_cpu); | |
355 | } else { | |
356 | /* We could delay the flush for the !page_mapping | |
357 | * case too. But that case is for exec env/arg | |
358 | * pages and those are %99 certainly going to get | |
359 | * faulted into the tlb (and thus flushed) anyways. | |
360 | */ | |
361 | flush_dcache_page_impl(page); | |
362 | } | |
363 | ||
364 | out: | |
365 | put_cpu(); | |
366 | } | |
367 | ||
05e14cb3 | 368 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 369 | { |
a43fe0e7 | 370 | /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ |
1da177e4 LT |
371 | if (tlb_type == spitfire) { |
372 | unsigned long kaddr; | |
373 | ||
a94aa253 DM |
374 | /* This code only runs on Spitfire cpus so this is |
375 | * why we can assume _PAGE_PADDR_4U. | |
376 | */ | |
377 | for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { | |
378 | unsigned long paddr, mask = _PAGE_PADDR_4U; | |
379 | ||
380 | if (kaddr >= PAGE_OFFSET) | |
381 | paddr = kaddr & mask; | |
382 | else { | |
383 | pgd_t *pgdp = pgd_offset_k(kaddr); | |
384 | pud_t *pudp = pud_offset(pgdp, kaddr); | |
385 | pmd_t *pmdp = pmd_offset(pudp, kaddr); | |
386 | pte_t *ptep = pte_offset_kernel(pmdp, kaddr); | |
387 | ||
388 | paddr = pte_val(*ptep) & mask; | |
389 | } | |
390 | __flush_icache_page(paddr); | |
391 | } | |
1da177e4 LT |
392 | } |
393 | } | |
394 | ||
1da177e4 LT |
395 | void show_mem(void) |
396 | { | |
5be4a963 DM |
397 | unsigned long total = 0, reserved = 0; |
398 | unsigned long shared = 0, cached = 0; | |
399 | pg_data_t *pgdat; | |
400 | ||
28256ca2 | 401 | printk(KERN_INFO "Mem-info:\n"); |
1da177e4 | 402 | show_free_areas(); |
28256ca2 | 403 | printk(KERN_INFO "Free swap: %6ldkB\n", |
1da177e4 | 404 | nr_swap_pages << (PAGE_SHIFT-10)); |
5be4a963 DM |
405 | for_each_online_pgdat(pgdat) { |
406 | unsigned long i, flags; | |
407 | ||
408 | pgdat_resize_lock(pgdat, &flags); | |
409 | for (i = 0; i < pgdat->node_spanned_pages; i++) { | |
410 | struct page *page = pgdat_page_nr(pgdat, i); | |
411 | total++; | |
412 | if (PageReserved(page)) | |
413 | reserved++; | |
414 | else if (PageSwapCache(page)) | |
415 | cached++; | |
416 | else if (page_count(page)) | |
417 | shared += page_count(page) - 1; | |
418 | } | |
419 | pgdat_resize_unlock(pgdat, &flags); | |
420 | } | |
421 | ||
422 | printk(KERN_INFO "%lu pages of RAM\n", total); | |
423 | printk(KERN_INFO "%lu reserved pages\n", reserved); | |
424 | printk(KERN_INFO "%lu pages shared\n", shared); | |
425 | printk(KERN_INFO "%lu pages swap cached\n", cached); | |
426 | ||
427 | printk(KERN_INFO "%lu pages dirty\n", | |
428 | global_page_state(NR_FILE_DIRTY)); | |
429 | printk(KERN_INFO "%lu pages writeback\n", | |
430 | global_page_state(NR_WRITEBACK)); | |
431 | printk(KERN_INFO "%lu pages mapped\n", | |
432 | global_page_state(NR_FILE_MAPPED)); | |
433 | printk(KERN_INFO "%lu pages slab\n", | |
434 | global_page_state(NR_SLAB_RECLAIMABLE) + | |
435 | global_page_state(NR_SLAB_UNRECLAIMABLE)); | |
436 | printk(KERN_INFO "%lu pages pagetables\n", | |
437 | global_page_state(NR_PAGETABLE)); | |
1da177e4 LT |
438 | } |
439 | ||
440 | void mmu_info(struct seq_file *m) | |
441 | { | |
442 | if (tlb_type == cheetah) | |
443 | seq_printf(m, "MMU Type\t: Cheetah\n"); | |
444 | else if (tlb_type == cheetah_plus) | |
445 | seq_printf(m, "MMU Type\t: Cheetah+\n"); | |
446 | else if (tlb_type == spitfire) | |
447 | seq_printf(m, "MMU Type\t: Spitfire\n"); | |
a43fe0e7 DM |
448 | else if (tlb_type == hypervisor) |
449 | seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); | |
1da177e4 LT |
450 | else |
451 | seq_printf(m, "MMU Type\t: ???\n"); | |
452 | ||
453 | #ifdef CONFIG_DEBUG_DCFLUSH | |
454 | seq_printf(m, "DCPageFlushes\t: %d\n", | |
455 | atomic_read(&dcpage_flushes)); | |
456 | #ifdef CONFIG_SMP | |
457 | seq_printf(m, "DCPageFlushesXC\t: %d\n", | |
458 | atomic_read(&dcpage_flushes_xcall)); | |
459 | #endif /* CONFIG_SMP */ | |
460 | #endif /* CONFIG_DEBUG_DCFLUSH */ | |
461 | } | |
462 | ||
a94aa253 DM |
463 | struct linux_prom_translation { |
464 | unsigned long virt; | |
465 | unsigned long size; | |
466 | unsigned long data; | |
467 | }; | |
468 | ||
469 | /* Exported for kernel TLB miss handling in ktlb.S */ | |
470 | struct linux_prom_translation prom_trans[512] __read_mostly; | |
471 | unsigned int prom_trans_ents __read_mostly; | |
472 | ||
1da177e4 LT |
473 | /* Exported for SMP bootup purposes. */ |
474 | unsigned long kern_locked_tte_data; | |
475 | ||
c9c10830 DM |
476 | /* The obp translations are saved based on 8k pagesize, since obp can |
477 | * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> | |
74bf4312 | 478 | * HI_OBP_ADDRESS range are handled in ktlb.S. |
c9c10830 | 479 | */ |
5085b4a5 DM |
480 | static inline int in_obp_range(unsigned long vaddr) |
481 | { | |
482 | return (vaddr >= LOW_OBP_ADDRESS && | |
483 | vaddr < HI_OBP_ADDRESS); | |
484 | } | |
485 | ||
c9c10830 | 486 | static int cmp_ptrans(const void *a, const void *b) |
405599bd | 487 | { |
c9c10830 | 488 | const struct linux_prom_translation *x = a, *y = b; |
405599bd | 489 | |
c9c10830 DM |
490 | if (x->virt > y->virt) |
491 | return 1; | |
492 | if (x->virt < y->virt) | |
493 | return -1; | |
494 | return 0; | |
405599bd DM |
495 | } |
496 | ||
c9c10830 | 497 | /* Read OBP translations property into 'prom_trans[]'. */ |
9ad98c5b | 498 | static void __init read_obp_translations(void) |
405599bd | 499 | { |
c9c10830 | 500 | int n, node, ents, first, last, i; |
1da177e4 LT |
501 | |
502 | node = prom_finddevice("/virtual-memory"); | |
503 | n = prom_getproplen(node, "translations"); | |
405599bd | 504 | if (unlikely(n == 0 || n == -1)) { |
b206fc4c | 505 | prom_printf("prom_mappings: Couldn't get size.\n"); |
1da177e4 LT |
506 | prom_halt(); |
507 | } | |
405599bd DM |
508 | if (unlikely(n > sizeof(prom_trans))) { |
509 | prom_printf("prom_mappings: Size %Zd is too big.\n", n); | |
1da177e4 LT |
510 | prom_halt(); |
511 | } | |
405599bd | 512 | |
b206fc4c | 513 | if ((n = prom_getproperty(node, "translations", |
405599bd DM |
514 | (char *)&prom_trans[0], |
515 | sizeof(prom_trans))) == -1) { | |
b206fc4c | 516 | prom_printf("prom_mappings: Couldn't get property.\n"); |
1da177e4 LT |
517 | prom_halt(); |
518 | } | |
9ad98c5b | 519 | |
b206fc4c | 520 | n = n / sizeof(struct linux_prom_translation); |
9ad98c5b | 521 | |
c9c10830 DM |
522 | ents = n; |
523 | ||
524 | sort(prom_trans, ents, sizeof(struct linux_prom_translation), | |
525 | cmp_ptrans, NULL); | |
526 | ||
527 | /* Now kick out all the non-OBP entries. */ | |
528 | for (i = 0; i < ents; i++) { | |
529 | if (in_obp_range(prom_trans[i].virt)) | |
530 | break; | |
531 | } | |
532 | first = i; | |
533 | for (; i < ents; i++) { | |
534 | if (!in_obp_range(prom_trans[i].virt)) | |
535 | break; | |
536 | } | |
537 | last = i; | |
538 | ||
539 | for (i = 0; i < (last - first); i++) { | |
540 | struct linux_prom_translation *src = &prom_trans[i + first]; | |
541 | struct linux_prom_translation *dest = &prom_trans[i]; | |
542 | ||
543 | *dest = *src; | |
544 | } | |
545 | for (; i < ents; i++) { | |
546 | struct linux_prom_translation *dest = &prom_trans[i]; | |
547 | dest->virt = dest->size = dest->data = 0x0UL; | |
548 | } | |
549 | ||
550 | prom_trans_ents = last - first; | |
551 | ||
552 | if (tlb_type == spitfire) { | |
553 | /* Clear diag TTE bits. */ | |
554 | for (i = 0; i < prom_trans_ents; i++) | |
555 | prom_trans[i].data &= ~0x0003fe0000000000UL; | |
556 | } | |
405599bd | 557 | } |
1da177e4 | 558 | |
d82ace7d DM |
559 | static void __init hypervisor_tlb_lock(unsigned long vaddr, |
560 | unsigned long pte, | |
561 | unsigned long mmu) | |
562 | { | |
7db35f31 DM |
563 | unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); |
564 | ||
565 | if (ret != 0) { | |
12e126ad | 566 | prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: " |
7db35f31 | 567 | "errors with %lx\n", vaddr, 0, pte, mmu, ret); |
12e126ad DM |
568 | prom_halt(); |
569 | } | |
d82ace7d DM |
570 | } |
571 | ||
c4bce90e DM |
572 | static unsigned long kern_large_tte(unsigned long paddr); |
573 | ||
898cf0ec | 574 | static void __init remap_kernel(void) |
405599bd DM |
575 | { |
576 | unsigned long phys_page, tte_vaddr, tte_data; | |
64658743 | 577 | int i, tlb_ent = sparc64_highest_locked_tlbent(); |
405599bd | 578 | |
1da177e4 | 579 | tte_vaddr = (unsigned long) KERNBASE; |
bff06d55 | 580 | phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL; |
c4bce90e | 581 | tte_data = kern_large_tte(phys_page); |
1da177e4 LT |
582 | |
583 | kern_locked_tte_data = tte_data; | |
584 | ||
d82ace7d DM |
585 | /* Now lock us into the TLBs via Hypervisor or OBP. */ |
586 | if (tlb_type == hypervisor) { | |
64658743 | 587 | for (i = 0; i < num_kernel_image_mappings; i++) { |
d82ace7d DM |
588 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); |
589 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); | |
64658743 DM |
590 | tte_vaddr += 0x400000; |
591 | tte_data += 0x400000; | |
d82ace7d DM |
592 | } |
593 | } else { | |
64658743 DM |
594 | for (i = 0; i < num_kernel_image_mappings; i++) { |
595 | prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
596 | prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
597 | tte_vaddr += 0x400000; | |
598 | tte_data += 0x400000; | |
d82ace7d | 599 | } |
64658743 | 600 | sparc64_highest_unlocked_tlb_ent = tlb_ent - i; |
1da177e4 | 601 | } |
0835ae0f DM |
602 | if (tlb_type == cheetah_plus) { |
603 | sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | | |
604 | CTX_CHEETAH_PLUS_NUC); | |
605 | sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; | |
606 | sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; | |
607 | } | |
405599bd | 608 | } |
1da177e4 | 609 | |
405599bd | 610 | |
c9c10830 | 611 | static void __init inherit_prom_mappings(void) |
9ad98c5b DM |
612 | { |
613 | read_obp_translations(); | |
405599bd DM |
614 | |
615 | /* Now fixup OBP's idea about where we really are mapped. */ | |
3c62a2d3 | 616 | printk("Remapping the kernel... "); |
405599bd | 617 | remap_kernel(); |
3c62a2d3 | 618 | printk("done.\n"); |
1da177e4 LT |
619 | } |
620 | ||
1da177e4 LT |
621 | void prom_world(int enter) |
622 | { | |
1da177e4 LT |
623 | if (!enter) |
624 | set_fs((mm_segment_t) { get_thread_current_ds() }); | |
625 | ||
3487d1d4 | 626 | __asm__ __volatile__("flushw"); |
1da177e4 LT |
627 | } |
628 | ||
1da177e4 LT |
629 | void __flush_dcache_range(unsigned long start, unsigned long end) |
630 | { | |
631 | unsigned long va; | |
632 | ||
633 | if (tlb_type == spitfire) { | |
634 | int n = 0; | |
635 | ||
636 | for (va = start; va < end; va += 32) { | |
637 | spitfire_put_dcache_tag(va & 0x3fe0, 0x0); | |
638 | if (++n >= 512) | |
639 | break; | |
640 | } | |
a43fe0e7 | 641 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
642 | start = __pa(start); |
643 | end = __pa(end); | |
644 | for (va = start; va < end; va += 32) | |
645 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
646 | "membar #Sync" | |
647 | : /* no outputs */ | |
648 | : "r" (va), | |
649 | "i" (ASI_DCACHE_INVALIDATE)); | |
650 | } | |
651 | } | |
1da177e4 | 652 | |
85f1e1f6 DM |
653 | /* get_new_mmu_context() uses "cache + 1". */ |
654 | DEFINE_SPINLOCK(ctx_alloc_lock); | |
655 | unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1; | |
656 | #define MAX_CTX_NR (1UL << CTX_NR_BITS) | |
657 | #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) | |
658 | DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); | |
659 | ||
1da177e4 LT |
660 | /* Caller does TLB context flushing on local CPU if necessary. |
661 | * The caller also ensures that CTX_VALID(mm->context) is false. | |
662 | * | |
663 | * We must be careful about boundary cases so that we never | |
664 | * let the user have CTX 0 (nucleus) or we ever use a CTX | |
665 | * version of zero (and thus NO_CONTEXT would not be caught | |
666 | * by version mis-match tests in mmu_context.h). | |
a0663a79 DM |
667 | * |
668 | * Always invoked with interrupts disabled. | |
1da177e4 LT |
669 | */ |
670 | void get_new_mmu_context(struct mm_struct *mm) | |
671 | { | |
672 | unsigned long ctx, new_ctx; | |
673 | unsigned long orig_pgsz_bits; | |
a77754b4 | 674 | unsigned long flags; |
a0663a79 | 675 | int new_version; |
1da177e4 | 676 | |
a77754b4 | 677 | spin_lock_irqsave(&ctx_alloc_lock, flags); |
1da177e4 LT |
678 | orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); |
679 | ctx = (tlb_context_cache + 1) & CTX_NR_MASK; | |
680 | new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); | |
a0663a79 | 681 | new_version = 0; |
1da177e4 LT |
682 | if (new_ctx >= (1 << CTX_NR_BITS)) { |
683 | new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); | |
684 | if (new_ctx >= ctx) { | |
685 | int i; | |
686 | new_ctx = (tlb_context_cache & CTX_VERSION_MASK) + | |
687 | CTX_FIRST_VERSION; | |
688 | if (new_ctx == 1) | |
689 | new_ctx = CTX_FIRST_VERSION; | |
690 | ||
691 | /* Don't call memset, for 16 entries that's just | |
692 | * plain silly... | |
693 | */ | |
694 | mmu_context_bmap[0] = 3; | |
695 | mmu_context_bmap[1] = 0; | |
696 | mmu_context_bmap[2] = 0; | |
697 | mmu_context_bmap[3] = 0; | |
698 | for (i = 4; i < CTX_BMAP_SLOTS; i += 4) { | |
699 | mmu_context_bmap[i + 0] = 0; | |
700 | mmu_context_bmap[i + 1] = 0; | |
701 | mmu_context_bmap[i + 2] = 0; | |
702 | mmu_context_bmap[i + 3] = 0; | |
703 | } | |
a0663a79 | 704 | new_version = 1; |
1da177e4 LT |
705 | goto out; |
706 | } | |
707 | } | |
708 | mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); | |
709 | new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); | |
710 | out: | |
711 | tlb_context_cache = new_ctx; | |
712 | mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; | |
a77754b4 | 713 | spin_unlock_irqrestore(&ctx_alloc_lock, flags); |
a0663a79 DM |
714 | |
715 | if (unlikely(new_version)) | |
716 | smp_new_mmu_context_version(); | |
1da177e4 LT |
717 | } |
718 | ||
919ee677 DM |
719 | static int numa_enabled = 1; |
720 | static int numa_debug; | |
721 | ||
722 | static int __init early_numa(char *p) | |
1da177e4 | 723 | { |
919ee677 DM |
724 | if (!p) |
725 | return 0; | |
726 | ||
727 | if (strstr(p, "off")) | |
728 | numa_enabled = 0; | |
d1112018 | 729 | |
919ee677 DM |
730 | if (strstr(p, "debug")) |
731 | numa_debug = 1; | |
d1112018 | 732 | |
919ee677 | 733 | return 0; |
d1112018 | 734 | } |
919ee677 DM |
735 | early_param("numa", early_numa); |
736 | ||
737 | #define numadbg(f, a...) \ | |
738 | do { if (numa_debug) \ | |
739 | printk(KERN_INFO f, ## a); \ | |
740 | } while (0) | |
d1112018 | 741 | |
4e82c9a6 DM |
742 | static void __init find_ramdisk(unsigned long phys_base) |
743 | { | |
744 | #ifdef CONFIG_BLK_DEV_INITRD | |
745 | if (sparc_ramdisk_image || sparc_ramdisk_image64) { | |
746 | unsigned long ramdisk_image; | |
747 | ||
748 | /* Older versions of the bootloader only supported a | |
749 | * 32-bit physical address for the ramdisk image | |
750 | * location, stored at sparc_ramdisk_image. Newer | |
751 | * SILO versions set sparc_ramdisk_image to zero and | |
752 | * provide a full 64-bit physical address at | |
753 | * sparc_ramdisk_image64. | |
754 | */ | |
755 | ramdisk_image = sparc_ramdisk_image; | |
756 | if (!ramdisk_image) | |
757 | ramdisk_image = sparc_ramdisk_image64; | |
758 | ||
759 | /* Another bootloader quirk. The bootloader normalizes | |
760 | * the physical address to KERNBASE, so we have to | |
761 | * factor that back out and add in the lowest valid | |
762 | * physical page address to get the true physical address. | |
763 | */ | |
764 | ramdisk_image -= KERNBASE; | |
765 | ramdisk_image += phys_base; | |
766 | ||
919ee677 DM |
767 | numadbg("Found ramdisk at physical address 0x%lx, size %u\n", |
768 | ramdisk_image, sparc_ramdisk_size); | |
769 | ||
4e82c9a6 DM |
770 | initrd_start = ramdisk_image; |
771 | initrd_end = ramdisk_image + sparc_ramdisk_size; | |
3b2a7e23 DM |
772 | |
773 | lmb_reserve(initrd_start, initrd_end); | |
4e82c9a6 DM |
774 | } |
775 | #endif | |
776 | } | |
777 | ||
919ee677 DM |
778 | struct node_mem_mask { |
779 | unsigned long mask; | |
780 | unsigned long val; | |
781 | unsigned long bootmem_paddr; | |
782 | }; | |
783 | static struct node_mem_mask node_masks[MAX_NUMNODES]; | |
784 | static int num_node_masks; | |
785 | ||
786 | int numa_cpu_lookup_table[NR_CPUS]; | |
787 | cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; | |
788 | ||
789 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
790 | static bootmem_data_t plat_node_bdata[MAX_NUMNODES]; | |
791 | ||
792 | struct mdesc_mblock { | |
793 | u64 base; | |
794 | u64 size; | |
795 | u64 offset; /* RA-to-PA */ | |
796 | }; | |
797 | static struct mdesc_mblock *mblocks; | |
798 | static int num_mblocks; | |
799 | ||
800 | static unsigned long ra_to_pa(unsigned long addr) | |
801 | { | |
802 | int i; | |
803 | ||
804 | for (i = 0; i < num_mblocks; i++) { | |
805 | struct mdesc_mblock *m = &mblocks[i]; | |
806 | ||
807 | if (addr >= m->base && | |
808 | addr < (m->base + m->size)) { | |
809 | addr += m->offset; | |
810 | break; | |
811 | } | |
812 | } | |
813 | return addr; | |
814 | } | |
815 | ||
816 | static int find_node(unsigned long addr) | |
817 | { | |
818 | int i; | |
819 | ||
820 | addr = ra_to_pa(addr); | |
821 | for (i = 0; i < num_node_masks; i++) { | |
822 | struct node_mem_mask *p = &node_masks[i]; | |
823 | ||
824 | if ((addr & p->mask) == p->val) | |
825 | return i; | |
826 | } | |
827 | return -1; | |
828 | } | |
829 | ||
830 | static unsigned long nid_range(unsigned long start, unsigned long end, | |
831 | int *nid) | |
832 | { | |
833 | *nid = find_node(start); | |
834 | start += PAGE_SIZE; | |
835 | while (start < end) { | |
836 | int n = find_node(start); | |
837 | ||
838 | if (n != *nid) | |
839 | break; | |
840 | start += PAGE_SIZE; | |
841 | } | |
842 | ||
843 | return start; | |
844 | } | |
845 | #else | |
846 | static unsigned long nid_range(unsigned long start, unsigned long end, | |
847 | int *nid) | |
848 | { | |
849 | *nid = 0; | |
850 | return end; | |
851 | } | |
852 | #endif | |
853 | ||
854 | /* This must be invoked after performing all of the necessary | |
855 | * add_active_range() calls for 'nid'. We need to be able to get | |
856 | * correct data from get_pfn_range_for_nid(). | |
f1cfdb55 | 857 | */ |
919ee677 DM |
858 | static void __init allocate_node_data(int nid) |
859 | { | |
860 | unsigned long paddr, num_pages, start_pfn, end_pfn; | |
861 | struct pglist_data *p; | |
862 | ||
863 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
864 | paddr = lmb_alloc_nid(sizeof(struct pglist_data), | |
865 | SMP_CACHE_BYTES, nid, nid_range); | |
866 | if (!paddr) { | |
867 | prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); | |
868 | prom_halt(); | |
869 | } | |
870 | NODE_DATA(nid) = __va(paddr); | |
871 | memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); | |
872 | ||
873 | NODE_DATA(nid)->bdata = &plat_node_bdata[nid]; | |
874 | #endif | |
875 | ||
876 | p = NODE_DATA(nid); | |
877 | ||
878 | get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); | |
879 | p->node_start_pfn = start_pfn; | |
880 | p->node_spanned_pages = end_pfn - start_pfn; | |
881 | ||
882 | if (p->node_spanned_pages) { | |
883 | num_pages = bootmem_bootmap_pages(p->node_spanned_pages); | |
884 | ||
885 | paddr = lmb_alloc_nid(num_pages << PAGE_SHIFT, PAGE_SIZE, nid, | |
886 | nid_range); | |
887 | if (!paddr) { | |
888 | prom_printf("Cannot allocate bootmap for nid[%d]\n", | |
889 | nid); | |
890 | prom_halt(); | |
891 | } | |
892 | node_masks[nid].bootmem_paddr = paddr; | |
893 | } | |
894 | } | |
895 | ||
896 | static void init_node_masks_nonnuma(void) | |
d1112018 | 897 | { |
1da177e4 LT |
898 | int i; |
899 | ||
919ee677 | 900 | numadbg("Initializing tables for non-numa.\n"); |
6fc5bae7 | 901 | |
919ee677 DM |
902 | node_masks[0].mask = node_masks[0].val = 0; |
903 | num_node_masks = 1; | |
d1112018 | 904 | |
919ee677 DM |
905 | for (i = 0; i < NR_CPUS; i++) |
906 | numa_cpu_lookup_table[i] = 0; | |
1da177e4 | 907 | |
919ee677 DM |
908 | numa_cpumask_lookup_table[0] = CPU_MASK_ALL; |
909 | } | |
910 | ||
911 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
912 | struct pglist_data *node_data[MAX_NUMNODES]; | |
913 | ||
914 | EXPORT_SYMBOL(numa_cpu_lookup_table); | |
915 | EXPORT_SYMBOL(numa_cpumask_lookup_table); | |
916 | EXPORT_SYMBOL(node_data); | |
917 | ||
918 | struct mdesc_mlgroup { | |
919 | u64 node; | |
920 | u64 latency; | |
921 | u64 match; | |
922 | u64 mask; | |
923 | }; | |
924 | static struct mdesc_mlgroup *mlgroups; | |
925 | static int num_mlgroups; | |
926 | ||
927 | static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, | |
928 | u32 cfg_handle) | |
929 | { | |
930 | u64 arc; | |
931 | ||
932 | mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { | |
933 | u64 target = mdesc_arc_target(md, arc); | |
934 | const u64 *val; | |
935 | ||
936 | val = mdesc_get_property(md, target, | |
937 | "cfg-handle", NULL); | |
938 | if (val && *val == cfg_handle) | |
939 | return 0; | |
940 | } | |
941 | return -ENODEV; | |
942 | } | |
943 | ||
944 | static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, | |
945 | u32 cfg_handle) | |
946 | { | |
947 | u64 arc, candidate, best_latency = ~(u64)0; | |
948 | ||
949 | candidate = MDESC_NODE_NULL; | |
950 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
951 | u64 target = mdesc_arc_target(md, arc); | |
952 | const char *name = mdesc_node_name(md, target); | |
953 | const u64 *val; | |
954 | ||
955 | if (strcmp(name, "pio-latency-group")) | |
956 | continue; | |
957 | ||
958 | val = mdesc_get_property(md, target, "latency", NULL); | |
959 | if (!val) | |
960 | continue; | |
961 | ||
962 | if (*val < best_latency) { | |
963 | candidate = target; | |
964 | best_latency = *val; | |
965 | } | |
966 | } | |
967 | ||
968 | if (candidate == MDESC_NODE_NULL) | |
969 | return -ENODEV; | |
970 | ||
971 | return scan_pio_for_cfg_handle(md, candidate, cfg_handle); | |
972 | } | |
973 | ||
974 | int of_node_to_nid(struct device_node *dp) | |
975 | { | |
976 | const struct linux_prom64_registers *regs; | |
977 | struct mdesc_handle *md; | |
978 | u32 cfg_handle; | |
979 | int count, nid; | |
980 | u64 grp; | |
981 | ||
982 | if (!mlgroups) | |
983 | return -1; | |
984 | ||
985 | regs = of_get_property(dp, "reg", NULL); | |
986 | if (!regs) | |
987 | return -1; | |
988 | ||
989 | cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; | |
990 | ||
991 | md = mdesc_grab(); | |
992 | ||
993 | count = 0; | |
994 | nid = -1; | |
995 | mdesc_for_each_node_by_name(md, grp, "group") { | |
996 | if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { | |
997 | nid = count; | |
998 | break; | |
999 | } | |
1000 | count++; | |
1001 | } | |
1002 | ||
1003 | mdesc_release(md); | |
1004 | ||
1005 | return nid; | |
1006 | } | |
1007 | ||
1008 | static void add_node_ranges(void) | |
1009 | { | |
1010 | int i; | |
1011 | ||
1012 | for (i = 0; i < lmb.memory.cnt; i++) { | |
1013 | unsigned long size = lmb_size_bytes(&lmb.memory, i); | |
1014 | unsigned long start, end; | |
1015 | ||
1016 | start = lmb.memory.region[i].base; | |
1017 | end = start + size; | |
1018 | while (start < end) { | |
1019 | unsigned long this_end; | |
1020 | int nid; | |
1021 | ||
1022 | this_end = nid_range(start, end, &nid); | |
1023 | ||
1024 | numadbg("Adding active range nid[%d] " | |
1025 | "start[%lx] end[%lx]\n", | |
1026 | nid, start, this_end); | |
1027 | ||
1028 | add_active_range(nid, | |
1029 | start >> PAGE_SHIFT, | |
1030 | this_end >> PAGE_SHIFT); | |
1031 | ||
1032 | start = this_end; | |
1033 | } | |
1034 | } | |
1035 | } | |
1036 | ||
1037 | static int __init grab_mlgroups(struct mdesc_handle *md) | |
1038 | { | |
1039 | unsigned long paddr; | |
1040 | int count = 0; | |
1041 | u64 node; | |
1042 | ||
1043 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") | |
1044 | count++; | |
1045 | if (!count) | |
1046 | return -ENOENT; | |
1047 | ||
1048 | paddr = lmb_alloc(count * sizeof(struct mdesc_mlgroup), | |
1049 | SMP_CACHE_BYTES); | |
1050 | if (!paddr) | |
1051 | return -ENOMEM; | |
1052 | ||
1053 | mlgroups = __va(paddr); | |
1054 | num_mlgroups = count; | |
1055 | ||
1056 | count = 0; | |
1057 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") { | |
1058 | struct mdesc_mlgroup *m = &mlgroups[count++]; | |
1059 | const u64 *val; | |
1060 | ||
1061 | m->node = node; | |
1062 | ||
1063 | val = mdesc_get_property(md, node, "latency", NULL); | |
1064 | m->latency = *val; | |
1065 | val = mdesc_get_property(md, node, "address-match", NULL); | |
1066 | m->match = *val; | |
1067 | val = mdesc_get_property(md, node, "address-mask", NULL); | |
1068 | m->mask = *val; | |
1069 | ||
1070 | numadbg("MLGROUP[%d]: node[%lx] latency[%lx] " | |
1071 | "match[%lx] mask[%lx]\n", | |
1072 | count - 1, m->node, m->latency, m->match, m->mask); | |
1073 | } | |
1074 | ||
1075 | return 0; | |
1076 | } | |
1077 | ||
1078 | static int __init grab_mblocks(struct mdesc_handle *md) | |
1079 | { | |
1080 | unsigned long paddr; | |
1081 | int count = 0; | |
1082 | u64 node; | |
1083 | ||
1084 | mdesc_for_each_node_by_name(md, node, "mblock") | |
1085 | count++; | |
1086 | if (!count) | |
1087 | return -ENOENT; | |
1088 | ||
1089 | paddr = lmb_alloc(count * sizeof(struct mdesc_mblock), | |
1090 | SMP_CACHE_BYTES); | |
1091 | if (!paddr) | |
1092 | return -ENOMEM; | |
1093 | ||
1094 | mblocks = __va(paddr); | |
1095 | num_mblocks = count; | |
1096 | ||
1097 | count = 0; | |
1098 | mdesc_for_each_node_by_name(md, node, "mblock") { | |
1099 | struct mdesc_mblock *m = &mblocks[count++]; | |
1100 | const u64 *val; | |
1101 | ||
1102 | val = mdesc_get_property(md, node, "base", NULL); | |
1103 | m->base = *val; | |
1104 | val = mdesc_get_property(md, node, "size", NULL); | |
1105 | m->size = *val; | |
1106 | val = mdesc_get_property(md, node, | |
1107 | "address-congruence-offset", NULL); | |
1108 | m->offset = *val; | |
1109 | ||
1110 | numadbg("MBLOCK[%d]: base[%lx] size[%lx] offset[%lx]\n", | |
1111 | count - 1, m->base, m->size, m->offset); | |
1112 | } | |
1113 | ||
1114 | return 0; | |
1115 | } | |
1116 | ||
1117 | static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, | |
1118 | u64 grp, cpumask_t *mask) | |
1119 | { | |
1120 | u64 arc; | |
1121 | ||
1122 | cpus_clear(*mask); | |
1123 | ||
1124 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { | |
1125 | u64 target = mdesc_arc_target(md, arc); | |
1126 | const char *name = mdesc_node_name(md, target); | |
1127 | const u64 *id; | |
1128 | ||
1129 | if (strcmp(name, "cpu")) | |
1130 | continue; | |
1131 | id = mdesc_get_property(md, target, "id", NULL); | |
1132 | if (*id < NR_CPUS) | |
1133 | cpu_set(*id, *mask); | |
1134 | } | |
1135 | } | |
1136 | ||
1137 | static struct mdesc_mlgroup * __init find_mlgroup(u64 node) | |
1138 | { | |
1139 | int i; | |
1140 | ||
1141 | for (i = 0; i < num_mlgroups; i++) { | |
1142 | struct mdesc_mlgroup *m = &mlgroups[i]; | |
1143 | if (m->node == node) | |
1144 | return m; | |
1145 | } | |
1146 | return NULL; | |
1147 | } | |
1148 | ||
1149 | static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, | |
1150 | int index) | |
1151 | { | |
1152 | struct mdesc_mlgroup *candidate = NULL; | |
1153 | u64 arc, best_latency = ~(u64)0; | |
1154 | struct node_mem_mask *n; | |
1155 | ||
1156 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
1157 | u64 target = mdesc_arc_target(md, arc); | |
1158 | struct mdesc_mlgroup *m = find_mlgroup(target); | |
1159 | if (!m) | |
1160 | continue; | |
1161 | if (m->latency < best_latency) { | |
1162 | candidate = m; | |
1163 | best_latency = m->latency; | |
1164 | } | |
1165 | } | |
1166 | if (!candidate) | |
1167 | return -ENOENT; | |
1168 | ||
1169 | if (num_node_masks != index) { | |
1170 | printk(KERN_ERR "Inconsistent NUMA state, " | |
1171 | "index[%d] != num_node_masks[%d]\n", | |
1172 | index, num_node_masks); | |
1173 | return -EINVAL; | |
1174 | } | |
1175 | ||
1176 | n = &node_masks[num_node_masks++]; | |
1177 | ||
1178 | n->mask = candidate->mask; | |
1179 | n->val = candidate->match; | |
1da177e4 | 1180 | |
919ee677 DM |
1181 | numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%lx])\n", |
1182 | index, n->mask, n->val, candidate->latency); | |
1da177e4 | 1183 | |
919ee677 DM |
1184 | return 0; |
1185 | } | |
1186 | ||
1187 | static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, | |
1188 | int index) | |
1189 | { | |
1190 | cpumask_t mask; | |
1191 | int cpu; | |
1192 | ||
1193 | numa_parse_mdesc_group_cpus(md, grp, &mask); | |
1194 | ||
1195 | for_each_cpu_mask(cpu, mask) | |
1196 | numa_cpu_lookup_table[cpu] = index; | |
1197 | numa_cpumask_lookup_table[index] = mask; | |
1198 | ||
1199 | if (numa_debug) { | |
1200 | printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); | |
1201 | for_each_cpu_mask(cpu, mask) | |
1202 | printk("%d ", cpu); | |
1203 | printk("]\n"); | |
1204 | } | |
1205 | ||
1206 | return numa_attach_mlgroup(md, grp, index); | |
1207 | } | |
1208 | ||
1209 | static int __init numa_parse_mdesc(void) | |
1210 | { | |
1211 | struct mdesc_handle *md = mdesc_grab(); | |
1212 | int i, err, count; | |
1213 | u64 node; | |
1214 | ||
1215 | node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); | |
1216 | if (node == MDESC_NODE_NULL) { | |
1217 | mdesc_release(md); | |
1218 | return -ENOENT; | |
1219 | } | |
1220 | ||
1221 | err = grab_mblocks(md); | |
1222 | if (err < 0) | |
1223 | goto out; | |
1224 | ||
1225 | err = grab_mlgroups(md); | |
1226 | if (err < 0) | |
1227 | goto out; | |
1228 | ||
1229 | count = 0; | |
1230 | mdesc_for_each_node_by_name(md, node, "group") { | |
1231 | err = numa_parse_mdesc_group(md, node, count); | |
1232 | if (err < 0) | |
1233 | break; | |
1234 | count++; | |
1235 | } | |
1236 | ||
1237 | add_node_ranges(); | |
1238 | ||
1239 | for (i = 0; i < num_node_masks; i++) { | |
1240 | allocate_node_data(i); | |
1241 | node_set_online(i); | |
1242 | } | |
1243 | ||
1244 | err = 0; | |
1245 | out: | |
1246 | mdesc_release(md); | |
1247 | return err; | |
1248 | } | |
1249 | ||
1250 | static int __init numa_parse_sun4u(void) | |
1251 | { | |
1252 | return -1; | |
1253 | } | |
1254 | ||
1255 | static int __init bootmem_init_numa(void) | |
1256 | { | |
1257 | int err = -1; | |
1258 | ||
1259 | numadbg("bootmem_init_numa()\n"); | |
1260 | ||
1261 | if (numa_enabled) { | |
1262 | if (tlb_type == hypervisor) | |
1263 | err = numa_parse_mdesc(); | |
1264 | else | |
1265 | err = numa_parse_sun4u(); | |
1266 | } | |
1267 | return err; | |
1268 | } | |
1269 | ||
1270 | #else | |
1da177e4 | 1271 | |
919ee677 DM |
1272 | static int bootmem_init_numa(void) |
1273 | { | |
1274 | return -1; | |
1275 | } | |
1276 | ||
1277 | #endif | |
1278 | ||
1279 | static void __init bootmem_init_nonnuma(void) | |
1280 | { | |
1281 | unsigned long top_of_ram = lmb_end_of_DRAM(); | |
1282 | unsigned long total_ram = lmb_phys_mem_size(); | |
1283 | unsigned int i; | |
1284 | ||
1285 | numadbg("bootmem_init_nonnuma()\n"); | |
1286 | ||
1287 | printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", | |
1288 | top_of_ram, total_ram); | |
1289 | printk(KERN_INFO "Memory hole size: %ldMB\n", | |
1290 | (top_of_ram - total_ram) >> 20); | |
1291 | ||
1292 | init_node_masks_nonnuma(); | |
1293 | ||
1294 | for (i = 0; i < lmb.memory.cnt; i++) { | |
1295 | unsigned long size = lmb_size_bytes(&lmb.memory, i); | |
1296 | unsigned long start_pfn, end_pfn; | |
1297 | ||
1298 | if (!size) | |
1299 | continue; | |
1da177e4 | 1300 | |
9422273b | 1301 | start_pfn = lmb.memory.region[i].base >> PAGE_SHIFT; |
919ee677 DM |
1302 | end_pfn = start_pfn + lmb_size_pages(&lmb.memory, i); |
1303 | add_active_range(0, start_pfn, end_pfn); | |
1304 | } | |
d1112018 | 1305 | |
919ee677 DM |
1306 | allocate_node_data(0); |
1307 | ||
1308 | node_set_online(0); | |
1309 | } | |
1310 | ||
1311 | static void __init reserve_range_in_node(int nid, unsigned long start, | |
1312 | unsigned long end) | |
1313 | { | |
1314 | numadbg(" reserve_range_in_node(nid[%d],start[%lx],end[%lx]\n", | |
1315 | nid, start, end); | |
1316 | while (start < end) { | |
1317 | unsigned long this_end; | |
1318 | int n; | |
1319 | ||
1320 | this_end = nid_range(start, end, &n); | |
1321 | if (n == nid) { | |
1322 | numadbg(" MATCH reserving range [%lx:%lx]\n", | |
1323 | start, this_end); | |
1324 | reserve_bootmem_node(NODE_DATA(nid), start, | |
1325 | (this_end - start), BOOTMEM_DEFAULT); | |
1326 | } else | |
1327 | numadbg(" NO MATCH, advancing start to %lx\n", | |
1328 | this_end); | |
1329 | ||
1330 | start = this_end; | |
d1112018 | 1331 | } |
919ee677 DM |
1332 | } |
1333 | ||
1334 | static void __init trim_reserved_in_node(int nid) | |
1335 | { | |
1336 | int i; | |
1337 | ||
1338 | numadbg(" trim_reserved_in_node(%d)\n", nid); | |
1339 | ||
1340 | for (i = 0; i < lmb.reserved.cnt; i++) { | |
1341 | unsigned long start = lmb.reserved.region[i].base; | |
1342 | unsigned long size = lmb_size_bytes(&lmb.reserved, i); | |
1343 | unsigned long end = start + size; | |
1344 | ||
1345 | reserve_range_in_node(nid, start, end); | |
1346 | } | |
1347 | } | |
1348 | ||
1349 | static void __init bootmem_init_one_node(int nid) | |
1350 | { | |
1351 | struct pglist_data *p; | |
1352 | ||
1353 | numadbg("bootmem_init_one_node(%d)\n", nid); | |
1354 | ||
1355 | p = NODE_DATA(nid); | |
1356 | ||
1357 | if (p->node_spanned_pages) { | |
1358 | unsigned long paddr = node_masks[nid].bootmem_paddr; | |
1359 | unsigned long end_pfn; | |
1360 | ||
1361 | end_pfn = p->node_start_pfn + p->node_spanned_pages; | |
1362 | ||
1363 | numadbg(" init_bootmem_node(%d, %lx, %lx, %lx)\n", | |
1364 | nid, paddr >> PAGE_SHIFT, p->node_start_pfn, end_pfn); | |
1365 | ||
1366 | init_bootmem_node(p, paddr >> PAGE_SHIFT, | |
1367 | p->node_start_pfn, end_pfn); | |
1368 | ||
1369 | numadbg(" free_bootmem_with_active_regions(%d, %lx)\n", | |
1370 | nid, end_pfn); | |
1371 | free_bootmem_with_active_regions(nid, end_pfn); | |
1372 | ||
1373 | trim_reserved_in_node(nid); | |
1374 | ||
1375 | numadbg(" sparse_memory_present_with_active_regions(%d)\n", | |
1376 | nid); | |
1377 | sparse_memory_present_with_active_regions(nid); | |
1378 | } | |
1379 | } | |
1380 | ||
1381 | static unsigned long __init bootmem_init(unsigned long phys_base) | |
1382 | { | |
1383 | unsigned long end_pfn; | |
1384 | int nid; | |
1385 | ||
1386 | end_pfn = lmb_end_of_DRAM() >> PAGE_SHIFT; | |
1387 | max_pfn = max_low_pfn = end_pfn; | |
1388 | min_low_pfn = (phys_base >> PAGE_SHIFT); | |
1389 | ||
1390 | if (bootmem_init_numa() < 0) | |
1391 | bootmem_init_nonnuma(); | |
1392 | ||
1393 | /* XXX cpu notifier XXX */ | |
1394 | ||
1395 | for_each_online_node(nid) | |
1396 | bootmem_init_one_node(nid); | |
d1112018 DM |
1397 | |
1398 | sparse_init(); | |
1399 | ||
1da177e4 LT |
1400 | return end_pfn; |
1401 | } | |
1402 | ||
9cc3a1ac DM |
1403 | static struct linux_prom64_registers pall[MAX_BANKS] __initdata; |
1404 | static int pall_ents __initdata; | |
1405 | ||
56425306 | 1406 | #ifdef CONFIG_DEBUG_PAGEALLOC |
896aef43 SR |
1407 | static unsigned long __ref kernel_map_range(unsigned long pstart, |
1408 | unsigned long pend, pgprot_t prot) | |
56425306 DM |
1409 | { |
1410 | unsigned long vstart = PAGE_OFFSET + pstart; | |
1411 | unsigned long vend = PAGE_OFFSET + pend; | |
1412 | unsigned long alloc_bytes = 0UL; | |
1413 | ||
1414 | if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { | |
13edad7a | 1415 | prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", |
56425306 DM |
1416 | vstart, vend); |
1417 | prom_halt(); | |
1418 | } | |
1419 | ||
1420 | while (vstart < vend) { | |
1421 | unsigned long this_end, paddr = __pa(vstart); | |
1422 | pgd_t *pgd = pgd_offset_k(vstart); | |
1423 | pud_t *pud; | |
1424 | pmd_t *pmd; | |
1425 | pte_t *pte; | |
1426 | ||
1427 | pud = pud_offset(pgd, vstart); | |
1428 | if (pud_none(*pud)) { | |
1429 | pmd_t *new; | |
1430 | ||
1431 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1432 | alloc_bytes += PAGE_SIZE; | |
1433 | pud_populate(&init_mm, pud, new); | |
1434 | } | |
1435 | ||
1436 | pmd = pmd_offset(pud, vstart); | |
1437 | if (!pmd_present(*pmd)) { | |
1438 | pte_t *new; | |
1439 | ||
1440 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1441 | alloc_bytes += PAGE_SIZE; | |
1442 | pmd_populate_kernel(&init_mm, pmd, new); | |
1443 | } | |
1444 | ||
1445 | pte = pte_offset_kernel(pmd, vstart); | |
1446 | this_end = (vstart + PMD_SIZE) & PMD_MASK; | |
1447 | if (this_end > vend) | |
1448 | this_end = vend; | |
1449 | ||
1450 | while (vstart < this_end) { | |
1451 | pte_val(*pte) = (paddr | pgprot_val(prot)); | |
1452 | ||
1453 | vstart += PAGE_SIZE; | |
1454 | paddr += PAGE_SIZE; | |
1455 | pte++; | |
1456 | } | |
1457 | } | |
1458 | ||
1459 | return alloc_bytes; | |
1460 | } | |
1461 | ||
56425306 | 1462 | extern unsigned int kvmap_linear_patch[1]; |
9cc3a1ac DM |
1463 | #endif /* CONFIG_DEBUG_PAGEALLOC */ |
1464 | ||
1465 | static void __init mark_kpte_bitmap(unsigned long start, unsigned long end) | |
1466 | { | |
1467 | const unsigned long shift_256MB = 28; | |
1468 | const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL); | |
1469 | const unsigned long size_256MB = (1UL << shift_256MB); | |
1470 | ||
1471 | while (start < end) { | |
1472 | long remains; | |
1473 | ||
f7c00338 DM |
1474 | remains = end - start; |
1475 | if (remains < size_256MB) | |
1476 | break; | |
1477 | ||
9cc3a1ac DM |
1478 | if (start & mask_256MB) { |
1479 | start = (start + size_256MB) & ~mask_256MB; | |
1480 | continue; | |
1481 | } | |
1482 | ||
9cc3a1ac DM |
1483 | while (remains >= size_256MB) { |
1484 | unsigned long index = start >> shift_256MB; | |
1485 | ||
1486 | __set_bit(index, kpte_linear_bitmap); | |
1487 | ||
1488 | start += size_256MB; | |
1489 | remains -= size_256MB; | |
1490 | } | |
1491 | } | |
1492 | } | |
56425306 | 1493 | |
8f361453 | 1494 | static void __init init_kpte_bitmap(void) |
56425306 | 1495 | { |
9cc3a1ac | 1496 | unsigned long i; |
13edad7a DM |
1497 | |
1498 | for (i = 0; i < pall_ents; i++) { | |
56425306 DM |
1499 | unsigned long phys_start, phys_end; |
1500 | ||
13edad7a DM |
1501 | phys_start = pall[i].phys_addr; |
1502 | phys_end = phys_start + pall[i].reg_size; | |
9cc3a1ac DM |
1503 | |
1504 | mark_kpte_bitmap(phys_start, phys_end); | |
8f361453 DM |
1505 | } |
1506 | } | |
9cc3a1ac | 1507 | |
8f361453 DM |
1508 | static void __init kernel_physical_mapping_init(void) |
1509 | { | |
9cc3a1ac | 1510 | #ifdef CONFIG_DEBUG_PAGEALLOC |
8f361453 DM |
1511 | unsigned long i, mem_alloced = 0UL; |
1512 | ||
1513 | for (i = 0; i < pall_ents; i++) { | |
1514 | unsigned long phys_start, phys_end; | |
1515 | ||
1516 | phys_start = pall[i].phys_addr; | |
1517 | phys_end = phys_start + pall[i].reg_size; | |
1518 | ||
56425306 DM |
1519 | mem_alloced += kernel_map_range(phys_start, phys_end, |
1520 | PAGE_KERNEL); | |
56425306 DM |
1521 | } |
1522 | ||
1523 | printk("Allocated %ld bytes for kernel page tables.\n", | |
1524 | mem_alloced); | |
1525 | ||
1526 | kvmap_linear_patch[0] = 0x01000000; /* nop */ | |
1527 | flushi(&kvmap_linear_patch[0]); | |
1528 | ||
1529 | __flush_tlb_all(); | |
9cc3a1ac | 1530 | #endif |
56425306 DM |
1531 | } |
1532 | ||
9cc3a1ac | 1533 | #ifdef CONFIG_DEBUG_PAGEALLOC |
56425306 DM |
1534 | void kernel_map_pages(struct page *page, int numpages, int enable) |
1535 | { | |
1536 | unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; | |
1537 | unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); | |
1538 | ||
1539 | kernel_map_range(phys_start, phys_end, | |
1540 | (enable ? PAGE_KERNEL : __pgprot(0))); | |
1541 | ||
74bf4312 DM |
1542 | flush_tsb_kernel_range(PAGE_OFFSET + phys_start, |
1543 | PAGE_OFFSET + phys_end); | |
1544 | ||
56425306 DM |
1545 | /* we should perform an IPI and flush all tlbs, |
1546 | * but that can deadlock->flush only current cpu. | |
1547 | */ | |
1548 | __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, | |
1549 | PAGE_OFFSET + phys_end); | |
1550 | } | |
1551 | #endif | |
1552 | ||
10147570 DM |
1553 | unsigned long __init find_ecache_flush_span(unsigned long size) |
1554 | { | |
0836a0eb DM |
1555 | int i; |
1556 | ||
13edad7a DM |
1557 | for (i = 0; i < pavail_ents; i++) { |
1558 | if (pavail[i].reg_size >= size) | |
1559 | return pavail[i].phys_addr; | |
0836a0eb DM |
1560 | } |
1561 | ||
13edad7a | 1562 | return ~0UL; |
0836a0eb DM |
1563 | } |
1564 | ||
517af332 DM |
1565 | static void __init tsb_phys_patch(void) |
1566 | { | |
d257d5da | 1567 | struct tsb_ldquad_phys_patch_entry *pquad; |
517af332 DM |
1568 | struct tsb_phys_patch_entry *p; |
1569 | ||
d257d5da DM |
1570 | pquad = &__tsb_ldquad_phys_patch; |
1571 | while (pquad < &__tsb_ldquad_phys_patch_end) { | |
1572 | unsigned long addr = pquad->addr; | |
1573 | ||
1574 | if (tlb_type == hypervisor) | |
1575 | *(unsigned int *) addr = pquad->sun4v_insn; | |
1576 | else | |
1577 | *(unsigned int *) addr = pquad->sun4u_insn; | |
1578 | wmb(); | |
1579 | __asm__ __volatile__("flush %0" | |
1580 | : /* no outputs */ | |
1581 | : "r" (addr)); | |
1582 | ||
1583 | pquad++; | |
1584 | } | |
1585 | ||
517af332 DM |
1586 | p = &__tsb_phys_patch; |
1587 | while (p < &__tsb_phys_patch_end) { | |
1588 | unsigned long addr = p->addr; | |
1589 | ||
1590 | *(unsigned int *) addr = p->insn; | |
1591 | wmb(); | |
1592 | __asm__ __volatile__("flush %0" | |
1593 | : /* no outputs */ | |
1594 | : "r" (addr)); | |
1595 | ||
1596 | p++; | |
1597 | } | |
1598 | } | |
1599 | ||
490384e7 | 1600 | /* Don't mark as init, we give this to the Hypervisor. */ |
d1acb421 DM |
1601 | #ifndef CONFIG_DEBUG_PAGEALLOC |
1602 | #define NUM_KTSB_DESCR 2 | |
1603 | #else | |
1604 | #define NUM_KTSB_DESCR 1 | |
1605 | #endif | |
1606 | static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; | |
490384e7 DM |
1607 | extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; |
1608 | ||
1609 | static void __init sun4v_ktsb_init(void) | |
1610 | { | |
1611 | unsigned long ktsb_pa; | |
1612 | ||
d7744a09 | 1613 | /* First KTSB for PAGE_SIZE mappings. */ |
490384e7 DM |
1614 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); |
1615 | ||
1616 | switch (PAGE_SIZE) { | |
1617 | case 8 * 1024: | |
1618 | default: | |
1619 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; | |
1620 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; | |
1621 | break; | |
1622 | ||
1623 | case 64 * 1024: | |
1624 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; | |
1625 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; | |
1626 | break; | |
1627 | ||
1628 | case 512 * 1024: | |
1629 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; | |
1630 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; | |
1631 | break; | |
1632 | ||
1633 | case 4 * 1024 * 1024: | |
1634 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1635 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; | |
1636 | break; | |
1637 | }; | |
1638 | ||
3f19a84e | 1639 | ktsb_descr[0].assoc = 1; |
490384e7 DM |
1640 | ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; |
1641 | ktsb_descr[0].ctx_idx = 0; | |
1642 | ktsb_descr[0].tsb_base = ktsb_pa; | |
1643 | ktsb_descr[0].resv = 0; | |
1644 | ||
d1acb421 | 1645 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 DM |
1646 | /* Second KTSB for 4MB/256MB mappings. */ |
1647 | ktsb_pa = (kern_base + | |
1648 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
1649 | ||
1650 | ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; | |
1651 | ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB | | |
1652 | HV_PGSZ_MASK_256MB); | |
1653 | ktsb_descr[1].assoc = 1; | |
1654 | ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; | |
1655 | ktsb_descr[1].ctx_idx = 0; | |
1656 | ktsb_descr[1].tsb_base = ktsb_pa; | |
1657 | ktsb_descr[1].resv = 0; | |
d1acb421 | 1658 | #endif |
490384e7 DM |
1659 | } |
1660 | ||
1661 | void __cpuinit sun4v_ktsb_register(void) | |
1662 | { | |
7db35f31 | 1663 | unsigned long pa, ret; |
490384e7 DM |
1664 | |
1665 | pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); | |
1666 | ||
7db35f31 DM |
1667 | ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); |
1668 | if (ret != 0) { | |
1669 | prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " | |
1670 | "errors with %lx\n", pa, ret); | |
1671 | prom_halt(); | |
1672 | } | |
490384e7 DM |
1673 | } |
1674 | ||
1da177e4 LT |
1675 | /* paging_init() sets up the page tables */ |
1676 | ||
5cbc3073 DM |
1677 | extern void central_probe(void); |
1678 | ||
1da177e4 | 1679 | static unsigned long last_valid_pfn; |
56425306 | 1680 | pgd_t swapper_pg_dir[2048]; |
1da177e4 | 1681 | |
c4bce90e DM |
1682 | static void sun4u_pgprot_init(void); |
1683 | static void sun4v_pgprot_init(void); | |
1684 | ||
3afc6202 | 1685 | /* Dummy function */ |
1686 | void __init setup_per_cpu_areas(void) | |
1687 | { | |
1688 | } | |
1689 | ||
1da177e4 LT |
1690 | void __init paging_init(void) |
1691 | { | |
919ee677 | 1692 | unsigned long end_pfn, shift, phys_base; |
0836a0eb DM |
1693 | unsigned long real_end, i; |
1694 | ||
22adb358 DM |
1695 | /* These build time checkes make sure that the dcache_dirty_cpu() |
1696 | * page->flags usage will work. | |
1697 | * | |
1698 | * When a page gets marked as dcache-dirty, we store the | |
1699 | * cpu number starting at bit 32 in the page->flags. Also, | |
1700 | * functions like clear_dcache_dirty_cpu use the cpu mask | |
1701 | * in 13-bit signed-immediate instruction fields. | |
1702 | */ | |
9223b419 CL |
1703 | |
1704 | /* | |
1705 | * Page flags must not reach into upper 32 bits that are used | |
1706 | * for the cpu number | |
1707 | */ | |
1708 | BUILD_BUG_ON(NR_PAGEFLAGS > 32); | |
1709 | ||
1710 | /* | |
1711 | * The bit fields placed in the high range must not reach below | |
1712 | * the 32 bit boundary. Otherwise we cannot place the cpu field | |
1713 | * at the 32 bit boundary. | |
1714 | */ | |
22adb358 | 1715 | BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + |
9223b419 CL |
1716 | ilog2(roundup_pow_of_two(NR_CPUS)) > 32); |
1717 | ||
22adb358 DM |
1718 | BUILD_BUG_ON(NR_CPUS > 4096); |
1719 | ||
481295f9 DM |
1720 | kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL; |
1721 | kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; | |
1722 | ||
22d6a1cb DM |
1723 | sstate_booting(); |
1724 | ||
d7744a09 | 1725 | /* Invalidate both kernel TSBs. */ |
8b234274 | 1726 | memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); |
d1acb421 | 1727 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 | 1728 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); |
d1acb421 | 1729 | #endif |
8b234274 | 1730 | |
c4bce90e DM |
1731 | if (tlb_type == hypervisor) |
1732 | sun4v_pgprot_init(); | |
1733 | else | |
1734 | sun4u_pgprot_init(); | |
1735 | ||
d257d5da DM |
1736 | if (tlb_type == cheetah_plus || |
1737 | tlb_type == hypervisor) | |
517af332 DM |
1738 | tsb_phys_patch(); |
1739 | ||
490384e7 | 1740 | if (tlb_type == hypervisor) { |
d257d5da | 1741 | sun4v_patch_tlb_handlers(); |
490384e7 DM |
1742 | sun4v_ktsb_init(); |
1743 | } | |
d257d5da | 1744 | |
3b2a7e23 DM |
1745 | lmb_init(); |
1746 | ||
13edad7a DM |
1747 | /* Find available physical memory... */ |
1748 | read_obp_memory("available", &pavail[0], &pavail_ents); | |
0836a0eb DM |
1749 | |
1750 | phys_base = 0xffffffffffffffffUL; | |
3b2a7e23 | 1751 | for (i = 0; i < pavail_ents; i++) { |
13edad7a | 1752 | phys_base = min(phys_base, pavail[i].phys_addr); |
3b2a7e23 DM |
1753 | lmb_add(pavail[i].phys_addr, pavail[i].reg_size); |
1754 | } | |
1755 | ||
1756 | lmb_reserve(kern_base, kern_size); | |
0836a0eb | 1757 | |
4e82c9a6 DM |
1758 | find_ramdisk(phys_base); |
1759 | ||
25b0c659 DM |
1760 | if (cmdline_memory_size) |
1761 | lmb_enforce_memory_limit(phys_base + cmdline_memory_size); | |
1762 | ||
3b2a7e23 DM |
1763 | lmb_analyze(); |
1764 | lmb_dump_all(); | |
1765 | ||
1da177e4 LT |
1766 | set_bit(0, mmu_context_bmap); |
1767 | ||
2bdb3cb2 DM |
1768 | shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); |
1769 | ||
1da177e4 | 1770 | real_end = (unsigned long)_end; |
64658743 DM |
1771 | num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22); |
1772 | printk("Kernel: Using %d locked TLB entries for main kernel image.\n", | |
1773 | num_kernel_image_mappings); | |
2bdb3cb2 DM |
1774 | |
1775 | /* Set kernel pgd to upper alias so physical page computations | |
1da177e4 LT |
1776 | * work. |
1777 | */ | |
1778 | init_mm.pgd += ((shift) / (sizeof(pgd_t))); | |
1779 | ||
56425306 | 1780 | memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir)); |
1da177e4 LT |
1781 | |
1782 | /* Now can init the kernel/bad page tables. */ | |
1783 | pud_set(pud_offset(&swapper_pg_dir[0], 0), | |
56425306 | 1784 | swapper_low_pmd_dir + (shift / sizeof(pgd_t))); |
1da177e4 | 1785 | |
c9c10830 | 1786 | inherit_prom_mappings(); |
5085b4a5 | 1787 | |
8f361453 DM |
1788 | read_obp_memory("reg", &pall[0], &pall_ents); |
1789 | ||
1790 | init_kpte_bitmap(); | |
1791 | ||
a8b900d8 DM |
1792 | /* Ok, we can use our TLB miss and window trap handlers safely. */ |
1793 | setup_tba(); | |
1da177e4 | 1794 | |
c9c10830 | 1795 | __flush_tlb_all(); |
9ad98c5b | 1796 | |
490384e7 DM |
1797 | if (tlb_type == hypervisor) |
1798 | sun4v_ktsb_register(); | |
1799 | ||
b9709456 DM |
1800 | /* We must setup the per-cpu areas before we pull in the |
1801 | * PROM and the MDESC. The code there fills in cpu and | |
1802 | * other information into per-cpu data structures. | |
1803 | */ | |
1804 | real_setup_per_cpu_areas(); | |
1805 | ||
ad072004 DM |
1806 | prom_build_devicetree(); |
1807 | ||
4a283339 DM |
1808 | if (tlb_type == hypervisor) |
1809 | sun4v_mdesc_init(); | |
1810 | ||
2bdb3cb2 | 1811 | /* Setup bootmem... */ |
919ee677 | 1812 | last_valid_pfn = end_pfn = bootmem_init(phys_base); |
d1112018 | 1813 | |
919ee677 | 1814 | #ifndef CONFIG_NEED_MULTIPLE_NODES |
17b0e199 | 1815 | max_mapnr = last_valid_pfn; |
919ee677 | 1816 | #endif |
56425306 | 1817 | kernel_physical_mapping_init(); |
56425306 | 1818 | |
1da177e4 | 1819 | { |
919ee677 | 1820 | unsigned long max_zone_pfns[MAX_NR_ZONES]; |
1da177e4 | 1821 | |
919ee677 | 1822 | memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); |
1da177e4 | 1823 | |
919ee677 | 1824 | max_zone_pfns[ZONE_NORMAL] = end_pfn; |
1da177e4 | 1825 | |
919ee677 | 1826 | free_area_init_nodes(max_zone_pfns); |
1da177e4 LT |
1827 | } |
1828 | ||
3c62a2d3 | 1829 | printk("Booting Linux...\n"); |
5cbc3073 DM |
1830 | |
1831 | central_probe(); | |
1832 | cpu_probe(); | |
1da177e4 LT |
1833 | } |
1834 | ||
919ee677 DM |
1835 | int __init page_in_phys_avail(unsigned long paddr) |
1836 | { | |
1837 | int i; | |
1838 | ||
1839 | paddr &= PAGE_MASK; | |
1840 | ||
1841 | for (i = 0; i < pavail_ents; i++) { | |
1842 | unsigned long start, end; | |
1843 | ||
1844 | start = pavail[i].phys_addr; | |
1845 | end = start + pavail[i].reg_size; | |
1846 | ||
1847 | if (paddr >= start && paddr < end) | |
1848 | return 1; | |
1849 | } | |
1850 | if (paddr >= kern_base && paddr < (kern_base + kern_size)) | |
1851 | return 1; | |
1852 | #ifdef CONFIG_BLK_DEV_INITRD | |
1853 | if (paddr >= __pa(initrd_start) && | |
1854 | paddr < __pa(PAGE_ALIGN(initrd_end))) | |
1855 | return 1; | |
1856 | #endif | |
1857 | ||
1858 | return 0; | |
1859 | } | |
1860 | ||
1861 | static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata; | |
1862 | static int pavail_rescan_ents __initdata; | |
1863 | ||
1864 | /* Certain OBP calls, such as fetching "available" properties, can | |
1865 | * claim physical memory. So, along with initializing the valid | |
1866 | * address bitmap, what we do here is refetch the physical available | |
1867 | * memory list again, and make sure it provides at least as much | |
1868 | * memory as 'pavail' does. | |
1869 | */ | |
1870 | static void setup_valid_addr_bitmap_from_pavail(void) | |
1da177e4 | 1871 | { |
1da177e4 LT |
1872 | int i; |
1873 | ||
13edad7a | 1874 | read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents); |
1da177e4 | 1875 | |
13edad7a | 1876 | for (i = 0; i < pavail_ents; i++) { |
1da177e4 LT |
1877 | unsigned long old_start, old_end; |
1878 | ||
13edad7a | 1879 | old_start = pavail[i].phys_addr; |
919ee677 | 1880 | old_end = old_start + pavail[i].reg_size; |
1da177e4 LT |
1881 | while (old_start < old_end) { |
1882 | int n; | |
1883 | ||
c2a5a46b | 1884 | for (n = 0; n < pavail_rescan_ents; n++) { |
1da177e4 LT |
1885 | unsigned long new_start, new_end; |
1886 | ||
13edad7a DM |
1887 | new_start = pavail_rescan[n].phys_addr; |
1888 | new_end = new_start + | |
1889 | pavail_rescan[n].reg_size; | |
1da177e4 LT |
1890 | |
1891 | if (new_start <= old_start && | |
1892 | new_end >= (old_start + PAGE_SIZE)) { | |
13edad7a DM |
1893 | set_bit(old_start >> 22, |
1894 | sparc64_valid_addr_bitmap); | |
1da177e4 LT |
1895 | goto do_next_page; |
1896 | } | |
1897 | } | |
919ee677 DM |
1898 | |
1899 | prom_printf("mem_init: Lost memory in pavail\n"); | |
1900 | prom_printf("mem_init: OLD start[%lx] size[%lx]\n", | |
1901 | pavail[i].phys_addr, | |
1902 | pavail[i].reg_size); | |
1903 | prom_printf("mem_init: NEW start[%lx] size[%lx]\n", | |
1904 | pavail_rescan[i].phys_addr, | |
1905 | pavail_rescan[i].reg_size); | |
1906 | prom_printf("mem_init: Cannot continue, aborting.\n"); | |
1907 | prom_halt(); | |
1da177e4 LT |
1908 | |
1909 | do_next_page: | |
1910 | old_start += PAGE_SIZE; | |
1911 | } | |
1912 | } | |
1913 | } | |
1914 | ||
1915 | void __init mem_init(void) | |
1916 | { | |
1917 | unsigned long codepages, datapages, initpages; | |
1918 | unsigned long addr, last; | |
1919 | int i; | |
1920 | ||
1921 | i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6); | |
1922 | i += 1; | |
2bdb3cb2 | 1923 | sparc64_valid_addr_bitmap = (unsigned long *) alloc_bootmem(i << 3); |
1da177e4 LT |
1924 | if (sparc64_valid_addr_bitmap == NULL) { |
1925 | prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n"); | |
1926 | prom_halt(); | |
1927 | } | |
1928 | memset(sparc64_valid_addr_bitmap, 0, i << 3); | |
1929 | ||
1930 | addr = PAGE_OFFSET + kern_base; | |
1931 | last = PAGE_ALIGN(kern_size) + addr; | |
1932 | while (addr < last) { | |
1933 | set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap); | |
1934 | addr += PAGE_SIZE; | |
1935 | } | |
1936 | ||
919ee677 | 1937 | setup_valid_addr_bitmap_from_pavail(); |
1da177e4 | 1938 | |
1da177e4 LT |
1939 | high_memory = __va(last_valid_pfn << PAGE_SHIFT); |
1940 | ||
919ee677 DM |
1941 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
1942 | for_each_online_node(i) { | |
1943 | if (NODE_DATA(i)->node_spanned_pages != 0) { | |
1944 | totalram_pages += | |
1945 | free_all_bootmem_node(NODE_DATA(i)); | |
1946 | } | |
1947 | } | |
1948 | #else | |
1949 | totalram_pages = free_all_bootmem(); | |
1950 | #endif | |
1951 | ||
f1cfdb55 DM |
1952 | /* We subtract one to account for the mem_map_zero page |
1953 | * allocated below. | |
1954 | */ | |
919ee677 DM |
1955 | totalram_pages -= 1; |
1956 | num_physpages = totalram_pages; | |
1da177e4 LT |
1957 | |
1958 | /* | |
1959 | * Set up the zero page, mark it reserved, so that page count | |
1960 | * is not manipulated when freeing the page from user ptes. | |
1961 | */ | |
1962 | mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); | |
1963 | if (mem_map_zero == NULL) { | |
1964 | prom_printf("paging_init: Cannot alloc zero page.\n"); | |
1965 | prom_halt(); | |
1966 | } | |
1967 | SetPageReserved(mem_map_zero); | |
1968 | ||
1969 | codepages = (((unsigned long) _etext) - ((unsigned long) _start)); | |
1970 | codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT; | |
1971 | datapages = (((unsigned long) _edata) - ((unsigned long) _etext)); | |
1972 | datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT; | |
1973 | initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin)); | |
1974 | initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT; | |
1975 | ||
96177299 | 1976 | printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n", |
1da177e4 LT |
1977 | nr_free_pages() << (PAGE_SHIFT-10), |
1978 | codepages << (PAGE_SHIFT-10), | |
1979 | datapages << (PAGE_SHIFT-10), | |
1980 | initpages << (PAGE_SHIFT-10), | |
1981 | PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT)); | |
1982 | ||
1983 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
1984 | cheetah_ecache_flush_init(); | |
1985 | } | |
1986 | ||
898cf0ec | 1987 | void free_initmem(void) |
1da177e4 LT |
1988 | { |
1989 | unsigned long addr, initend; | |
1990 | ||
1991 | /* | |
1992 | * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. | |
1993 | */ | |
1994 | addr = PAGE_ALIGN((unsigned long)(__init_begin)); | |
1995 | initend = (unsigned long)(__init_end) & PAGE_MASK; | |
1996 | for (; addr < initend; addr += PAGE_SIZE) { | |
1997 | unsigned long page; | |
1998 | struct page *p; | |
1999 | ||
2000 | page = (addr + | |
2001 | ((unsigned long) __va(kern_base)) - | |
2002 | ((unsigned long) KERNBASE)); | |
c9cf5528 | 2003 | memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); |
1da177e4 LT |
2004 | p = virt_to_page(page); |
2005 | ||
2006 | ClearPageReserved(p); | |
7835e98b | 2007 | init_page_count(p); |
1da177e4 LT |
2008 | __free_page(p); |
2009 | num_physpages++; | |
2010 | totalram_pages++; | |
2011 | } | |
2012 | } | |
2013 | ||
2014 | #ifdef CONFIG_BLK_DEV_INITRD | |
2015 | void free_initrd_mem(unsigned long start, unsigned long end) | |
2016 | { | |
2017 | if (start < end) | |
2018 | printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10); | |
2019 | for (; start < end; start += PAGE_SIZE) { | |
2020 | struct page *p = virt_to_page(start); | |
2021 | ||
2022 | ClearPageReserved(p); | |
7835e98b | 2023 | init_page_count(p); |
1da177e4 LT |
2024 | __free_page(p); |
2025 | num_physpages++; | |
2026 | totalram_pages++; | |
2027 | } | |
2028 | } | |
2029 | #endif | |
c4bce90e | 2030 | |
c4bce90e DM |
2031 | #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) |
2032 | #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) | |
2033 | #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) | |
2034 | #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) | |
2035 | #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) | |
2036 | #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) | |
2037 | ||
2038 | pgprot_t PAGE_KERNEL __read_mostly; | |
2039 | EXPORT_SYMBOL(PAGE_KERNEL); | |
2040 | ||
2041 | pgprot_t PAGE_KERNEL_LOCKED __read_mostly; | |
2042 | pgprot_t PAGE_COPY __read_mostly; | |
0f15952a DM |
2043 | |
2044 | pgprot_t PAGE_SHARED __read_mostly; | |
2045 | EXPORT_SYMBOL(PAGE_SHARED); | |
2046 | ||
c4bce90e DM |
2047 | pgprot_t PAGE_EXEC __read_mostly; |
2048 | unsigned long pg_iobits __read_mostly; | |
2049 | ||
2050 | unsigned long _PAGE_IE __read_mostly; | |
987c74fc | 2051 | EXPORT_SYMBOL(_PAGE_IE); |
b2bef442 | 2052 | |
c4bce90e | 2053 | unsigned long _PAGE_E __read_mostly; |
b2bef442 DM |
2054 | EXPORT_SYMBOL(_PAGE_E); |
2055 | ||
c4bce90e | 2056 | unsigned long _PAGE_CACHE __read_mostly; |
b2bef442 | 2057 | EXPORT_SYMBOL(_PAGE_CACHE); |
c4bce90e | 2058 | |
46644c24 DM |
2059 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
2060 | ||
2061 | #define VMEMMAP_CHUNK_SHIFT 22 | |
2062 | #define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT) | |
2063 | #define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL) | |
2064 | #define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK) | |
2065 | ||
2066 | #define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \ | |
2067 | sizeof(struct page *)) >> VMEMMAP_CHUNK_SHIFT) | |
2068 | unsigned long vmemmap_table[VMEMMAP_SIZE]; | |
2069 | ||
2070 | int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node) | |
2071 | { | |
2072 | unsigned long vstart = (unsigned long) start; | |
2073 | unsigned long vend = (unsigned long) (start + nr); | |
2074 | unsigned long phys_start = (vstart - VMEMMAP_BASE); | |
2075 | unsigned long phys_end = (vend - VMEMMAP_BASE); | |
2076 | unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK; | |
2077 | unsigned long end = VMEMMAP_ALIGN(phys_end); | |
2078 | unsigned long pte_base; | |
2079 | ||
2080 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2081 | _PAGE_CP_4U | _PAGE_CV_4U | | |
2082 | _PAGE_P_4U | _PAGE_W_4U); | |
2083 | if (tlb_type == hypervisor) | |
2084 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
2085 | _PAGE_CP_4V | _PAGE_CV_4V | | |
2086 | _PAGE_P_4V | _PAGE_W_4V); | |
2087 | ||
2088 | for (; addr < end; addr += VMEMMAP_CHUNK) { | |
2089 | unsigned long *vmem_pp = | |
2090 | vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT); | |
2091 | void *block; | |
2092 | ||
2093 | if (!(*vmem_pp & _PAGE_VALID)) { | |
2094 | block = vmemmap_alloc_block(1UL << 22, node); | |
2095 | if (!block) | |
2096 | return -ENOMEM; | |
2097 | ||
2098 | *vmem_pp = pte_base | __pa(block); | |
2099 | ||
2100 | printk(KERN_INFO "[%p-%p] page_structs=%lu " | |
2101 | "node=%d entry=%lu/%lu\n", start, block, nr, | |
2102 | node, | |
2103 | addr >> VMEMMAP_CHUNK_SHIFT, | |
2104 | VMEMMAP_SIZE >> VMEMMAP_CHUNK_SHIFT); | |
2105 | } | |
2106 | } | |
2107 | return 0; | |
2108 | } | |
2109 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ | |
2110 | ||
c4bce90e DM |
2111 | static void prot_init_common(unsigned long page_none, |
2112 | unsigned long page_shared, | |
2113 | unsigned long page_copy, | |
2114 | unsigned long page_readonly, | |
2115 | unsigned long page_exec_bit) | |
2116 | { | |
2117 | PAGE_COPY = __pgprot(page_copy); | |
0f15952a | 2118 | PAGE_SHARED = __pgprot(page_shared); |
c4bce90e DM |
2119 | |
2120 | protection_map[0x0] = __pgprot(page_none); | |
2121 | protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); | |
2122 | protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); | |
2123 | protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); | |
2124 | protection_map[0x4] = __pgprot(page_readonly); | |
2125 | protection_map[0x5] = __pgprot(page_readonly); | |
2126 | protection_map[0x6] = __pgprot(page_copy); | |
2127 | protection_map[0x7] = __pgprot(page_copy); | |
2128 | protection_map[0x8] = __pgprot(page_none); | |
2129 | protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); | |
2130 | protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); | |
2131 | protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); | |
2132 | protection_map[0xc] = __pgprot(page_readonly); | |
2133 | protection_map[0xd] = __pgprot(page_readonly); | |
2134 | protection_map[0xe] = __pgprot(page_shared); | |
2135 | protection_map[0xf] = __pgprot(page_shared); | |
2136 | } | |
2137 | ||
2138 | static void __init sun4u_pgprot_init(void) | |
2139 | { | |
2140 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2141 | unsigned long page_exec_bit; | |
2142 | ||
2143 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2144 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2145 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2146 | _PAGE_EXEC_4U); | |
2147 | PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2148 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2149 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2150 | _PAGE_EXEC_4U | _PAGE_L_4U); | |
2151 | PAGE_EXEC = __pgprot(_PAGE_EXEC_4U); | |
2152 | ||
2153 | _PAGE_IE = _PAGE_IE_4U; | |
2154 | _PAGE_E = _PAGE_E_4U; | |
2155 | _PAGE_CACHE = _PAGE_CACHE_4U; | |
2156 | ||
2157 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | | |
2158 | __ACCESS_BITS_4U | _PAGE_E_4U); | |
2159 | ||
d1acb421 DM |
2160 | #ifdef CONFIG_DEBUG_PAGEALLOC |
2161 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^ | |
2162 | 0xfffff80000000000; | |
2163 | #else | |
9cc3a1ac | 2164 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ |
c4bce90e | 2165 | 0xfffff80000000000; |
d1acb421 | 2166 | #endif |
9cc3a1ac DM |
2167 | kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | |
2168 | _PAGE_P_4U | _PAGE_W_4U); | |
2169 | ||
2170 | /* XXX Should use 256MB on Panther. XXX */ | |
2171 | kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; | |
c4bce90e DM |
2172 | |
2173 | _PAGE_SZBITS = _PAGE_SZBITS_4U; | |
2174 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | | |
2175 | _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | | |
2176 | _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); | |
2177 | ||
2178 | ||
2179 | page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; | |
2180 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2181 | __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); | |
2182 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2183 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2184 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2185 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2186 | ||
2187 | page_exec_bit = _PAGE_EXEC_4U; | |
2188 | ||
2189 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2190 | page_exec_bit); | |
2191 | } | |
2192 | ||
2193 | static void __init sun4v_pgprot_init(void) | |
2194 | { | |
2195 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2196 | unsigned long page_exec_bit; | |
2197 | ||
2198 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | | |
2199 | _PAGE_CACHE_4V | _PAGE_P_4V | | |
2200 | __ACCESS_BITS_4V | __DIRTY_BITS_4V | | |
2201 | _PAGE_EXEC_4V); | |
2202 | PAGE_KERNEL_LOCKED = PAGE_KERNEL; | |
2203 | PAGE_EXEC = __pgprot(_PAGE_EXEC_4V); | |
2204 | ||
2205 | _PAGE_IE = _PAGE_IE_4V; | |
2206 | _PAGE_E = _PAGE_E_4V; | |
2207 | _PAGE_CACHE = _PAGE_CACHE_4V; | |
2208 | ||
d1acb421 DM |
2209 | #ifdef CONFIG_DEBUG_PAGEALLOC |
2210 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ | |
2211 | 0xfffff80000000000; | |
2212 | #else | |
9cc3a1ac DM |
2213 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ |
2214 | 0xfffff80000000000; | |
d1acb421 | 2215 | #endif |
9cc3a1ac DM |
2216 | kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
2217 | _PAGE_P_4V | _PAGE_W_4V); | |
2218 | ||
d1acb421 DM |
2219 | #ifdef CONFIG_DEBUG_PAGEALLOC |
2220 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^ | |
2221 | 0xfffff80000000000; | |
2222 | #else | |
9cc3a1ac | 2223 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ |
c4bce90e | 2224 | 0xfffff80000000000; |
d1acb421 | 2225 | #endif |
9cc3a1ac DM |
2226 | kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V | |
2227 | _PAGE_P_4V | _PAGE_W_4V); | |
c4bce90e DM |
2228 | |
2229 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | | |
2230 | __ACCESS_BITS_4V | _PAGE_E_4V); | |
2231 | ||
2232 | _PAGE_SZBITS = _PAGE_SZBITS_4V; | |
2233 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | | |
2234 | _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | | |
2235 | _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | | |
2236 | _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); | |
2237 | ||
2238 | page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V; | |
2239 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2240 | __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); | |
2241 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2242 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
2243 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V | | |
2244 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); | |
2245 | ||
2246 | page_exec_bit = _PAGE_EXEC_4V; | |
2247 | ||
2248 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2249 | page_exec_bit); | |
2250 | } | |
2251 | ||
2252 | unsigned long pte_sz_bits(unsigned long sz) | |
2253 | { | |
2254 | if (tlb_type == hypervisor) { | |
2255 | switch (sz) { | |
2256 | case 8 * 1024: | |
2257 | default: | |
2258 | return _PAGE_SZ8K_4V; | |
2259 | case 64 * 1024: | |
2260 | return _PAGE_SZ64K_4V; | |
2261 | case 512 * 1024: | |
2262 | return _PAGE_SZ512K_4V; | |
2263 | case 4 * 1024 * 1024: | |
2264 | return _PAGE_SZ4MB_4V; | |
2265 | }; | |
2266 | } else { | |
2267 | switch (sz) { | |
2268 | case 8 * 1024: | |
2269 | default: | |
2270 | return _PAGE_SZ8K_4U; | |
2271 | case 64 * 1024: | |
2272 | return _PAGE_SZ64K_4U; | |
2273 | case 512 * 1024: | |
2274 | return _PAGE_SZ512K_4U; | |
2275 | case 4 * 1024 * 1024: | |
2276 | return _PAGE_SZ4MB_4U; | |
2277 | }; | |
2278 | } | |
2279 | } | |
2280 | ||
2281 | pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) | |
2282 | { | |
2283 | pte_t pte; | |
cf627156 DM |
2284 | |
2285 | pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); | |
c4bce90e DM |
2286 | pte_val(pte) |= (((unsigned long)space) << 32); |
2287 | pte_val(pte) |= pte_sz_bits(page_size); | |
c4bce90e | 2288 | |
cf627156 | 2289 | return pte; |
c4bce90e DM |
2290 | } |
2291 | ||
2292 | static unsigned long kern_large_tte(unsigned long paddr) | |
2293 | { | |
2294 | unsigned long val; | |
2295 | ||
2296 | val = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2297 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | | |
2298 | _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); | |
2299 | if (tlb_type == hypervisor) | |
2300 | val = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
2301 | _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V | | |
2302 | _PAGE_EXEC_4V | _PAGE_W_4V); | |
2303 | ||
2304 | return val | paddr; | |
2305 | } | |
2306 | ||
c4bce90e DM |
2307 | /* If not locked, zap it. */ |
2308 | void __flush_tlb_all(void) | |
2309 | { | |
2310 | unsigned long pstate; | |
2311 | int i; | |
2312 | ||
2313 | __asm__ __volatile__("flushw\n\t" | |
2314 | "rdpr %%pstate, %0\n\t" | |
2315 | "wrpr %0, %1, %%pstate" | |
2316 | : "=r" (pstate) | |
2317 | : "i" (PSTATE_IE)); | |
8f361453 DM |
2318 | if (tlb_type == hypervisor) { |
2319 | sun4v_mmu_demap_all(); | |
2320 | } else if (tlb_type == spitfire) { | |
c4bce90e DM |
2321 | for (i = 0; i < 64; i++) { |
2322 | /* Spitfire Errata #32 workaround */ | |
2323 | /* NOTE: Always runs on spitfire, so no | |
2324 | * cheetah+ page size encodings. | |
2325 | */ | |
2326 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2327 | "flush %%g6" | |
2328 | : /* No outputs */ | |
2329 | : "r" (0), | |
2330 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2331 | ||
2332 | if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { | |
2333 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2334 | "membar #Sync" | |
2335 | : /* no outputs */ | |
2336 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); | |
2337 | spitfire_put_dtlb_data(i, 0x0UL); | |
2338 | } | |
2339 | ||
2340 | /* Spitfire Errata #32 workaround */ | |
2341 | /* NOTE: Always runs on spitfire, so no | |
2342 | * cheetah+ page size encodings. | |
2343 | */ | |
2344 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2345 | "flush %%g6" | |
2346 | : /* No outputs */ | |
2347 | : "r" (0), | |
2348 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2349 | ||
2350 | if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { | |
2351 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2352 | "membar #Sync" | |
2353 | : /* no outputs */ | |
2354 | : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); | |
2355 | spitfire_put_itlb_data(i, 0x0UL); | |
2356 | } | |
2357 | } | |
2358 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
2359 | cheetah_flush_dtlb_all(); | |
2360 | cheetah_flush_itlb_all(); | |
2361 | } | |
2362 | __asm__ __volatile__("wrpr %0, 0, %%pstate" | |
2363 | : : "r" (pstate)); | |
2364 | } | |
88d70794 DM |
2365 | |
2366 | #ifdef CONFIG_MEMORY_HOTPLUG | |
2367 | ||
2368 | void online_page(struct page *page) | |
2369 | { | |
2370 | ClearPageReserved(page); | |
fcab1e51 NP |
2371 | init_page_count(page); |
2372 | __free_page(page); | |
88d70794 DM |
2373 | totalram_pages++; |
2374 | num_physpages++; | |
2375 | } | |
2376 | ||
88d70794 | 2377 | #endif /* CONFIG_MEMORY_HOTPLUG */ |