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[SPARC64]: Remove ktlb.S instruction patching.
[linux-2.6-block.git] / arch / sparc64 / mm / init.c
CommitLineData
1da177e4
LT		 1/* $Id: init.c,v 1.209 2002/02/09 19:49:31 davem Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/config.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/slab.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
05e14cb3 22#include <linux/kprobes.h>
1ac4f5eb 23#include <linux/cache.h>
1da177e4
LT		 24
25#include <asm/head.h>
26#include <asm/system.h>
27#include <asm/page.h>
28#include <asm/pgalloc.h>
29#include <asm/pgtable.h>
30#include <asm/oplib.h>
31#include <asm/iommu.h>
32#include <asm/io.h>
33#include <asm/uaccess.h>
34#include <asm/mmu_context.h>
35#include <asm/tlbflush.h>
36#include <asm/dma.h>
37#include <asm/starfire.h>
38#include <asm/tlb.h>
39#include <asm/spitfire.h>
40#include <asm/sections.h>
41
42extern void device_scan(void);
43
44struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
45
46unsigned long *sparc64_valid_addr_bitmap;
47
48/* Ugly, but necessary... -DaveM */
1ac4f5eb
DM		 49unsigned long phys_base __read_mostly;
50unsigned long kern_base __read_mostly;
51unsigned long kern_size __read_mostly;
52unsigned long pfn_base __read_mostly;
1da177e4
LT		 53
54/* This is even uglier. We have a problem where the kernel may not be
55 * located at phys_base. However, initial __alloc_bootmem() calls need to
56 * be adjusted to be within the 4-8Megs that the kernel is mapped to, else
57 * those page mappings wont work. Things are ok after inherit_prom_mappings
58 * is called though. Dave says he'll clean this up some other time.
59 * -- BenC
60 */
61static unsigned long bootmap_base;
62
63/* get_new_mmu_context() uses "cache + 1". */
64DEFINE_SPINLOCK(ctx_alloc_lock);
65unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
66#define CTX_BMAP_SLOTS (1UL << (CTX_NR_BITS - 6))
67unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
68
69/* References to special section boundaries */
70extern char _start[], _end[];
71
72/* Initial ramdisk setup */
73extern unsigned long sparc_ramdisk_image64;
74extern unsigned int sparc_ramdisk_image;
75extern unsigned int sparc_ramdisk_size;
76
1ac4f5eb 77struct page *mem_map_zero __read_mostly;
1da177e4
LT		 78
79int bigkernel = 0;
80
81/* XXX Tune this... */
82#define PGT_CACHE_LOW 25
83#define PGT_CACHE_HIGH 50
84
85void check_pgt_cache(void)
86{
87 preempt_disable();
88 if (pgtable_cache_size > PGT_CACHE_HIGH) {
89 do {
90 if (pgd_quicklist)
91 free_pgd_slow(get_pgd_fast());
92 if (pte_quicklist[0])
93 free_pte_slow(pte_alloc_one_fast(NULL, 0));
94 if (pte_quicklist[1])
95 free_pte_slow(pte_alloc_one_fast(NULL, 1 << (PAGE_SHIFT + 10)));
96 } while (pgtable_cache_size > PGT_CACHE_LOW);
97 }
98 preempt_enable();
99}
100
101#ifdef CONFIG_DEBUG_DCFLUSH
102atomic_t dcpage_flushes = ATOMIC_INIT(0);
103#ifdef CONFIG_SMP
104atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
105#endif
106#endif
107
108__inline__ void flush_dcache_page_impl(struct page *page)
109{
110#ifdef CONFIG_DEBUG_DCFLUSH
111 atomic_inc(&dcpage_flushes);
112#endif
113
114#ifdef DCACHE_ALIASING_POSSIBLE
115 __flush_dcache_page(page_address(page),
116 ((tlb_type == spitfire) &&
117 page_mapping(page) != NULL));
118#else
119 if (page_mapping(page) != NULL &&
120 tlb_type == spitfire)
121 __flush_icache_page(__pa(page_address(page)));
122#endif
123}
124
125#define PG_dcache_dirty PG_arch_1
48b0e548
DM		 126#define PG_dcache_cpu_shift 24
127#define PG_dcache_cpu_mask (256 - 1)
128
129#if NR_CPUS > 256
130#error D-cache dirty tracking and thread_info->cpu need fixing for > 256 cpus
131#endif
1da177e4
LT		 132
133#define dcache_dirty_cpu(page) \
48b0e548 134 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
1da177e4
LT		 135
136static __inline__ void set_dcache_dirty(struct page *page, int this_cpu)
137{
138 unsigned long mask = this_cpu;
48b0e548
DM		 139 unsigned long non_cpu_bits;
140
141 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
142 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
143
1da177e4
LT		 144 __asm__ __volatile__("1:\n\t"
145 "ldx [%2], %%g7\n\t"
146 "and %%g7, %1, %%g1\n\t"
147 "or %%g1, %0, %%g1\n\t"
148 "casx [%2], %%g7, %%g1\n\t"
149 "cmp %%g7, %%g1\n\t"
b445e26c 150 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 151 "bne,pn %%xcc, 1b\n\t"
b445e26c 152 " nop"
1da177e4
LT		 153 : /* no outputs */
154 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
155 : "g1", "g7");
156}
157
158static __inline__ void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
159{
160 unsigned long mask = (1UL << PG_dcache_dirty);
161
162 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
163 "1:\n\t"
164 "ldx [%2], %%g7\n\t"
48b0e548 165 "srlx %%g7, %4, %%g1\n\t"
1da177e4
LT		 166 "and %%g1, %3, %%g1\n\t"
167 "cmp %%g1, %0\n\t"
168 "bne,pn %%icc, 2f\n\t"
169 " andn %%g7, %1, %%g1\n\t"
170 "casx [%2], %%g7, %%g1\n\t"
171 "cmp %%g7, %%g1\n\t"
b445e26c 172 "membar #StoreLoad | #StoreStore\n\t"
1da177e4 173 "bne,pn %%xcc, 1b\n\t"
b445e26c 174 " nop\n"
1da177e4
LT		 175 "2:"
176 : /* no outputs */
177 : "r" (cpu), "r" (mask), "r" (&page->flags),
48b0e548
DM		 178 "i" (PG_dcache_cpu_mask),
179 "i" (PG_dcache_cpu_shift)
1da177e4
LT		 180 : "g1", "g7");
181}
182
183extern void __update_mmu_cache(unsigned long mmu_context_hw, unsigned long address, pte_t pte, int code);
184
185void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t pte)
186{
187 struct page *page;
188 unsigned long pfn;
189 unsigned long pg_flags;
190
191 pfn = pte_pfn(pte);
192 if (pfn_valid(pfn) &&
193 (page = pfn_to_page(pfn), page_mapping(page)) &&
194 ((pg_flags = page->flags) & (1UL << PG_dcache_dirty))) {
48b0e548
DM		 195 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
196 PG_dcache_cpu_mask);
1da177e4
LT		 197 int this_cpu = get_cpu();
198
199 /* This is just to optimize away some function calls
200 * in the SMP case.
201 */
202 if (cpu == this_cpu)
203 flush_dcache_page_impl(page);
204 else
205 smp_flush_dcache_page_impl(page, cpu);
206
207 clear_dcache_dirty_cpu(page, cpu);
208
209 put_cpu();
210 }
211
212 if (get_thread_fault_code())
213 __update_mmu_cache(CTX_NRBITS(vma->vm_mm->context),
214 address, pte, get_thread_fault_code());
215}
216
217void flush_dcache_page(struct page *page)
218{
a9546f59
DM		 219 struct address_space *mapping;
220 int this_cpu;
1da177e4 221
a9546f59
DM		 222 /* Do not bother with the expensive D-cache flush if it
223 * is merely the zero page. The 'bigcore' testcase in GDB
224 * causes this case to run millions of times.
225 */
226 if (page == ZERO_PAGE(0))
227 return;
228
229 this_cpu = get_cpu();
230
231 mapping = page_mapping(page);
1da177e4 232 if (mapping && !mapping_mapped(mapping)) {
a9546f59 233 int dirty = test_bit(PG_dcache_dirty, &page->flags);
1da177e4 234 if (dirty) {
a9546f59
DM		 235 int dirty_cpu = dcache_dirty_cpu(page);
236
1da177e4
LT		 237 if (dirty_cpu == this_cpu)
238 goto out;
239 smp_flush_dcache_page_impl(page, dirty_cpu);
240 }
241 set_dcache_dirty(page, this_cpu);
242 } else {
243 /* We could delay the flush for the !page_mapping
244 * case too. But that case is for exec env/arg
245 * pages and those are %99 certainly going to get
246 * faulted into the tlb (and thus flushed) anyways.
247 */
248 flush_dcache_page_impl(page);
249 }
250
251out:
252 put_cpu();
253}
254
05e14cb3 255void __kprobes flush_icache_range(unsigned long start, unsigned long end)
1da177e4
LT		 256{
257 /* Cheetah has coherent I-cache. */
258 if (tlb_type == spitfire) {
259 unsigned long kaddr;
260
261 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE)
262 __flush_icache_page(__get_phys(kaddr));
263 }
264}
265
266unsigned long page_to_pfn(struct page *page)
267{
268 return (unsigned long) ((page - mem_map) + pfn_base);
269}
270
271struct page *pfn_to_page(unsigned long pfn)
272{
273 return (mem_map + (pfn - pfn_base));
274}
275
276void show_mem(void)
277{
278 printk("Mem-info:\n");
279 show_free_areas();
280 printk("Free swap: %6ldkB\n",
281 nr_swap_pages << (PAGE_SHIFT-10));
282 printk("%ld pages of RAM\n", num_physpages);
283 printk("%d free pages\n", nr_free_pages());
284 printk("%d pages in page table cache\n",pgtable_cache_size);
285}
286
287void mmu_info(struct seq_file *m)
288{
289 if (tlb_type == cheetah)
290 seq_printf(m, "MMU Type\t: Cheetah\n");
291 else if (tlb_type == cheetah_plus)
292 seq_printf(m, "MMU Type\t: Cheetah+\n");
293 else if (tlb_type == spitfire)
294 seq_printf(m, "MMU Type\t: Spitfire\n");
295 else
296 seq_printf(m, "MMU Type\t: ???\n");
297
298#ifdef CONFIG_DEBUG_DCFLUSH
299 seq_printf(m, "DCPageFlushes\t: %d\n",
300 atomic_read(&dcpage_flushes));
301#ifdef CONFIG_SMP
302 seq_printf(m, "DCPageFlushesXC\t: %d\n",
303 atomic_read(&dcpage_flushes_xcall));
304#endif /* CONFIG_SMP */
305#endif /* CONFIG_DEBUG_DCFLUSH */
306}
307
308struct linux_prom_translation {
309 unsigned long virt;
310 unsigned long size;
311 unsigned long data;
312};
313
314extern unsigned long prom_boot_page;
315extern void prom_remap(unsigned long physpage, unsigned long virtpage, int mmu_ihandle);
316extern int prom_get_mmu_ihandle(void);
317extern void register_prom_callbacks(void);
318
319/* Exported for SMP bootup purposes. */
320unsigned long kern_locked_tte_data;
321
1ac4f5eb
DM		 322/* Exported for kernel TLB miss handling in ktlb.S */
323unsigned long prom_pmd_phys __read_mostly;
324unsigned int swapper_pgd_zero __read_mostly;
325
1da177e4
LT		 326void __init early_pgtable_allocfail(char *type)
327{
328 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
329 prom_halt();
330}
331
332#define BASE_PAGE_SIZE 8192
333static pmd_t *prompmd;
334
335/*
336 * Translate PROM's mapping we capture at boot time into physical address.
337 * The second parameter is only set from prom_callback() invocations.
338 */
339unsigned long prom_virt_to_phys(unsigned long promva, int *error)
340{
341 pmd_t *pmdp = prompmd + ((promva >> 23) & 0x7ff);
342 pte_t *ptep;
343 unsigned long base;
344
345 if (pmd_none(*pmdp)) {
346 if (error)
347 *error = 1;
348 return(0);
349 }
350 ptep = (pte_t *)__pmd_page(*pmdp) + ((promva >> 13) & 0x3ff);
351 if (!pte_present(*ptep)) {
352 if (error)
353 *error = 1;
354 return(0);
355 }
356 if (error) {
357 *error = 0;
358 return(pte_val(*ptep));
359 }
360 base = pte_val(*ptep) & _PAGE_PADDR;
361 return(base + (promva & (BASE_PAGE_SIZE - 1)));
362}
363
364static void inherit_prom_mappings(void)
365{
366 struct linux_prom_translation *trans;
367 unsigned long phys_page, tte_vaddr, tte_data;
368 void (*remap_func)(unsigned long, unsigned long, int);
369 pmd_t *pmdp;
370 pte_t *ptep;
371 int node, n, i, tsz;
1da177e4
LT		 372
373 node = prom_finddevice("/virtual-memory");
374 n = prom_getproplen(node, "translations");
375 if (n == 0 || n == -1) {
376 prom_printf("Couldn't get translation property\n");
377 prom_halt();
378 }
379 n += 5 * sizeof(struct linux_prom_translation);
380 for (tsz = 1; tsz < n; tsz <<= 1)
381 /* empty */;
382 trans = __alloc_bootmem(tsz, SMP_CACHE_BYTES, bootmap_base);
383 if (trans == NULL) {
384 prom_printf("inherit_prom_mappings: Cannot alloc translations.\n");
385 prom_halt();
386 }
387 memset(trans, 0, tsz);
388
389 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
390 prom_printf("Couldn't get translation property\n");
391 prom_halt();
392 }
393 n = n / sizeof(*trans);
394
395 /*
396 * The obp translations are saved based on 8k pagesize, since obp can
397 * use a mixture of pagesizes. Misses to the 0xf0000000 - 0x100000000,
398 * ie obp range, are handled in entry.S and do not use the vpte scheme
399 * (see rant in inherit_locked_prom_mappings()).
400 */
401#define OBP_PMD_SIZE 2048
402 prompmd = __alloc_bootmem(OBP_PMD_SIZE, OBP_PMD_SIZE, bootmap_base);
403 if (prompmd == NULL)
404 early_pgtable_allocfail("pmd");
405 memset(prompmd, 0, OBP_PMD_SIZE);
406 for (i = 0; i < n; i++) {
407 unsigned long vaddr;
408
409 if (trans[i].virt >= LOW_OBP_ADDRESS && trans[i].virt < HI_OBP_ADDRESS) {
410 for (vaddr = trans[i].virt;
411 ((vaddr < trans[i].virt + trans[i].size) &&
412 (vaddr < HI_OBP_ADDRESS));
413 vaddr += BASE_PAGE_SIZE) {
414 unsigned long val;
415
416 pmdp = prompmd + ((vaddr >> 23) & 0x7ff);
417 if (pmd_none(*pmdp)) {
418 ptep = __alloc_bootmem(BASE_PAGE_SIZE,
419 BASE_PAGE_SIZE,
420 bootmap_base);
421 if (ptep == NULL)
422 early_pgtable_allocfail("pte");
423 memset(ptep, 0, BASE_PAGE_SIZE);
424 pmd_set(pmdp, ptep);
425 }
426 ptep = (pte_t *)__pmd_page(*pmdp) +
427 ((vaddr >> 13) & 0x3ff);
428
429 val = trans[i].data;
430
431 /* Clear diag TTE bits. */
432 if (tlb_type == spitfire)
433 val &= ~0x0003fe0000000000UL;
434
435 set_pte_at(&init_mm, vaddr,
436 ptep, __pte(val | _PAGE_MODIFIED));
437 trans[i].data += BASE_PAGE_SIZE;
438 }
439 }
440 }
1ac4f5eb 441 prom_pmd_phys = __pa(prompmd);
1da177e4
LT		 442
443 /* Now fixup OBP's idea about where we really are mapped. */
444 prom_printf("Remapping the kernel... ");
445
446 /* Spitfire Errata #32 workaround */
447 /* NOTE: Using plain zero for the context value is
448 * correct here, we are not using the Linux trap
449 * tables yet so we should not use the special
450 * UltraSPARC-III+ page size encodings yet.
451 */
452 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
453 "flush %%g6"
454 : /* No outputs */
455 : "r" (0), "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
456
457 switch (tlb_type) {
458 default:
459 case spitfire:
460 phys_page = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
461 break;
462
463 case cheetah:
464 case cheetah_plus:
465 phys_page = cheetah_get_litlb_data(sparc64_highest_locked_tlbent());
466 break;
467 };
468
469 phys_page &= _PAGE_PADDR;
470 phys_page += ((unsigned long)&prom_boot_page -
471 (unsigned long)KERNBASE);
472
473 if (tlb_type == spitfire) {
474 /* Lock this into i/d tlb entry 59 */
475 __asm__ __volatile__(
476 "stxa %%g0, [%2] %3\n\t"
477 "stxa %0, [%1] %4\n\t"
478 "membar #Sync\n\t"
479 "flush %%g6\n\t"
480 "stxa %%g0, [%2] %5\n\t"
481 "stxa %0, [%1] %6\n\t"
482 "membar #Sync\n\t"
483 "flush %%g6"
484 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
485 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
486 "r" (59 << 3), "r" (TLB_TAG_ACCESS),
487 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
488 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
489 : "memory");
490 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
491 /* Lock this into i/d tlb-0 entry 11 */
492 __asm__ __volatile__(
493 "stxa %%g0, [%2] %3\n\t"
494 "stxa %0, [%1] %4\n\t"
495 "membar #Sync\n\t"
496 "flush %%g6\n\t"
497 "stxa %%g0, [%2] %5\n\t"
498 "stxa %0, [%1] %6\n\t"
499 "membar #Sync\n\t"
500 "flush %%g6"
501 : : "r" (phys_page | _PAGE_VALID | _PAGE_SZ8K | _PAGE_CP |
502 _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W),
503 "r" ((0 << 16) | (11 << 3)), "r" (TLB_TAG_ACCESS),
504 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS),
505 "i" (ASI_IMMU), "i" (ASI_ITLB_DATA_ACCESS)
506 : "memory");
507 } else {
508 /* Implement me :-) */
509 BUG();
510 }
511
512 tte_vaddr = (unsigned long) KERNBASE;
513
514 /* Spitfire Errata #32 workaround */
515 /* NOTE: Using plain zero for the context value is
516 * correct here, we are not using the Linux trap
517 * tables yet so we should not use the special
518 * UltraSPARC-III+ page size encodings yet.
519 */
520 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
521 "flush %%g6"
522 : /* No outputs */
523 : "r" (0),
524 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
525
526 if (tlb_type == spitfire)
527 tte_data = spitfire_get_dtlb_data(sparc64_highest_locked_tlbent());
528 else
529 tte_data = cheetah_get_ldtlb_data(sparc64_highest_locked_tlbent());
530
531 kern_locked_tte_data = tte_data;
532
533 remap_func = (void *) ((unsigned long) &prom_remap -
534 (unsigned long) &prom_boot_page);
535
536
537 /* Spitfire Errata #32 workaround */
538 /* NOTE: Using plain zero for the context value is
539 * correct here, we are not using the Linux trap
540 * tables yet so we should not use the special
541 * UltraSPARC-III+ page size encodings yet.
542 */
543 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
544 "flush %%g6"
545 : /* No outputs */
546 : "r" (0),
547 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
548
549 remap_func((tlb_type == spitfire ?
550 (spitfire_get_dtlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR) :
551 (cheetah_get_litlb_data(sparc64_highest_locked_tlbent()) & _PAGE_PADDR)),
552 (unsigned long) KERNBASE,
553 prom_get_mmu_ihandle());
554
555 if (bigkernel)
556 remap_func(((tte_data + 0x400000) & _PAGE_PADDR),
557 (unsigned long) KERNBASE + 0x400000, prom_get_mmu_ihandle());
558
559 /* Flush out that temporary mapping. */
560 spitfire_flush_dtlb_nucleus_page(0x0);
561 spitfire_flush_itlb_nucleus_page(0x0);
562
563 /* Now lock us back into the TLBs via OBP. */
564 prom_dtlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
565 prom_itlb_load(sparc64_highest_locked_tlbent(), tte_data, tte_vaddr);
566 if (bigkernel) {
567 prom_dtlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
568 tte_vaddr + 0x400000);
569 prom_itlb_load(sparc64_highest_locked_tlbent()-1, tte_data + 0x400000,
570 tte_vaddr + 0x400000);
571 }
572
573 /* Re-read translations property. */
574 if ((n = prom_getproperty(node, "translations", (char *)trans, tsz)) == -1) {
575 prom_printf("Couldn't get translation property\n");
576 prom_halt();
577 }
578 n = n / sizeof(*trans);
579
580 for (i = 0; i < n; i++) {
581 unsigned long vaddr = trans[i].virt;
582 unsigned long size = trans[i].size;
583
584 if (vaddr < 0xf0000000UL) {
585 unsigned long avoid_start = (unsigned long) KERNBASE;
586 unsigned long avoid_end = avoid_start + (4 * 1024 * 1024);
587
588 if (bigkernel)
589 avoid_end += (4 * 1024 * 1024);
590 if (vaddr < avoid_start) {
591 unsigned long top = vaddr + size;
592
593 if (top > avoid_start)
594 top = avoid_start;
595 prom_unmap(top - vaddr, vaddr);
596 }
597 if ((vaddr + size) > avoid_end) {
598 unsigned long bottom = vaddr;
599
600 if (bottom < avoid_end)
601 bottom = avoid_end;
602 prom_unmap((vaddr + size) - bottom, bottom);
603 }
604 }
605 }
606
607 prom_printf("done.\n");
608
609 register_prom_callbacks();
610}
611
612/* The OBP specifications for sun4u mark 0xfffffffc00000000 and
613 * upwards as reserved for use by the firmware (I wonder if this
614 * will be the same on Cheetah...). We use this virtual address
615 * range for the VPTE table mappings of the nucleus so we need
616 * to zap them when we enter the PROM. -DaveM
617 */
618static void __flush_nucleus_vptes(void)
619{
620 unsigned long prom_reserved_base = 0xfffffffc00000000UL;
621 int i;
622
623 /* Only DTLB must be checked for VPTE entries. */
624 if (tlb_type == spitfire) {
625 for (i = 0; i < 63; i++) {
626 unsigned long tag;
627
628 /* Spitfire Errata #32 workaround */
629 /* NOTE: Always runs on spitfire, so no cheetah+
630 * page size encodings.
631 */
632 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
633 "flush %%g6"
634 : /* No outputs */
635 : "r" (0),
636 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
637
638 tag = spitfire_get_dtlb_tag(i);
639 if (((tag & ~(PAGE_MASK)) == 0) &&
640 ((tag & (PAGE_MASK)) >= prom_reserved_base)) {
641 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
642 "membar #Sync"
643 : /* no outputs */
644 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
645 spitfire_put_dtlb_data(i, 0x0UL);
646 }
647 }
648 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
649 for (i = 0; i < 512; i++) {
650 unsigned long tag = cheetah_get_dtlb_tag(i, 2);
651
652 if ((tag & ~PAGE_MASK) == 0 &&
653 (tag & PAGE_MASK) >= prom_reserved_base) {
654 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
655 "membar #Sync"
656 : /* no outputs */
657 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
658 cheetah_put_dtlb_data(i, 0x0UL, 2);
659 }
660
661 if (tlb_type != cheetah_plus)
662 continue;
663
664 tag = cheetah_get_dtlb_tag(i, 3);
665
666 if ((tag & ~PAGE_MASK) == 0 &&
667 (tag & PAGE_MASK) >= prom_reserved_base) {
668 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
669 "membar #Sync"
670 : /* no outputs */
671 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
672 cheetah_put_dtlb_data(i, 0x0UL, 3);
673 }
674 }
675 } else {
676 /* Implement me :-) */
677 BUG();
678 }
679}
680
681static int prom_ditlb_set;
682struct prom_tlb_entry {
683 int tlb_ent;
684 unsigned long tlb_tag;
685 unsigned long tlb_data;
686};
687struct prom_tlb_entry prom_itlb[16], prom_dtlb[16];
688
689void prom_world(int enter)
690{
691 unsigned long pstate;
692 int i;
693
694 if (!enter)
695 set_fs((mm_segment_t) { get_thread_current_ds() });
696
697 if (!prom_ditlb_set)
698 return;
699
700 /* Make sure the following runs atomically. */
701 __asm__ __volatile__("flushw\n\t"
702 "rdpr %%pstate, %0\n\t"
703 "wrpr %0, %1, %%pstate"
704 : "=r" (pstate)
705 : "i" (PSTATE_IE));
706
707 if (enter) {
708 /* Kick out nucleus VPTEs. */
709 __flush_nucleus_vptes();
710
711 /* Install PROM world. */
712 for (i = 0; i < 16; i++) {
713 if (prom_dtlb[i].tlb_ent != -1) {
714 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
715 "membar #Sync"
716 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
717 "i" (ASI_DMMU));
718 if (tlb_type == spitfire)
719 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
720 prom_dtlb[i].tlb_data);
721 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
722 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
723 prom_dtlb[i].tlb_data);
724 }
725 if (prom_itlb[i].tlb_ent != -1) {
726 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
727 "membar #Sync"
728 : : "r" (prom_itlb[i].tlb_tag),
729 "r" (TLB_TAG_ACCESS),
730 "i" (ASI_IMMU));
731 if (tlb_type == spitfire)
732 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
733 prom_itlb[i].tlb_data);
734 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
735 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
736 prom_itlb[i].tlb_data);
737 }
738 }
739 } else {
740 for (i = 0; i < 16; i++) {
741 if (prom_dtlb[i].tlb_ent != -1) {
742 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
743 "membar #Sync"
744 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
745 if (tlb_type == spitfire)
746 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
747 else
748 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
749 }
750 if (prom_itlb[i].tlb_ent != -1) {
751 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
752 "membar #Sync"
753 : : "r" (TLB_TAG_ACCESS),
754 "i" (ASI_IMMU));
755 if (tlb_type == spitfire)
756 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
757 else
758 cheetah_put_litlb_data(prom_itlb[i].tlb_ent, 0x0UL);
759 }
760 }
761 }
762 __asm__ __volatile__("wrpr %0, 0, %%pstate"
763 : : "r" (pstate));
764}
765
766void inherit_locked_prom_mappings(int save_p)
767{
768 int i;
769 int dtlb_seen = 0;
770 int itlb_seen = 0;
771
772 /* Fucking losing PROM has more mappings in the TLB, but
773 * it (conveniently) fails to mention any of these in the
774 * translations property. The only ones that matter are
775 * the locked PROM tlb entries, so we impose the following
776 * irrecovable rule on the PROM, it is allowed 8 locked
777 * entries in the ITLB and 8 in the DTLB.
778 *
779 * Supposedly the upper 16GB of the address space is
780 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
781 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
782 * used between the client program and the firmware on sun5
783 * systems to coordinate mmu mappings is also COMPLETELY
784 * UNDOCUMENTED!!!!!! Thanks S(t)un!
785 */
786 if (save_p) {
787 for (i = 0; i < 16; i++) {
788 prom_itlb[i].tlb_ent = -1;
789 prom_dtlb[i].tlb_ent = -1;
790 }
791 }
792 if (tlb_type == spitfire) {
793 int high = SPITFIRE_HIGHEST_LOCKED_TLBENT - bigkernel;
794 for (i = 0; i < high; i++) {
795 unsigned long data;
796
797 /* Spitfire Errata #32 workaround */
798 /* NOTE: Always runs on spitfire, so no cheetah+
799 * page size encodings.
800 */
801 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
802 "flush %%g6"
803 : /* No outputs */
804 : "r" (0),
805 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
806
807 data = spitfire_get_dtlb_data(i);
808 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
809 unsigned long tag;
810
811 /* Spitfire Errata #32 workaround */
812 /* NOTE: Always runs on spitfire, so no
813 * cheetah+ page size encodings.
814 */
815 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
816 "flush %%g6"
817 : /* No outputs */
818 : "r" (0),
819 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
820
821 tag = spitfire_get_dtlb_tag(i);
822 if (save_p) {
823 prom_dtlb[dtlb_seen].tlb_ent = i;
824 prom_dtlb[dtlb_seen].tlb_tag = tag;
825 prom_dtlb[dtlb_seen].tlb_data = data;
826 }
827 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
828 "membar #Sync"
829 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
830 spitfire_put_dtlb_data(i, 0x0UL);
831
832 dtlb_seen++;
833 if (dtlb_seen > 15)
834 break;
835 }
836 }
837
838 for (i = 0; i < high; i++) {
839 unsigned long data;
840
841 /* Spitfire Errata #32 workaround */
842 /* NOTE: Always runs on spitfire, so no
843 * cheetah+ page size encodings.
844 */
845 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
846 "flush %%g6"
847 : /* No outputs */
848 : "r" (0),
849 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
850
851 data = spitfire_get_itlb_data(i);
852 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
853 unsigned long tag;
854
855 /* Spitfire Errata #32 workaround */
856 /* NOTE: Always runs on spitfire, so no
857 * cheetah+ page size encodings.
858 */
859 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
860 "flush %%g6"
861 : /* No outputs */
862 : "r" (0),
863 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
864
865 tag = spitfire_get_itlb_tag(i);
866 if (save_p) {
867 prom_itlb[itlb_seen].tlb_ent = i;
868 prom_itlb[itlb_seen].tlb_tag = tag;
869 prom_itlb[itlb_seen].tlb_data = data;
870 }
871 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
872 "membar #Sync"
873 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
874 spitfire_put_itlb_data(i, 0x0UL);
875
876 itlb_seen++;
877 if (itlb_seen > 15)
878 break;
879 }
880 }
881 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
882 int high = CHEETAH_HIGHEST_LOCKED_TLBENT - bigkernel;
883
884 for (i = 0; i < high; i++) {
885 unsigned long data;
886
887 data = cheetah_get_ldtlb_data(i);
888 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
889 unsigned long tag;
890
891 tag = cheetah_get_ldtlb_tag(i);
892 if (save_p) {
893 prom_dtlb[dtlb_seen].tlb_ent = i;
894 prom_dtlb[dtlb_seen].tlb_tag = tag;
895 prom_dtlb[dtlb_seen].tlb_data = data;
896 }
897 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
898 "membar #Sync"
899 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
900 cheetah_put_ldtlb_data(i, 0x0UL);
901
902 dtlb_seen++;
903 if (dtlb_seen > 15)
904 break;
905 }
906 }
907
908 for (i = 0; i < high; i++) {
909 unsigned long data;
910
911 data = cheetah_get_litlb_data(i);
912 if ((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
913 unsigned long tag;
914
915 tag = cheetah_get_litlb_tag(i);
916 if (save_p) {
917 prom_itlb[itlb_seen].tlb_ent = i;
918 prom_itlb[itlb_seen].tlb_tag = tag;
919 prom_itlb[itlb_seen].tlb_data = data;
920 }
921 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
922 "membar #Sync"
923 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
924 cheetah_put_litlb_data(i, 0x0UL);
925
926 itlb_seen++;
927 if (itlb_seen > 15)
928 break;
929 }
930 }
931 } else {
932 /* Implement me :-) */
933 BUG();
934 }
935 if (save_p)
936 prom_ditlb_set = 1;
937}
938
939/* Give PROM back his world, done during reboots... */
940void prom_reload_locked(void)
941{
942 int i;
943
944 for (i = 0; i < 16; i++) {
945 if (prom_dtlb[i].tlb_ent != -1) {
946 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
947 "membar #Sync"
948 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
949 "i" (ASI_DMMU));
950 if (tlb_type == spitfire)
951 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
952 prom_dtlb[i].tlb_data);
953 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
954 cheetah_put_ldtlb_data(prom_dtlb[i].tlb_ent,
955 prom_dtlb[i].tlb_data);
956 }
957
958 if (prom_itlb[i].tlb_ent != -1) {
959 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
960 "membar #Sync"
961 : : "r" (prom_itlb[i].tlb_tag),
962 "r" (TLB_TAG_ACCESS),
963 "i" (ASI_IMMU));
964 if (tlb_type == spitfire)
965 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
966 prom_itlb[i].tlb_data);
967 else
968 cheetah_put_litlb_data(prom_itlb[i].tlb_ent,
969 prom_itlb[i].tlb_data);
970 }
971 }
972}
973
974#ifdef DCACHE_ALIASING_POSSIBLE
975void __flush_dcache_range(unsigned long start, unsigned long end)
976{
977 unsigned long va;
978
979 if (tlb_type == spitfire) {
980 int n = 0;
981
982 for (va = start; va < end; va += 32) {
983 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
984 if (++n >= 512)
985 break;
986 }
987 } else {
988 start = __pa(start);
989 end = __pa(end);
990 for (va = start; va < end; va += 32)
991 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
992 "membar #Sync"
993 : /* no outputs */
994 : "r" (va),
995 "i" (ASI_DCACHE_INVALIDATE));
996 }
997}
998#endif /* DCACHE_ALIASING_POSSIBLE */
999
1000/* If not locked, zap it. */
1001void __flush_tlb_all(void)
1002{
1003 unsigned long pstate;
1004 int i;
1005
1006 __asm__ __volatile__("flushw\n\t"
1007 "rdpr %%pstate, %0\n\t"
1008 "wrpr %0, %1, %%pstate"
1009 : "=r" (pstate)
1010 : "i" (PSTATE_IE));
1011 if (tlb_type == spitfire) {
1012 for (i = 0; i < 64; i++) {
1013 /* Spitfire Errata #32 workaround */
1014 /* NOTE: Always runs on spitfire, so no
1015 * cheetah+ page size encodings.
1016 */
1017 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1018 "flush %%g6"
1019 : /* No outputs */
1020 : "r" (0),
1021 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1022
1023 if (!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
1024 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1025 "membar #Sync"
1026 : /* no outputs */
1027 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
1028 spitfire_put_dtlb_data(i, 0x0UL);
1029 }
1030
1031 /* Spitfire Errata #32 workaround */
1032 /* NOTE: Always runs on spitfire, so no
1033 * cheetah+ page size encodings.
1034 */
1035 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
1036 "flush %%g6"
1037 : /* No outputs */
1038 : "r" (0),
1039 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
1040
1041 if (!(spitfire_get_itlb_data(i) & _PAGE_L)) {
1042 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
1043 "membar #Sync"
1044 : /* no outputs */
1045 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
1046 spitfire_put_itlb_data(i, 0x0UL);
1047 }
1048 }
1049 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1050 cheetah_flush_dtlb_all();
1051 cheetah_flush_itlb_all();
1052 }
1053 __asm__ __volatile__("wrpr %0, 0, %%pstate"
1054 : : "r" (pstate));
1055}
1056
1057/* Caller does TLB context flushing on local CPU if necessary.
1058 * The caller also ensures that CTX_VALID(mm->context) is false.
1059 *
1060 * We must be careful about boundary cases so that we never
1061 * let the user have CTX 0 (nucleus) or we ever use a CTX
1062 * version of zero (and thus NO_CONTEXT would not be caught
1063 * by version mis-match tests in mmu_context.h).
1064 */
1065void get_new_mmu_context(struct mm_struct *mm)
1066{
1067 unsigned long ctx, new_ctx;
1068 unsigned long orig_pgsz_bits;
1069
1070
1071 spin_lock(&ctx_alloc_lock);
1072 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
1073 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
1074 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
1075 if (new_ctx >= (1 << CTX_NR_BITS)) {
1076 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
1077 if (new_ctx >= ctx) {
1078 int i;
1079 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
1080 CTX_FIRST_VERSION;
1081 if (new_ctx == 1)
1082 new_ctx = CTX_FIRST_VERSION;
1083
1084 /* Don't call memset, for 16 entries that's just
1085 * plain silly...
1086 */
1087 mmu_context_bmap[0] = 3;
1088 mmu_context_bmap[1] = 0;
1089 mmu_context_bmap[2] = 0;
1090 mmu_context_bmap[3] = 0;
1091 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1092 mmu_context_bmap[i + 0] = 0;
1093 mmu_context_bmap[i + 1] = 0;
1094 mmu_context_bmap[i + 2] = 0;
1095 mmu_context_bmap[i + 3] = 0;
1096 }
1097 goto out;
1098 }
1099 }
1100 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1101 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1102out:
1103 tlb_context_cache = new_ctx;
1104 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
1105 spin_unlock(&ctx_alloc_lock);
1106}
1107
1108#ifndef CONFIG_SMP
1109struct pgtable_cache_struct pgt_quicklists;
1110#endif
1111
1112/* OK, we have to color these pages. The page tables are accessed
1113 * by non-Dcache enabled mapping in the VPTE area by the dtlb_backend.S
1114 * code, as well as by PAGE_OFFSET range direct-mapped addresses by
1115 * other parts of the kernel. By coloring, we make sure that the tlbmiss
1116 * fast handlers do not get data from old/garbage dcache lines that
1117 * correspond to an old/stale virtual address (user/kernel) that
1118 * previously mapped the pagetable page while accessing vpte range
1119 * addresses. The idea is that if the vpte color and PAGE_OFFSET range
1120 * color is the same, then when the kernel initializes the pagetable
1121 * using the later address range, accesses with the first address
1122 * range will see the newly initialized data rather than the garbage.
1123 */
1124#ifdef DCACHE_ALIASING_POSSIBLE
1125#define DC_ALIAS_SHIFT 1
1126#else
1127#define DC_ALIAS_SHIFT 0
1128#endif
8edf72eb 1129pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
1da177e4
LT		 1130{
1131 struct page *page;
1132 unsigned long color;
1133
1134 {
1135 pte_t *ptep = pte_alloc_one_fast(mm, address);
1136
1137 if (ptep)
1138 return ptep;
1139 }
1140
1141 color = VPTE_COLOR(address);
1142 page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, DC_ALIAS_SHIFT);
1143 if (page) {
1144 unsigned long *to_free;
1145 unsigned long paddr;
1146 pte_t *pte;
1147
1148#ifdef DCACHE_ALIASING_POSSIBLE
1149 set_page_count(page, 1);
1150 ClearPageCompound(page);
1151
1152 set_page_count((page + 1), 1);
1153 ClearPageCompound(page + 1);
1154#endif
1155 paddr = (unsigned long) page_address(page);
1156 memset((char *)paddr, 0, (PAGE_SIZE << DC_ALIAS_SHIFT));
1157
1158 if (!color) {
1159 pte = (pte_t *) paddr;
1160 to_free = (unsigned long *) (paddr + PAGE_SIZE);
1161 } else {
1162 pte = (pte_t *) (paddr + PAGE_SIZE);
1163 to_free = (unsigned long *) paddr;
1164 }
1165
1166#ifdef DCACHE_ALIASING_POSSIBLE
1167 /* Now free the other one up, adjust cache size. */
1168 preempt_disable();
1169 *to_free = (unsigned long) pte_quicklist[color ^ 0x1];
1170 pte_quicklist[color ^ 0x1] = to_free;
1171 pgtable_cache_size++;
1172 preempt_enable();
1173#endif
1174
1175 return pte;
1176 }
1177 return NULL;
1178}
1179
1180void sparc_ultra_dump_itlb(void)
1181{
1182 int slot;
1183
1184 if (tlb_type == spitfire) {
1185 printk ("Contents of itlb: ");
1186 for (slot = 0; slot < 14; slot++) printk (" ");
1187 printk ("%2x:%016lx,%016lx\n",
1188 0,
1189 spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1190 for (slot = 1; slot < 64; slot+=3) {
1191 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1192 slot,
1193 spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1194 slot+1,
1195 spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1196 slot+2,
1197 spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1198 }
1199 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1200 printk ("Contents of itlb0:\n");
1201 for (slot = 0; slot < 16; slot+=2) {
1202 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1203 slot,
1204 cheetah_get_litlb_tag(slot), cheetah_get_litlb_data(slot),
1205 slot+1,
1206 cheetah_get_litlb_tag(slot+1), cheetah_get_litlb_data(slot+1));
1207 }
1208 printk ("Contents of itlb2:\n");
1209 for (slot = 0; slot < 128; slot+=2) {
1210 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1211 slot,
1212 cheetah_get_itlb_tag(slot), cheetah_get_itlb_data(slot),
1213 slot+1,
1214 cheetah_get_itlb_tag(slot+1), cheetah_get_itlb_data(slot+1));
1215 }
1216 }
1217}
1218
1219void sparc_ultra_dump_dtlb(void)
1220{
1221 int slot;
1222
1223 if (tlb_type == spitfire) {
1224 printk ("Contents of dtlb: ");
1225 for (slot = 0; slot < 14; slot++) printk (" ");
1226 printk ("%2x:%016lx,%016lx\n", 0,
1227 spitfire_get_dtlb_tag(0), spitfire_get_dtlb_data(0));
1228 for (slot = 1; slot < 64; slot+=3) {
1229 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1230 slot,
1231 spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1232 slot+1,
1233 spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1234 slot+2,
1235 spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1236 }
1237 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1238 printk ("Contents of dtlb0:\n");
1239 for (slot = 0; slot < 16; slot+=2) {
1240 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1241 slot,
1242 cheetah_get_ldtlb_tag(slot), cheetah_get_ldtlb_data(slot),
1243 slot+1,
1244 cheetah_get_ldtlb_tag(slot+1), cheetah_get_ldtlb_data(slot+1));
1245 }
1246 printk ("Contents of dtlb2:\n");
1247 for (slot = 0; slot < 512; slot+=2) {
1248 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1249 slot,
1250 cheetah_get_dtlb_tag(slot, 2), cheetah_get_dtlb_data(slot, 2),
1251 slot+1,
1252 cheetah_get_dtlb_tag(slot+1, 2), cheetah_get_dtlb_data(slot+1, 2));
1253 }
1254 if (tlb_type == cheetah_plus) {
1255 printk ("Contents of dtlb3:\n");
1256 for (slot = 0; slot < 512; slot+=2) {
1257 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1258 slot,
1259 cheetah_get_dtlb_tag(slot, 3), cheetah_get_dtlb_data(slot, 3),
1260 slot+1,
1261 cheetah_get_dtlb_tag(slot+1, 3), cheetah_get_dtlb_data(slot+1, 3));
1262 }
1263 }
1264 }
1265}
1266
1267extern unsigned long cmdline_memory_size;
1268
1269unsigned long __init bootmem_init(unsigned long *pages_avail)
1270{
1271 unsigned long bootmap_size, start_pfn, end_pfn;
1272 unsigned long end_of_phys_memory = 0UL;
1273 unsigned long bootmap_pfn, bytes_avail, size;
1274 int i;
1275
1276#ifdef CONFIG_DEBUG_BOOTMEM
1277 prom_printf("bootmem_init: Scan sp_banks, ");
1278#endif
1279
1280 bytes_avail = 0UL;
1281 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1282 end_of_phys_memory = sp_banks[i].base_addr +
1283 sp_banks[i].num_bytes;
1284 bytes_avail += sp_banks[i].num_bytes;
1285 if (cmdline_memory_size) {
1286 if (bytes_avail > cmdline_memory_size) {
1287 unsigned long slack = bytes_avail - cmdline_memory_size;
1288
1289 bytes_avail -= slack;
1290 end_of_phys_memory -= slack;
1291
1292 sp_banks[i].num_bytes -= slack;
1293 if (sp_banks[i].num_bytes == 0) {
1294 sp_banks[i].base_addr = 0xdeadbeef;
1295 } else {
1296 sp_banks[i+1].num_bytes = 0;
1297 sp_banks[i+1].base_addr = 0xdeadbeef;
1298 }
1299 break;
1300 }
1301 }
1302 }
1303
1304 *pages_avail = bytes_avail >> PAGE_SHIFT;
1305
1306 /* Start with page aligned address of last symbol in kernel
1307 * image. The kernel is hard mapped below PAGE_OFFSET in a
1308 * 4MB locked TLB translation.
1309 */
1310 start_pfn = PAGE_ALIGN(kern_base + kern_size) >> PAGE_SHIFT;
1311
1312 bootmap_pfn = start_pfn;
1313
1314 end_pfn = end_of_phys_memory >> PAGE_SHIFT;
1315
1316#ifdef CONFIG_BLK_DEV_INITRD
1317 /* Now have to check initial ramdisk, so that bootmap does not overwrite it */
1318 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
1319 unsigned long ramdisk_image = sparc_ramdisk_image ?
1320 sparc_ramdisk_image : sparc_ramdisk_image64;
1321 if (ramdisk_image >= (unsigned long)_end - 2 * PAGE_SIZE)
1322 ramdisk_image -= KERNBASE;
1323 initrd_start = ramdisk_image + phys_base;
1324 initrd_end = initrd_start + sparc_ramdisk_size;
1325 if (initrd_end > end_of_phys_memory) {
1326 printk(KERN_CRIT "initrd extends beyond end of memory "
1327 "(0x%016lx > 0x%016lx)\ndisabling initrd\n",
1328 initrd_end, end_of_phys_memory);
1329 initrd_start = 0;
1330 }
1331 if (initrd_start) {
1332 if (initrd_start >= (start_pfn << PAGE_SHIFT) &&
1333 initrd_start < (start_pfn << PAGE_SHIFT) + 2 * PAGE_SIZE)
1334 bootmap_pfn = PAGE_ALIGN (initrd_end) >> PAGE_SHIFT;
1335 }
1336 }
1337#endif
1338 /* Initialize the boot-time allocator. */
1339 max_pfn = max_low_pfn = end_pfn;
1340 min_low_pfn = pfn_base;
1341
1342#ifdef CONFIG_DEBUG_BOOTMEM
1343 prom_printf("init_bootmem(min[%lx], bootmap[%lx], max[%lx])\n",
1344 min_low_pfn, bootmap_pfn, max_low_pfn);
1345#endif
1346 bootmap_size = init_bootmem_node(NODE_DATA(0), bootmap_pfn, pfn_base, end_pfn);
1347
1348 bootmap_base = bootmap_pfn << PAGE_SHIFT;
1349
1350 /* Now register the available physical memory with the
1351 * allocator.
1352 */
1353 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1354#ifdef CONFIG_DEBUG_BOOTMEM
1355 prom_printf("free_bootmem(sp_banks:%d): base[%lx] size[%lx]\n",
1356 i, sp_banks[i].base_addr, sp_banks[i].num_bytes);
1357#endif
1358 free_bootmem(sp_banks[i].base_addr, sp_banks[i].num_bytes);
1359 }
1360
1361#ifdef CONFIG_BLK_DEV_INITRD
1362 if (initrd_start) {
1363 size = initrd_end - initrd_start;
1364
1365 /* Resert the initrd image area. */
1366#ifdef CONFIG_DEBUG_BOOTMEM
1367 prom_printf("reserve_bootmem(initrd): base[%llx] size[%lx]\n",
1368 initrd_start, initrd_end);
1369#endif
1370 reserve_bootmem(initrd_start, size);
1371 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1372
1373 initrd_start += PAGE_OFFSET;
1374 initrd_end += PAGE_OFFSET;
1375 }
1376#endif
1377 /* Reserve the kernel text/data/bss. */
1378#ifdef CONFIG_DEBUG_BOOTMEM
1379 prom_printf("reserve_bootmem(kernel): base[%lx] size[%lx]\n", kern_base, kern_size);
1380#endif
1381 reserve_bootmem(kern_base, kern_size);
1382 *pages_avail -= PAGE_ALIGN(kern_size) >> PAGE_SHIFT;
1383
1384 /* Reserve the bootmem map. We do not account for it
1385 * in pages_avail because we will release that memory
1386 * in free_all_bootmem.
1387 */
1388 size = bootmap_size;
1389#ifdef CONFIG_DEBUG_BOOTMEM
1390 prom_printf("reserve_bootmem(bootmap): base[%lx] size[%lx]\n",
1391 (bootmap_pfn << PAGE_SHIFT), size);
1392#endif
1393 reserve_bootmem((bootmap_pfn << PAGE_SHIFT), size);
1394 *pages_avail -= PAGE_ALIGN(size) >> PAGE_SHIFT;
1395
1396 return end_pfn;
1397}
1398
1399/* paging_init() sets up the page tables */
1400
1401extern void cheetah_ecache_flush_init(void);
1402
1403static unsigned long last_valid_pfn;
1404
1405void __init paging_init(void)
1406{
1407 extern pmd_t swapper_pmd_dir[1024];
1da177e4
LT		 1408 unsigned long alias_base = kern_base + PAGE_OFFSET;
1409 unsigned long second_alias_page = 0;
1410 unsigned long pt, flags, end_pfn, pages_avail;
1411 unsigned long shift = alias_base - ((unsigned long)KERNBASE);
1412 unsigned long real_end;
1413
1414 set_bit(0, mmu_context_bmap);
1415
1416 real_end = (unsigned long)_end;
1417 if ((real_end > ((unsigned long)KERNBASE + 0x400000)))
1418 bigkernel = 1;
1419#ifdef CONFIG_BLK_DEV_INITRD
1420 if (sparc_ramdisk_image || sparc_ramdisk_image64)
1421 real_end = (PAGE_ALIGN(real_end) + PAGE_ALIGN(sparc_ramdisk_size));
1422#endif
1423
1424 /* We assume physical memory starts at some 4mb multiple,
1425 * if this were not true we wouldn't boot up to this point
1426 * anyways.
1427 */
1428 pt = kern_base | _PAGE_VALID | _PAGE_SZ4MB;
1429 pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1430 local_irq_save(flags);
1431 if (tlb_type == spitfire) {
1432 __asm__ __volatile__(
1433 " stxa %1, [%0] %3\n"
1434 " stxa %2, [%5] %4\n"
1435 " membar #Sync\n"
1436 " flush %%g6\n"
1437 " nop\n"
1438 " nop\n"
1439 " nop\n"
1440 : /* No outputs */
1441 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1442 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1443 : "memory");
1444 if (real_end >= KERNBASE + 0x340000) {
1445 second_alias_page = alias_base + 0x400000;
1446 __asm__ __volatile__(
1447 " stxa %1, [%0] %3\n"
1448 " stxa %2, [%5] %4\n"
1449 " membar #Sync\n"
1450 " flush %%g6\n"
1451 " nop\n"
1452 " nop\n"
1453 " nop\n"
1454 : /* No outputs */
1455 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1456 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1457 : "memory");
1458 }
1459 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1460 __asm__ __volatile__(
1461 " stxa %1, [%0] %3\n"
1462 " stxa %2, [%5] %4\n"
1463 " membar #Sync\n"
1464 " flush %%g6\n"
1465 " nop\n"
1466 " nop\n"
1467 " nop\n"
1468 : /* No outputs */
1469 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1470 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (13<<3))
1471 : "memory");
1472 if (real_end >= KERNBASE + 0x340000) {
1473 second_alias_page = alias_base + 0x400000;
1474 __asm__ __volatile__(
1475 " stxa %1, [%0] %3\n"
1476 " stxa %2, [%5] %4\n"
1477 " membar #Sync\n"
1478 " flush %%g6\n"
1479 " nop\n"
1480 " nop\n"
1481 " nop\n"
1482 : /* No outputs */
1483 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1484 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" ((0<<16) | (12<<3))
1485 : "memory");
1486 }
1487 }
1488 local_irq_restore(flags);
1489
1490 /* Now set kernel pgd to upper alias so physical page computations
1491 * work.
1492 */
1493 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1494
1495 memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1496
1497 /* Now can init the kernel/bad page tables. */
1498 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1499 swapper_pmd_dir + (shift / sizeof(pgd_t)));
1500
1ac4f5eb 1501 swapper_pgd_zero = pgd_val(init_mm.pgd[0]);
1da177e4
LT		 1502
1503 /* Setup bootmem... */
1504 pages_avail = 0;
1505 last_valid_pfn = end_pfn = bootmem_init(&pages_avail);
1506
1507 /* Inherit non-locked OBP mappings. */
1508 inherit_prom_mappings();
1509
1510 /* Ok, we can use our TLB miss and window trap handlers safely.
1511 * We need to do a quick peek here to see if we are on StarFire
1512 * or not, so setup_tba can setup the IRQ globals correctly (it
1513 * needs to get the hard smp processor id correctly).
1514 */
1515 {
1516 extern void setup_tba(int);
1517 setup_tba(this_is_starfire);
1518 }
1519
1520 inherit_locked_prom_mappings(1);
1521
1522 /* We only created DTLB mapping of this stuff. */
1523 spitfire_flush_dtlb_nucleus_page(alias_base);
1524 if (second_alias_page)
1525 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1526
1527 __flush_tlb_all();
1528
1529 {
1530 unsigned long zones_size[MAX_NR_ZONES];
1531 unsigned long zholes_size[MAX_NR_ZONES];
1532 unsigned long npages;
1533 int znum;
1534
1535 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1536 zones_size[znum] = zholes_size[znum] = 0;
1537
1538 npages = end_pfn - pfn_base;
1539 zones_size[ZONE_DMA] = npages;
1540 zholes_size[ZONE_DMA] = npages - pages_avail;
1541
1542 free_area_init_node(0, &contig_page_data, zones_size,
1543 phys_base >> PAGE_SHIFT, zholes_size);
1544 }
1545
1546 device_scan();
1547}
1548
1549/* Ok, it seems that the prom can allocate some more memory chunks
1550 * as a side effect of some prom calls we perform during the
1551 * boot sequence. My most likely theory is that it is from the
1552 * prom_set_traptable() call, and OBP is allocating a scratchpad
1553 * for saving client program register state etc.
1554 */
1555static void __init sort_memlist(struct linux_mlist_p1275 *thislist)
1556{
1557 int swapi = 0;
1558 int i, mitr;
1559 unsigned long tmpaddr, tmpsize;
1560 unsigned long lowest;
1561
1562 for (i = 0; thislist[i].theres_more != 0; i++) {
1563 lowest = thislist[i].start_adr;
1564 for (mitr = i+1; thislist[mitr-1].theres_more != 0; mitr++)
1565 if (thislist[mitr].start_adr < lowest) {
1566 lowest = thislist[mitr].start_adr;
1567 swapi = mitr;
1568 }
1569 if (lowest == thislist[i].start_adr)
1570 continue;
1571 tmpaddr = thislist[swapi].start_adr;
1572 tmpsize = thislist[swapi].num_bytes;
1573 for (mitr = swapi; mitr > i; mitr--) {
1574 thislist[mitr].start_adr = thislist[mitr-1].start_adr;
1575 thislist[mitr].num_bytes = thislist[mitr-1].num_bytes;
1576 }
1577 thislist[i].start_adr = tmpaddr;
1578 thislist[i].num_bytes = tmpsize;
1579 }
1580}
1581
1582void __init rescan_sp_banks(void)
1583{
1584 struct linux_prom64_registers memlist[64];
1585 struct linux_mlist_p1275 avail[64], *mlist;
1586 unsigned long bytes, base_paddr;
1587 int num_regs, node = prom_finddevice("/memory");
1588 int i;
1589
1590 num_regs = prom_getproperty(node, "available",
1591 (char *) memlist, sizeof(memlist));
1592 num_regs = (num_regs / sizeof(struct linux_prom64_registers));
1593 for (i = 0; i < num_regs; i++) {
1594 avail[i].start_adr = memlist[i].phys_addr;
1595 avail[i].num_bytes = memlist[i].reg_size;
1596 avail[i].theres_more = &avail[i + 1];
1597 }
1598 avail[i - 1].theres_more = NULL;
1599 sort_memlist(avail);
1600
1601 mlist = &avail[0];
1602 i = 0;
1603 bytes = mlist->num_bytes;
1604 base_paddr = mlist->start_adr;
1605
1606 sp_banks[0].base_addr = base_paddr;
1607 sp_banks[0].num_bytes = bytes;
1608
1609 while (mlist->theres_more != NULL){
1610 i++;
1611 mlist = mlist->theres_more;
1612 bytes = mlist->num_bytes;
1613 if (i >= SPARC_PHYS_BANKS-1) {
1614 printk ("The machine has more banks than "
1615 "this kernel can support\n"
1616 "Increase the SPARC_PHYS_BANKS "
1617 "setting (currently %d)\n",
1618 SPARC_PHYS_BANKS);
1619 i = SPARC_PHYS_BANKS-1;
1620 break;
1621 }
1622
1623 sp_banks[i].base_addr = mlist->start_adr;
1624 sp_banks[i].num_bytes = mlist->num_bytes;
1625 }
1626
1627 i++;
1628 sp_banks[i].base_addr = 0xdeadbeefbeefdeadUL;
1629 sp_banks[i].num_bytes = 0;
1630
1631 for (i = 0; sp_banks[i].num_bytes != 0; i++)
1632 sp_banks[i].num_bytes &= PAGE_MASK;
1633}
1634
1635static void __init taint_real_pages(void)
1636{
1637 struct sparc_phys_banks saved_sp_banks[SPARC_PHYS_BANKS];
1638 int i;
1639
1640 for (i = 0; i < SPARC_PHYS_BANKS; i++) {
1641 saved_sp_banks[i].base_addr =
1642 sp_banks[i].base_addr;
1643 saved_sp_banks[i].num_bytes =
1644 sp_banks[i].num_bytes;
1645 }
1646
1647 rescan_sp_banks();
1648
1649 /* Find changes discovered in the sp_bank rescan and
1650 * reserve the lost portions in the bootmem maps.
1651 */
1652 for (i = 0; saved_sp_banks[i].num_bytes; i++) {
1653 unsigned long old_start, old_end;
1654
1655 old_start = saved_sp_banks[i].base_addr;
1656 old_end = old_start +
1657 saved_sp_banks[i].num_bytes;
1658 while (old_start < old_end) {
1659 int n;
1660
1661 for (n = 0; sp_banks[n].num_bytes; n++) {
1662 unsigned long new_start, new_end;
1663
1664 new_start = sp_banks[n].base_addr;
1665 new_end = new_start + sp_banks[n].num_bytes;
1666
1667 if (new_start <= old_start &&
1668 new_end >= (old_start + PAGE_SIZE)) {
1669 set_bit (old_start >> 22,
1670 sparc64_valid_addr_bitmap);
1671 goto do_next_page;
1672 }
1673 }
1674 reserve_bootmem(old_start, PAGE_SIZE);
1675
1676 do_next_page:
1677 old_start += PAGE_SIZE;
1678 }
1679 }
1680}
1681
1682void __init mem_init(void)
1683{
1684 unsigned long codepages, datapages, initpages;
1685 unsigned long addr, last;
1686 int i;
1687
1688 i = last_valid_pfn >> ((22 - PAGE_SHIFT) + 6);
1689 i += 1;
1690 sparc64_valid_addr_bitmap = (unsigned long *)
1691 __alloc_bootmem(i << 3, SMP_CACHE_BYTES, bootmap_base);
1692 if (sparc64_valid_addr_bitmap == NULL) {
1693 prom_printf("mem_init: Cannot alloc valid_addr_bitmap.\n");
1694 prom_halt();
1695 }
1696 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1697
1698 addr = PAGE_OFFSET + kern_base;
1699 last = PAGE_ALIGN(kern_size) + addr;
1700 while (addr < last) {
1701 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1702 addr += PAGE_SIZE;
1703 }
1704
1705 taint_real_pages();
1706
1707 max_mapnr = last_valid_pfn - pfn_base;
1708 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1709
1710#ifdef CONFIG_DEBUG_BOOTMEM
1711 prom_printf("mem_init: Calling free_all_bootmem().\n");
1712#endif
1713 totalram_pages = num_physpages = free_all_bootmem() - 1;
1714
1715 /*
1716 * Set up the zero page, mark it reserved, so that page count
1717 * is not manipulated when freeing the page from user ptes.
1718 */
1719 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1720 if (mem_map_zero == NULL) {
1721 prom_printf("paging_init: Cannot alloc zero page.\n");
1722 prom_halt();
1723 }
1724 SetPageReserved(mem_map_zero);
1725
1726 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1727 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1728 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1729 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1730 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1731 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1732
1733 printk("Memory: %uk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1734 nr_free_pages() << (PAGE_SHIFT-10),
1735 codepages << (PAGE_SHIFT-10),
1736 datapages << (PAGE_SHIFT-10),
1737 initpages << (PAGE_SHIFT-10),
1738 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1739
1740 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1741 cheetah_ecache_flush_init();
1742}
1743
1744void free_initmem (void)
1745{
1746 unsigned long addr, initend;
1747
1748 /*
1749 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1750 */
1751 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1752 initend = (unsigned long)(__init_end) & PAGE_MASK;
1753 for (; addr < initend; addr += PAGE_SIZE) {
1754 unsigned long page;
1755 struct page *p;
1756
1757 page = (addr +
1758 ((unsigned long) __va(kern_base)) -
1759 ((unsigned long) KERNBASE));
1760 memset((void *)addr, 0xcc, PAGE_SIZE);
1761 p = virt_to_page(page);
1762
1763 ClearPageReserved(p);
1764 set_page_count(p, 1);
1765 __free_page(p);
1766 num_physpages++;
1767 totalram_pages++;
1768 }
1769}
1770
1771#ifdef CONFIG_BLK_DEV_INITRD
1772void free_initrd_mem(unsigned long start, unsigned long end)
1773{
1774 if (start < end)
1775 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1776 for (; start < end; start += PAGE_SIZE) {
1777 struct page *p = virt_to_page(start);
1778
1779 ClearPageReserved(p);
1780 set_page_count(p, 1);
1781 __free_page(p);
1782 num_physpages++;
1783 totalram_pages++;
1784 }
1785}
1786#endif
Linux 6.x block layer and io_uring tree(s)