projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 314ef685 | 1 | /* winfixup.S: Handle cases where user stack pointer is found to be bogus. |
| 1da177e4 | 2 | * |
| 314ef685 | 3 | * Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net) |
| 1da177e4 LT |
4 | */ |
| 5 | ||
| 6 | #include <asm/asi.h> | |
| 7 | #include <asm/head.h> | |
| 8 | #include <asm/page.h> | |
| 9 | #include <asm/ptrace.h> | |
| 10 | #include <asm/processor.h> | |
| 11 | #include <asm/spitfire.h> | |
| 12 | #include <asm/thread_info.h> | |
| 13 | ||
| 14 | .text | |
| 15 | ||
| 314ef685 DM |
16 | /* It used to be the case that these register window fault |
| 17 | * handlers could run via the save and restore instructions | |
| 18 | * done by the trap entry and exit code. They now do the | |
| 19 | * window spill/fill by hand, so that case no longer can occur. | |
| 20 | */ | |
| 1da177e4 | 21 | |
| 1da177e4 | 22 | .align 32 |
| 1da177e4 | 23 | fill_fixup: |
| ffe483d5 | 24 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
| 314ef685 DM |
25 | rdpr %tstate, %g1 |
| 26 | and %g1, TSTATE_CWP, %g1 | |
| 27 | or %g4, FAULT_CODE_WINFIXUP, %g4 | |
| 28 | stb %g4, [%g6 + TI_FAULT_CODE] | |
| 29 | stx %g5, [%g6 + TI_FAULT_ADDR] | |
| 30 | wrpr %g1, %cwp | |
| 31 | ba,pt %xcc, etrap | |
| 32 | rd %pc, %g7 | |
| 33 | call do_sparc64_fault | |
| 34 | add %sp, PTREGS_OFF, %o0 | |
| 35 | ba,pt %xcc, rtrap_clr_l6 | |
| 1da177e4 | 36 | nop |
| 1da177e4 | 37 | |
| 314ef685 DM |
38 | /* Be very careful about usage of the trap globals here. |
| 39 | * You cannot touch %g5 as that has the fault information. | |
| 1da177e4 LT |
40 | */ |
| 41 | spill_fixup: | |
| 314ef685 DM |
42 | spill_fixup_mna: |
| 43 | spill_fixup_dax: | |
| ffe483d5 | 44 | TRAP_LOAD_THREAD_REG(%g6, %g1) |
| 314ef685 DM |
45 | ldx [%g6 + TI_FLAGS], %g1 |
| 46 | andcc %g1, _TIF_32BIT, %g0 | |
| 47 | ldub [%g6 + TI_WSAVED], %g1 | |
| 48 | sll %g1, 3, %g3 | |
| 49 | add %g6, %g3, %g3 | |
| 50 | stx %sp, [%g3 + TI_RWIN_SPTRS] | |
| 51 | sll %g1, 7, %g3 | |
| 52 | bne,pt %xcc, 1f | |
| 53 | add %g6, %g3, %g3 | |
| 54 | stx %l0, [%g3 + TI_REG_WINDOW + 0x00] | |
| 55 | stx %l1, [%g3 + TI_REG_WINDOW + 0x08] | |
| 56 | stx %l2, [%g3 + TI_REG_WINDOW + 0x10] | |
| 57 | stx %l3, [%g3 + TI_REG_WINDOW + 0x18] | |
| 58 | stx %l4, [%g3 + TI_REG_WINDOW + 0x20] | |
| 59 | stx %l5, [%g3 + TI_REG_WINDOW + 0x28] | |
| 60 | stx %l6, [%g3 + TI_REG_WINDOW + 0x30] | |
| 61 | stx %l7, [%g3 + TI_REG_WINDOW + 0x38] | |
| 62 | stx %i0, [%g3 + TI_REG_WINDOW + 0x40] | |
| 63 | stx %i1, [%g3 + TI_REG_WINDOW + 0x48] | |
| 64 | stx %i2, [%g3 + TI_REG_WINDOW + 0x50] | |
| 65 | stx %i3, [%g3 + TI_REG_WINDOW + 0x58] | |
| 66 | stx %i4, [%g3 + TI_REG_WINDOW + 0x60] | |
| 67 | stx %i5, [%g3 + TI_REG_WINDOW + 0x68] | |
| 68 | stx %i6, [%g3 + TI_REG_WINDOW + 0x70] | |
| 69 | ba,pt %xcc, 2f | |
| 70 | stx %i7, [%g3 + TI_REG_WINDOW + 0x78] | |
| 71 | 1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00] | |
| 72 | stw %l1, [%g3 + TI_REG_WINDOW + 0x04] | |
| 73 | stw %l2, [%g3 + TI_REG_WINDOW + 0x08] | |
| 74 | stw %l3, [%g3 + TI_REG_WINDOW + 0x0c] | |
| 75 | stw %l4, [%g3 + TI_REG_WINDOW + 0x10] | |
| 76 | stw %l5, [%g3 + TI_REG_WINDOW + 0x14] | |
| 77 | stw %l6, [%g3 + TI_REG_WINDOW + 0x18] | |
| 78 | stw %l7, [%g3 + TI_REG_WINDOW + 0x1c] | |
| 79 | stw %i0, [%g3 + TI_REG_WINDOW + 0x20] | |
| 80 | stw %i1, [%g3 + TI_REG_WINDOW + 0x24] | |
| 81 | stw %i2, [%g3 + TI_REG_WINDOW + 0x28] | |
| 82 | stw %i3, [%g3 + TI_REG_WINDOW + 0x2c] | |
| 83 | stw %i4, [%g3 + TI_REG_WINDOW + 0x30] | |
| 84 | stw %i5, [%g3 + TI_REG_WINDOW + 0x34] | |
| 85 | stw %i6, [%g3 + TI_REG_WINDOW + 0x38] | |
| 86 | stw %i7, [%g3 + TI_REG_WINDOW + 0x3c] | |
| 87 | 2: add %g1, 1, %g1 | |
| 88 | stb %g1, [%g6 + TI_WSAVED] | |
| 89 | rdpr %tstate, %g1 | |
| 90 | andcc %g1, TSTATE_PRIV, %g0 | |
| 1da177e4 | 91 | saved |
| 314ef685 DM |
92 | be,pn %xcc, 1f |
| 93 | and %g1, TSTATE_CWP, %g1 | |
| 1da177e4 | 94 | retry |
| 314ef685 DM |
95 | 1: mov FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4 |
| 96 | stb %g4, [%g6 + TI_FAULT_CODE] | |
| 97 | stx %g5, [%g6 + TI_FAULT_ADDR] | |
| 98 | wrpr %g1, %cwp | |
| 99 | ba,pt %xcc, etrap | |
| 100 | rd %pc, %g7 | |
| 101 | call do_sparc64_fault | |
| 102 | add %sp, PTREGS_OFF, %o0 | |
| 103 | ba,a,pt %xcc, rtrap_clr_l6 | |
| 1da177e4 | 104 | |
| 1da177e4 | 105 | winfix_mna: |
| 314ef685 DM |
106 | andn %g3, 0x7f, %g3 |
| 107 | add %g3, 0x78, %g3 | |
| 108 | wrpr %g3, %tnpc | |
| 1da177e4 | 109 | done |
| 1da177e4 | 110 | |
| 314ef685 | 111 | fill_fixup_mna: |
| 314ef685 DM |
112 | rdpr %tstate, %g1 |
| 113 | and %g1, TSTATE_CWP, %g1 | |
| 114 | wrpr %g1, %cwp | |
| 115 | ba,pt %xcc, etrap | |
| 116 | rd %pc, %g7 | |
| ed6b0b45 DM |
117 | sethi %hi(tlb_type), %g1 |
| 118 | mov %l4, %o1 | |
| 119 | lduw [%g1 + %lo(tlb_type)], %g1 | |
| 120 | mov %l5, %o2 | |
| 121 | cmp %g1, 3 | |
| 122 | bne,pt %icc, 1f | |
| 314ef685 | 123 | add %sp, PTREGS_OFF, %o0 |
| ed6b0b45 DM |
124 | call sun4v_mna |
| 125 | nop | |
| 126 | ba,a,pt %xcc, rtrap_clr_l6 | |
| 127 | 1: call mem_address_unaligned | |
| 128 | nop | |
| 314ef685 | 129 | ba,a,pt %xcc, rtrap_clr_l6 |
| 1da177e4 | 130 | |
| 1da177e4 | 131 | winfix_dax: |
| 314ef685 DM |
132 | andn %g3, 0x7f, %g3 |
| 133 | add %g3, 0x74, %g3 | |
| 134 | wrpr %g3, %tnpc | |
| 1da177e4 | 135 | done |
| 1da177e4 | 136 | |
| 314ef685 | 137 | fill_fixup_dax: |
| 314ef685 DM |
138 | rdpr %tstate, %g1 |
| 139 | and %g1, TSTATE_CWP, %g1 | |
| 140 | wrpr %g1, %cwp | |
| 141 | ba,pt %xcc, etrap | |
| 142 | rd %pc, %g7 | |
| ed6b0b45 | 143 | sethi %hi(tlb_type), %g1 |
| 314ef685 | 144 | mov %l4, %o1 |
| ed6b0b45 | 145 | lduw [%g1 + %lo(tlb_type)], %g1 |
| 314ef685 | 146 | mov %l5, %o2 |
| ed6b0b45 DM |
147 | cmp %g1, 3 |
| 148 | bne,pt %icc, 1f | |
| 314ef685 | 149 | add %sp, PTREGS_OFF, %o0 |
| ed6b0b45 DM |
150 | call sun4v_data_access_exception |
| 151 | nop | |
| 152 | ba,a,pt %xcc, rtrap_clr_l6 | |
| 153 | 1: call spitfire_data_access_exception | |
| 154 | nop | |
| 314ef685 | 155 | ba,a,pt %xcc, rtrap_clr_l6 |