Commit | Line | Data |
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1da177e4 LT |
1 | /* smp.c: Sparc64 SMP support. |
2 | * | |
3 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
4 | */ | |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/sched.h> | |
9 | #include <linux/mm.h> | |
10 | #include <linux/pagemap.h> | |
11 | #include <linux/threads.h> | |
12 | #include <linux/smp.h> | |
13 | #include <linux/smp_lock.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/kernel_stat.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/seq_file.h> | |
21 | #include <linux/cache.h> | |
22 | #include <linux/jiffies.h> | |
23 | #include <linux/profile.h> | |
24 | #include <linux/bootmem.h> | |
25 | ||
26 | #include <asm/head.h> | |
27 | #include <asm/ptrace.h> | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/tlbflush.h> | |
30 | #include <asm/mmu_context.h> | |
31 | #include <asm/cpudata.h> | |
32 | ||
33 | #include <asm/irq.h> | |
34 | #include <asm/page.h> | |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/oplib.h> | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/timer.h> | |
39 | #include <asm/starfire.h> | |
40 | #include <asm/tlb.h> | |
41 | ||
1da177e4 LT |
42 | extern void calibrate_delay(void); |
43 | ||
44 | /* Please don't make this stuff initdata!!! --DaveM */ | |
45 | static unsigned char boot_cpu_id; | |
46 | ||
c12a8289 AM |
47 | cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE; |
48 | cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE; | |
1da177e4 LT |
49 | static cpumask_t smp_commenced_mask; |
50 | static cpumask_t cpu_callout_map; | |
51 | ||
52 | void smp_info(struct seq_file *m) | |
53 | { | |
54 | int i; | |
55 | ||
56 | seq_printf(m, "State:\n"); | |
57 | for (i = 0; i < NR_CPUS; i++) { | |
58 | if (cpu_online(i)) | |
59 | seq_printf(m, | |
60 | "CPU%d:\t\tonline\n", i); | |
61 | } | |
62 | } | |
63 | ||
64 | void smp_bogo(struct seq_file *m) | |
65 | { | |
66 | int i; | |
67 | ||
68 | for (i = 0; i < NR_CPUS; i++) | |
69 | if (cpu_online(i)) | |
70 | seq_printf(m, | |
71 | "Cpu%dBogo\t: %lu.%02lu\n" | |
72 | "Cpu%dClkTck\t: %016lx\n", | |
73 | i, cpu_data(i).udelay_val / (500000/HZ), | |
74 | (cpu_data(i).udelay_val / (5000/HZ)) % 100, | |
75 | i, cpu_data(i).clock_tick); | |
76 | } | |
77 | ||
78 | void __init smp_store_cpu_info(int id) | |
79 | { | |
80 | int cpu_node; | |
81 | ||
82 | /* multiplier and counter set by | |
83 | smp_setup_percpu_timer() */ | |
84 | cpu_data(id).udelay_val = loops_per_jiffy; | |
85 | ||
86 | cpu_find_by_mid(id, &cpu_node); | |
87 | cpu_data(id).clock_tick = prom_getintdefault(cpu_node, | |
88 | "clock-frequency", 0); | |
89 | ||
90 | cpu_data(id).pgcache_size = 0; | |
91 | cpu_data(id).pte_cache[0] = NULL; | |
92 | cpu_data(id).pte_cache[1] = NULL; | |
93 | cpu_data(id).pgd_cache = NULL; | |
94 | cpu_data(id).idle_volume = 1; | |
80dc0d6b DM |
95 | |
96 | cpu_data(id).dcache_size = prom_getintdefault(cpu_node, "dcache-size", | |
97 | 16 * 1024); | |
98 | cpu_data(id).dcache_line_size = | |
99 | prom_getintdefault(cpu_node, "dcache-line-size", 32); | |
100 | cpu_data(id).icache_size = prom_getintdefault(cpu_node, "icache-size", | |
101 | 16 * 1024); | |
102 | cpu_data(id).icache_line_size = | |
103 | prom_getintdefault(cpu_node, "icache-line-size", 32); | |
104 | cpu_data(id).ecache_size = prom_getintdefault(cpu_node, "ecache-size", | |
105 | 4 * 1024 * 1024); | |
106 | cpu_data(id).ecache_line_size = | |
107 | prom_getintdefault(cpu_node, "ecache-line-size", 64); | |
108 | printk("CPU[%d]: Caches " | |
109 | "D[sz(%d):line_sz(%d)] " | |
110 | "I[sz(%d):line_sz(%d)] " | |
111 | "E[sz(%d):line_sz(%d)]\n", | |
112 | id, | |
113 | cpu_data(id).dcache_size, cpu_data(id).dcache_line_size, | |
114 | cpu_data(id).icache_size, cpu_data(id).icache_line_size, | |
115 | cpu_data(id).ecache_size, cpu_data(id).ecache_line_size); | |
1da177e4 LT |
116 | } |
117 | ||
118 | static void smp_setup_percpu_timer(void); | |
119 | ||
120 | static volatile unsigned long callin_flag = 0; | |
121 | ||
122 | extern void inherit_locked_prom_mappings(int save_p); | |
123 | ||
124 | static inline void cpu_setup_percpu_base(unsigned long cpu_id) | |
125 | { | |
74bf4312 | 126 | #error IMMU TSB usage must be fixed |
1da177e4 LT |
127 | __asm__ __volatile__("mov %0, %%g5\n\t" |
128 | "stxa %0, [%1] %2\n\t" | |
129 | "membar #Sync" | |
130 | : /* no outputs */ | |
131 | : "r" (__per_cpu_offset(cpu_id)), | |
132 | "r" (TSB_REG), "i" (ASI_IMMU)); | |
133 | } | |
134 | ||
135 | void __init smp_callin(void) | |
136 | { | |
137 | int cpuid = hard_smp_processor_id(); | |
138 | ||
139 | inherit_locked_prom_mappings(0); | |
140 | ||
141 | __flush_tlb_all(); | |
142 | ||
143 | cpu_setup_percpu_base(cpuid); | |
144 | ||
145 | smp_setup_percpu_timer(); | |
146 | ||
816242da DM |
147 | if (cheetah_pcache_forced_on) |
148 | cheetah_enable_pcache(); | |
149 | ||
1da177e4 LT |
150 | local_irq_enable(); |
151 | ||
152 | calibrate_delay(); | |
153 | smp_store_cpu_info(cpuid); | |
154 | callin_flag = 1; | |
155 | __asm__ __volatile__("membar #Sync\n\t" | |
156 | "flush %%g6" : : : "memory"); | |
157 | ||
158 | /* Clear this or we will die instantly when we | |
159 | * schedule back to this idler... | |
160 | */ | |
db7d9a4e | 161 | current_thread_info()->new_child = 0; |
1da177e4 LT |
162 | |
163 | /* Attach to the address space of init_task. */ | |
164 | atomic_inc(&init_mm.mm_count); | |
165 | current->active_mm = &init_mm; | |
166 | ||
167 | while (!cpu_isset(cpuid, smp_commenced_mask)) | |
4f07118f | 168 | rmb(); |
1da177e4 LT |
169 | |
170 | cpu_set(cpuid, cpu_online_map); | |
5bfb5d69 NP |
171 | |
172 | /* idle thread is expected to have preempt disabled */ | |
173 | preempt_disable(); | |
1da177e4 LT |
174 | } |
175 | ||
176 | void cpu_panic(void) | |
177 | { | |
178 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
179 | panic("SMP bolixed\n"); | |
180 | } | |
181 | ||
d369ddd2 | 182 | static unsigned long current_tick_offset __read_mostly; |
1da177e4 LT |
183 | |
184 | /* This tick register synchronization scheme is taken entirely from | |
185 | * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit. | |
186 | * | |
187 | * The only change I've made is to rework it so that the master | |
188 | * initiates the synchonization instead of the slave. -DaveM | |
189 | */ | |
190 | ||
191 | #define MASTER 0 | |
192 | #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long)) | |
193 | ||
194 | #define NUM_ROUNDS 64 /* magic value */ | |
195 | #define NUM_ITERS 5 /* likewise */ | |
196 | ||
197 | static DEFINE_SPINLOCK(itc_sync_lock); | |
198 | static unsigned long go[SLAVE + 1]; | |
199 | ||
200 | #define DEBUG_TICK_SYNC 0 | |
201 | ||
202 | static inline long get_delta (long *rt, long *master) | |
203 | { | |
204 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; | |
205 | unsigned long tcenter, t0, t1, tm; | |
206 | unsigned long i; | |
207 | ||
208 | for (i = 0; i < NUM_ITERS; i++) { | |
209 | t0 = tick_ops->get_tick(); | |
210 | go[MASTER] = 1; | |
4f07118f | 211 | membar_storeload(); |
1da177e4 | 212 | while (!(tm = go[SLAVE])) |
4f07118f | 213 | rmb(); |
1da177e4 | 214 | go[SLAVE] = 0; |
4f07118f | 215 | wmb(); |
1da177e4 LT |
216 | t1 = tick_ops->get_tick(); |
217 | ||
218 | if (t1 - t0 < best_t1 - best_t0) | |
219 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
220 | } | |
221 | ||
222 | *rt = best_t1 - best_t0; | |
223 | *master = best_tm - best_t0; | |
224 | ||
225 | /* average best_t0 and best_t1 without overflow: */ | |
226 | tcenter = (best_t0/2 + best_t1/2); | |
227 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
228 | tcenter++; | |
229 | return tcenter - best_tm; | |
230 | } | |
231 | ||
232 | void smp_synchronize_tick_client(void) | |
233 | { | |
234 | long i, delta, adj, adjust_latency = 0, done = 0; | |
235 | unsigned long flags, rt, master_time_stamp, bound; | |
236 | #if DEBUG_TICK_SYNC | |
237 | struct { | |
238 | long rt; /* roundtrip time */ | |
239 | long master; /* master's timestamp */ | |
240 | long diff; /* difference between midpoint and master's timestamp */ | |
241 | long lat; /* estimate of itc adjustment latency */ | |
242 | } t[NUM_ROUNDS]; | |
243 | #endif | |
244 | ||
245 | go[MASTER] = 1; | |
246 | ||
247 | while (go[MASTER]) | |
4f07118f | 248 | rmb(); |
1da177e4 LT |
249 | |
250 | local_irq_save(flags); | |
251 | { | |
252 | for (i = 0; i < NUM_ROUNDS; i++) { | |
253 | delta = get_delta(&rt, &master_time_stamp); | |
254 | if (delta == 0) { | |
255 | done = 1; /* let's lock on to this... */ | |
256 | bound = rt; | |
257 | } | |
258 | ||
259 | if (!done) { | |
260 | if (i > 0) { | |
261 | adjust_latency += -delta; | |
262 | adj = -delta + adjust_latency/4; | |
263 | } else | |
264 | adj = -delta; | |
265 | ||
266 | tick_ops->add_tick(adj, current_tick_offset); | |
267 | } | |
268 | #if DEBUG_TICK_SYNC | |
269 | t[i].rt = rt; | |
270 | t[i].master = master_time_stamp; | |
271 | t[i].diff = delta; | |
272 | t[i].lat = adjust_latency/4; | |
273 | #endif | |
274 | } | |
275 | } | |
276 | local_irq_restore(flags); | |
277 | ||
278 | #if DEBUG_TICK_SYNC | |
279 | for (i = 0; i < NUM_ROUNDS; i++) | |
280 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
281 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
282 | #endif | |
283 | ||
284 | printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles," | |
285 | "maxerr %lu cycles)\n", smp_processor_id(), delta, rt); | |
286 | } | |
287 | ||
288 | static void smp_start_sync_tick_client(int cpu); | |
289 | ||
290 | static void smp_synchronize_one_tick(int cpu) | |
291 | { | |
292 | unsigned long flags, i; | |
293 | ||
294 | go[MASTER] = 0; | |
295 | ||
296 | smp_start_sync_tick_client(cpu); | |
297 | ||
298 | /* wait for client to be ready */ | |
299 | while (!go[MASTER]) | |
4f07118f | 300 | rmb(); |
1da177e4 LT |
301 | |
302 | /* now let the client proceed into his loop */ | |
303 | go[MASTER] = 0; | |
4f07118f | 304 | membar_storeload(); |
1da177e4 LT |
305 | |
306 | spin_lock_irqsave(&itc_sync_lock, flags); | |
307 | { | |
308 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) { | |
309 | while (!go[MASTER]) | |
4f07118f | 310 | rmb(); |
1da177e4 | 311 | go[MASTER] = 0; |
4f07118f | 312 | wmb(); |
1da177e4 | 313 | go[SLAVE] = tick_ops->get_tick(); |
4f07118f | 314 | membar_storeload(); |
1da177e4 LT |
315 | } |
316 | } | |
317 | spin_unlock_irqrestore(&itc_sync_lock, flags); | |
318 | } | |
319 | ||
320 | extern unsigned long sparc64_cpu_startup; | |
321 | ||
322 | /* The OBP cpu startup callback truncates the 3rd arg cookie to | |
323 | * 32-bits (I think) so to be safe we have it read the pointer | |
324 | * contained here so we work on >4GB machines. -DaveM | |
325 | */ | |
326 | static struct thread_info *cpu_new_thread = NULL; | |
327 | ||
328 | static int __devinit smp_boot_one_cpu(unsigned int cpu) | |
329 | { | |
330 | unsigned long entry = | |
331 | (unsigned long)(&sparc64_cpu_startup); | |
332 | unsigned long cookie = | |
333 | (unsigned long)(&cpu_new_thread); | |
334 | struct task_struct *p; | |
335 | int timeout, ret, cpu_node; | |
336 | ||
337 | p = fork_idle(cpu); | |
338 | callin_flag = 0; | |
f3169641 | 339 | cpu_new_thread = task_thread_info(p); |
1da177e4 LT |
340 | cpu_set(cpu, cpu_callout_map); |
341 | ||
342 | cpu_find_by_mid(cpu, &cpu_node); | |
343 | prom_startcpu(cpu_node, entry, cookie); | |
344 | ||
345 | for (timeout = 0; timeout < 5000000; timeout++) { | |
346 | if (callin_flag) | |
347 | break; | |
348 | udelay(100); | |
349 | } | |
350 | if (callin_flag) { | |
351 | ret = 0; | |
352 | } else { | |
353 | printk("Processor %d is stuck.\n", cpu); | |
354 | cpu_clear(cpu, cpu_callout_map); | |
355 | ret = -ENODEV; | |
356 | } | |
357 | cpu_new_thread = NULL; | |
358 | ||
359 | return ret; | |
360 | } | |
361 | ||
362 | static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) | |
363 | { | |
364 | u64 result, target; | |
365 | int stuck, tmp; | |
366 | ||
367 | if (this_is_starfire) { | |
368 | /* map to real upaid */ | |
369 | cpu = (((cpu & 0x3c) << 1) | | |
370 | ((cpu & 0x40) >> 4) | | |
371 | (cpu & 0x3)); | |
372 | } | |
373 | ||
374 | target = (cpu << 14) | 0x70; | |
375 | again: | |
376 | /* Ok, this is the real Spitfire Errata #54. | |
377 | * One must read back from a UDB internal register | |
378 | * after writes to the UDB interrupt dispatch, but | |
379 | * before the membar Sync for that write. | |
380 | * So we use the high UDB control register (ASI 0x7f, | |
381 | * ADDR 0x20) for the dummy read. -DaveM | |
382 | */ | |
383 | tmp = 0x40; | |
384 | __asm__ __volatile__( | |
385 | "wrpr %1, %2, %%pstate\n\t" | |
386 | "stxa %4, [%0] %3\n\t" | |
387 | "stxa %5, [%0+%8] %3\n\t" | |
388 | "add %0, %8, %0\n\t" | |
389 | "stxa %6, [%0+%8] %3\n\t" | |
390 | "membar #Sync\n\t" | |
391 | "stxa %%g0, [%7] %3\n\t" | |
392 | "membar #Sync\n\t" | |
393 | "mov 0x20, %%g1\n\t" | |
394 | "ldxa [%%g1] 0x7f, %%g0\n\t" | |
395 | "membar #Sync" | |
396 | : "=r" (tmp) | |
397 | : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), | |
398 | "r" (data0), "r" (data1), "r" (data2), "r" (target), | |
399 | "r" (0x10), "0" (tmp) | |
400 | : "g1"); | |
401 | ||
402 | /* NOTE: PSTATE_IE is still clear. */ | |
403 | stuck = 100000; | |
404 | do { | |
405 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
406 | : "=r" (result) | |
407 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
408 | if (result == 0) { | |
409 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
410 | : : "r" (pstate)); | |
411 | return; | |
412 | } | |
413 | stuck -= 1; | |
414 | if (stuck == 0) | |
415 | break; | |
416 | } while (result & 0x1); | |
417 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
418 | : : "r" (pstate)); | |
419 | if (stuck == 0) { | |
420 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
421 | smp_processor_id(), result); | |
422 | } else { | |
423 | udelay(2); | |
424 | goto again; | |
425 | } | |
426 | } | |
427 | ||
428 | static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
429 | { | |
430 | u64 pstate; | |
431 | int i; | |
432 | ||
433 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
434 | for_each_cpu_mask(i, mask) | |
435 | spitfire_xcall_helper(data0, data1, data2, pstate, i); | |
436 | } | |
437 | ||
438 | /* Cheetah now allows to send the whole 64-bytes of data in the interrupt | |
439 | * packet, but we have no use for that. However we do take advantage of | |
440 | * the new pipelining feature (ie. dispatch to multiple cpus simultaneously). | |
441 | */ | |
442 | static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
443 | { | |
444 | u64 pstate, ver; | |
445 | int nack_busy_id, is_jalapeno; | |
446 | ||
447 | if (cpus_empty(mask)) | |
448 | return; | |
449 | ||
450 | /* Unfortunately, someone at Sun had the brilliant idea to make the | |
451 | * busy/nack fields hard-coded by ITID number for this Ultra-III | |
452 | * derivative processor. | |
453 | */ | |
454 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
455 | is_jalapeno = ((ver >> 32) == 0x003e0016); | |
456 | ||
457 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
458 | ||
459 | retry: | |
460 | __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t" | |
461 | : : "r" (pstate), "i" (PSTATE_IE)); | |
462 | ||
463 | /* Setup the dispatch data registers. */ | |
464 | __asm__ __volatile__("stxa %0, [%3] %6\n\t" | |
465 | "stxa %1, [%4] %6\n\t" | |
466 | "stxa %2, [%5] %6\n\t" | |
467 | "membar #Sync\n\t" | |
468 | : /* no outputs */ | |
469 | : "r" (data0), "r" (data1), "r" (data2), | |
470 | "r" (0x40), "r" (0x50), "r" (0x60), | |
471 | "i" (ASI_INTR_W)); | |
472 | ||
473 | nack_busy_id = 0; | |
474 | { | |
475 | int i; | |
476 | ||
477 | for_each_cpu_mask(i, mask) { | |
478 | u64 target = (i << 14) | 0x70; | |
479 | ||
480 | if (!is_jalapeno) | |
481 | target |= (nack_busy_id << 24); | |
482 | __asm__ __volatile__( | |
483 | "stxa %%g0, [%0] %1\n\t" | |
484 | "membar #Sync\n\t" | |
485 | : /* no outputs */ | |
486 | : "r" (target), "i" (ASI_INTR_W)); | |
487 | nack_busy_id++; | |
488 | } | |
489 | } | |
490 | ||
491 | /* Now, poll for completion. */ | |
492 | { | |
493 | u64 dispatch_stat; | |
494 | long stuck; | |
495 | ||
496 | stuck = 100000 * nack_busy_id; | |
497 | do { | |
498 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
499 | : "=r" (dispatch_stat) | |
500 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
501 | if (dispatch_stat == 0UL) { | |
502 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
503 | : : "r" (pstate)); | |
504 | return; | |
505 | } | |
506 | if (!--stuck) | |
507 | break; | |
508 | } while (dispatch_stat & 0x5555555555555555UL); | |
509 | ||
510 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
511 | : : "r" (pstate)); | |
512 | ||
513 | if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) { | |
514 | /* Busy bits will not clear, continue instead | |
515 | * of freezing up on this cpu. | |
516 | */ | |
517 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
518 | smp_processor_id(), dispatch_stat); | |
519 | } else { | |
520 | int i, this_busy_nack = 0; | |
521 | ||
522 | /* Delay some random time with interrupts enabled | |
523 | * to prevent deadlock. | |
524 | */ | |
525 | udelay(2 * nack_busy_id); | |
526 | ||
527 | /* Clear out the mask bits for cpus which did not | |
528 | * NACK us. | |
529 | */ | |
530 | for_each_cpu_mask(i, mask) { | |
531 | u64 check_mask; | |
532 | ||
533 | if (is_jalapeno) | |
534 | check_mask = (0x2UL << (2*i)); | |
535 | else | |
536 | check_mask = (0x2UL << | |
537 | this_busy_nack); | |
538 | if ((dispatch_stat & check_mask) == 0) | |
539 | cpu_clear(i, mask); | |
540 | this_busy_nack += 2; | |
541 | } | |
542 | ||
543 | goto retry; | |
544 | } | |
545 | } | |
546 | } | |
547 | ||
548 | /* Send cross call to all processors mentioned in MASK | |
549 | * except self. | |
550 | */ | |
551 | static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask) | |
552 | { | |
553 | u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff)); | |
554 | int this_cpu = get_cpu(); | |
555 | ||
556 | cpus_and(mask, mask, cpu_online_map); | |
557 | cpu_clear(this_cpu, mask); | |
558 | ||
559 | if (tlb_type == spitfire) | |
560 | spitfire_xcall_deliver(data0, data1, data2, mask); | |
561 | else | |
562 | cheetah_xcall_deliver(data0, data1, data2, mask); | |
563 | /* NOTE: Caller runs local copy on master. */ | |
564 | ||
565 | put_cpu(); | |
566 | } | |
567 | ||
568 | extern unsigned long xcall_sync_tick; | |
569 | ||
570 | static void smp_start_sync_tick_client(int cpu) | |
571 | { | |
572 | cpumask_t mask = cpumask_of_cpu(cpu); | |
573 | ||
574 | smp_cross_call_masked(&xcall_sync_tick, | |
575 | 0, 0, 0, mask); | |
576 | } | |
577 | ||
578 | /* Send cross call to all processors except self. */ | |
579 | #define smp_cross_call(func, ctx, data1, data2) \ | |
580 | smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map) | |
581 | ||
582 | struct call_data_struct { | |
583 | void (*func) (void *info); | |
584 | void *info; | |
585 | atomic_t finished; | |
586 | int wait; | |
587 | }; | |
588 | ||
589 | static DEFINE_SPINLOCK(call_lock); | |
590 | static struct call_data_struct *call_data; | |
591 | ||
592 | extern unsigned long xcall_call_function; | |
593 | ||
594 | /* | |
595 | * You must not call this function with disabled interrupts or from a | |
596 | * hardware interrupt handler or from a bottom half handler. | |
597 | */ | |
598 | int smp_call_function(void (*func)(void *info), void *info, | |
599 | int nonatomic, int wait) | |
600 | { | |
601 | struct call_data_struct data; | |
602 | int cpus = num_online_cpus() - 1; | |
603 | long timeout; | |
604 | ||
605 | if (!cpus) | |
606 | return 0; | |
607 | ||
608 | /* Can deadlock when called with interrupts disabled */ | |
609 | WARN_ON(irqs_disabled()); | |
610 | ||
611 | data.func = func; | |
612 | data.info = info; | |
613 | atomic_set(&data.finished, 0); | |
614 | data.wait = wait; | |
615 | ||
616 | spin_lock(&call_lock); | |
617 | ||
618 | call_data = &data; | |
619 | ||
620 | smp_cross_call(&xcall_call_function, 0, 0, 0); | |
621 | ||
622 | /* | |
623 | * Wait for other cpus to complete function or at | |
624 | * least snap the call data. | |
625 | */ | |
626 | timeout = 1000000; | |
627 | while (atomic_read(&data.finished) != cpus) { | |
628 | if (--timeout <= 0) | |
629 | goto out_timeout; | |
630 | barrier(); | |
631 | udelay(1); | |
632 | } | |
633 | ||
634 | spin_unlock(&call_lock); | |
635 | ||
636 | return 0; | |
637 | ||
638 | out_timeout: | |
639 | spin_unlock(&call_lock); | |
640 | printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n", | |
641 | (long) num_online_cpus() - 1L, | |
642 | (long) atomic_read(&data.finished)); | |
643 | return 0; | |
644 | } | |
645 | ||
646 | void smp_call_function_client(int irq, struct pt_regs *regs) | |
647 | { | |
648 | void (*func) (void *info) = call_data->func; | |
649 | void *info = call_data->info; | |
650 | ||
651 | clear_softint(1 << irq); | |
652 | if (call_data->wait) { | |
653 | /* let initiator proceed only after completion */ | |
654 | func(info); | |
655 | atomic_inc(&call_data->finished); | |
656 | } else { | |
657 | /* let initiator proceed after getting data */ | |
658 | atomic_inc(&call_data->finished); | |
659 | func(info); | |
660 | } | |
661 | } | |
662 | ||
663 | extern unsigned long xcall_flush_tlb_mm; | |
664 | extern unsigned long xcall_flush_tlb_pending; | |
665 | extern unsigned long xcall_flush_tlb_kernel_range; | |
1da177e4 LT |
666 | extern unsigned long xcall_report_regs; |
667 | extern unsigned long xcall_receive_signal; | |
668 | ||
669 | #ifdef DCACHE_ALIASING_POSSIBLE | |
670 | extern unsigned long xcall_flush_dcache_page_cheetah; | |
671 | #endif | |
672 | extern unsigned long xcall_flush_dcache_page_spitfire; | |
673 | ||
674 | #ifdef CONFIG_DEBUG_DCFLUSH | |
675 | extern atomic_t dcpage_flushes; | |
676 | extern atomic_t dcpage_flushes_xcall; | |
677 | #endif | |
678 | ||
679 | static __inline__ void __local_flush_dcache_page(struct page *page) | |
680 | { | |
681 | #ifdef DCACHE_ALIASING_POSSIBLE | |
682 | __flush_dcache_page(page_address(page), | |
683 | ((tlb_type == spitfire) && | |
684 | page_mapping(page) != NULL)); | |
685 | #else | |
686 | if (page_mapping(page) != NULL && | |
687 | tlb_type == spitfire) | |
688 | __flush_icache_page(__pa(page_address(page))); | |
689 | #endif | |
690 | } | |
691 | ||
692 | void smp_flush_dcache_page_impl(struct page *page, int cpu) | |
693 | { | |
694 | cpumask_t mask = cpumask_of_cpu(cpu); | |
695 | int this_cpu = get_cpu(); | |
696 | ||
697 | #ifdef CONFIG_DEBUG_DCFLUSH | |
698 | atomic_inc(&dcpage_flushes); | |
699 | #endif | |
700 | if (cpu == this_cpu) { | |
701 | __local_flush_dcache_page(page); | |
702 | } else if (cpu_online(cpu)) { | |
703 | void *pg_addr = page_address(page); | |
704 | u64 data0; | |
705 | ||
706 | if (tlb_type == spitfire) { | |
707 | data0 = | |
708 | ((u64)&xcall_flush_dcache_page_spitfire); | |
709 | if (page_mapping(page) != NULL) | |
710 | data0 |= ((u64)1 << 32); | |
711 | spitfire_xcall_deliver(data0, | |
712 | __pa(pg_addr), | |
713 | (u64) pg_addr, | |
714 | mask); | |
715 | } else { | |
716 | #ifdef DCACHE_ALIASING_POSSIBLE | |
717 | data0 = | |
718 | ((u64)&xcall_flush_dcache_page_cheetah); | |
719 | cheetah_xcall_deliver(data0, | |
720 | __pa(pg_addr), | |
721 | 0, mask); | |
722 | #endif | |
723 | } | |
724 | #ifdef CONFIG_DEBUG_DCFLUSH | |
725 | atomic_inc(&dcpage_flushes_xcall); | |
726 | #endif | |
727 | } | |
728 | ||
729 | put_cpu(); | |
730 | } | |
731 | ||
732 | void flush_dcache_page_all(struct mm_struct *mm, struct page *page) | |
733 | { | |
734 | void *pg_addr = page_address(page); | |
735 | cpumask_t mask = cpu_online_map; | |
736 | u64 data0; | |
737 | int this_cpu = get_cpu(); | |
738 | ||
739 | cpu_clear(this_cpu, mask); | |
740 | ||
741 | #ifdef CONFIG_DEBUG_DCFLUSH | |
742 | atomic_inc(&dcpage_flushes); | |
743 | #endif | |
744 | if (cpus_empty(mask)) | |
745 | goto flush_self; | |
746 | if (tlb_type == spitfire) { | |
747 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); | |
748 | if (page_mapping(page) != NULL) | |
749 | data0 |= ((u64)1 << 32); | |
750 | spitfire_xcall_deliver(data0, | |
751 | __pa(pg_addr), | |
752 | (u64) pg_addr, | |
753 | mask); | |
754 | } else { | |
755 | #ifdef DCACHE_ALIASING_POSSIBLE | |
756 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); | |
757 | cheetah_xcall_deliver(data0, | |
758 | __pa(pg_addr), | |
759 | 0, mask); | |
760 | #endif | |
761 | } | |
762 | #ifdef CONFIG_DEBUG_DCFLUSH | |
763 | atomic_inc(&dcpage_flushes_xcall); | |
764 | #endif | |
765 | flush_self: | |
766 | __local_flush_dcache_page(page); | |
767 | ||
768 | put_cpu(); | |
769 | } | |
770 | ||
771 | void smp_receive_signal(int cpu) | |
772 | { | |
773 | cpumask_t mask = cpumask_of_cpu(cpu); | |
774 | ||
775 | if (cpu_online(cpu)) { | |
776 | u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff); | |
777 | ||
778 | if (tlb_type == spitfire) | |
779 | spitfire_xcall_deliver(data0, 0, 0, mask); | |
780 | else | |
781 | cheetah_xcall_deliver(data0, 0, 0, mask); | |
782 | } | |
783 | } | |
784 | ||
785 | void smp_receive_signal_client(int irq, struct pt_regs *regs) | |
786 | { | |
787 | /* Just return, rtrap takes care of the rest. */ | |
788 | clear_softint(1 << irq); | |
789 | } | |
790 | ||
791 | void smp_report_regs(void) | |
792 | { | |
793 | smp_cross_call(&xcall_report_regs, 0, 0, 0); | |
794 | } | |
795 | ||
1da177e4 LT |
796 | /* We know that the window frames of the user have been flushed |
797 | * to the stack before we get here because all callers of us | |
798 | * are flush_tlb_*() routines, and these run after flush_cache_*() | |
799 | * which performs the flushw. | |
800 | * | |
801 | * The SMP TLB coherency scheme we use works as follows: | |
802 | * | |
803 | * 1) mm->cpu_vm_mask is a bit mask of which cpus an address | |
804 | * space has (potentially) executed on, this is the heuristic | |
805 | * we use to avoid doing cross calls. | |
806 | * | |
807 | * Also, for flushing from kswapd and also for clones, we | |
808 | * use cpu_vm_mask as the list of cpus to make run the TLB. | |
809 | * | |
810 | * 2) TLB context numbers are shared globally across all processors | |
811 | * in the system, this allows us to play several games to avoid | |
812 | * cross calls. | |
813 | * | |
814 | * One invariant is that when a cpu switches to a process, and | |
815 | * that processes tsk->active_mm->cpu_vm_mask does not have the | |
816 | * current cpu's bit set, that tlb context is flushed locally. | |
817 | * | |
818 | * If the address space is non-shared (ie. mm->count == 1) we avoid | |
819 | * cross calls when we want to flush the currently running process's | |
820 | * tlb state. This is done by clearing all cpu bits except the current | |
821 | * processor's in current->active_mm->cpu_vm_mask and performing the | |
822 | * flush locally only. This will force any subsequent cpus which run | |
823 | * this task to flush the context from the local tlb if the process | |
824 | * migrates to another cpu (again). | |
825 | * | |
826 | * 3) For shared address spaces (threads) and swapping we bite the | |
827 | * bullet for most cases and perform the cross call (but only to | |
828 | * the cpus listed in cpu_vm_mask). | |
829 | * | |
830 | * The performance gain from "optimizing" away the cross call for threads is | |
831 | * questionable (in theory the big win for threads is the massive sharing of | |
832 | * address space state across processors). | |
833 | */ | |
62dbec78 DM |
834 | |
835 | /* This currently is only used by the hugetlb arch pre-fault | |
836 | * hook on UltraSPARC-III+ and later when changing the pagesize | |
837 | * bits of the context register for an address space. | |
838 | */ | |
1da177e4 LT |
839 | void smp_flush_tlb_mm(struct mm_struct *mm) |
840 | { | |
62dbec78 DM |
841 | u32 ctx = CTX_HWBITS(mm->context); |
842 | int cpu = get_cpu(); | |
1da177e4 | 843 | |
62dbec78 DM |
844 | if (atomic_read(&mm->mm_users) == 1) { |
845 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); | |
846 | goto local_flush_and_out; | |
847 | } | |
1da177e4 | 848 | |
62dbec78 DM |
849 | smp_cross_call_masked(&xcall_flush_tlb_mm, |
850 | ctx, 0, 0, | |
851 | mm->cpu_vm_mask); | |
1da177e4 | 852 | |
62dbec78 DM |
853 | local_flush_and_out: |
854 | __flush_tlb_mm(ctx, SECONDARY_CONTEXT); | |
1da177e4 | 855 | |
62dbec78 | 856 | put_cpu(); |
1da177e4 LT |
857 | } |
858 | ||
859 | void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs) | |
860 | { | |
861 | u32 ctx = CTX_HWBITS(mm->context); | |
862 | int cpu = get_cpu(); | |
863 | ||
dedeb002 | 864 | if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) |
1da177e4 | 865 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); |
dedeb002 HD |
866 | else |
867 | smp_cross_call_masked(&xcall_flush_tlb_pending, | |
868 | ctx, nr, (unsigned long) vaddrs, | |
869 | mm->cpu_vm_mask); | |
1da177e4 | 870 | |
1da177e4 LT |
871 | __flush_tlb_pending(ctx, nr, vaddrs); |
872 | ||
873 | put_cpu(); | |
874 | } | |
875 | ||
876 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
877 | { | |
878 | start &= PAGE_MASK; | |
879 | end = PAGE_ALIGN(end); | |
880 | if (start != end) { | |
881 | smp_cross_call(&xcall_flush_tlb_kernel_range, | |
882 | 0, start, end); | |
883 | ||
884 | __flush_tlb_kernel_range(start, end); | |
885 | } | |
886 | } | |
887 | ||
888 | /* CPU capture. */ | |
889 | /* #define CAPTURE_DEBUG */ | |
890 | extern unsigned long xcall_capture; | |
891 | ||
892 | static atomic_t smp_capture_depth = ATOMIC_INIT(0); | |
893 | static atomic_t smp_capture_registry = ATOMIC_INIT(0); | |
894 | static unsigned long penguins_are_doing_time; | |
895 | ||
896 | void smp_capture(void) | |
897 | { | |
898 | int result = atomic_add_ret(1, &smp_capture_depth); | |
899 | ||
900 | if (result == 1) { | |
901 | int ncpus = num_online_cpus(); | |
902 | ||
903 | #ifdef CAPTURE_DEBUG | |
904 | printk("CPU[%d]: Sending penguins to jail...", | |
905 | smp_processor_id()); | |
906 | #endif | |
907 | penguins_are_doing_time = 1; | |
4f07118f | 908 | membar_storestore_loadstore(); |
1da177e4 LT |
909 | atomic_inc(&smp_capture_registry); |
910 | smp_cross_call(&xcall_capture, 0, 0, 0); | |
911 | while (atomic_read(&smp_capture_registry) != ncpus) | |
4f07118f | 912 | rmb(); |
1da177e4 LT |
913 | #ifdef CAPTURE_DEBUG |
914 | printk("done\n"); | |
915 | #endif | |
916 | } | |
917 | } | |
918 | ||
919 | void smp_release(void) | |
920 | { | |
921 | if (atomic_dec_and_test(&smp_capture_depth)) { | |
922 | #ifdef CAPTURE_DEBUG | |
923 | printk("CPU[%d]: Giving pardon to " | |
924 | "imprisoned penguins\n", | |
925 | smp_processor_id()); | |
926 | #endif | |
927 | penguins_are_doing_time = 0; | |
4f07118f | 928 | membar_storeload_storestore(); |
1da177e4 LT |
929 | atomic_dec(&smp_capture_registry); |
930 | } | |
931 | } | |
932 | ||
933 | /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they | |
934 | * can service tlb flush xcalls... | |
935 | */ | |
936 | extern void prom_world(int); | |
937 | extern void save_alternate_globals(unsigned long *); | |
938 | extern void restore_alternate_globals(unsigned long *); | |
939 | void smp_penguin_jailcell(int irq, struct pt_regs *regs) | |
940 | { | |
941 | unsigned long global_save[24]; | |
942 | ||
943 | clear_softint(1 << irq); | |
944 | ||
945 | preempt_disable(); | |
946 | ||
947 | __asm__ __volatile__("flushw"); | |
948 | save_alternate_globals(global_save); | |
949 | prom_world(1); | |
950 | atomic_inc(&smp_capture_registry); | |
4f07118f | 951 | membar_storeload_storestore(); |
1da177e4 | 952 | while (penguins_are_doing_time) |
4f07118f | 953 | rmb(); |
1da177e4 LT |
954 | restore_alternate_globals(global_save); |
955 | atomic_dec(&smp_capture_registry); | |
956 | prom_world(0); | |
957 | ||
958 | preempt_enable(); | |
959 | } | |
960 | ||
1da177e4 LT |
961 | #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier |
962 | #define prof_counter(__cpu) cpu_data(__cpu).counter | |
963 | ||
964 | void smp_percpu_timer_interrupt(struct pt_regs *regs) | |
965 | { | |
966 | unsigned long compare, tick, pstate; | |
967 | int cpu = smp_processor_id(); | |
968 | int user = user_mode(regs); | |
969 | ||
970 | /* | |
971 | * Check for level 14 softint. | |
972 | */ | |
973 | { | |
974 | unsigned long tick_mask = tick_ops->softint_mask; | |
975 | ||
976 | if (!(get_softint() & tick_mask)) { | |
977 | extern void handler_irq(int, struct pt_regs *); | |
978 | ||
979 | handler_irq(14, regs); | |
980 | return; | |
981 | } | |
982 | clear_softint(tick_mask); | |
983 | } | |
984 | ||
985 | do { | |
986 | profile_tick(CPU_PROFILING, regs); | |
987 | if (!--prof_counter(cpu)) { | |
988 | irq_enter(); | |
989 | ||
990 | if (cpu == boot_cpu_id) { | |
991 | kstat_this_cpu.irqs[0]++; | |
992 | timer_tick_interrupt(regs); | |
993 | } | |
994 | ||
995 | update_process_times(user); | |
996 | ||
997 | irq_exit(); | |
998 | ||
999 | prof_counter(cpu) = prof_multiplier(cpu); | |
1000 | } | |
1001 | ||
1002 | /* Guarantee that the following sequences execute | |
1003 | * uninterrupted. | |
1004 | */ | |
1005 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
1006 | "wrpr %0, %1, %%pstate" | |
1007 | : "=r" (pstate) | |
1008 | : "i" (PSTATE_IE)); | |
1009 | ||
1010 | compare = tick_ops->add_compare(current_tick_offset); | |
1011 | tick = tick_ops->get_tick(); | |
1012 | ||
1013 | /* Restore PSTATE_IE. */ | |
1014 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
1015 | : /* no outputs */ | |
1016 | : "r" (pstate)); | |
1017 | } while (time_after_eq(tick, compare)); | |
1018 | } | |
1019 | ||
1020 | static void __init smp_setup_percpu_timer(void) | |
1021 | { | |
1022 | int cpu = smp_processor_id(); | |
1023 | unsigned long pstate; | |
1024 | ||
1025 | prof_counter(cpu) = prof_multiplier(cpu) = 1; | |
1026 | ||
1027 | /* Guarantee that the following sequences execute | |
1028 | * uninterrupted. | |
1029 | */ | |
1030 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
1031 | "wrpr %0, %1, %%pstate" | |
1032 | : "=r" (pstate) | |
1033 | : "i" (PSTATE_IE)); | |
1034 | ||
1035 | tick_ops->init_tick(current_tick_offset); | |
1036 | ||
1037 | /* Restore PSTATE_IE. */ | |
1038 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
1039 | : /* no outputs */ | |
1040 | : "r" (pstate)); | |
1041 | } | |
1042 | ||
1043 | void __init smp_tick_init(void) | |
1044 | { | |
1045 | boot_cpu_id = hard_smp_processor_id(); | |
1046 | current_tick_offset = timer_tick_offset; | |
1047 | ||
1048 | cpu_set(boot_cpu_id, cpu_online_map); | |
1049 | prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1; | |
1050 | } | |
1051 | ||
1052 | /* /proc/profile writes can call this, don't __init it please. */ | |
1053 | static DEFINE_SPINLOCK(prof_setup_lock); | |
1054 | ||
1055 | int setup_profiling_timer(unsigned int multiplier) | |
1056 | { | |
1057 | unsigned long flags; | |
1058 | int i; | |
1059 | ||
1060 | if ((!multiplier) || (timer_tick_offset / multiplier) < 1000) | |
1061 | return -EINVAL; | |
1062 | ||
1063 | spin_lock_irqsave(&prof_setup_lock, flags); | |
1064 | for (i = 0; i < NR_CPUS; i++) | |
1065 | prof_multiplier(i) = multiplier; | |
1066 | current_tick_offset = (timer_tick_offset / multiplier); | |
1067 | spin_unlock_irqrestore(&prof_setup_lock, flags); | |
1068 | ||
1069 | return 0; | |
1070 | } | |
1071 | ||
7abea921 | 1072 | /* Constrain the number of cpus to max_cpus. */ |
1da177e4 LT |
1073 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1074 | { | |
1da177e4 | 1075 | if (num_possible_cpus() > max_cpus) { |
7abea921 DM |
1076 | int instance, mid; |
1077 | ||
1da177e4 LT |
1078 | instance = 0; |
1079 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
1080 | if (mid != boot_cpu_id) { | |
1081 | cpu_clear(mid, phys_cpu_present_map); | |
1082 | if (num_possible_cpus() <= max_cpus) | |
1083 | break; | |
1084 | } | |
1085 | instance++; | |
1086 | } | |
1087 | } | |
1088 | ||
1089 | smp_store_cpu_info(boot_cpu_id); | |
1090 | } | |
1091 | ||
7abea921 DM |
1092 | /* Set this up early so that things like the scheduler can init |
1093 | * properly. We use the same cpu mask for both the present and | |
1094 | * possible cpu map. | |
1095 | */ | |
1096 | void __init smp_setup_cpu_possible_map(void) | |
1097 | { | |
1098 | int instance, mid; | |
1099 | ||
1100 | instance = 0; | |
1101 | while (!cpu_find_by_instance(instance, NULL, &mid)) { | |
1102 | if (mid < NR_CPUS) | |
1103 | cpu_set(mid, phys_cpu_present_map); | |
1104 | instance++; | |
1105 | } | |
1106 | } | |
1107 | ||
1da177e4 LT |
1108 | void __devinit smp_prepare_boot_cpu(void) |
1109 | { | |
1110 | if (hard_smp_processor_id() >= NR_CPUS) { | |
1111 | prom_printf("Serious problem, boot cpu id >= NR_CPUS\n"); | |
1112 | prom_halt(); | |
1113 | } | |
1114 | ||
1115 | current_thread_info()->cpu = hard_smp_processor_id(); | |
1116 | ||
1117 | cpu_set(smp_processor_id(), cpu_online_map); | |
1118 | cpu_set(smp_processor_id(), phys_cpu_present_map); | |
1119 | } | |
1120 | ||
1121 | int __devinit __cpu_up(unsigned int cpu) | |
1122 | { | |
1123 | int ret = smp_boot_one_cpu(cpu); | |
1124 | ||
1125 | if (!ret) { | |
1126 | cpu_set(cpu, smp_commenced_mask); | |
1127 | while (!cpu_isset(cpu, cpu_online_map)) | |
1128 | mb(); | |
1129 | if (!cpu_isset(cpu, cpu_online_map)) { | |
1130 | ret = -ENODEV; | |
1131 | } else { | |
1132 | smp_synchronize_one_tick(cpu); | |
1133 | } | |
1134 | } | |
1135 | return ret; | |
1136 | } | |
1137 | ||
1138 | void __init smp_cpus_done(unsigned int max_cpus) | |
1139 | { | |
1140 | unsigned long bogosum = 0; | |
1141 | int i; | |
1142 | ||
1143 | for (i = 0; i < NR_CPUS; i++) { | |
1144 | if (cpu_online(i)) | |
1145 | bogosum += cpu_data(i).udelay_val; | |
1146 | } | |
1147 | printk("Total of %ld processors activated " | |
1148 | "(%lu.%02lu BogoMIPS).\n", | |
1149 | (long) num_online_cpus(), | |
1150 | bogosum/(500000/HZ), | |
1151 | (bogosum/(5000/HZ))%100); | |
1152 | } | |
1153 | ||
1da177e4 LT |
1154 | void smp_send_reschedule(int cpu) |
1155 | { | |
64c7c8f8 | 1156 | smp_receive_signal(cpu); |
1da177e4 LT |
1157 | } |
1158 | ||
1159 | /* This is a nop because we capture all other cpus | |
1160 | * anyways when making the PROM active. | |
1161 | */ | |
1162 | void smp_send_stop(void) | |
1163 | { | |
1164 | } | |
1165 | ||
d369ddd2 DM |
1166 | unsigned long __per_cpu_base __read_mostly; |
1167 | unsigned long __per_cpu_shift __read_mostly; | |
1da177e4 LT |
1168 | |
1169 | EXPORT_SYMBOL(__per_cpu_base); | |
1170 | EXPORT_SYMBOL(__per_cpu_shift); | |
1171 | ||
1172 | void __init setup_per_cpu_areas(void) | |
1173 | { | |
1174 | unsigned long goal, size, i; | |
1175 | char *ptr; | |
1176 | /* Created by linker magic */ | |
1177 | extern char __per_cpu_start[], __per_cpu_end[]; | |
1178 | ||
1179 | /* Copy section for each CPU (we discard the original) */ | |
1180 | goal = ALIGN(__per_cpu_end - __per_cpu_start, PAGE_SIZE); | |
1181 | ||
1182 | #ifdef CONFIG_MODULES | |
1183 | if (goal < PERCPU_ENOUGH_ROOM) | |
1184 | goal = PERCPU_ENOUGH_ROOM; | |
1185 | #endif | |
1186 | __per_cpu_shift = 0; | |
1187 | for (size = 1UL; size < goal; size <<= 1UL) | |
1188 | __per_cpu_shift++; | |
1189 | ||
1190 | /* Make sure the resulting __per_cpu_base value | |
1191 | * will fit in the 43-bit sign extended IMMU | |
1192 | * TSB register. | |
1193 | */ | |
1194 | ptr = __alloc_bootmem(size * NR_CPUS, PAGE_SIZE, | |
1195 | (unsigned long) __per_cpu_start); | |
1196 | ||
1197 | __per_cpu_base = ptr - __per_cpu_start; | |
1198 | ||
1199 | if ((__per_cpu_shift < PAGE_SHIFT) || | |
1200 | (__per_cpu_base & ~PAGE_MASK) || | |
1201 | (__per_cpu_base != (((long) __per_cpu_base << 20) >> 20))) { | |
1202 | prom_printf("PER_CPU: Invalid layout, " | |
1203 | "ptr[%p] shift[%lx] base[%lx]\n", | |
1204 | ptr, __per_cpu_shift, __per_cpu_base); | |
1205 | prom_halt(); | |
1206 | } | |
1207 | ||
1208 | for (i = 0; i < NR_CPUS; i++, ptr += size) | |
1209 | memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start); | |
1210 | ||
1211 | /* Finally, load in the boot cpu's base value. | |
1212 | * We abuse the IMMU TSB register for trap handler | |
1213 | * entry and exit loading of %g5. That is why it | |
1214 | * has to be page aligned. | |
1215 | */ | |
1216 | cpu_setup_percpu_base(hard_smp_processor_id()); | |
1217 | } |