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sparc64: Get rid of pci_controller_info.
[linux-2.6-block.git] / arch / sparc64 / kernel / pci_sabre.c
CommitLineData
16ce82d8 1/* pci_sabre.c: Sabre specific PCI controller support.
1da177e4 2 *
16ce82d8 3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/slab.h>
13#include <linux/interrupt.h>
764f2579 14#include <linux/of_device.h>
1da177e4
LT		 15
16#include <asm/apb.h>
1da177e4
LT		 17#include <asm/iommu.h>
18#include <asm/irq.h>
e87dc350 19#include <asm/prom.h>
1da177e4
LT		 20
21#include "pci_impl.h"
22#include "iommu_common.h"
23
edbe805b
DM		 24#define DRIVER_NAME "sabre"
25#define PFX DRIVER_NAME ": "
26
1da177e4
LT		 27/* All SABRE registers are 64-bits. The following accessor
28 * routines are how they are accessed. The REG parameter
29 * is a physical address.
30 */
31#define sabre_read(__reg) \
32({ u64 __ret; \
33 __asm__ __volatile__("ldxa [%1] %2, %0" \
34 : "=r" (__ret) \
35 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
36 : "memory"); \
37 __ret; \
38})
39#define sabre_write(__reg, __val) \
40 __asm__ __volatile__("stxa %0, [%1] %2" \
41 : /* no outputs */ \
42 : "r" (__val), "r" (__reg), \
43 "i" (ASI_PHYS_BYPASS_EC_E) \
44 : "memory")
45
46/* SABRE PCI controller register offsets and definitions. */
47#define SABRE_UE_AFSR 0x0030UL
48#define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
49#define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
50#define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
51#define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
52#define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
53#define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
54#define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
55#define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
56#define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
57#define SABRE_UECE_AFAR 0x0038UL
58#define SABRE_CE_AFSR 0x0040UL
59#define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
60#define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
61#define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
62#define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
63#define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */
64#define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
65#define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */
66#define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */
67#define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
68#define SABRE_IOMMU_CONTROL 0x0200UL
69#define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */
70#define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */
71#define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */
72#define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */
73#define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
74#define SABRE_IOMMU_TSBSZ_1K 0x0000000000000000
75#define SABRE_IOMMU_TSBSZ_2K 0x0000000000010000
76#define SABRE_IOMMU_TSBSZ_4K 0x0000000000020000
77#define SABRE_IOMMU_TSBSZ_8K 0x0000000000030000
78#define SABRE_IOMMU_TSBSZ_16K 0x0000000000040000
79#define SABRE_IOMMU_TSBSZ_32K 0x0000000000050000
80#define SABRE_IOMMU_TSBSZ_64K 0x0000000000060000
81#define SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
82#define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */
83#define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
84#define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
85#define SABRE_IOMMU_TSBBASE 0x0208UL
86#define SABRE_IOMMU_FLUSH 0x0210UL
87#define SABRE_IMAP_A_SLOT0 0x0c00UL
88#define SABRE_IMAP_B_SLOT0 0x0c20UL
89#define SABRE_IMAP_SCSI 0x1000UL
90#define SABRE_IMAP_ETH 0x1008UL
91#define SABRE_IMAP_BPP 0x1010UL
92#define SABRE_IMAP_AU_REC 0x1018UL
93#define SABRE_IMAP_AU_PLAY 0x1020UL
94#define SABRE_IMAP_PFAIL 0x1028UL
95#define SABRE_IMAP_KMS 0x1030UL
96#define SABRE_IMAP_FLPY 0x1038UL
97#define SABRE_IMAP_SHW 0x1040UL
98#define SABRE_IMAP_KBD 0x1048UL
99#define SABRE_IMAP_MS 0x1050UL
100#define SABRE_IMAP_SER 0x1058UL
101#define SABRE_IMAP_UE 0x1070UL
102#define SABRE_IMAP_CE 0x1078UL
103#define SABRE_IMAP_PCIERR 0x1080UL
104#define SABRE_IMAP_GFX 0x1098UL
105#define SABRE_IMAP_EUPA 0x10a0UL
106#define SABRE_ICLR_A_SLOT0 0x1400UL
107#define SABRE_ICLR_B_SLOT0 0x1480UL
108#define SABRE_ICLR_SCSI 0x1800UL
109#define SABRE_ICLR_ETH 0x1808UL
110#define SABRE_ICLR_BPP 0x1810UL
111#define SABRE_ICLR_AU_REC 0x1818UL
112#define SABRE_ICLR_AU_PLAY 0x1820UL
113#define SABRE_ICLR_PFAIL 0x1828UL
114#define SABRE_ICLR_KMS 0x1830UL
115#define SABRE_ICLR_FLPY 0x1838UL
116#define SABRE_ICLR_SHW 0x1840UL
117#define SABRE_ICLR_KBD 0x1848UL
118#define SABRE_ICLR_MS 0x1850UL
119#define SABRE_ICLR_SER 0x1858UL
120#define SABRE_ICLR_UE 0x1870UL
121#define SABRE_ICLR_CE 0x1878UL
122#define SABRE_ICLR_PCIERR 0x1880UL
123#define SABRE_WRSYNC 0x1c20UL
124#define SABRE_PCICTRL 0x2000UL
125#define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */
126#define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */
127#define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
128#define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
129#define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */
130#define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */
131#define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */
132#define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */
133#define SABRE_PIOAFSR 0x2010UL
134#define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */
135#define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */
136#define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
137#define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
138#define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */
139#define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */
140#define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
141#define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
142#define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */
143#define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */
144#define SABRE_PIOAFAR 0x2018UL
145#define SABRE_PCIDIAG 0x2020UL
146#define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */
147#define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */
148#define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */
149#define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */
150#define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
151#define SABRE_PCITASR 0x2028UL
152#define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
153#define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
154#define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
155#define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
156#define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */
157#define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */
158#define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */
159#define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */
160#define SABRE_PIOBUF_DIAG 0x5000UL
161#define SABRE_DMABUF_DIAGLO 0x5100UL
162#define SABRE_DMABUF_DIAGHI 0x51c0UL
163#define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */
164#define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */
165#define SABRE_IOMMU_VADIAG 0xa400UL
166#define SABRE_IOMMU_TCDIAG 0xa408UL
167#define SABRE_IOMMU_TAG 0xa580UL
168#define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */
169#define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */
170#define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */
171#define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */
172#define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */
173#define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */
174#define SABRE_IOMMU_DATA 0xa600UL
175#define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */
176#define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */
177#define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */
178#define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */
179#define SABRE_PCI_IRQSTATE 0xa800UL
180#define SABRE_OBIO_IRQSTATE 0xa808UL
181#define SABRE_FFBCFG 0xf000UL
182#define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */
183#define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */
184#define SABRE_MCCTRL0 0xf010UL
185#define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */
186#define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */
187#define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */
188#define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */
189#define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */
190#define SABRE_MCCTRL1 0xf018UL
191#define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */
192#define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */
193#define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */
194#define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */
195#define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */
196#define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */
197#define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */
198#define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */
199#define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */
200#define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */
201#define SABRE_RESETCTRL 0xf020UL
202
203#define SABRE_CONFIGSPACE 0x001000000UL
204#define SABRE_IOSPACE 0x002000000UL
205#define SABRE_IOSPACE_SIZE 0x000ffffffUL
206#define SABRE_MEMSPACE 0x100000000UL
207#define SABRE_MEMSPACE_SIZE 0x07fffffffUL
208
1da177e4
LT		 209static int hummingbird_p;
210static struct pci_bus *sabre_root_bus;
211
1da177e4 212/* SABRE error handling support. */
6c108f12 213static void sabre_check_iommu_error(struct pci_pbm_info *pbm,
1da177e4
LT		 214 unsigned long afsr,
215 unsigned long afar)
216{
6c108f12 217 struct iommu *iommu = pbm->iommu;
1da177e4
LT		 218 unsigned long iommu_tag[16];
219 unsigned long iommu_data[16];
220 unsigned long flags;
221 u64 control;
222 int i;
223
224 spin_lock_irqsave(&iommu->lock, flags);
225 control = sabre_read(iommu->iommu_control);
226 if (control & SABRE_IOMMUCTRL_ERR) {
227 char *type_string;
228
229 /* Clear the error encountered bit.
230 * NOTE: On Sabre this is write 1 to clear,
231 * which is different from Psycho.
232 */
233 sabre_write(iommu->iommu_control, control);
234 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
235 case 1:
236 type_string = "Invalid Error";
237 break;
238 case 3:
239 type_string = "ECC Error";
240 break;
241 default:
242 type_string = "Unknown";
243 break;
244 };
6c108f12
DM		 245 printk("%s: IOMMU Error, type[%s]\n",
246 pbm->name, type_string);
1da177e4
LT		 247
248 /* Enter diagnostic mode and probe for error'd
249 * entries in the IOTLB.
250 */
251 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
252 sabre_write(iommu->iommu_control,
253 (control | SABRE_IOMMUCTRL_DENAB));
254 for (i = 0; i < 16; i++) {
6c108f12 255 unsigned long base = pbm->controller_regs;
1da177e4
LT		 256
257 iommu_tag[i] =
258 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
259 iommu_data[i] =
260 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
261 sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
262 sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
263 }
264 sabre_write(iommu->iommu_control, control);
265
266 for (i = 0; i < 16; i++) {
267 unsigned long tag, data;
268
269 tag = iommu_tag[i];
270 if (!(tag & SABRE_IOMMUTAG_ERR))
271 continue;
272
273 data = iommu_data[i];
274 switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
275 case 1:
276 type_string = "Invalid Error";
277 break;
278 case 3:
279 type_string = "ECC Error";
280 break;
281 default:
282 type_string = "Unknown";
283 break;
284 };
6c108f12
DM		 285 printk("%s: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
286 pbm->name, i, tag, type_string,
1da177e4
LT		 287 ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
288 ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
289 ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
6c108f12
DM		 290 printk("%s: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
291 pbm->name, i, data,
1da177e4
LT		 292 ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
293 ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
294 ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
295 ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
296 }
297 }
298 spin_unlock_irqrestore(&iommu->lock, flags);
299}
300
6d24c8dc 301static irqreturn_t sabre_ue_intr(int irq, void *dev_id)
1da177e4 302{
6c108f12
DM		 303 struct pci_pbm_info *pbm = dev_id;
304 unsigned long afsr_reg = pbm->controller_regs + SABRE_UE_AFSR;
305 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
1da177e4
LT		 306 unsigned long afsr, afar, error_bits;
307 int reported;
308
309 /* Latch uncorrectable error status. */
310 afar = sabre_read(afar_reg);
311 afsr = sabre_read(afsr_reg);
312
313 /* Clear the primary/secondary error status bits. */
314 error_bits = afsr &
315 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
316 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
317 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
318 if (!error_bits)
319 return IRQ_NONE;
320 sabre_write(afsr_reg, error_bits);
321
322 /* Log the error. */
6c108f12
DM		 323 printk("%s: Uncorrectable Error, primary error type[%s%s]\n",
324 pbm->name,
1da177e4
LT		 325 ((error_bits & SABRE_UEAFSR_PDRD) ?
326 "DMA Read" :
327 ((error_bits & SABRE_UEAFSR_PDWR) ?
328 "DMA Write" : "???")),
329 ((error_bits & SABRE_UEAFSR_PDTE) ?
330 ":Translation Error" : ""));
6c108f12
DM		 331 printk("%s: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
332 pbm->name,
1da177e4
LT		 333 (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
334 (afsr & SABRE_UEAFSR_OFF) >> 29UL,
335 ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
6c108f12
DM		 336 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
337 printk("%s: UE Secondary errors [", pbm->name);
1da177e4
LT		 338 reported = 0;
339 if (afsr & SABRE_UEAFSR_SDRD) {
340 reported++;
341 printk("(DMA Read)");
342 }
343 if (afsr & SABRE_UEAFSR_SDWR) {
344 reported++;
345 printk("(DMA Write)");
346 }
347 if (afsr & SABRE_UEAFSR_SDTE) {
348 reported++;
349 printk("(Translation Error)");
350 }
351 if (!reported)
352 printk("(none)");
353 printk("]\n");
354
355 /* Interrogate IOMMU for error status. */
6c108f12 356 sabre_check_iommu_error(pbm, afsr, afar);
1da177e4
LT		 357
358 return IRQ_HANDLED;
359}
360
6d24c8dc 361static irqreturn_t sabre_ce_intr(int irq, void *dev_id)
1da177e4 362{
6c108f12
DM		 363 struct pci_pbm_info *pbm = dev_id;
364 unsigned long afsr_reg = pbm->controller_regs + SABRE_CE_AFSR;
365 unsigned long afar_reg = pbm->controller_regs + SABRE_UECE_AFAR;
1da177e4
LT		 366 unsigned long afsr, afar, error_bits;
367 int reported;
368
369 /* Latch error status. */
370 afar = sabre_read(afar_reg);
371 afsr = sabre_read(afsr_reg);
372
373 /* Clear primary/secondary error status bits. */
374 error_bits = afsr &
375 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
376 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
377 if (!error_bits)
378 return IRQ_NONE;
379 sabre_write(afsr_reg, error_bits);
380
381 /* Log the error. */
6c108f12
DM		 382 printk("%s: Correctable Error, primary error type[%s]\n",
383 pbm->name,
1da177e4
LT		 384 ((error_bits & SABRE_CEAFSR_PDRD) ?
385 "DMA Read" :
386 ((error_bits & SABRE_CEAFSR_PDWR) ?
387 "DMA Write" : "???")));
388
389 /* XXX Use syndrome and afar to print out module string just like
390 * XXX UDB CE trap handler does... -DaveM
391 */
6c108f12 392 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
1da177e4 393 "was_block(%d)\n",
6c108f12 394 pbm->name,
1da177e4
LT		 395 (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
396 (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
397 (afsr & SABRE_CEAFSR_OFF) >> 29UL,
398 ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
6c108f12
DM		 399 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
400 printk("%s: CE Secondary errors [", pbm->name);
1da177e4
LT		 401 reported = 0;
402 if (afsr & SABRE_CEAFSR_SDRD) {
403 reported++;
404 printk("(DMA Read)");
405 }
406 if (afsr & SABRE_CEAFSR_SDWR) {
407 reported++;
408 printk("(DMA Write)");
409 }
410 if (!reported)
411 printk("(none)");
412 printk("]\n");
413
414 return IRQ_HANDLED;
415}
416
6c108f12 417static irqreturn_t sabre_pcierr_intr_other(struct pci_pbm_info *pbm)
1da177e4
LT		 418{
419 unsigned long csr_reg, csr, csr_error_bits;
420 irqreturn_t ret = IRQ_NONE;
421 u16 stat;
422
6c108f12 423 csr_reg = pbm->controller_regs + SABRE_PCICTRL;
1da177e4
LT		 424 csr = sabre_read(csr_reg);
425 csr_error_bits =
426 csr & SABRE_PCICTRL_SERR;
427 if (csr_error_bits) {
428 /* Clear the errors. */
429 sabre_write(csr_reg, csr);
430
431 /* Log 'em. */
432 if (csr_error_bits & SABRE_PCICTRL_SERR)
6c108f12
DM		 433 printk("%s: PCI SERR signal asserted.\n",
434 pbm->name);
1da177e4
LT		 435 ret = IRQ_HANDLED;
436 }
a2fb23af
DM		 437 pci_bus_read_config_word(sabre_root_bus, 0,
438 PCI_STATUS, &stat);
1da177e4
LT		 439 if (stat & (PCI_STATUS_PARITY |
440 PCI_STATUS_SIG_TARGET_ABORT |
441 PCI_STATUS_REC_TARGET_ABORT |
442 PCI_STATUS_REC_MASTER_ABORT |
443 PCI_STATUS_SIG_SYSTEM_ERROR)) {
6c108f12
DM		 444 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
445 pbm->name, stat);
a2fb23af
DM		 446 pci_bus_write_config_word(sabre_root_bus, 0,
447 PCI_STATUS, 0xffff);
1da177e4
LT		 448 ret = IRQ_HANDLED;
449 }
450 return ret;
451}
452
6d24c8dc 453static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id)
1da177e4 454{
6c108f12 455 struct pci_pbm_info *pbm = dev_id;
1da177e4
LT		 456 unsigned long afsr_reg, afar_reg;
457 unsigned long afsr, afar, error_bits;
458 int reported;
459
6c108f12
DM		 460 afsr_reg = pbm->controller_regs + SABRE_PIOAFSR;
461 afar_reg = pbm->controller_regs + SABRE_PIOAFAR;
1da177e4
LT		 462
463 /* Latch error status. */
464 afar = sabre_read(afar_reg);
465 afsr = sabre_read(afsr_reg);
466
467 /* Clear primary/secondary error status bits. */
468 error_bits = afsr &
469 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
470 SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
471 SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
472 SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
473 if (!error_bits)
6c108f12 474 return sabre_pcierr_intr_other(pbm);
1da177e4
LT		 475 sabre_write(afsr_reg, error_bits);
476
477 /* Log the error. */
6c108f12
DM		 478 printk("%s: PCI Error, primary error type[%s]\n",
479 pbm->name,
1da177e4
LT		 480 (((error_bits & SABRE_PIOAFSR_PMA) ?
481 "Master Abort" :
482 ((error_bits & SABRE_PIOAFSR_PTA) ?
483 "Target Abort" :
484 ((error_bits & SABRE_PIOAFSR_PRTRY) ?
485 "Excessive Retries" :
486 ((error_bits & SABRE_PIOAFSR_PPERR) ?
487 "Parity Error" : "???"))))));
6c108f12
DM		 488 printk("%s: bytemask[%04lx] was_block(%d)\n",
489 pbm->name,
1da177e4
LT		 490 (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
491 (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
6c108f12
DM		 492 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
493 printk("%s: PCI Secondary errors [", pbm->name);
1da177e4
LT		 494 reported = 0;
495 if (afsr & SABRE_PIOAFSR_SMA) {
496 reported++;
497 printk("(Master Abort)");
498 }
499 if (afsr & SABRE_PIOAFSR_STA) {
500 reported++;
501 printk("(Target Abort)");
502 }
503 if (afsr & SABRE_PIOAFSR_SRTRY) {
504 reported++;
505 printk("(Excessive Retries)");
506 }
507 if (afsr & SABRE_PIOAFSR_SPERR) {
508 reported++;
509 printk("(Parity Error)");
510 }
511 if (!reported)
512 printk("(none)");
513 printk("]\n");
514
515 /* For the error types shown, scan both PCI buses for devices
516 * which have logged that error type.
517 */
518
519 /* If we see a Target Abort, this could be the result of an
520 * IOMMU translation error of some sort. It is extremely
521 * useful to log this information as usually it indicates
522 * a bug in the IOMMU support code or a PCI device driver.
523 */
524 if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
6c108f12
DM		 525 sabre_check_iommu_error(pbm, afsr, afar);
526 pci_scan_for_target_abort(pbm, pbm->pci_bus);
1da177e4 527 }
01f94c4a 528 if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA))
6c108f12 529 pci_scan_for_master_abort(pbm, pbm->pci_bus);
01f94c4a 530
1da177e4
LT		 531 /* For excessive retries, SABRE/PBM will abort the device
532 * and there is no way to specifically check for excessive
533 * retries in the config space status registers. So what
534 * we hope is that we'll catch it via the master/target
535 * abort events.
536 */
537
01f94c4a 538 if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR))
6c108f12 539 pci_scan_for_parity_error(pbm, pbm->pci_bus);
1da177e4
LT		 540
541 return IRQ_HANDLED;
542}
543
34768bc8 544static void sabre_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 545{
2b1e5978
DM		 546 struct device_node *dp = pbm->prom_node;
547 struct of_device *op;
1da177e4 548 unsigned long base = pbm->controller_regs;
1da177e4 549 u64 tmp;
af80318e 550 int err;
1da177e4 551
2b1e5978
DM		 552 if (pbm->chip_type == PBM_CHIP_TYPE_SABRE)
553 dp = dp->parent;
554
555 op = of_find_device_by_node(dp);
556 if (!op)
557 return;
558
559 /* Sabre/Hummingbird IRQ property layout is:
560 * 0: PCI ERR
561 * 1: UE ERR
562 * 2: CE ERR
563 * 3: POWER FAIL
564 */
565 if (op->num_irqs < 4)
566 return;
567
1da177e4
LT		 568 /* We clear the error bits in the appropriate AFSR before
569 * registering the handler so that we don't get spurious
570 * interrupts.
571 */
572 sabre_write(base + SABRE_UE_AFSR,
573 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
574 SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
575 SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
2b1e5978 576
af80318e
DM		 577 err = request_irq(op->irqs[1], sabre_ue_intr, 0, "SABRE_UE", pbm);
578 if (err)
579 printk(KERN_WARNING "%s: Couldn't register UE, err=%d.\n",
580 pbm->name, err);
1da177e4
LT		 581
582 sabre_write(base + SABRE_CE_AFSR,
583 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
584 SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
1da177e4 585
af80318e
DM		 586 err = request_irq(op->irqs[2], sabre_ce_intr, 0, "SABRE_CE", pbm);
587 if (err)
588 printk(KERN_WARNING "%s: Couldn't register CE, err=%d.\n",
589 pbm->name, err);
590 err = request_irq(op->irqs[0], sabre_pcierr_intr, 0,
591 "SABRE_PCIERR", pbm);
592 if (err)
593 printk(KERN_WARNING "%s: Couldn't register PCIERR, err=%d.\n",
594 pbm->name, err);
1da177e4
LT		 595
596 tmp = sabre_read(base + SABRE_PCICTRL);
597 tmp |= SABRE_PCICTRL_ERREN;
598 sabre_write(base + SABRE_PCICTRL, tmp);
599}
600
34768bc8 601static void apb_init(struct pci_bus *sabre_bus)
1da177e4
LT		 602{
603 struct pci_dev *pdev;
604
605 list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
1da177e4
LT		 606 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
607 pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
1da177e4
LT		 608 u16 word16;
609
01f94c4a 610 pci_read_config_word(pdev, PCI_COMMAND, &word16);
1da177e4
LT		 611 word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
612 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
613 PCI_COMMAND_IO;
01f94c4a 614 pci_write_config_word(pdev, PCI_COMMAND, word16);
1da177e4
LT		 615
616 /* Status register bits are "write 1 to clear". */
01f94c4a
DM		 617 pci_write_config_word(pdev, PCI_STATUS, 0xffff);
618 pci_write_config_word(pdev, PCI_SEC_STATUS, 0xffff);
1da177e4
LT		 619
620 /* Use a primary/seconday latency timer value
621 * of 64.
622 */
01f94c4a
DM		 623 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
624 pci_write_config_byte(pdev, PCI_SEC_LATENCY_TIMER, 64);
1da177e4
LT		 625
626 /* Enable reporting/forwarding of master aborts,
627 * parity, and SERR.
628 */
01f94c4a
DM		 629 pci_write_config_byte(pdev, PCI_BRIDGE_CONTROL,
630 (PCI_BRIDGE_CTL_PARITY |
631 PCI_BRIDGE_CTL_SERR |
632 PCI_BRIDGE_CTL_MASTER_ABORT));
1da177e4
LT		 633 }
634 }
635}
636
e822358a
DM		 637static void __init sabre_scan_bus(struct pci_pbm_info *pbm,
638 struct device *parent)
1da177e4
LT		 639{
640 static int once;
1da177e4
LT		 641
642 /* The APB bridge speaks to the Sabre host PCI bridge
643 * at 66Mhz, but the front side of APB runs at 33Mhz
644 * for both segments.
321566c2
DM		 645 *
646 * Hummingbird systems do not use APB, so they run
647 * at 66MHZ.
1da177e4 648 */
321566c2
DM		 649 if (hummingbird_p)
650 pbm->is_66mhz_capable = 1;
651 else
652 pbm->is_66mhz_capable = 0;
1da177e4
LT		 653
654 /* This driver has not been verified to handle
655 * multiple SABREs yet, so trap this.
656 *
657 * Also note that the SABRE host bridge is hardwired
658 * to live at bus 0.
659 */
660 if (once != 0) {
edbe805b
DM		 661 printk(KERN_ERR PFX "Multiple controllers unsupported.\n");
662 return;
1da177e4
LT		 663 }
664 once++;
665
e822358a 666 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
321566c2 667 if (!pbm->pci_bus)
a2fb23af 668 return;
1da177e4 669
321566c2 670 sabre_root_bus = pbm->pci_bus;
1da177e4 671
321566c2 672 apb_init(pbm->pci_bus);
1da177e4 673
34768bc8 674 sabre_register_error_handlers(pbm);
1da177e4
LT		 675}
676
ad7ad57c
DM		 677static int sabre_iommu_init(struct pci_pbm_info *pbm,
678 int tsbsize, unsigned long dvma_offset,
679 u32 dma_mask)
1da177e4 680{
28113a99 681 struct iommu *iommu = pbm->iommu;
51e85136 682 unsigned long i;
1da177e4 683 u64 control;
ad7ad57c 684 int err;
1da177e4 685
1da177e4 686 /* Register addresses. */
28113a99
DM		 687 iommu->iommu_control = pbm->controller_regs + SABRE_IOMMU_CONTROL;
688 iommu->iommu_tsbbase = pbm->controller_regs + SABRE_IOMMU_TSBBASE;
689 iommu->iommu_flush = pbm->controller_regs + SABRE_IOMMU_FLUSH;
ad7ad57c 690 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
28113a99 691 iommu->write_complete_reg = pbm->controller_regs + SABRE_WRSYNC;
1da177e4
LT		 692 /* Sabre's IOMMU lacks ctx flushing. */
693 iommu->iommu_ctxflush = 0;
694
695 /* Invalidate TLB Entries. */
28113a99 696 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
1da177e4 697 control |= SABRE_IOMMUCTRL_DENAB;
28113a99 698 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
1da177e4
LT		 699
700 for(i = 0; i < 16; i++) {
28113a99
DM		 701 sabre_write(pbm->controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
702 sabre_write(pbm->controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
1da177e4
LT		 703 }
704
705 /* Leave diag mode enabled for full-flushing done
706 * in pci_iommu.c
707 */
ad7ad57c 708 err = iommu_table_init(iommu, tsbsize * 1024 * 8,
c1b1a5f1 709 dvma_offset, dma_mask, pbm->numa_node);
edbe805b
DM		 710 if (err) {
711 printk(KERN_ERR PFX "iommu_table_init() failed\n");
ad7ad57c 712 return err;
edbe805b 713 }
1da177e4 714
28113a99 715 sabre_write(pbm->controller_regs + SABRE_IOMMU_TSBBASE,
51e85136 716 __pa(iommu->page_table));
1da177e4 717
28113a99 718 control = sabre_read(pbm->controller_regs + SABRE_IOMMU_CONTROL);
1da177e4
LT		 719 control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
720 control |= SABRE_IOMMUCTRL_ENAB;
721 switch(tsbsize) {
722 case 64:
723 control |= SABRE_IOMMU_TSBSZ_64K;
1da177e4
LT		 724 break;
725 case 128:
726 control |= SABRE_IOMMU_TSBSZ_128K;
1da177e4
LT		 727 break;
728 default:
edbe805b
DM		 729 printk(KERN_ERR PFX "Illegal TSB size %d\n", tsbsize);
730 return -EINVAL;
1da177e4 731 }
28113a99 732 sabre_write(pbm->controller_regs + SABRE_IOMMU_CONTROL, control);
ad7ad57c
DM		 733
734 return 0;
1da177e4
LT		 735}
736
d3ae4b5b
DM		 737static void __init sabre_pbm_init(struct pci_pbm_info *pbm,
738 struct of_device *op)
1da177e4 739{
e822358a
DM		 740 struct device_node *dp = op->node;
741
01f94c4a
DM		 742 pbm->name = dp->full_name;
743 printk("%s: SABRE PCI Bus Module\n", pbm->name);
744
c1b1a5f1
DM		 745 pbm->numa_node = -1;
746
ca3dd88e
DM		 747 pbm->pci_ops = &sun4u_pci_ops;
748 pbm->config_space_reg_bits = 8;
34768bc8 749
6c108f12
DM		 750 pbm->index = pci_num_pbms++;
751
01f94c4a 752 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
01f94c4a 753 pbm->prom_node = dp;
cfa0652c 754 pci_get_pbm_props(pbm);
01f94c4a 755
9fd8b647 756 pci_determine_mem_io_space(pbm);
edbe805b 757
e822358a 758 sabre_scan_bus(pbm, &op->dev);
1da177e4
LT		 759}
760
edbe805b
DM		 761static int __devinit sabre_probe(struct of_device *op,
762 const struct of_device_id *match)
1da177e4 763{
a165b420 764 const struct linux_prom64_registers *pr_regs;
edbe805b 765 struct device_node *dp = op->node;
28113a99 766 struct pci_pbm_info *pbm;
edbe805b 767 u32 upa_portid, dma_mask;
16ce82d8 768 struct iommu *iommu;
edbe805b 769 int tsbsize, err;
a165b420 770 const u32 *vdma;
1da177e4
LT		 771 u64 clear_irq;
772
edbe805b
DM		 773 hummingbird_p = (match->data != NULL);
774 if (!hummingbird_p) {
775 struct device_node *cpu_dp;
776
777 /* Of course, Sun has to encode things a thousand
778 * different ways, inconsistently.
779 */
780 for_each_node_by_type(cpu_dp, "cpu") {
781 if (!strcmp(cpu_dp->name, "SUNW,UltraSPARC-IIe"))
782 hummingbird_p = 1;
1da177e4
LT		 783 }
784 }
785
edbe805b 786 err = -ENOMEM;
d3ae4b5b
DM		 787 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
788 if (!pbm) {
789 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
d7472c38 790 goto out_err;
edbe805b 791 }
1da177e4 792
d3ae4b5b 793 iommu = kzalloc(sizeof(*iommu), GFP_KERNEL);
edbe805b
DM		 794 if (!iommu) {
795 printk(KERN_ERR PFX "Cannot allocate PBM iommu.\n");
d7472c38 796 goto out_free_controller;
edbe805b
DM		 797 }
798
28113a99 799 pbm->iommu = iommu;
1da177e4 800
01f94c4a 801 upa_portid = of_getintprop_default(dp, "upa-portid", 0xff);
1da177e4 802
28113a99 803 pbm->portid = upa_portid;
1da177e4
LT		 804
805 /*
806 * Map in SABRE register set and report the presence of this SABRE.
807 */
e87dc350 808
01f94c4a 809 pr_regs = of_get_property(dp, "reg", NULL);
edbe805b
DM		 810 err = -ENODEV;
811 if (!pr_regs) {
812 printk(KERN_ERR PFX "No reg property\n");
d7472c38 813 goto out_free_iommu;
edbe805b 814 }
1da177e4
LT		 815
816 /*
817 * First REG in property is base of entire SABRE register space.
818 */
28113a99 819 pbm->controller_regs = pr_regs[0].phys_addr;
1da177e4 820
1da177e4
LT		 821 /* Clear interrupts */
822
823 /* PCI first */
824 for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
28113a99 825 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
1da177e4
LT		 826
827 /* Then OBIO */
828 for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
28113a99 829 sabre_write(pbm->controller_regs + clear_irq, 0x0UL);
1da177e4
LT		 830
831 /* Error interrupts are enabled later after the bus scan. */
28113a99 832 sabre_write(pbm->controller_regs + SABRE_PCICTRL,
1da177e4
LT		 833 (SABRE_PCICTRL_MRLEN | SABRE_PCICTRL_SERR |
834 SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
835
836 /* Now map in PCI config space for entire SABRE. */
d3ae4b5b 837 pbm->config_space = pbm->controller_regs + SABRE_CONFIGSPACE;
e87dc350 838
01f94c4a 839 vdma = of_get_property(dp, "virtual-dma", NULL);
edbe805b
DM		 840 if (!vdma) {
841 printk(KERN_ERR PFX "No virtual-dma property\n");
d7472c38 842 goto out_free_iommu;
edbe805b 843 }
1da177e4
LT		 844
845 dma_mask = vdma[0];
846 switch(vdma[1]) {
847 case 0x20000000:
848 dma_mask |= 0x1fffffff;
849 tsbsize = 64;
850 break;
851 case 0x40000000:
852 dma_mask |= 0x3fffffff;
853 tsbsize = 128;
854 break;
855
856 case 0x80000000:
857 dma_mask |= 0x7fffffff;
858 tsbsize = 128;
859 break;
860 default:
edbe805b 861 printk(KERN_ERR PFX "Strange virtual-dma size.\n");
d7472c38 862 goto out_free_iommu;
1da177e4
LT		 863 }
864
edbe805b
DM		 865 err = sabre_iommu_init(pbm, tsbsize, vdma[0], dma_mask);
866 if (err)
d7472c38 867 goto out_free_iommu;
1da177e4 868
1da177e4
LT		 869 /*
870 * Look for APB underneath.
871 */
d3ae4b5b
DM		 872 sabre_pbm_init(pbm, op);
873
874 pbm->next = pci_pbm_root;
875 pci_pbm_root = pbm;
876
877 dev_set_drvdata(&op->dev, pbm);
878
edbe805b 879 return 0;
ad7ad57c 880
d7472c38 881out_free_iommu:
d3ae4b5b 882 kfree(pbm->iommu);
d7472c38
DM		 883
884out_free_controller:
d3ae4b5b 885 kfree(pbm);
d7472c38
DM		 886
887out_err:
edbe805b 888 return err;
1da177e4 889}
edbe805b 890
fd098316 891static struct of_device_id __initdata sabre_match[] = {
edbe805b
DM		 892 {
893 .name = "pci",
894 .compatible = "pci108e,a001",
895 .data = (void *) 1,
896 },
897 {
898 .name = "pci",
899 .compatible = "pci108e,a000",
900 },
901 {},
902};
903
904static struct of_platform_driver sabre_driver = {
905 .name = DRIVER_NAME,
906 .match_table = sabre_match,
907 .probe = sabre_probe,
908};
909
910static int __init sabre_init(void)
911{
912 return of_register_driver(&sabre_driver, &of_bus_type);
913}
914
915subsys_initcall(sabre_init);
Linux 6.x block layer and io_uring tree(s)