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[SPARC64]: Move {setup,teardown}_msi_irq into pci_pbm_info.
[linux-2.6-block.git] / arch / sparc64 / kernel / pci_psycho.c
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9fd8b647 1/* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
1da177e4 2 *
9fd8b647 3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/slab.h>
13#include <linux/interrupt.h>
14
15#include <asm/pbm.h>
16#include <asm/iommu.h>
17#include <asm/irq.h>
18#include <asm/starfire.h>
e87dc350 19#include <asm/prom.h>
2b1e5978 20#include <asm/of_device.h>
1da177e4
LT		 21
22#include "pci_impl.h"
23#include "iommu_common.h"
24
25/* All PSYCHO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
28 */
29#define psycho_read(__reg) \
30({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36})
37#define psycho_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43
44/* Misc. PSYCHO PCI controller register offsets and definitions. */
45#define PSYCHO_CONTROL 0x0010UL
46#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
47#define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
48#define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
49#define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
50#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
51#define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
52#define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
53#define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
54#define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
55#define PSYCHO_PCIA_CTRL 0x2000UL
56#define PSYCHO_PCIB_CTRL 0x4000UL
57#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
58#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
59#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
60#define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
61#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
62#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
63#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
64#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
65#define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
66#define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
67#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
68#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
69
70/* U2P Programmer's Manual, page 13-55, configuration space
71 * address format:
72 *
73 * 32 24 23 16 15 11 10 8 7 2 1 0
74 * ---------------------------------------------------------
75 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
76 * ---------------------------------------------------------
77 */
78#define PSYCHO_CONFIG_BASE(PBM) \
79 ((PBM)->config_space | (1UL << 24))
80#define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 (((unsigned long)(BUS) << 16) | \
82 ((unsigned long)(DEVFN) << 8) | \
83 ((unsigned long)(REG)))
84
85static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
86 unsigned char bus,
87 unsigned int devfn,
88 int where)
89{
90 if (!pbm)
91 return NULL;
92 return (void *)
93 (PSYCHO_CONFIG_BASE(pbm) |
94 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
95}
96
97static int psycho_out_of_range(struct pci_pbm_info *pbm,
98 unsigned char bus,
99 unsigned char devfn)
100{
101 return ((pbm->parent == 0) ||
102 ((pbm == &pbm->parent->pbm_B) &&
103 (bus == pbm->pci_first_busno) &&
104 PCI_SLOT(devfn) > 8) ||
105 ((pbm == &pbm->parent->pbm_A) &&
106 (bus == pbm->pci_first_busno) &&
107 PCI_SLOT(devfn) > 8));
108}
109
110/* PSYCHO PCI configuration space accessors. */
111
112static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
113 int where, int size, u32 *value)
114{
115 struct pci_pbm_info *pbm = bus_dev->sysdata;
116 unsigned char bus = bus_dev->number;
117 u32 *addr;
118 u16 tmp16;
119 u8 tmp8;
120
97b3cf05
DM		 121 if (bus_dev == pbm->pci_bus && devfn == 0x00)
122 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
123 size, value);
124
1da177e4
LT		 125 switch (size) {
126 case 1:
127 *value = 0xff;
128 break;
129 case 2:
130 *value = 0xffff;
131 break;
132 case 4:
133 *value = 0xffffffff;
134 break;
135 }
136
137 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
138 if (!addr)
139 return PCIBIOS_SUCCESSFUL;
140
141 if (psycho_out_of_range(pbm, bus, devfn))
142 return PCIBIOS_SUCCESSFUL;
143 switch (size) {
144 case 1:
145 pci_config_read8((u8 *)addr, &tmp8);
146 *value = (u32) tmp8;
147 break;
148
149 case 2:
150 if (where & 0x01) {
151 printk("pci_read_config_word: misaligned reg [%x]\n",
152 where);
153 return PCIBIOS_SUCCESSFUL;
154 }
155 pci_config_read16((u16 *)addr, &tmp16);
156 *value = (u32) tmp16;
157 break;
158
159 case 4:
160 if (where & 0x03) {
161 printk("pci_read_config_dword: misaligned reg [%x]\n",
162 where);
163 return PCIBIOS_SUCCESSFUL;
164 }
165 pci_config_read32(addr, value);
166 break;
167 }
168 return PCIBIOS_SUCCESSFUL;
169}
170
171static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
172 int where, int size, u32 value)
173{
174 struct pci_pbm_info *pbm = bus_dev->sysdata;
175 unsigned char bus = bus_dev->number;
176 u32 *addr;
177
97b3cf05
DM		 178 if (bus_dev == pbm->pci_bus && devfn == 0x00)
179 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
180 size, value);
1da177e4
LT		 181 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
182 if (!addr)
183 return PCIBIOS_SUCCESSFUL;
184
185 if (psycho_out_of_range(pbm, bus, devfn))
186 return PCIBIOS_SUCCESSFUL;
187
188 switch (size) {
189 case 1:
190 pci_config_write8((u8 *)addr, value);
191 break;
192
193 case 2:
194 if (where & 0x01) {
195 printk("pci_write_config_word: misaligned reg [%x]\n",
196 where);
197 return PCIBIOS_SUCCESSFUL;
198 }
199 pci_config_write16((u16 *)addr, value);
200 break;
201
202 case 4:
203 if (where & 0x03) {
204 printk("pci_write_config_dword: misaligned reg [%x]\n",
205 where);
206 return PCIBIOS_SUCCESSFUL;
207 }
208 pci_config_write32(addr, value);
209 }
210 return PCIBIOS_SUCCESSFUL;
211}
212
213static struct pci_ops psycho_ops = {
214 .read = psycho_read_pci_cfg,
215 .write = psycho_write_pci_cfg,
216};
217
1da177e4
LT		 218/* PSYCHO error handling support. */
219enum psycho_error_type {
220 UE_ERR, CE_ERR, PCI_ERR
221};
222
223/* Helper function of IOMMU error checking, which checks out
224 * the state of the streaming buffers. The IOMMU lock is
225 * held when this is called.
226 *
227 * For the PCI error case we know which PBM (and thus which
228 * streaming buffer) caused the error, but for the uncorrectable
229 * error case we do not. So we always check both streaming caches.
230 */
231#define PSYCHO_STRBUF_CONTROL_A 0x2800UL
232#define PSYCHO_STRBUF_CONTROL_B 0x4800UL
233#define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
234#define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
235#define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
236#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
237#define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
238#define PSYCHO_STRBUF_FLUSH_A 0x2808UL
239#define PSYCHO_STRBUF_FLUSH_B 0x4808UL
240#define PSYCHO_STRBUF_FSYNC_A 0x2810UL
241#define PSYCHO_STRBUF_FSYNC_B 0x4810UL
242#define PSYCHO_STC_DATA_A 0xb000UL
243#define PSYCHO_STC_DATA_B 0xc000UL
244#define PSYCHO_STC_ERR_A 0xb400UL
245#define PSYCHO_STC_ERR_B 0xc400UL
246#define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
247#define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
248#define PSYCHO_STC_TAG_A 0xb800UL
249#define PSYCHO_STC_TAG_B 0xc800UL
250#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
251#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
252#define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
253#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
254#define PSYCHO_STC_LINE_A 0xb900UL
255#define PSYCHO_STC_LINE_B 0xc900UL
256#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
257#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
258#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
259#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
260#define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
261#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
262
263static DEFINE_SPINLOCK(stc_buf_lock);
264static unsigned long stc_error_buf[128];
265static unsigned long stc_tag_buf[16];
266static unsigned long stc_line_buf[16];
267
34768bc8 268static void __psycho_check_one_stc(struct pci_pbm_info *pbm,
1da177e4
LT		 269 int is_pbm_a)
270{
34768bc8 271 struct pci_controller_info *p = pbm->parent;
16ce82d8 272 struct strbuf *strbuf = &pbm->stc;
34768bc8 273 unsigned long regbase = pbm->controller_regs;
1da177e4
LT		 274 unsigned long err_base, tag_base, line_base;
275 u64 control;
276 int i;
277
278 if (is_pbm_a) {
279 err_base = regbase + PSYCHO_STC_ERR_A;
280 tag_base = regbase + PSYCHO_STC_TAG_A;
281 line_base = regbase + PSYCHO_STC_LINE_A;
282 } else {
283 err_base = regbase + PSYCHO_STC_ERR_B;
284 tag_base = regbase + PSYCHO_STC_TAG_B;
285 line_base = regbase + PSYCHO_STC_LINE_B;
286 }
287
288 spin_lock(&stc_buf_lock);
289
290 /* This is __REALLY__ dangerous. When we put the
291 * streaming buffer into diagnostic mode to probe
292 * it's tags and error status, we _must_ clear all
293 * of the line tag valid bits before re-enabling
294 * the streaming buffer. If any dirty data lives
295 * in the STC when we do this, we will end up
296 * invalidating it before it has a chance to reach
297 * main memory.
298 */
299 control = psycho_read(strbuf->strbuf_control);
300 psycho_write(strbuf->strbuf_control,
301 (control | PSYCHO_STRBUF_CTRL_DENAB));
302 for (i = 0; i < 128; i++) {
303 unsigned long val;
304
305 val = psycho_read(err_base + (i * 8UL));
306 psycho_write(err_base + (i * 8UL), 0UL);
307 stc_error_buf[i] = val;
308 }
309 for (i = 0; i < 16; i++) {
310 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
311 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
312 psycho_write(tag_base + (i * 8UL), 0UL);
313 psycho_write(line_base + (i * 8UL), 0UL);
314 }
315
316 /* OK, state is logged, exit diagnostic mode. */
317 psycho_write(strbuf->strbuf_control, control);
318
319 for (i = 0; i < 16; i++) {
320 int j, saw_error, first, last;
321
322 saw_error = 0;
323 first = i * 8;
324 last = first + 8;
325 for (j = first; j < last; j++) {
326 unsigned long errval = stc_error_buf[j];
327 if (errval != 0) {
328 saw_error++;
329 printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n",
330 p->index,
331 (is_pbm_a ? 'A' : 'B'),
332 j,
333 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
334 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
335 }
336 }
337 if (saw_error != 0) {
338 unsigned long tagval = stc_tag_buf[i];
339 unsigned long lineval = stc_line_buf[i];
340 printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
341 p->index,
342 (is_pbm_a ? 'A' : 'B'),
343 i,
344 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
345 (tagval & PSYCHO_STCTAG_VPN),
346 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
347 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
348 printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
349 "V(%d)FOFN(%d)]\n",
350 p->index,
351 (is_pbm_a ? 'A' : 'B'),
352 i,
353 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
354 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
355 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
356 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
357 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
358 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
359 }
360 }
361
362 spin_unlock(&stc_buf_lock);
363}
364
34768bc8 365static void __psycho_check_stc_error(struct pci_pbm_info *pbm,
1da177e4
LT		 366 unsigned long afsr,
367 unsigned long afar,
368 enum psycho_error_type type)
369{
34768bc8
DM		 370 __psycho_check_one_stc(pbm,
371 (pbm == &pbm->parent->pbm_A));
1da177e4
LT		 372}
373
374/* When an Uncorrectable Error or a PCI Error happens, we
375 * interrogate the IOMMU state to see if it is the cause.
376 */
377#define PSYCHO_IOMMU_CONTROL 0x0200UL
378#define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
379#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
380#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
381#define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
382#define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
383#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
384#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
385#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
386#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
387#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
388#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
389#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
390#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
391#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
392#define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
393#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
394#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
395#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
396#define PSYCHO_IOMMU_TSBBASE 0x0208UL
397#define PSYCHO_IOMMU_FLUSH 0x0210UL
398#define PSYCHO_IOMMU_TAG 0xa580UL
399#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
400#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
401#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
402#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
403#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
404#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
405#define PSYCHO_IOMMU_DATA 0xa600UL
406#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
407#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
408#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
34768bc8 409static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
1da177e4
LT		 410 unsigned long afsr,
411 unsigned long afar,
412 enum psycho_error_type type)
413{
34768bc8
DM		 414 struct pci_controller_info *p = pbm->parent;
415 struct iommu *iommu = pbm->iommu;
1da177e4
LT		 416 unsigned long iommu_tag[16];
417 unsigned long iommu_data[16];
418 unsigned long flags;
419 u64 control;
420 int i;
421
422 spin_lock_irqsave(&iommu->lock, flags);
423 control = psycho_read(iommu->iommu_control);
424 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
425 char *type_string;
426
427 /* Clear the error encountered bit. */
428 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
429 psycho_write(iommu->iommu_control, control);
430
431 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
432 case 0:
433 type_string = "Protection Error";
434 break;
435 case 1:
436 type_string = "Invalid Error";
437 break;
438 case 2:
439 type_string = "TimeOut Error";
440 break;
441 case 3:
442 default:
443 type_string = "ECC Error";
444 break;
445 };
446 printk("PSYCHO%d: IOMMU Error, type[%s]\n",
447 p->index, type_string);
448
449 /* Put the IOMMU into diagnostic mode and probe
450 * it's TLB for entries with error status.
451 *
452 * It is very possible for another DVMA to occur
453 * while we do this probe, and corrupt the system
454 * further. But we are so screwed at this point
455 * that we are likely to crash hard anyways, so
456 * get as much diagnostic information to the
457 * console as we can.
458 */
459 psycho_write(iommu->iommu_control,
460 control | PSYCHO_IOMMU_CTRL_DENAB);
461 for (i = 0; i < 16; i++) {
34768bc8 462 unsigned long base = pbm->controller_regs;
1da177e4
LT		 463
464 iommu_tag[i] =
465 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
466 iommu_data[i] =
467 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
468
469 /* Now clear out the entry. */
470 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
471 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
472 }
473
474 /* Leave diagnostic mode. */
475 psycho_write(iommu->iommu_control, control);
476
477 for (i = 0; i < 16; i++) {
478 unsigned long tag, data;
479
480 tag = iommu_tag[i];
481 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
482 continue;
483
484 data = iommu_data[i];
485 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
486 case 0:
487 type_string = "Protection Error";
488 break;
489 case 1:
490 type_string = "Invalid Error";
491 break;
492 case 2:
493 type_string = "TimeOut Error";
494 break;
495 case 3:
496 default:
497 type_string = "ECC Error";
498 break;
499 };
500 printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
501 p->index, i, type_string,
502 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
503 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
504 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
505 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
506 printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
507 p->index, i,
508 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
509 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
510 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
511 }
512 }
34768bc8 513 __psycho_check_stc_error(pbm, afsr, afar, type);
1da177e4
LT		 514 spin_unlock_irqrestore(&iommu->lock, flags);
515}
516
517/* Uncorrectable Errors. Cause of the error and the address are
518 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
519 * relating to UPA interface transactions.
520 */
521#define PSYCHO_UE_AFSR 0x0030UL
522#define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
523#define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
524#define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
525#define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
526#define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
527#define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
528#define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
529#define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
530#define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
531#define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
532#define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
533#define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
534#define PSYCHO_UE_AFAR 0x0038UL
535
6d24c8dc 536static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
1da177e4 537{
34768bc8
DM		 538 struct pci_pbm_info *pbm = dev_id;
539 struct pci_controller_info *p = pbm->parent;
540 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
541 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
1da177e4
LT		 542 unsigned long afsr, afar, error_bits;
543 int reported;
544
545 /* Latch uncorrectable error status. */
546 afar = psycho_read(afar_reg);
547 afsr = psycho_read(afsr_reg);
548
549 /* Clear the primary/secondary error status bits. */
550 error_bits = afsr &
551 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
552 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
553 if (!error_bits)
554 return IRQ_NONE;
555 psycho_write(afsr_reg, error_bits);
556
557 /* Log the error. */
558 printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n",
559 p->index,
560 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
561 "PIO" :
562 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
563 "DMA Read" :
564 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
565 "DMA Write" : "???")))));
566 printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
567 p->index,
568 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
569 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
570 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
571 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
572 printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar);
573 printk("PSYCHO%d: UE Secondary errors [", p->index);
574 reported = 0;
575 if (afsr & PSYCHO_UEAFSR_SPIO) {
576 reported++;
577 printk("(PIO)");
578 }
579 if (afsr & PSYCHO_UEAFSR_SDRD) {
580 reported++;
581 printk("(DMA Read)");
582 }
583 if (afsr & PSYCHO_UEAFSR_SDWR) {
584 reported++;
585 printk("(DMA Write)");
586 }
587 if (!reported)
588 printk("(none)");
589 printk("]\n");
590
34768bc8
DM		 591 /* Interrogate both IOMMUs for error status. */
592 psycho_check_iommu_error(&p->pbm_A, afsr, afar, UE_ERR);
593 psycho_check_iommu_error(&p->pbm_B, afsr, afar, UE_ERR);
1da177e4
LT		 594
595 return IRQ_HANDLED;
596}
597
598/* Correctable Errors. */
599#define PSYCHO_CE_AFSR 0x0040UL
600#define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
601#define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
602#define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
603#define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
604#define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
605#define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
606#define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
607#define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
608#define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
609#define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
610#define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
611#define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
612#define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
613#define PSYCHO_CE_AFAR 0x0040UL
614
6d24c8dc 615static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
1da177e4 616{
34768bc8
DM		 617 struct pci_pbm_info *pbm = dev_id;
618 struct pci_controller_info *p = pbm->parent;
619 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
620 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
1da177e4
LT		 621 unsigned long afsr, afar, error_bits;
622 int reported;
623
624 /* Latch error status. */
625 afar = psycho_read(afar_reg);
626 afsr = psycho_read(afsr_reg);
627
628 /* Clear primary/secondary error status bits. */
629 error_bits = afsr &
630 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
631 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
632 if (!error_bits)
633 return IRQ_NONE;
634 psycho_write(afsr_reg, error_bits);
635
636 /* Log the error. */
637 printk("PSYCHO%d: Correctable Error, primary error type[%s]\n",
638 p->index,
639 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
640 "PIO" :
641 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
642 "DMA Read" :
643 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
644 "DMA Write" : "???")))));
645
646 /* XXX Use syndrome and afar to print out module string just like
647 * XXX UDB CE trap handler does... -DaveM
648 */
649 printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
650 "UPA_MID[%02lx] was_block(%d)\n",
651 p->index,
652 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
653 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
654 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
655 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
656 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
657 printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar);
658 printk("PSYCHO%d: CE Secondary errors [", p->index);
659 reported = 0;
660 if (afsr & PSYCHO_CEAFSR_SPIO) {
661 reported++;
662 printk("(PIO)");
663 }
664 if (afsr & PSYCHO_CEAFSR_SDRD) {
665 reported++;
666 printk("(DMA Read)");
667 }
668 if (afsr & PSYCHO_CEAFSR_SDWR) {
669 reported++;
670 printk("(DMA Write)");
671 }
672 if (!reported)
673 printk("(none)");
674 printk("]\n");
675
676 return IRQ_HANDLED;
677}
678
679/* PCI Errors. They are signalled by the PCI bus module since they
680 * are associated with a specific bus segment.
681 */
682#define PSYCHO_PCI_AFSR_A 0x2010UL
683#define PSYCHO_PCI_AFSR_B 0x4010UL
684#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
685#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
686#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
687#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
688#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
689#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
690#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
691#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
692#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
693#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
694#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
695#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
696#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
697#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
698#define PSYCHO_PCI_AFAR_A 0x2018UL
699#define PSYCHO_PCI_AFAR_B 0x4018UL
700
701static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
702{
703 unsigned long csr_reg, csr, csr_error_bits;
704 irqreturn_t ret = IRQ_NONE;
705 u16 stat;
706
707 if (is_pbm_a) {
708 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
709 } else {
710 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
711 }
712 csr = psycho_read(csr_reg);
713 csr_error_bits =
714 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
715 if (csr_error_bits) {
716 /* Clear the errors. */
717 psycho_write(csr_reg, csr);
718
719 /* Log 'em. */
720 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
721 printk("%s: PCI streaming byte hole error asserted.\n",
722 pbm->name);
723 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
724 printk("%s: PCI SERR signal asserted.\n", pbm->name);
725 ret = IRQ_HANDLED;
726 }
727 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
728 if (stat & (PCI_STATUS_PARITY |
729 PCI_STATUS_SIG_TARGET_ABORT |
730 PCI_STATUS_REC_TARGET_ABORT |
731 PCI_STATUS_REC_MASTER_ABORT |
732 PCI_STATUS_SIG_SYSTEM_ERROR)) {
733 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
734 pbm->name, stat);
735 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
736 ret = IRQ_HANDLED;
737 }
738 return ret;
739}
740
6d24c8dc 741static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
1da177e4
LT		 742{
743 struct pci_pbm_info *pbm = dev_id;
744 struct pci_controller_info *p = pbm->parent;
745 unsigned long afsr_reg, afar_reg;
746 unsigned long afsr, afar, error_bits;
747 int is_pbm_a, reported;
748
749 is_pbm_a = (pbm == &pbm->parent->pbm_A);
750 if (is_pbm_a) {
751 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
752 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
753 } else {
754 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
755 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
756 }
757
758 /* Latch error status. */
759 afar = psycho_read(afar_reg);
760 afsr = psycho_read(afsr_reg);
761
762 /* Clear primary/secondary error status bits. */
763 error_bits = afsr &
764 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
765 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
766 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
767 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
768 if (!error_bits)
769 return psycho_pcierr_intr_other(pbm, is_pbm_a);
770 psycho_write(afsr_reg, error_bits);
771
772 /* Log the error. */
773 printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n",
774 p->index, (is_pbm_a ? 'A' : 'B'),
775 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
776 "Master Abort" :
777 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
778 "Target Abort" :
779 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
780 "Excessive Retries" :
781 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
782 "Parity Error" : "???"))))));
783 printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
784 p->index, (is_pbm_a ? 'A' : 'B'),
785 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
786 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
787 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
788 printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n",
789 p->index, (is_pbm_a ? 'A' : 'B'), afar);
790 printk("PSYCHO%d(PBM%c): PCI Secondary errors [",
791 p->index, (is_pbm_a ? 'A' : 'B'));
792 reported = 0;
793 if (afsr & PSYCHO_PCIAFSR_SMA) {
794 reported++;
795 printk("(Master Abort)");
796 }
797 if (afsr & PSYCHO_PCIAFSR_STA) {
798 reported++;
799 printk("(Target Abort)");
800 }
801 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
802 reported++;
803 printk("(Excessive Retries)");
804 }
805 if (afsr & PSYCHO_PCIAFSR_SPERR) {
806 reported++;
807 printk("(Parity Error)");
808 }
809 if (!reported)
810 printk("(none)");
811 printk("]\n");
812
813 /* For the error types shown, scan PBM's PCI bus for devices
814 * which have logged that error type.
815 */
816
817 /* If we see a Target Abort, this could be the result of an
818 * IOMMU translation error of some sort. It is extremely
819 * useful to log this information as usually it indicates
820 * a bug in the IOMMU support code or a PCI device driver.
821 */
822 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
34768bc8
DM		 823 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
824 pci_scan_for_target_abort(pbm->parent, pbm, pbm->pci_bus);
1da177e4
LT		 825 }
826 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
34768bc8 827 pci_scan_for_master_abort(pbm->parent, pbm, pbm->pci_bus);
1da177e4
LT		 828
829 /* For excessive retries, PSYCHO/PBM will abort the device
830 * and there is no way to specifically check for excessive
831 * retries in the config space status registers. So what
832 * we hope is that we'll catch it via the master/target
833 * abort events.
834 */
835
836 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
34768bc8 837 pci_scan_for_parity_error(pbm->parent, pbm, pbm->pci_bus);
1da177e4
LT		 838
839 return IRQ_HANDLED;
840}
841
842/* XXX What about PowerFail/PowerManagement??? -DaveM */
843#define PSYCHO_ECC_CTRL 0x0020
844#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
845#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
846#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
34768bc8 847static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 848{
2b1e5978 849 struct of_device *op = of_find_device_by_node(pbm->prom_node);
34768bc8 850 unsigned long base = pbm->controller_regs;
1da177e4
LT		 851 u64 tmp;
852
2b1e5978
DM		 853 if (!op)
854 return;
1da177e4 855
2b1e5978 856 /* Psycho interrupt property order is:
34768bc8 857 * 0: PCIERR INO for this PBM
2b1e5978
DM		 858 * 1: UE ERR
859 * 2: CE ERR
860 * 3: POWER FAIL
861 * 4: SPARE HARDWARE
34768bc8 862 * 5: POWER MANAGEMENT
2b1e5978 863 */
1da177e4 864
2b1e5978
DM		 865 if (op->num_irqs < 6)
866 return;
1da177e4 867
34768bc8
DM		 868 request_irq(op->irqs[1], psycho_ue_intr, 0,
869 "PSYCHO_UE", pbm);
870 request_irq(op->irqs[2], psycho_ce_intr, 0,
871 "PSYCHO_CE", pbm);
872 request_irq(op->irqs[0], psycho_pcierr_intr, 0,
873 "PSYCHO_PCIERR", pbm);
1da177e4
LT		 874
875 /* Enable UE and CE interrupts for controller. */
876 psycho_write(base + PSYCHO_ECC_CTRL,
877 (PSYCHO_ECCCTRL_EE |
878 PSYCHO_ECCCTRL_UE |
879 PSYCHO_ECCCTRL_CE));
880
881 /* Enable PCI Error interrupts and clear error
882 * bits for each PBM.
883 */
884 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
885 tmp |= (PSYCHO_PCICTRL_SERR |
886 PSYCHO_PCICTRL_SBH_ERR |
887 PSYCHO_PCICTRL_EEN);
888 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
889 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
890
891 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
892 tmp |= (PSYCHO_PCICTRL_SERR |
893 PSYCHO_PCICTRL_SBH_ERR |
894 PSYCHO_PCICTRL_EEN);
895 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
896 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
897}
898
899/* PSYCHO boot time probing and initialization. */
085ae41f 900static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 901{
902 u8 *addr;
903
904 /* Set cache-line size to 64 bytes, this is actually
905 * a nop but I do it for completeness.
906 */
907 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
908 0, PCI_CACHE_LINE_SIZE);
909 pci_config_write8(addr, 64 / sizeof(u32));
910
911 /* Set PBM latency timer to 64 PCI clocks. */
912 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
913 0, PCI_LATENCY_TIMER);
914 pci_config_write8(addr, 64);
915}
916
34768bc8 917static void psycho_scan_bus(struct pci_pbm_info *pbm)
1da177e4 918{
34768bc8
DM		 919 pbm_config_busmastering(pbm);
920 pbm->is_66mhz_capable = 0;
a2fb23af 921 pbm->pci_bus = pci_scan_one_pbm(pbm);
1da177e4
LT		 922
923 /* After the PCI bus scan is complete, we can register
924 * the error interrupt handlers.
925 */
34768bc8 926 psycho_register_error_handlers(pbm);
1da177e4
LT		 927}
928
085ae41f 929static void psycho_iommu_init(struct pci_controller_info *p)
1da177e4 930{
16ce82d8 931 struct iommu *iommu = p->pbm_A.iommu;
51e85136 932 unsigned long i;
1da177e4
LT		 933 u64 control;
934
1da177e4
LT		 935 /* Register addresses. */
936 iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
937 iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
938 iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
939 /* PSYCHO's IOMMU lacks ctx flushing. */
940 iommu->iommu_ctxflush = 0;
941
942 /* We use the main control register of PSYCHO as the write
943 * completion register.
944 */
945 iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
946
947 /*
948 * Invalidate TLB Entries.
949 */
950 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
951 control |= PSYCHO_IOMMU_CTRL_DENAB;
952 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
953 for(i = 0; i < 16; i++) {
954 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
955 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
956 }
957
958 /* Leave diag mode enabled for full-flushing done
959 * in pci_iommu.c
960 */
51e85136 961 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
1da177e4 962
51e85136
DM		 963 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
964 __pa(iommu->page_table));
1da177e4
LT		 965
966 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
967 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
968 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
969 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
970
971 /* If necessary, hook us up for starfire IRQ translations. */
51e85136 972 if (this_is_starfire)
286bbe87 973 starfire_hookup(p->pbm_A.portid);
1da177e4
LT		 974}
975
976#define PSYCHO_IRQ_RETRY 0x1a00UL
977#define PSYCHO_PCIA_DIAG 0x2020UL
978#define PSYCHO_PCIB_DIAG 0x4020UL
979#define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
980#define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
981#define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
982#define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
983#define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
984#define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
985#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
986#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
987
988static void psycho_controller_hwinit(struct pci_controller_info *p)
989{
990 u64 tmp;
991
864ae180 992 psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);
1da177e4
LT		 993
994 /* Enable arbiter for all PCI slots. */
995 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
996 tmp |= PSYCHO_PCICTRL_AEN;
997 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
998
999 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
1000 tmp |= PSYCHO_PCICTRL_AEN;
1001 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
1002
1003 /* Disable DMA write / PIO read synchronization on
1004 * both PCI bus segments.
1005 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
1006 */
1007 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
1008 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1009 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
1010
1011 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
1012 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1013 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
1014}
1015
1da177e4
LT		 1016static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1017 struct pci_pbm_info *pbm,
1018 int is_pbm_a)
1019{
1020 unsigned long base = pbm->controller_regs;
1021 u64 control;
1022
1023 if (is_pbm_a) {
1024 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1025 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1026 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1027 } else {
1028 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1029 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1030 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1031 }
1032 /* PSYCHO's streaming buffer lacks ctx flushing. */
1033 pbm->stc.strbuf_ctxflush = 0;
1034 pbm->stc.strbuf_ctxmatch_base = 0;
1035
1036 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1037 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1038 + 63UL)
1039 & ~63UL);
1040 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1041 __pa(pbm->stc.strbuf_flushflag);
1042
1043 /* Enable the streaming buffer. We have to be careful
1044 * just in case OBP left it with LRU locking enabled.
1045 *
1046 * It is possible to control if PBM will be rerun on
1047 * line misses. Currently I just retain whatever setting
1048 * OBP left us with. All checks so far show it having
1049 * a value of zero.
1050 */
1051#undef PSYCHO_STRBUF_RERUN_ENABLE
1052#undef PSYCHO_STRBUF_RERUN_DISABLE
1053 control = psycho_read(pbm->stc.strbuf_control);
1054 control |= PSYCHO_STRBUF_CTRL_ENAB;
1055 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1056#ifdef PSYCHO_STRBUF_RERUN_ENABLE
1057 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1058#else
1059#ifdef PSYCHO_STRBUF_RERUN_DISABLE
1060 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1061#endif
1062#endif
1063 psycho_write(pbm->stc.strbuf_control, control);
1064
1065 pbm->stc.strbuf_enabled = 1;
1066}
1067
1068#define PSYCHO_IOSPACE_A 0x002000000UL
1069#define PSYCHO_IOSPACE_B 0x002010000UL
1070#define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1071#define PSYCHO_MEMSPACE_A 0x100000000UL
1072#define PSYCHO_MEMSPACE_B 0x180000000UL
1073#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1074
1075static void psycho_pbm_init(struct pci_controller_info *p,
e87dc350 1076 struct device_node *dp, int is_pbm_a)
1da177e4 1077{
e87dc350 1078 struct property *prop;
1da177e4 1079 struct pci_pbm_info *pbm;
1da177e4 1080
0bba2dd8 1081 if (is_pbm_a)
1da177e4 1082 pbm = &p->pbm_A;
0bba2dd8 1083 else
1da177e4 1084 pbm = &p->pbm_B;
1da177e4 1085
34768bc8
DM		 1086 pbm->next = pci_pbm_root;
1087 pci_pbm_root = pbm;
1088
1089 pbm->scan_bus = psycho_scan_bus;
f1cd8de2 1090 pbm->pci_ops = &psycho_ops;
34768bc8 1091
1da177e4 1092 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
e87dc350
DM		 1093 pbm->chip_version = 0;
1094 prop = of_find_property(dp, "version#", NULL);
1095 if (prop)
1096 pbm->chip_version = *(int *) prop->value;
1097 pbm->chip_revision = 0;
1098 prop = of_find_property(dp, "module-revision#", NULL);
1099 if (prop)
1100 pbm->chip_revision = *(int *) prop->value;
1da177e4 1101
1da177e4 1102 pbm->parent = p;
e87dc350
DM		 1103 pbm->prom_node = dp;
1104 pbm->name = dp->full_name;
1105
1106 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1107 pbm->name,
1108 pbm->chip_version, pbm->chip_revision);
1109
0f3e2504
DM		 1110 pci_determine_mem_io_space(pbm);
1111
cfa0652c 1112 pci_get_pbm_props(pbm);
1da177e4
LT		 1113
1114 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1115}
1116
1117#define PSYCHO_CONFIGSPACE 0x001000000UL
1118
e87dc350 1119void psycho_init(struct device_node *dp, char *model_name)
1da177e4 1120{
e87dc350 1121 struct linux_prom64_registers *pr_regs;
1da177e4 1122 struct pci_controller_info *p;
34768bc8 1123 struct pci_pbm_info *pbm;
16ce82d8 1124 struct iommu *iommu;
e87dc350 1125 struct property *prop;
1da177e4 1126 u32 upa_portid;
e87dc350 1127 int is_pbm_a;
1da177e4 1128
e87dc350
DM		 1129 upa_portid = 0xff;
1130 prop = of_find_property(dp, "upa-portid", NULL);
1131 if (prop)
1132 upa_portid = *(u32 *) prop->value;
1da177e4 1133
34768bc8
DM		 1134 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1135 struct pci_controller_info *p = pbm->parent;
1136
1da177e4 1137 if (p->pbm_A.portid == upa_portid) {
e87dc350
DM		 1138 is_pbm_a = (p->pbm_A.prom_node == NULL);
1139 psycho_pbm_init(p, dp, is_pbm_a);
1da177e4
LT		 1140 return;
1141 }
1142 }
1143
9132983a 1144 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1da177e4
LT		 1145 if (!p) {
1146 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1147 prom_halt();
1148 }
16ce82d8 1149 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1da177e4
LT		 1150 if (!iommu) {
1151 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1152 prom_halt();
1153 }
1da177e4
LT		 1154 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1155
1da177e4
LT		 1156 p->pbm_A.portid = upa_portid;
1157 p->pbm_B.portid = upa_portid;
1158 p->index = pci_num_controllers++;
1da177e4 1159
e87dc350
DM		 1160 prop = of_find_property(dp, "reg", NULL);
1161 pr_regs = prop->value;
1da177e4
LT		 1162
1163 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1164 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1da177e4
LT		 1165
1166 p->pbm_A.config_space = p->pbm_B.config_space =
1167 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1da177e4
LT		 1168
1169 /*
1170 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1171 * we need to adjust our MEM space mask.
1172 */
1173 pci_memspace_mask = 0x7fffffffUL;
1174
1175 psycho_controller_hwinit(p);
1176
1177 psycho_iommu_init(p);
1178
1179 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
e87dc350 1180 psycho_pbm_init(p, dp, is_pbm_a);
1da177e4 1181}
Linux 6.x block layer and io_uring tree(s)