projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SPARC64]: Consolidate common PCI IOMMU init code.
[linux-2.6-block.git] / arch / sparc64 / kernel / pci_iommu.c
CommitLineData
1da177e4
LT		 1/* $Id: pci_iommu.c,v 1.17 2001/12/17 07:05:09 davem Exp $
2 * pci_iommu.c: UltraSparc PCI controller IOM/STC support.
3 *
4 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com)
6 */
7
8#include <linux/kernel.h>
9#include <linux/sched.h>
10#include <linux/mm.h>
4dbc30fb 11#include <linux/delay.h>
1da177e4
LT		 12
13#include <asm/pbm.h>
14
15#include "iommu_common.h"
16
17#define PCI_STC_CTXMATCH_ADDR(STC, CTX) \
18 ((STC)->strbuf_ctxmatch_base + ((CTX) << 3))
19
20/* Accessing IOMMU and Streaming Buffer registers.
21 * REG parameter is a physical address. All registers
22 * are 64-bits in size.
23 */
24#define pci_iommu_read(__reg) \
25({ u64 __ret; \
26 __asm__ __volatile__("ldxa [%1] %2, %0" \
27 : "=r" (__ret) \
28 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
29 : "memory"); \
30 __ret; \
31})
32#define pci_iommu_write(__reg, __val) \
33 __asm__ __volatile__("stxa %0, [%1] %2" \
34 : /* no outputs */ \
35 : "r" (__val), "r" (__reg), \
36 "i" (ASI_PHYS_BYPASS_EC_E))
37
38/* Must be invoked under the IOMMU lock. */
39static void __iommu_flushall(struct pci_iommu *iommu)
40{
41 unsigned long tag;
42 int entry;
43
44 tag = iommu->iommu_flush + (0xa580UL - 0x0210UL);
45 for (entry = 0; entry < 16; entry++) {
46 pci_iommu_write(tag, 0);
47 tag += 8;
48 }
49
50 /* Ensure completion of previous PIO writes. */
51 (void) pci_iommu_read(iommu->write_complete_reg);
52
53 /* Now update everyone's flush point. */
54 for (entry = 0; entry < PBM_NCLUSTERS; entry++) {
55 iommu->alloc_info[entry].flush =
56 iommu->alloc_info[entry].next;
57 }
58}
59
60#define IOPTE_CONSISTENT(CTX) \
61 (IOPTE_VALID | IOPTE_CACHE | \
62 (((CTX) << 47) & IOPTE_CONTEXT))
63
64#define IOPTE_STREAMING(CTX) \
65 (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF)
66
67/* Existing mappings are never marked invalid, instead they
68 * are pointed to a dummy page.
69 */
70#define IOPTE_IS_DUMMY(iommu, iopte) \
71 ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa)
72
73static void inline iopte_make_dummy(struct pci_iommu *iommu, iopte_t *iopte)
74{
75 unsigned long val = iopte_val(*iopte);
76
77 val &= ~IOPTE_PAGE;
78 val |= iommu->dummy_page_pa;
79
80 iopte_val(*iopte) = val;
81}
82
51e85136 83void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask)
1da177e4 84{
51e85136
DM		 85 unsigned long i, tsbbase, order;
86
87 /* Setup initial software IOMMU state. */
88 spin_lock_init(&iommu->lock);
89 iommu->ctx_lowest_free = 1;
90 iommu->page_table_map_base = dma_offset;
91 iommu->dma_addr_mask = dma_addr_mask;
92
93 switch (tsbsize / (8 * 1024)) {
94 case 64:
95 iommu->page_table_sz_bits = 16;
96 break;
97 case 128:
98 iommu->page_table_sz_bits = 17;
99 break;
100 default:
101 prom_printf("PCI_IOMMU: Illegal TSB size %d\n",
102 tsbsize / (8 * 1024));
103 prom_halt();
104 break;
105 };
106
107 iommu->lowest_consistent_map =
108 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
109
110 for (i = 0; i < PBM_NCLUSTERS; i++) {
111 iommu->alloc_info[i].flush = 0;
112 iommu->alloc_info[i].next = 0;
113 }
1da177e4 114
51e85136
DM		 115 /* Allocate and initialize the dummy page which we
116 * set inactive IO PTEs to point to.
117 */
118 iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
119 if (!iommu->dummy_page) {
120 prom_printf("PCI_IOMMU: Error, gfp(dummy_page) failed.\n");
121 prom_halt();
122 }
123 memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
124 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
125
126 /* Now allocate and setup the IOMMU page table itself. */
127 order = get_order(tsbsize);
128 tsbbase = __get_free_pages(GFP_KERNEL, order);
129 if (!tsbbase) {
130 prom_printf("PCI_IOMMU: Error, gfp(tsb) failed.\n");
131 prom_halt();
132 }
133 iommu->page_table = (iopte_t *)tsbbase;
1da177e4 134
51e85136 135 for (i = 0; i < tsbsize / sizeof(iopte_t); i++)
1da177e4
LT		 136 iopte_make_dummy(iommu, &iommu->page_table[i]);
137}
138
139static iopte_t *alloc_streaming_cluster(struct pci_iommu *iommu, unsigned long npages)
140{
141 iopte_t *iopte, *limit, *first;
142 unsigned long cnum, ent, flush_point;
143
144 cnum = 0;
145 while ((1UL << cnum) < npages)
146 cnum++;
147 iopte = (iommu->page_table +
148 (cnum << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
149
150 if (cnum == 0)
151 limit = (iommu->page_table +
152 iommu->lowest_consistent_map);
153 else
154 limit = (iopte +
155 (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
156
157 iopte += ((ent = iommu->alloc_info[cnum].next) << cnum);
158 flush_point = iommu->alloc_info[cnum].flush;
159
160 first = iopte;
161 for (;;) {
162 if (IOPTE_IS_DUMMY(iommu, iopte)) {
163 if ((iopte + (1 << cnum)) >= limit)
164 ent = 0;
165 else
166 ent = ent + 1;
167 iommu->alloc_info[cnum].next = ent;
168 if (ent == flush_point)
169 __iommu_flushall(iommu);
170 break;
171 }
172 iopte += (1 << cnum);
173 ent++;
174 if (iopte >= limit) {
175 iopte = (iommu->page_table +
176 (cnum <<
177 (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
178 ent = 0;
179 }
180 if (ent == flush_point)
181 __iommu_flushall(iommu);
182 if (iopte == first)
183 goto bad;
184 }
185
186 /* I've got your streaming cluster right here buddy boy... */
187 return iopte;
188
189bad:
190 printk(KERN_EMERG "pci_iommu: alloc_streaming_cluster of npages(%ld) failed!\n",
191 npages);
192 return NULL;
193}
194
195static void free_streaming_cluster(struct pci_iommu *iommu, dma_addr_t base,
196 unsigned long npages, unsigned long ctx)
197{
198 unsigned long cnum, ent;
199
200 cnum = 0;
201 while ((1UL << cnum) < npages)
202 cnum++;
203
204 ent = (base << (32 - IO_PAGE_SHIFT + PBM_LOGCLUSTERS - iommu->page_table_sz_bits))
205 >> (32 + PBM_LOGCLUSTERS + cnum - iommu->page_table_sz_bits);
206
207 /* If the global flush might not have caught this entry,
208 * adjust the flush point such that we will flush before
209 * ever trying to reuse it.
210 */
211#define between(X,Y,Z) (((Z) - (Y)) >= ((X) - (Y)))
212 if (between(ent, iommu->alloc_info[cnum].next, iommu->alloc_info[cnum].flush))
213 iommu->alloc_info[cnum].flush = ent;
214#undef between
215}
216
217/* We allocate consistent mappings from the end of cluster zero. */
218static iopte_t *alloc_consistent_cluster(struct pci_iommu *iommu, unsigned long npages)
219{
220 iopte_t *iopte;
221
222 iopte = iommu->page_table + (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS));
223 while (iopte > iommu->page_table) {
224 iopte--;
225 if (IOPTE_IS_DUMMY(iommu, iopte)) {
226 unsigned long tmp = npages;
227
228 while (--tmp) {
229 iopte--;
230 if (!IOPTE_IS_DUMMY(iommu, iopte))
231 break;
232 }
233 if (tmp == 0) {
234 u32 entry = (iopte - iommu->page_table);
235
236 if (entry < iommu->lowest_consistent_map)
237 iommu->lowest_consistent_map = entry;
238 return iopte;
239 }
240 }
241 }
242 return NULL;
243}
244
7c963ad1
DM		 245static int iommu_alloc_ctx(struct pci_iommu *iommu)
246{
247 int lowest = iommu->ctx_lowest_free;
248 int sz = IOMMU_NUM_CTXS - lowest;
249 int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest);
250
251 if (unlikely(n == sz)) {
252 n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1);
253 if (unlikely(n == lowest)) {
254 printk(KERN_WARNING "IOMMU: Ran out of contexts.\n");
255 n = 0;
256 }
257 }
258 if (n)
259 __set_bit(n, iommu->ctx_bitmap);
260
261 return n;
262}
263
264static inline void iommu_free_ctx(struct pci_iommu *iommu, int ctx)
265{
266 if (likely(ctx)) {
267 __clear_bit(ctx, iommu->ctx_bitmap);
268 if (ctx < iommu->ctx_lowest_free)
269 iommu->ctx_lowest_free = ctx;
270 }
271}
272
1da177e4
LT		 273/* Allocate and map kernel buffer of size SIZE using consistent mode
274 * DMA for PCI device PDEV. Return non-NULL cpu-side address if
275 * successful and set *DMA_ADDRP to the PCI side dma address.
276 */
277void *pci_alloc_consistent(struct pci_dev *pdev, size_t size, dma_addr_t *dma_addrp)
278{
279 struct pcidev_cookie *pcp;
280 struct pci_iommu *iommu;
281 iopte_t *iopte;
282 unsigned long flags, order, first_page, ctx;
283 void *ret;
284 int npages;
285
286 size = IO_PAGE_ALIGN(size);
287 order = get_order(size);
288 if (order >= 10)
289 return NULL;
290
291 first_page = __get_free_pages(GFP_ATOMIC, order);
292 if (first_page == 0UL)
293 return NULL;
294 memset((char *)first_page, 0, PAGE_SIZE << order);
295
296 pcp = pdev->sysdata;
297 iommu = pcp->pbm->iommu;
298
299 spin_lock_irqsave(&iommu->lock, flags);
300 iopte = alloc_consistent_cluster(iommu, size >> IO_PAGE_SHIFT);
301 if (iopte == NULL) {
302 spin_unlock_irqrestore(&iommu->lock, flags);
303 free_pages(first_page, order);
304 return NULL;
305 }
306
307 *dma_addrp = (iommu->page_table_map_base +
308 ((iopte - iommu->page_table) << IO_PAGE_SHIFT));
309 ret = (void *) first_page;
310 npages = size >> IO_PAGE_SHIFT;
311 ctx = 0;
312 if (iommu->iommu_ctxflush)
7c963ad1 313 ctx = iommu_alloc_ctx(iommu);
1da177e4
LT		 314 first_page = __pa(first_page);
315 while (npages--) {
316 iopte_val(*iopte) = (IOPTE_CONSISTENT(ctx) |
317 IOPTE_WRITE |
318 (first_page & IOPTE_PAGE));
319 iopte++;
320 first_page += IO_PAGE_SIZE;
321 }
322
323 {
324 int i;
325 u32 daddr = *dma_addrp;
326
327 npages = size >> IO_PAGE_SHIFT;
328 for (i = 0; i < npages; i++) {
329 pci_iommu_write(iommu->iommu_flush, daddr);
330 daddr += IO_PAGE_SIZE;
331 }
332 }
333
334 spin_unlock_irqrestore(&iommu->lock, flags);
335
336 return ret;
337}
338
339/* Free and unmap a consistent DMA translation. */
340void pci_free_consistent(struct pci_dev *pdev, size_t size, void *cpu, dma_addr_t dvma)
341{
342 struct pcidev_cookie *pcp;
343 struct pci_iommu *iommu;
344 iopte_t *iopte;
345 unsigned long flags, order, npages, i, ctx;
346
347 npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT;
348 pcp = pdev->sysdata;
349 iommu = pcp->pbm->iommu;
350 iopte = iommu->page_table +
351 ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
352
353 spin_lock_irqsave(&iommu->lock, flags);
354
355 if ((iopte - iommu->page_table) ==
356 iommu->lowest_consistent_map) {
357 iopte_t *walk = iopte + npages;
358 iopte_t *limit;
359
360 limit = (iommu->page_table +
361 (1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS)));
362 while (walk < limit) {
363 if (!IOPTE_IS_DUMMY(iommu, walk))
364 break;
365 walk++;
366 }
367 iommu->lowest_consistent_map =
368 (walk - iommu->page_table);
369 }
370
371 /* Data for consistent mappings cannot enter the streaming
372 * buffers, so we only need to update the TSB. We flush
373 * the IOMMU here as well to prevent conflicts with the
374 * streaming mapping deferred tlb flush scheme.
375 */
376
377 ctx = 0;
378 if (iommu->iommu_ctxflush)
379 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
380
381 for (i = 0; i < npages; i++, iopte++)
382 iopte_make_dummy(iommu, iopte);
383
384 if (iommu->iommu_ctxflush) {
385 pci_iommu_write(iommu->iommu_ctxflush, ctx);
386 } else {
387 for (i = 0; i < npages; i++) {
388 u32 daddr = dvma + (i << IO_PAGE_SHIFT);
389
390 pci_iommu_write(iommu->iommu_flush, daddr);
391 }
392 }
393
7c963ad1
DM		 394 iommu_free_ctx(iommu, ctx);
395
1da177e4
LT		 396 spin_unlock_irqrestore(&iommu->lock, flags);
397
398 order = get_order(size);
399 if (order < 10)
400 free_pages((unsigned long)cpu, order);
401}
402
403/* Map a single buffer at PTR of SZ bytes for PCI DMA
404 * in streaming mode.
405 */
406dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr, size_t sz, int direction)
407{
408 struct pcidev_cookie *pcp;
409 struct pci_iommu *iommu;
410 struct pci_strbuf *strbuf;
411 iopte_t *base;
412 unsigned long flags, npages, oaddr;
413 unsigned long i, base_paddr, ctx;
414 u32 bus_addr, ret;
415 unsigned long iopte_protection;
416
417 pcp = pdev->sysdata;
418 iommu = pcp->pbm->iommu;
419 strbuf = &pcp->pbm->stc;
420
421 if (direction == PCI_DMA_NONE)
422 BUG();
423
424 oaddr = (unsigned long)ptr;
425 npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK);
426 npages >>= IO_PAGE_SHIFT;
427
428 spin_lock_irqsave(&iommu->lock, flags);
429
430 base = alloc_streaming_cluster(iommu, npages);
431 if (base == NULL)
432 goto bad;
433 bus_addr = (iommu->page_table_map_base +
434 ((base - iommu->page_table) << IO_PAGE_SHIFT));
435 ret = bus_addr | (oaddr & ~IO_PAGE_MASK);
436 base_paddr = __pa(oaddr & IO_PAGE_MASK);
437 ctx = 0;
438 if (iommu->iommu_ctxflush)
7c963ad1 439 ctx = iommu_alloc_ctx(iommu);
1da177e4
LT		 440 if (strbuf->strbuf_enabled)
441 iopte_protection = IOPTE_STREAMING(ctx);
442 else
443 iopte_protection = IOPTE_CONSISTENT(ctx);
444 if (direction != PCI_DMA_TODEVICE)
445 iopte_protection |= IOPTE_WRITE;
446
447 for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE)
448 iopte_val(*base) = iopte_protection | base_paddr;
449
450 spin_unlock_irqrestore(&iommu->lock, flags);
451
452 return ret;
453
454bad:
455 spin_unlock_irqrestore(&iommu->lock, flags);
456 return PCI_DMA_ERROR_CODE;
457}
458
7c963ad1 459static void pci_strbuf_flush(struct pci_strbuf *strbuf, struct pci_iommu *iommu, u32 vaddr, unsigned long ctx, unsigned long npages, int direction)
4dbc30fb
DM		 460{
461 int limit;
462
4dbc30fb
DM		 463 if (strbuf->strbuf_ctxflush &&
464 iommu->iommu_ctxflush) {
465 unsigned long matchreg, flushreg;
7c963ad1 466 u64 val;
4dbc30fb
DM		 467
468 flushreg = strbuf->strbuf_ctxflush;
469 matchreg = PCI_STC_CTXMATCH_ADDR(strbuf, ctx);
470
a228dfd5 471 pci_iommu_write(flushreg, ctx);
88314ee7
DM		 472 val = pci_iommu_read(matchreg);
473 val &= 0xffff;
474 if (!val)
7c963ad1
DM		 475 goto do_flush_sync;
476
7c963ad1
DM		 477 while (val) {
478 if (val & 0x1)
479 pci_iommu_write(flushreg, ctx);
480 val >>= 1;
a228dfd5 481 }
7c963ad1
DM		 482 val = pci_iommu_read(matchreg);
483 if (unlikely(val)) {
4dbc30fb 484 printk(KERN_WARNING "pci_strbuf_flush: ctx flush "
7c963ad1
DM		 485 "timeout matchreg[%lx] ctx[%lx]\n",
486 val, ctx);
487 goto do_page_flush;
488 }
4dbc30fb
DM		 489 } else {
490 unsigned long i;
491
7c963ad1 492 do_page_flush:
4dbc30fb
DM		 493 for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE)
494 pci_iommu_write(strbuf->strbuf_pflush, vaddr);
495 }
496
7c963ad1
DM		 497do_flush_sync:
498 /* If the device could not have possibly put dirty data into
499 * the streaming cache, no flush-flag synchronization needs
500 * to be performed.
501 */
502 if (direction == PCI_DMA_TODEVICE)
503 return;
504
505 PCI_STC_FLUSHFLAG_INIT(strbuf);
4dbc30fb
DM		 506 pci_iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa);
507 (void) pci_iommu_read(iommu->write_complete_reg);
508
a228dfd5 509 limit = 100000;
4dbc30fb
DM		 510 while (!PCI_STC_FLUSHFLAG_SET(strbuf)) {
511 limit--;
512 if (!limit)
513 break;
a228dfd5 514 udelay(1);
4f07118f 515 rmb();
4dbc30fb
DM		 516 }
517 if (!limit)
518 printk(KERN_WARNING "pci_strbuf_flush: flushflag timeout "
519 "vaddr[%08x] ctx[%lx] npages[%ld]\n",
520 vaddr, ctx, npages);
521}
522
1da177e4
LT		 523/* Unmap a single streaming mode DMA translation. */
524void pci_unmap_single(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
525{
526 struct pcidev_cookie *pcp;
527 struct pci_iommu *iommu;
528 struct pci_strbuf *strbuf;
529 iopte_t *base;
4dbc30fb 530 unsigned long flags, npages, ctx;
1da177e4
LT		 531
532 if (direction == PCI_DMA_NONE)
533 BUG();
534
535 pcp = pdev->sysdata;
536 iommu = pcp->pbm->iommu;
537 strbuf = &pcp->pbm->stc;
538
539 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
540 npages >>= IO_PAGE_SHIFT;
541 base = iommu->page_table +
542 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
543#ifdef DEBUG_PCI_IOMMU
544 if (IOPTE_IS_DUMMY(iommu, base))
545 printk("pci_unmap_single called on non-mapped region %08x,%08x from %016lx\n",
546 bus_addr, sz, __builtin_return_address(0));
547#endif
548 bus_addr &= IO_PAGE_MASK;
549
550 spin_lock_irqsave(&iommu->lock, flags);
551
552 /* Record the context, if any. */
553 ctx = 0;
554 if (iommu->iommu_ctxflush)
555 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
556
557 /* Step 1: Kick data out of streaming buffers if necessary. */
4dbc30fb 558 if (strbuf->strbuf_enabled)
7c963ad1 559 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
1da177e4
LT		 560
561 /* Step 2: Clear out first TSB entry. */
562 iopte_make_dummy(iommu, base);
563
564 free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
565 npages, ctx);
566
7c963ad1
DM		 567 iommu_free_ctx(iommu, ctx);
568
1da177e4
LT		 569 spin_unlock_irqrestore(&iommu->lock, flags);
570}
571
572#define SG_ENT_PHYS_ADDRESS(SG) \
573 (__pa(page_address((SG)->page)) + (SG)->offset)
574
575static inline void fill_sg(iopte_t *iopte, struct scatterlist *sg,
576 int nused, int nelems, unsigned long iopte_protection)
577{
578 struct scatterlist *dma_sg = sg;
579 struct scatterlist *sg_end = sg + nelems;
580 int i;
581
582 for (i = 0; i < nused; i++) {
583 unsigned long pteval = ~0UL;
584 u32 dma_npages;
585
586 dma_npages = ((dma_sg->dma_address & (IO_PAGE_SIZE - 1UL)) +
587 dma_sg->dma_length +
588 ((IO_PAGE_SIZE - 1UL))) >> IO_PAGE_SHIFT;
589 do {
590 unsigned long offset;
591 signed int len;
592
593 /* If we are here, we know we have at least one
594 * more page to map. So walk forward until we
595 * hit a page crossing, and begin creating new
596 * mappings from that spot.
597 */
598 for (;;) {
599 unsigned long tmp;
600
601 tmp = SG_ENT_PHYS_ADDRESS(sg);
602 len = sg->length;
603 if (((tmp ^ pteval) >> IO_PAGE_SHIFT) != 0UL) {
604 pteval = tmp & IO_PAGE_MASK;
605 offset = tmp & (IO_PAGE_SIZE - 1UL);
606 break;
607 }
608 if (((tmp ^ (tmp + len - 1UL)) >> IO_PAGE_SHIFT) != 0UL) {
609 pteval = (tmp + IO_PAGE_SIZE) & IO_PAGE_MASK;
610 offset = 0UL;
611 len -= (IO_PAGE_SIZE - (tmp & (IO_PAGE_SIZE - 1UL)));
612 break;
613 }
614 sg++;
615 }
616
617 pteval = iopte_protection | (pteval & IOPTE_PAGE);
618 while (len > 0) {
619 *iopte++ = __iopte(pteval);
620 pteval += IO_PAGE_SIZE;
621 len -= (IO_PAGE_SIZE - offset);
622 offset = 0;
623 dma_npages--;
624 }
625
626 pteval = (pteval & IOPTE_PAGE) + len;
627 sg++;
628
629 /* Skip over any tail mappings we've fully mapped,
630 * adjusting pteval along the way. Stop when we
631 * detect a page crossing event.
632 */
633 while (sg < sg_end &&
634 (pteval << (64 - IO_PAGE_SHIFT)) != 0UL &&
635 (pteval == SG_ENT_PHYS_ADDRESS(sg)) &&
636 ((pteval ^
637 (SG_ENT_PHYS_ADDRESS(sg) + sg->length - 1UL)) >> IO_PAGE_SHIFT) == 0UL) {
638 pteval += sg->length;
639 sg++;
640 }
641 if ((pteval << (64 - IO_PAGE_SHIFT)) == 0UL)
642 pteval = ~0UL;
643 } while (dma_npages != 0);
644 dma_sg++;
645 }
646}
647
648/* Map a set of buffers described by SGLIST with NELEMS array
649 * elements in streaming mode for PCI DMA.
650 * When making changes here, inspect the assembly output. I was having
651 * hard time to kepp this routine out of using stack slots for holding variables.
652 */
653int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
654{
655 struct pcidev_cookie *pcp;
656 struct pci_iommu *iommu;
657 struct pci_strbuf *strbuf;
658 unsigned long flags, ctx, npages, iopte_protection;
659 iopte_t *base;
660 u32 dma_base;
661 struct scatterlist *sgtmp;
662 int used;
663
664 /* Fast path single entry scatterlists. */
665 if (nelems == 1) {
666 sglist->dma_address =
667 pci_map_single(pdev,
668 (page_address(sglist->page) + sglist->offset),
669 sglist->length, direction);
670 sglist->dma_length = sglist->length;
671 return 1;
672 }
673
674 pcp = pdev->sysdata;
675 iommu = pcp->pbm->iommu;
676 strbuf = &pcp->pbm->stc;
677
678 if (direction == PCI_DMA_NONE)
679 BUG();
680
681 /* Step 1: Prepare scatter list. */
682
683 npages = prepare_sg(sglist, nelems);
684
685 /* Step 2: Allocate a cluster. */
686
687 spin_lock_irqsave(&iommu->lock, flags);
688
689 base = alloc_streaming_cluster(iommu, npages);
690 if (base == NULL)
691 goto bad;
692 dma_base = iommu->page_table_map_base + ((base - iommu->page_table) << IO_PAGE_SHIFT);
693
694 /* Step 3: Normalize DMA addresses. */
695 used = nelems;
696
697 sgtmp = sglist;
698 while (used && sgtmp->dma_length) {
699 sgtmp->dma_address += dma_base;
700 sgtmp++;
701 used--;
702 }
703 used = nelems - used;
704
705 /* Step 4: Choose a context if necessary. */
706 ctx = 0;
707 if (iommu->iommu_ctxflush)
7c963ad1 708 ctx = iommu_alloc_ctx(iommu);
1da177e4
LT		 709
710 /* Step 5: Create the mappings. */
711 if (strbuf->strbuf_enabled)
712 iopte_protection = IOPTE_STREAMING(ctx);
713 else
714 iopte_protection = IOPTE_CONSISTENT(ctx);
715 if (direction != PCI_DMA_TODEVICE)
716 iopte_protection |= IOPTE_WRITE;
717 fill_sg (base, sglist, used, nelems, iopte_protection);
718#ifdef VERIFY_SG
719 verify_sglist(sglist, nelems, base, npages);
720#endif
721
722 spin_unlock_irqrestore(&iommu->lock, flags);
723
724 return used;
725
726bad:
727 spin_unlock_irqrestore(&iommu->lock, flags);
728 return PCI_DMA_ERROR_CODE;
729}
730
731/* Unmap a set of streaming mode DMA translations. */
732void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
733{
734 struct pcidev_cookie *pcp;
735 struct pci_iommu *iommu;
736 struct pci_strbuf *strbuf;
737 iopte_t *base;
738 unsigned long flags, ctx, i, npages;
739 u32 bus_addr;
740
741 if (direction == PCI_DMA_NONE)
742 BUG();
743
744 pcp = pdev->sysdata;
745 iommu = pcp->pbm->iommu;
746 strbuf = &pcp->pbm->stc;
747
748 bus_addr = sglist->dma_address & IO_PAGE_MASK;
749
750 for (i = 1; i < nelems; i++)
751 if (sglist[i].dma_length == 0)
752 break;
753 i--;
754 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length) - bus_addr) >> IO_PAGE_SHIFT;
755
756 base = iommu->page_table +
757 ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
758
759#ifdef DEBUG_PCI_IOMMU
760 if (IOPTE_IS_DUMMY(iommu, base))
761 printk("pci_unmap_sg called on non-mapped region %016lx,%d from %016lx\n", sglist->dma_address, nelems, __builtin_return_address(0));
762#endif
763
764 spin_lock_irqsave(&iommu->lock, flags);
765
766 /* Record the context, if any. */
767 ctx = 0;
768 if (iommu->iommu_ctxflush)
769 ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL;
770
771 /* Step 1: Kick data out of streaming buffers if necessary. */
4dbc30fb 772 if (strbuf->strbuf_enabled)
7c963ad1 773 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
1da177e4
LT		 774
775 /* Step 2: Clear out first TSB entry. */
776 iopte_make_dummy(iommu, base);
777
778 free_streaming_cluster(iommu, bus_addr - iommu->page_table_map_base,
779 npages, ctx);
780
7c963ad1
DM		 781 iommu_free_ctx(iommu, ctx);
782
1da177e4
LT		 783 spin_unlock_irqrestore(&iommu->lock, flags);
784}
785
786/* Make physical memory consistent for a single
787 * streaming mode DMA translation after a transfer.
788 */
789void pci_dma_sync_single_for_cpu(struct pci_dev *pdev, dma_addr_t bus_addr, size_t sz, int direction)
790{
791 struct pcidev_cookie *pcp;
792 struct pci_iommu *iommu;
793 struct pci_strbuf *strbuf;
794 unsigned long flags, ctx, npages;
795
796 pcp = pdev->sysdata;
797 iommu = pcp->pbm->iommu;
798 strbuf = &pcp->pbm->stc;
799
800 if (!strbuf->strbuf_enabled)
801 return;
802
803 spin_lock_irqsave(&iommu->lock, flags);
804
805 npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK);
806 npages >>= IO_PAGE_SHIFT;
807 bus_addr &= IO_PAGE_MASK;
808
809 /* Step 1: Record the context, if any. */
810 ctx = 0;
811 if (iommu->iommu_ctxflush &&
812 strbuf->strbuf_ctxflush) {
813 iopte_t *iopte;
814
815 iopte = iommu->page_table +
816 ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT);
817 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
818 }
819
820 /* Step 2: Kick data out of streaming buffers. */
7c963ad1 821 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
1da177e4
LT		 822
823 spin_unlock_irqrestore(&iommu->lock, flags);
824}
825
826/* Make physical memory consistent for a set of streaming
827 * mode DMA translations after a transfer.
828 */
829void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev, struct scatterlist *sglist, int nelems, int direction)
830{
831 struct pcidev_cookie *pcp;
832 struct pci_iommu *iommu;
833 struct pci_strbuf *strbuf;
4dbc30fb
DM		 834 unsigned long flags, ctx, npages, i;
835 u32 bus_addr;
1da177e4
LT		 836
837 pcp = pdev->sysdata;
838 iommu = pcp->pbm->iommu;
839 strbuf = &pcp->pbm->stc;
840
841 if (!strbuf->strbuf_enabled)
842 return;
843
844 spin_lock_irqsave(&iommu->lock, flags);
845
846 /* Step 1: Record the context, if any. */
847 ctx = 0;
848 if (iommu->iommu_ctxflush &&
849 strbuf->strbuf_ctxflush) {
850 iopte_t *iopte;
851
852 iopte = iommu->page_table +
853 ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT);
854 ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL;
855 }
856
857 /* Step 2: Kick data out of streaming buffers. */
4dbc30fb
DM		 858 bus_addr = sglist[0].dma_address & IO_PAGE_MASK;
859 for(i = 1; i < nelems; i++)
860 if (!sglist[i].dma_length)
861 break;
862 i--;
863 npages = (IO_PAGE_ALIGN(sglist[i].dma_address + sglist[i].dma_length)
864 - bus_addr) >> IO_PAGE_SHIFT;
7c963ad1 865 pci_strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction);
1da177e4
LT		 866
867 spin_unlock_irqrestore(&iommu->lock, flags);
868}
869
870static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
871{
872 struct pci_dev *ali_isa_bridge;
873 u8 val;
874
875 /* ALI sound chips generate 31-bits of DMA, a special register
876 * determines what bit 31 is emitted as.
877 */
878 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
879 PCI_DEVICE_ID_AL_M1533,
880 NULL);
881
882 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
883 if (set_bit)
884 val |= 0x01;
885 else
886 val &= ~0x01;
887 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
888 pci_dev_put(ali_isa_bridge);
889}
890
891int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
892{
893 struct pcidev_cookie *pcp = pdev->sysdata;
894 u64 dma_addr_mask;
895
896 if (pdev == NULL) {
897 dma_addr_mask = 0xffffffff;
898 } else {
899 struct pci_iommu *iommu = pcp->pbm->iommu;
900
901 dma_addr_mask = iommu->dma_addr_mask;
902
903 if (pdev->vendor == PCI_VENDOR_ID_AL &&
904 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
905 device_mask == 0x7fffffff) {
906 ali_sound_dma_hack(pdev,
907 (dma_addr_mask & 0x80000000) != 0);
908 return 1;
909 }
910 }
911
912 if (device_mask >= (1UL << 32UL))
913 return 0;
914
915 return (device_mask & dma_addr_mask) == dma_addr_mask;
916}
Linux 6.x block layer and io_uring tree(s)