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9fd8b647 | 1 | /* pci_impl.h: Helper definitions for PCI controller support. |
1da177e4 | 2 | * |
9fd8b647 | 3 | * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | */ |
5 | ||
6 | #ifndef PCI_IMPL_H | |
7 | #define PCI_IMPL_H | |
8 | ||
9 | #include <linux/types.h> | |
10 | #include <linux/spinlock.h> | |
c57c2ffb DM |
11 | #include <linux/pci.h> |
12 | #include <linux/msi.h> | |
1da177e4 | 13 | #include <asm/io.h> |
de8d28b1 | 14 | #include <asm/prom.h> |
c57c2ffb DM |
15 | #include <asm/iommu.h> |
16 | ||
17 | /* The abstraction used here is that there are PCI controllers, | |
18 | * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules | |
19 | * underneath. Each PCI bus module uses an IOMMU (shared by both | |
20 | * PBMs of a controller, or per-PBM), and if a streaming buffer | |
21 | * is present, each PCI bus module has it's own. (ie. the IOMMU | |
22 | * might be shared between PBMs, the STC is never shared) | |
23 | * Furthermore, each PCI bus module controls it's own autonomous | |
24 | * PCI bus. | |
25 | */ | |
26 | ||
27 | #define PCI_STC_FLUSHFLAG_INIT(STC) \ | |
28 | (*((STC)->strbuf_flushflag) = 0UL) | |
29 | #define PCI_STC_FLUSHFLAG_SET(STC) \ | |
30 | (*((STC)->strbuf_flushflag) != 0UL) | |
31 | ||
32 | struct pci_controller_info; | |
33 | ||
34 | struct pci_pbm_info { | |
35 | struct pci_pbm_info *next; | |
36 | int index; | |
37 | ||
38 | /* PCI controller we sit under. */ | |
39 | struct pci_controller_info *parent; | |
40 | ||
41 | /* Physical address base of controller registers. */ | |
42 | unsigned long controller_regs; | |
43 | ||
44 | /* Physical address base of PBM registers. */ | |
45 | unsigned long pbm_regs; | |
46 | ||
47 | /* Physical address of DMA sync register, if any. */ | |
48 | unsigned long sync_reg; | |
49 | ||
50 | /* Opaque 32-bit system bus Port ID. */ | |
51 | u32 portid; | |
52 | ||
53 | /* Opaque 32-bit handle used for hypervisor calls. */ | |
54 | u32 devhandle; | |
55 | ||
56 | /* Chipset version information. */ | |
57 | int chip_type; | |
58 | #define PBM_CHIP_TYPE_SABRE 1 | |
59 | #define PBM_CHIP_TYPE_PSYCHO 2 | |
60 | #define PBM_CHIP_TYPE_SCHIZO 3 | |
61 | #define PBM_CHIP_TYPE_SCHIZO_PLUS 4 | |
62 | #define PBM_CHIP_TYPE_TOMATILLO 5 | |
63 | int chip_version; | |
64 | int chip_revision; | |
65 | ||
66 | /* Name used for top-level resources. */ | |
67 | char *name; | |
68 | ||
69 | /* OBP specific information. */ | |
70 | struct device_node *prom_node; | |
71 | u64 ino_bitmap; | |
72 | ||
73 | /* PBM I/O and Memory space resources. */ | |
74 | struct resource io_space; | |
75 | struct resource mem_space; | |
76 | ||
77 | /* Base of PCI Config space, can be per-PBM or shared. */ | |
78 | unsigned long config_space; | |
79 | ||
80 | /* State of 66MHz capabilities on this PBM. */ | |
81 | int is_66mhz_capable; | |
82 | int all_devs_66mhz; | |
83 | ||
84 | #ifdef CONFIG_PCI_MSI | |
85 | /* MSI info. */ | |
86 | u32 msiq_num; | |
87 | u32 msiq_ent_count; | |
88 | u32 msiq_first; | |
89 | u32 msiq_first_devino; | |
90 | u32 msi_num; | |
91 | u32 msi_first; | |
92 | u32 msi_data_mask; | |
93 | u32 msix_data_width; | |
94 | u64 msi32_start; | |
95 | u64 msi64_start; | |
96 | u32 msi32_len; | |
97 | u32 msi64_len; | |
98 | void *msi_queues; | |
99 | unsigned long *msi_bitmap; | |
100 | int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev, | |
101 | struct msi_desc *entry); | |
102 | void (*teardown_msi_irq)(unsigned int virt_irq, struct pci_dev *pdev); | |
103 | #endif /* !(CONFIG_PCI_MSI) */ | |
104 | ||
105 | /* This PBM's streaming buffer. */ | |
106 | struct strbuf stc; | |
107 | ||
108 | /* IOMMU state, potentially shared by both PBM segments. */ | |
109 | struct iommu *iommu; | |
110 | ||
111 | /* Now things for the actual PCI bus probes. */ | |
112 | unsigned int pci_first_busno; | |
113 | unsigned int pci_last_busno; | |
114 | struct pci_bus *pci_bus; | |
115 | void (*scan_bus)(struct pci_pbm_info *); | |
116 | struct pci_ops *pci_ops; | |
117 | }; | |
118 | ||
119 | struct pci_controller_info { | |
120 | /* The PCI bus modules controlled by us. */ | |
121 | struct pci_pbm_info pbm_A; | |
122 | struct pci_pbm_info pbm_B; | |
123 | }; | |
1da177e4 | 124 | |
34768bc8 | 125 | extern struct pci_pbm_info *pci_pbm_root; |
1e8a8cc5 | 126 | extern unsigned long pci_memspace_mask; |
1da177e4 | 127 | |
6c108f12 | 128 | extern int pci_num_pbms; |
1da177e4 LT |
129 | |
130 | /* PCI bus scanning and fixup support. */ | |
c57c2ffb DM |
131 | extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, |
132 | u32 dma_offset, u32 dma_addr_mask); | |
cfa0652c | 133 | extern void pci_get_pbm_props(struct pci_pbm_info *pbm); |
a2fb23af | 134 | extern struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm); |
9fd8b647 | 135 | extern void pci_determine_mem_io_space(struct pci_pbm_info *pbm); |
1da177e4 | 136 | |
97b3cf05 DM |
137 | extern int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev, |
138 | unsigned int devfn, | |
139 | int where, int size, | |
140 | u32 *value); | |
141 | extern int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev, | |
142 | unsigned int devfn, | |
143 | int where, int size, | |
144 | u32 value); | |
145 | ||
1da177e4 | 146 | /* Error reporting support. */ |
6c108f12 DM |
147 | extern void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *); |
148 | extern void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *); | |
149 | extern void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *); | |
1da177e4 LT |
150 | |
151 | /* Configuration space access. */ | |
152 | extern void pci_config_read8(u8 *addr, u8 *ret); | |
153 | extern void pci_config_read16(u16 *addr, u16 *ret); | |
154 | extern void pci_config_read32(u32 *addr, u32 *ret); | |
155 | extern void pci_config_write8(u8 *addr, u8 val); | |
156 | extern void pci_config_write16(u16 *addr, u16 val); | |
157 | extern void pci_config_write32(u32 *addr, u32 val); | |
158 | ||
159 | #endif /* !(PCI_IMPL_H) */ |