Commit | Line | Data |
---|---|---|
9fd8b647 | 1 | /* pci_common.c: PCI controller common support. |
1da177e4 | 2 | * |
9fd8b647 | 3 | * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | */ |
5 | ||
6 | #include <linux/string.h> | |
7 | #include <linux/slab.h> | |
8 | #include <linux/init.h> | |
cf69eab2 FMDN |
9 | #include <linux/pci.h> |
10 | #include <linux/device.h> | |
1da177e4 | 11 | |
de8d28b1 | 12 | #include <asm/prom.h> |
2b1e5978 | 13 | #include <asm/of_device.h> |
c57c2ffb | 14 | #include <asm/oplib.h> |
de8d28b1 DM |
15 | |
16 | #include "pci_impl.h" | |
ca3dd88e DM |
17 | #include "pci_sun4v.h" |
18 | ||
19 | static int config_out_of_range(struct pci_pbm_info *pbm, | |
20 | unsigned long bus, | |
21 | unsigned long devfn, | |
22 | unsigned long reg) | |
23 | { | |
24 | if (bus < pbm->pci_first_busno || | |
25 | bus > pbm->pci_last_busno) | |
26 | return 1; | |
27 | return 0; | |
28 | } | |
29 | ||
30 | static void *sun4u_config_mkaddr(struct pci_pbm_info *pbm, | |
31 | unsigned long bus, | |
32 | unsigned long devfn, | |
33 | unsigned long reg) | |
34 | { | |
35 | unsigned long rbits = pbm->config_space_reg_bits; | |
36 | ||
37 | if (config_out_of_range(pbm, bus, devfn, reg)) | |
38 | return NULL; | |
39 | ||
40 | reg = (reg & ((1 << rbits) - 1)); | |
41 | devfn <<= rbits; | |
42 | bus <<= rbits + 8; | |
43 | ||
44 | return (void *) (pbm->config_space | bus | devfn | reg); | |
45 | } | |
46 | ||
a2d6ea01 DM |
47 | /* At least on Sabre, it is necessary to access all PCI host controller |
48 | * registers at their natural size, otherwise zeros are returned. | |
49 | * Strange but true, and I see no language in the UltraSPARC-IIi | |
50 | * programmer's manual that mentions this even indirectly. | |
51 | */ | |
52 | static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm, | |
53 | unsigned char bus, unsigned int devfn, | |
54 | int where, int size, u32 *value) | |
55 | { | |
56 | u32 tmp32, *addr; | |
57 | u16 tmp16; | |
58 | u8 tmp8; | |
59 | ||
60 | addr = sun4u_config_mkaddr(pbm, bus, devfn, where); | |
61 | if (!addr) | |
62 | return PCIBIOS_SUCCESSFUL; | |
63 | ||
64 | switch (size) { | |
65 | case 1: | |
66 | if (where < 8) { | |
67 | unsigned long align = (unsigned long) addr; | |
68 | ||
69 | align &= ~1; | |
70 | pci_config_read16((u16 *)align, &tmp16); | |
71 | if (where & 1) | |
72 | *value = tmp16 >> 8; | |
73 | else | |
74 | *value = tmp16 & 0xff; | |
75 | } else { | |
76 | pci_config_read8((u8 *)addr, &tmp8); | |
77 | *value = (u32) tmp8; | |
78 | } | |
79 | break; | |
80 | ||
81 | case 2: | |
82 | if (where < 8) { | |
83 | pci_config_read16((u16 *)addr, &tmp16); | |
84 | *value = (u32) tmp16; | |
85 | } else { | |
86 | pci_config_read8((u8 *)addr, &tmp8); | |
87 | *value = (u32) tmp8; | |
88 | pci_config_read8(((u8 *)addr) + 1, &tmp8); | |
89 | *value |= ((u32) tmp8) << 8; | |
90 | } | |
91 | break; | |
92 | ||
93 | case 4: | |
94 | tmp32 = 0xffffffff; | |
95 | sun4u_read_pci_cfg_host(pbm, bus, devfn, | |
96 | where, 2, &tmp32); | |
97 | *value = tmp32; | |
98 | ||
99 | tmp32 = 0xffffffff; | |
100 | sun4u_read_pci_cfg_host(pbm, bus, devfn, | |
101 | where + 2, 2, &tmp32); | |
102 | *value |= tmp32 << 16; | |
103 | break; | |
104 | } | |
105 | return PCIBIOS_SUCCESSFUL; | |
106 | } | |
107 | ||
ca3dd88e DM |
108 | static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
109 | int where, int size, u32 *value) | |
110 | { | |
111 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
112 | unsigned char bus = bus_dev->number; | |
113 | u32 *addr; | |
114 | u16 tmp16; | |
115 | u8 tmp8; | |
116 | ||
ca3dd88e DM |
117 | switch (size) { |
118 | case 1: | |
119 | *value = 0xff; | |
120 | break; | |
121 | case 2: | |
122 | *value = 0xffff; | |
123 | break; | |
124 | case 4: | |
125 | *value = 0xffffffff; | |
126 | break; | |
127 | } | |
128 | ||
a2d6ea01 DM |
129 | if (!bus_dev->number && !PCI_SLOT(devfn)) |
130 | return sun4u_read_pci_cfg_host(pbm, bus, devfn, where, | |
131 | size, value); | |
132 | ||
ca3dd88e DM |
133 | addr = sun4u_config_mkaddr(pbm, bus, devfn, where); |
134 | if (!addr) | |
135 | return PCIBIOS_SUCCESSFUL; | |
136 | ||
137 | switch (size) { | |
138 | case 1: | |
139 | pci_config_read8((u8 *)addr, &tmp8); | |
140 | *value = (u32) tmp8; | |
141 | break; | |
142 | ||
143 | case 2: | |
144 | if (where & 0x01) { | |
145 | printk("pci_read_config_word: misaligned reg [%x]\n", | |
146 | where); | |
147 | return PCIBIOS_SUCCESSFUL; | |
148 | } | |
149 | pci_config_read16((u16 *)addr, &tmp16); | |
150 | *value = (u32) tmp16; | |
151 | break; | |
152 | ||
153 | case 4: | |
154 | if (where & 0x03) { | |
155 | printk("pci_read_config_dword: misaligned reg [%x]\n", | |
156 | where); | |
157 | return PCIBIOS_SUCCESSFUL; | |
158 | } | |
159 | pci_config_read32(addr, value); | |
160 | break; | |
161 | } | |
162 | return PCIBIOS_SUCCESSFUL; | |
163 | } | |
164 | ||
a2d6ea01 DM |
165 | static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm, |
166 | unsigned char bus, unsigned int devfn, | |
167 | int where, int size, u32 value) | |
168 | { | |
169 | u32 *addr; | |
170 | ||
171 | addr = sun4u_config_mkaddr(pbm, bus, devfn, where); | |
172 | if (!addr) | |
173 | return PCIBIOS_SUCCESSFUL; | |
174 | ||
175 | switch (size) { | |
176 | case 1: | |
177 | if (where < 8) { | |
178 | unsigned long align = (unsigned long) addr; | |
179 | u16 tmp16; | |
180 | ||
181 | align &= ~1; | |
182 | pci_config_read16((u16 *)align, &tmp16); | |
183 | if (where & 1) { | |
184 | tmp16 &= 0x00ff; | |
185 | tmp16 |= value << 8; | |
186 | } else { | |
187 | tmp16 &= 0xff00; | |
188 | tmp16 |= value; | |
189 | } | |
190 | pci_config_write16((u16 *)align, tmp16); | |
191 | } else | |
192 | pci_config_write8((u8 *)addr, value); | |
193 | break; | |
194 | case 2: | |
195 | if (where < 8) { | |
196 | pci_config_write16((u16 *)addr, value); | |
197 | } else { | |
198 | pci_config_write8((u8 *)addr, value & 0xff); | |
199 | pci_config_write8(((u8 *)addr) + 1, value >> 8); | |
200 | } | |
201 | break; | |
202 | case 4: | |
203 | sun4u_write_pci_cfg_host(pbm, bus, devfn, | |
204 | where, 2, value & 0xffff); | |
205 | sun4u_write_pci_cfg_host(pbm, bus, devfn, | |
206 | where + 2, 2, value >> 16); | |
207 | break; | |
208 | } | |
209 | return PCIBIOS_SUCCESSFUL; | |
210 | } | |
211 | ||
ca3dd88e DM |
212 | static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
213 | int where, int size, u32 value) | |
214 | { | |
215 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
216 | unsigned char bus = bus_dev->number; | |
217 | u32 *addr; | |
218 | ||
a2d6ea01 DM |
219 | if (!bus_dev->number && !PCI_SLOT(devfn)) |
220 | return sun4u_write_pci_cfg_host(pbm, bus, devfn, where, | |
221 | size, value); | |
222 | ||
ca3dd88e DM |
223 | addr = sun4u_config_mkaddr(pbm, bus, devfn, where); |
224 | if (!addr) | |
225 | return PCIBIOS_SUCCESSFUL; | |
226 | ||
227 | switch (size) { | |
228 | case 1: | |
229 | pci_config_write8((u8 *)addr, value); | |
230 | break; | |
231 | ||
232 | case 2: | |
233 | if (where & 0x01) { | |
234 | printk("pci_write_config_word: misaligned reg [%x]\n", | |
235 | where); | |
236 | return PCIBIOS_SUCCESSFUL; | |
237 | } | |
238 | pci_config_write16((u16 *)addr, value); | |
239 | break; | |
240 | ||
241 | case 4: | |
242 | if (where & 0x03) { | |
243 | printk("pci_write_config_dword: misaligned reg [%x]\n", | |
244 | where); | |
245 | return PCIBIOS_SUCCESSFUL; | |
246 | } | |
247 | pci_config_write32(addr, value); | |
248 | } | |
249 | return PCIBIOS_SUCCESSFUL; | |
250 | } | |
251 | ||
252 | struct pci_ops sun4u_pci_ops = { | |
253 | .read = sun4u_read_pci_cfg, | |
254 | .write = sun4u_write_pci_cfg, | |
255 | }; | |
256 | ||
257 | static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
258 | int where, int size, u32 *value) | |
259 | { | |
260 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
261 | u32 devhandle = pbm->devhandle; | |
262 | unsigned int bus = bus_dev->number; | |
263 | unsigned int device = PCI_SLOT(devfn); | |
264 | unsigned int func = PCI_FUNC(devfn); | |
265 | unsigned long ret; | |
266 | ||
27097ef9 | 267 | if (!bus && devfn == 0x00) |
ca3dd88e DM |
268 | return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where, |
269 | size, value); | |
270 | if (config_out_of_range(pbm, bus, devfn, where)) { | |
271 | ret = ~0UL; | |
272 | } else { | |
273 | ret = pci_sun4v_config_get(devhandle, | |
274 | HV_PCI_DEVICE_BUILD(bus, device, func), | |
275 | where, size); | |
276 | } | |
277 | switch (size) { | |
278 | case 1: | |
279 | *value = ret & 0xff; | |
280 | break; | |
281 | case 2: | |
282 | *value = ret & 0xffff; | |
283 | break; | |
284 | case 4: | |
285 | *value = ret & 0xffffffff; | |
286 | break; | |
287 | }; | |
288 | ||
289 | ||
290 | return PCIBIOS_SUCCESSFUL; | |
291 | } | |
292 | ||
293 | static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
294 | int where, int size, u32 value) | |
295 | { | |
296 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
297 | u32 devhandle = pbm->devhandle; | |
298 | unsigned int bus = bus_dev->number; | |
299 | unsigned int device = PCI_SLOT(devfn); | |
300 | unsigned int func = PCI_FUNC(devfn); | |
301 | unsigned long ret; | |
302 | ||
27097ef9 | 303 | if (!bus && devfn == 0x00) |
ca3dd88e DM |
304 | return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where, |
305 | size, value); | |
306 | if (config_out_of_range(pbm, bus, devfn, where)) { | |
307 | /* Do nothing. */ | |
308 | } else { | |
309 | ret = pci_sun4v_config_put(devhandle, | |
310 | HV_PCI_DEVICE_BUILD(bus, device, func), | |
311 | where, size, value); | |
312 | } | |
313 | return PCIBIOS_SUCCESSFUL; | |
314 | } | |
315 | ||
316 | struct pci_ops sun4v_pci_ops = { | |
317 | .read = sun4v_read_pci_cfg, | |
318 | .write = sun4v_write_pci_cfg, | |
319 | }; | |
1da177e4 | 320 | |
cfa0652c DM |
321 | void pci_get_pbm_props(struct pci_pbm_info *pbm) |
322 | { | |
323 | const u32 *val = of_get_property(pbm->prom_node, "bus-range", NULL); | |
324 | ||
325 | pbm->pci_first_busno = val[0]; | |
326 | pbm->pci_last_busno = val[1]; | |
327 | ||
328 | val = of_get_property(pbm->prom_node, "ino-bitmap", NULL); | |
329 | if (val) { | |
330 | pbm->ino_bitmap = (((u64)val[1] << 32UL) | | |
331 | ((u64)val[0] << 0UL)); | |
332 | } | |
333 | } | |
334 | ||
9fd8b647 DM |
335 | static void pci_register_legacy_regions(struct resource *io_res, |
336 | struct resource *mem_res) | |
1da177e4 LT |
337 | { |
338 | struct resource *p; | |
339 | ||
340 | /* VGA Video RAM. */ | |
9132983a | 341 | p = kzalloc(sizeof(*p), GFP_KERNEL); |
1da177e4 LT |
342 | if (!p) |
343 | return; | |
344 | ||
1da177e4 LT |
345 | p->name = "Video RAM area"; |
346 | p->start = mem_res->start + 0xa0000UL; | |
347 | p->end = p->start + 0x1ffffUL; | |
348 | p->flags = IORESOURCE_BUSY; | |
349 | request_resource(mem_res, p); | |
350 | ||
9132983a | 351 | p = kzalloc(sizeof(*p), GFP_KERNEL); |
1da177e4 LT |
352 | if (!p) |
353 | return; | |
354 | ||
1da177e4 LT |
355 | p->name = "System ROM"; |
356 | p->start = mem_res->start + 0xf0000UL; | |
357 | p->end = p->start + 0xffffUL; | |
358 | p->flags = IORESOURCE_BUSY; | |
359 | request_resource(mem_res, p); | |
360 | ||
9132983a | 361 | p = kzalloc(sizeof(*p), GFP_KERNEL); |
1da177e4 LT |
362 | if (!p) |
363 | return; | |
364 | ||
1da177e4 LT |
365 | p->name = "Video ROM"; |
366 | p->start = mem_res->start + 0xc0000UL; | |
367 | p->end = p->start + 0x7fffUL; | |
368 | p->flags = IORESOURCE_BUSY; | |
369 | request_resource(mem_res, p); | |
370 | } | |
371 | ||
9fd8b647 DM |
372 | static void pci_register_iommu_region(struct pci_pbm_info *pbm) |
373 | { | |
a165b420 | 374 | const u32 *vdma = of_get_property(pbm->prom_node, "virtual-dma", NULL); |
9fd8b647 DM |
375 | |
376 | if (vdma) { | |
377 | struct resource *rp = kmalloc(sizeof(*rp), GFP_KERNEL); | |
378 | ||
379 | if (!rp) { | |
380 | prom_printf("Cannot allocate IOMMU resource.\n"); | |
381 | prom_halt(); | |
382 | } | |
383 | rp->name = "IOMMU"; | |
384 | rp->start = pbm->mem_space.start + (unsigned long) vdma[0]; | |
385 | rp->end = rp->start + (unsigned long) vdma[1] - 1UL; | |
386 | rp->flags = IORESOURCE_BUSY; | |
387 | request_resource(&pbm->mem_space, rp); | |
388 | } | |
389 | } | |
390 | ||
391 | void pci_determine_mem_io_space(struct pci_pbm_info *pbm) | |
392 | { | |
a165b420 | 393 | const struct linux_prom_pci_ranges *pbm_ranges; |
9fd8b647 | 394 | int i, saw_mem, saw_io; |
3487a1f9 | 395 | int num_pbm_ranges; |
9fd8b647 DM |
396 | |
397 | saw_mem = saw_io = 0; | |
3487a1f9 DM |
398 | pbm_ranges = of_get_property(pbm->prom_node, "ranges", &i); |
399 | num_pbm_ranges = i / sizeof(*pbm_ranges); | |
400 | ||
401 | for (i = 0; i < num_pbm_ranges; i++) { | |
a165b420 | 402 | const struct linux_prom_pci_ranges *pr = &pbm_ranges[i]; |
56f5c0bd | 403 | unsigned long a, size; |
3487a1f9 | 404 | u32 parent_phys_hi, parent_phys_lo; |
56f5c0bd | 405 | u32 size_hi, size_lo; |
9fd8b647 DM |
406 | int type; |
407 | ||
3487a1f9 DM |
408 | parent_phys_hi = pr->parent_phys_hi; |
409 | parent_phys_lo = pr->parent_phys_lo; | |
410 | if (tlb_type == hypervisor) | |
411 | parent_phys_hi &= 0x0fffffff; | |
412 | ||
56f5c0bd DM |
413 | size_hi = pr->size_hi; |
414 | size_lo = pr->size_lo; | |
415 | ||
9fd8b647 | 416 | type = (pr->child_phys_hi >> 24) & 0x3; |
3487a1f9 DM |
417 | a = (((unsigned long)parent_phys_hi << 32UL) | |
418 | ((unsigned long)parent_phys_lo << 0UL)); | |
56f5c0bd DM |
419 | size = (((unsigned long)size_hi << 32UL) | |
420 | ((unsigned long)size_lo << 0UL)); | |
9fd8b647 DM |
421 | |
422 | switch (type) { | |
423 | case 0: | |
424 | /* PCI config space, 16MB */ | |
425 | pbm->config_space = a; | |
426 | break; | |
427 | ||
428 | case 1: | |
429 | /* 16-bit IO space, 16MB */ | |
430 | pbm->io_space.start = a; | |
56f5c0bd | 431 | pbm->io_space.end = a + size - 1UL; |
9fd8b647 DM |
432 | pbm->io_space.flags = IORESOURCE_IO; |
433 | saw_io = 1; | |
434 | break; | |
435 | ||
436 | case 2: | |
437 | /* 32-bit MEM space, 2GB */ | |
438 | pbm->mem_space.start = a; | |
56f5c0bd | 439 | pbm->mem_space.end = a + size - 1UL; |
9fd8b647 DM |
440 | pbm->mem_space.flags = IORESOURCE_MEM; |
441 | saw_mem = 1; | |
442 | break; | |
443 | ||
444 | case 3: | |
445 | /* XXX 64-bit MEM handling XXX */ | |
446 | ||
447 | default: | |
448 | break; | |
449 | }; | |
450 | } | |
451 | ||
452 | if (!saw_io || !saw_mem) { | |
453 | prom_printf("%s: Fatal error, missing %s PBM range.\n", | |
454 | pbm->name, | |
455 | (!saw_io ? "IO" : "MEM")); | |
456 | prom_halt(); | |
457 | } | |
458 | ||
459 | printk("%s: PCI IO[%lx] MEM[%lx]\n", | |
460 | pbm->name, | |
461 | pbm->io_space.start, | |
462 | pbm->mem_space.start); | |
463 | ||
464 | pbm->io_space.name = pbm->mem_space.name = pbm->name; | |
465 | ||
466 | request_resource(&ioport_resource, &pbm->io_space); | |
467 | request_resource(&iomem_resource, &pbm->mem_space); | |
468 | ||
469 | pci_register_legacy_regions(&pbm->io_space, | |
470 | &pbm->mem_space); | |
471 | pci_register_iommu_region(pbm); | |
472 | } | |
473 | ||
1da177e4 | 474 | /* Generic helper routines for PCI error reporting. */ |
6c108f12 | 475 | void pci_scan_for_target_abort(struct pci_pbm_info *pbm, |
1da177e4 LT |
476 | struct pci_bus *pbus) |
477 | { | |
478 | struct pci_dev *pdev; | |
479 | struct pci_bus *bus; | |
480 | ||
481 | list_for_each_entry(pdev, &pbus->devices, bus_list) { | |
482 | u16 status, error_bits; | |
483 | ||
484 | pci_read_config_word(pdev, PCI_STATUS, &status); | |
485 | error_bits = | |
486 | (status & (PCI_STATUS_SIG_TARGET_ABORT | | |
487 | PCI_STATUS_REC_TARGET_ABORT)); | |
488 | if (error_bits) { | |
489 | pci_write_config_word(pdev, PCI_STATUS, error_bits); | |
6c108f12 DM |
490 | printk("%s: Device %s saw Target Abort [%016x]\n", |
491 | pbm->name, pci_name(pdev), status); | |
1da177e4 LT |
492 | } |
493 | } | |
494 | ||
495 | list_for_each_entry(bus, &pbus->children, node) | |
6c108f12 | 496 | pci_scan_for_target_abort(pbm, bus); |
1da177e4 LT |
497 | } |
498 | ||
6c108f12 | 499 | void pci_scan_for_master_abort(struct pci_pbm_info *pbm, |
1da177e4 LT |
500 | struct pci_bus *pbus) |
501 | { | |
502 | struct pci_dev *pdev; | |
503 | struct pci_bus *bus; | |
504 | ||
505 | list_for_each_entry(pdev, &pbus->devices, bus_list) { | |
506 | u16 status, error_bits; | |
507 | ||
508 | pci_read_config_word(pdev, PCI_STATUS, &status); | |
509 | error_bits = | |
510 | (status & (PCI_STATUS_REC_MASTER_ABORT)); | |
511 | if (error_bits) { | |
512 | pci_write_config_word(pdev, PCI_STATUS, error_bits); | |
6c108f12 DM |
513 | printk("%s: Device %s received Master Abort [%016x]\n", |
514 | pbm->name, pci_name(pdev), status); | |
1da177e4 LT |
515 | } |
516 | } | |
517 | ||
518 | list_for_each_entry(bus, &pbus->children, node) | |
6c108f12 | 519 | pci_scan_for_master_abort(pbm, bus); |
1da177e4 LT |
520 | } |
521 | ||
6c108f12 | 522 | void pci_scan_for_parity_error(struct pci_pbm_info *pbm, |
1da177e4 LT |
523 | struct pci_bus *pbus) |
524 | { | |
525 | struct pci_dev *pdev; | |
526 | struct pci_bus *bus; | |
527 | ||
528 | list_for_each_entry(pdev, &pbus->devices, bus_list) { | |
529 | u16 status, error_bits; | |
530 | ||
531 | pci_read_config_word(pdev, PCI_STATUS, &status); | |
532 | error_bits = | |
533 | (status & (PCI_STATUS_PARITY | | |
534 | PCI_STATUS_DETECTED_PARITY)); | |
535 | if (error_bits) { | |
536 | pci_write_config_word(pdev, PCI_STATUS, error_bits); | |
6c108f12 DM |
537 | printk("%s: Device %s saw Parity Error [%016x]\n", |
538 | pbm->name, pci_name(pdev), status); | |
1da177e4 LT |
539 | } |
540 | } | |
541 | ||
542 | list_for_each_entry(bus, &pbus->children, node) | |
6c108f12 | 543 | pci_scan_for_parity_error(pbm, bus); |
1da177e4 | 544 | } |