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1da177e4 LT |
1 | /* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $ |
2 | * pci.c: UltraSparc PCI controller support. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
9 | #include <linux/config.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/string.h> | |
13 | #include <linux/sched.h> | |
14 | #include <linux/capability.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/smp_lock.h> | |
17 | #include <linux/init.h> | |
18 | ||
19 | #include <asm/uaccess.h> | |
20 | #include <asm/pbm.h> | |
21 | #include <asm/pgtable.h> | |
22 | #include <asm/irq.h> | |
23 | #include <asm/ebus.h> | |
24 | #include <asm/isa.h> | |
25 | ||
26 | unsigned long pci_memspace_mask = 0xffffffffUL; | |
27 | ||
28 | #ifndef CONFIG_PCI | |
29 | /* A "nop" PCI implementation. */ | |
30 | asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn, | |
31 | unsigned long off, unsigned long len, | |
32 | unsigned char *buf) | |
33 | { | |
34 | return 0; | |
35 | } | |
36 | asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn, | |
37 | unsigned long off, unsigned long len, | |
38 | unsigned char *buf) | |
39 | { | |
40 | return 0; | |
41 | } | |
42 | #else | |
43 | ||
44 | /* List of all PCI controllers found in the system. */ | |
45 | struct pci_controller_info *pci_controller_root = NULL; | |
46 | ||
47 | /* Each PCI controller found gets a unique index. */ | |
48 | int pci_num_controllers = 0; | |
49 | ||
50 | /* At boot time the user can give the kernel a command | |
51 | * line option which controls if and how PCI devices | |
52 | * are reordered at PCI bus probing time. | |
53 | */ | |
54 | int pci_device_reorder = 0; | |
55 | ||
56 | volatile int pci_poke_in_progress; | |
57 | volatile int pci_poke_cpu = -1; | |
58 | volatile int pci_poke_faulted; | |
59 | ||
60 | static DEFINE_SPINLOCK(pci_poke_lock); | |
61 | ||
62 | void pci_config_read8(u8 *addr, u8 *ret) | |
63 | { | |
64 | unsigned long flags; | |
65 | u8 byte; | |
66 | ||
67 | spin_lock_irqsave(&pci_poke_lock, flags); | |
68 | pci_poke_cpu = smp_processor_id(); | |
69 | pci_poke_in_progress = 1; | |
70 | pci_poke_faulted = 0; | |
71 | __asm__ __volatile__("membar #Sync\n\t" | |
72 | "lduba [%1] %2, %0\n\t" | |
73 | "membar #Sync" | |
74 | : "=r" (byte) | |
75 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
76 | : "memory"); | |
77 | pci_poke_in_progress = 0; | |
78 | pci_poke_cpu = -1; | |
79 | if (!pci_poke_faulted) | |
80 | *ret = byte; | |
81 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
82 | } | |
83 | ||
84 | void pci_config_read16(u16 *addr, u16 *ret) | |
85 | { | |
86 | unsigned long flags; | |
87 | u16 word; | |
88 | ||
89 | spin_lock_irqsave(&pci_poke_lock, flags); | |
90 | pci_poke_cpu = smp_processor_id(); | |
91 | pci_poke_in_progress = 1; | |
92 | pci_poke_faulted = 0; | |
93 | __asm__ __volatile__("membar #Sync\n\t" | |
94 | "lduha [%1] %2, %0\n\t" | |
95 | "membar #Sync" | |
96 | : "=r" (word) | |
97 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
98 | : "memory"); | |
99 | pci_poke_in_progress = 0; | |
100 | pci_poke_cpu = -1; | |
101 | if (!pci_poke_faulted) | |
102 | *ret = word; | |
103 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
104 | } | |
105 | ||
106 | void pci_config_read32(u32 *addr, u32 *ret) | |
107 | { | |
108 | unsigned long flags; | |
109 | u32 dword; | |
110 | ||
111 | spin_lock_irqsave(&pci_poke_lock, flags); | |
112 | pci_poke_cpu = smp_processor_id(); | |
113 | pci_poke_in_progress = 1; | |
114 | pci_poke_faulted = 0; | |
115 | __asm__ __volatile__("membar #Sync\n\t" | |
116 | "lduwa [%1] %2, %0\n\t" | |
117 | "membar #Sync" | |
118 | : "=r" (dword) | |
119 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
120 | : "memory"); | |
121 | pci_poke_in_progress = 0; | |
122 | pci_poke_cpu = -1; | |
123 | if (!pci_poke_faulted) | |
124 | *ret = dword; | |
125 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
126 | } | |
127 | ||
128 | void pci_config_write8(u8 *addr, u8 val) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&pci_poke_lock, flags); | |
133 | pci_poke_cpu = smp_processor_id(); | |
134 | pci_poke_in_progress = 1; | |
135 | pci_poke_faulted = 0; | |
136 | __asm__ __volatile__("membar #Sync\n\t" | |
137 | "stba %0, [%1] %2\n\t" | |
138 | "membar #Sync" | |
139 | : /* no outputs */ | |
140 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
141 | : "memory"); | |
142 | pci_poke_in_progress = 0; | |
143 | pci_poke_cpu = -1; | |
144 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
145 | } | |
146 | ||
147 | void pci_config_write16(u16 *addr, u16 val) | |
148 | { | |
149 | unsigned long flags; | |
150 | ||
151 | spin_lock_irqsave(&pci_poke_lock, flags); | |
152 | pci_poke_cpu = smp_processor_id(); | |
153 | pci_poke_in_progress = 1; | |
154 | pci_poke_faulted = 0; | |
155 | __asm__ __volatile__("membar #Sync\n\t" | |
156 | "stha %0, [%1] %2\n\t" | |
157 | "membar #Sync" | |
158 | : /* no outputs */ | |
159 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
160 | : "memory"); | |
161 | pci_poke_in_progress = 0; | |
162 | pci_poke_cpu = -1; | |
163 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
164 | } | |
165 | ||
166 | void pci_config_write32(u32 *addr, u32 val) | |
167 | { | |
168 | unsigned long flags; | |
169 | ||
170 | spin_lock_irqsave(&pci_poke_lock, flags); | |
171 | pci_poke_cpu = smp_processor_id(); | |
172 | pci_poke_in_progress = 1; | |
173 | pci_poke_faulted = 0; | |
174 | __asm__ __volatile__("membar #Sync\n\t" | |
175 | "stwa %0, [%1] %2\n\t" | |
176 | "membar #Sync" | |
177 | : /* no outputs */ | |
178 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
179 | : "memory"); | |
180 | pci_poke_in_progress = 0; | |
181 | pci_poke_cpu = -1; | |
182 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
183 | } | |
184 | ||
185 | /* Probe for all PCI controllers in the system. */ | |
186 | extern void sabre_init(int, char *); | |
187 | extern void psycho_init(int, char *); | |
188 | extern void schizo_init(int, char *); | |
189 | extern void schizo_plus_init(int, char *); | |
190 | extern void tomatillo_init(int, char *); | |
8f6a93a1 | 191 | extern void sun4v_pci_init(int, char *); |
1da177e4 LT |
192 | |
193 | static struct { | |
194 | char *model_name; | |
195 | void (*init)(int, char *); | |
196 | } pci_controller_table[] __initdata = { | |
197 | { "SUNW,sabre", sabre_init }, | |
198 | { "pci108e,a000", sabre_init }, | |
199 | { "pci108e,a001", sabre_init }, | |
200 | { "SUNW,psycho", psycho_init }, | |
201 | { "pci108e,8000", psycho_init }, | |
202 | { "SUNW,schizo", schizo_init }, | |
203 | { "pci108e,8001", schizo_init }, | |
204 | { "SUNW,schizo+", schizo_plus_init }, | |
205 | { "pci108e,8002", schizo_plus_init }, | |
206 | { "SUNW,tomatillo", tomatillo_init }, | |
207 | { "pci108e,a801", tomatillo_init }, | |
8f6a93a1 | 208 | { "SUNW,sun4v-pci", sun4v_pci_init }, |
1da177e4 LT |
209 | }; |
210 | #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \ | |
211 | sizeof(pci_controller_table[0])) | |
212 | ||
213 | static int __init pci_controller_init(char *model_name, int namelen, int node) | |
214 | { | |
215 | int i; | |
216 | ||
217 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
218 | if (!strncmp(model_name, | |
219 | pci_controller_table[i].model_name, | |
220 | namelen)) { | |
221 | pci_controller_table[i].init(node, model_name); | |
222 | return 1; | |
223 | } | |
224 | } | |
225 | printk("PCI: Warning unknown controller, model name [%s]\n", | |
226 | model_name); | |
227 | printk("PCI: Ignoring controller...\n"); | |
228 | ||
229 | return 0; | |
230 | } | |
231 | ||
232 | static int __init pci_is_controller(char *model_name, int namelen, int node) | |
233 | { | |
234 | int i; | |
235 | ||
236 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
237 | if (!strncmp(model_name, | |
238 | pci_controller_table[i].model_name, | |
239 | namelen)) { | |
240 | return 1; | |
241 | } | |
242 | } | |
243 | return 0; | |
244 | } | |
245 | ||
246 | static int __init pci_controller_scan(int (*handler)(char *, int, int)) | |
247 | { | |
248 | char namebuf[64]; | |
249 | int node; | |
250 | int count = 0; | |
251 | ||
252 | node = prom_getchild(prom_root_node); | |
253 | while ((node = prom_searchsiblings(node, "pci")) != 0) { | |
254 | int len; | |
255 | ||
256 | if ((len = prom_getproperty(node, "model", namebuf, sizeof(namebuf))) > 0 || | |
257 | (len = prom_getproperty(node, "compatible", namebuf, sizeof(namebuf))) > 0) { | |
258 | int item_len = 0; | |
259 | ||
260 | /* Our value may be a multi-valued string in the | |
261 | * case of some compatible properties. For sanity, | |
262 | * only try the first one. */ | |
263 | ||
264 | while (namebuf[item_len] && len) { | |
265 | len--; | |
266 | item_len++; | |
267 | } | |
268 | ||
269 | if (handler(namebuf, item_len, node)) | |
270 | count++; | |
271 | } | |
272 | ||
273 | node = prom_getsibling(node); | |
274 | if (!node) | |
275 | break; | |
276 | } | |
277 | ||
278 | return count; | |
279 | } | |
280 | ||
281 | ||
282 | /* Is there some PCI controller in the system? */ | |
283 | int __init pcic_present(void) | |
284 | { | |
285 | return pci_controller_scan(pci_is_controller); | |
286 | } | |
287 | ||
8f6a93a1 DM |
288 | struct pci_iommu_ops *pci_iommu_ops; |
289 | EXPORT_SYMBOL(pci_iommu_ops); | |
290 | ||
291 | extern struct pci_iommu_ops pci_sun4u_iommu_ops, | |
292 | pci_sun4v_iommu_ops; | |
293 | ||
1da177e4 LT |
294 | /* Find each controller in the system, attach and initialize |
295 | * software state structure for each and link into the | |
296 | * pci_controller_root. Setup the controller enough such | |
297 | * that bus scanning can be done. | |
298 | */ | |
299 | static void __init pci_controller_probe(void) | |
300 | { | |
8f6a93a1 DM |
301 | if (tlb_type == hypervisor) |
302 | pci_iommu_ops = &pci_sun4v_iommu_ops; | |
303 | else | |
304 | pci_iommu_ops = &pci_sun4u_iommu_ops; | |
305 | ||
1da177e4 LT |
306 | printk("PCI: Probing for controllers.\n"); |
307 | ||
308 | pci_controller_scan(pci_controller_init); | |
309 | } | |
310 | ||
311 | static void __init pci_scan_each_controller_bus(void) | |
312 | { | |
313 | struct pci_controller_info *p; | |
314 | ||
315 | for (p = pci_controller_root; p; p = p->next) | |
316 | p->scan_bus(p); | |
317 | } | |
318 | ||
319 | /* Reorder the pci_dev chain, so that onboard devices come first | |
320 | * and then come the pluggable cards. | |
321 | */ | |
322 | static void __init pci_reorder_devs(void) | |
323 | { | |
324 | struct list_head *pci_onboard = &pci_devices; | |
325 | struct list_head *walk = pci_onboard->next; | |
326 | ||
327 | while (walk != pci_onboard) { | |
328 | struct pci_dev *pdev = pci_dev_g(walk); | |
329 | struct list_head *walk_next = walk->next; | |
330 | ||
331 | if (pdev->irq && (__irq_ino(pdev->irq) & 0x20)) { | |
332 | list_del(walk); | |
333 | list_add(walk, pci_onboard); | |
334 | } | |
335 | ||
336 | walk = walk_next; | |
337 | } | |
338 | } | |
339 | ||
340 | extern void clock_probe(void); | |
341 | extern void power_init(void); | |
342 | ||
343 | static int __init pcibios_init(void) | |
344 | { | |
345 | pci_controller_probe(); | |
346 | if (pci_controller_root == NULL) | |
347 | return 0; | |
348 | ||
349 | pci_scan_each_controller_bus(); | |
350 | ||
351 | if (pci_device_reorder) | |
352 | pci_reorder_devs(); | |
353 | ||
354 | isa_init(); | |
355 | ebus_init(); | |
356 | clock_probe(); | |
357 | power_init(); | |
358 | ||
359 | return 0; | |
360 | } | |
361 | ||
362 | subsys_initcall(pcibios_init); | |
363 | ||
364 | void pcibios_fixup_bus(struct pci_bus *pbus) | |
365 | { | |
366 | struct pci_pbm_info *pbm = pbus->sysdata; | |
367 | ||
368 | /* Generic PCI bus probing sets these to point at | |
369 | * &io{port,mem}_resouce which is wrong for us. | |
370 | */ | |
371 | pbus->resource[0] = &pbm->io_space; | |
372 | pbus->resource[1] = &pbm->mem_space; | |
373 | } | |
374 | ||
085ae41f | 375 | struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r) |
1da177e4 LT |
376 | { |
377 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
085ae41f | 378 | struct resource *root = NULL; |
1da177e4 | 379 | |
085ae41f | 380 | if (r->flags & IORESOURCE_IO) |
1da177e4 | 381 | root = &pbm->io_space; |
085ae41f | 382 | if (r->flags & IORESOURCE_MEM) |
1da177e4 LT |
383 | root = &pbm->mem_space; |
384 | ||
085ae41f | 385 | return root; |
1da177e4 LT |
386 | } |
387 | ||
388 | void pcibios_update_irq(struct pci_dev *pdev, int irq) | |
389 | { | |
390 | } | |
391 | ||
392 | void pcibios_align_resource(void *data, struct resource *res, | |
393 | unsigned long size, unsigned long align) | |
394 | { | |
395 | } | |
396 | ||
397 | int pcibios_enable_device(struct pci_dev *pdev, int mask) | |
398 | { | |
399 | return 0; | |
400 | } | |
401 | ||
402 | void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, | |
403 | struct resource *res) | |
404 | { | |
405 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
406 | struct resource zero_res, *root; | |
407 | ||
408 | zero_res.start = 0; | |
409 | zero_res.end = 0; | |
410 | zero_res.flags = res->flags; | |
411 | ||
412 | if (res->flags & IORESOURCE_IO) | |
413 | root = &pbm->io_space; | |
414 | else | |
415 | root = &pbm->mem_space; | |
416 | ||
417 | pbm->parent->resource_adjust(pdev, &zero_res, root); | |
418 | ||
419 | region->start = res->start - zero_res.start; | |
420 | region->end = res->end - zero_res.start; | |
421 | } | |
422 | ||
423 | void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, | |
424 | struct pci_bus_region *region) | |
425 | { | |
426 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
427 | struct resource *root; | |
428 | ||
429 | res->start = region->start; | |
430 | res->end = region->end; | |
431 | ||
432 | if (res->flags & IORESOURCE_IO) | |
433 | root = &pbm->io_space; | |
434 | else | |
435 | root = &pbm->mem_space; | |
436 | ||
437 | pbm->parent->resource_adjust(pdev, res, root); | |
438 | } | |
41290c14 | 439 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 LT |
440 | |
441 | char * __init pcibios_setup(char *str) | |
442 | { | |
443 | if (!strcmp(str, "onboardfirst")) { | |
444 | pci_device_reorder = 1; | |
445 | return NULL; | |
446 | } | |
447 | if (!strcmp(str, "noreorder")) { | |
448 | pci_device_reorder = 0; | |
449 | return NULL; | |
450 | } | |
451 | return str; | |
452 | } | |
453 | ||
454 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
455 | ||
456 | /* If the user uses a host-bridge as the PCI device, he may use | |
457 | * this to perform a raw mmap() of the I/O or MEM space behind | |
458 | * that controller. | |
459 | * | |
460 | * This can be useful for execution of x86 PCI bios initialization code | |
461 | * on a PCI card, like the xfree86 int10 stuff does. | |
462 | */ | |
463 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
464 | enum pci_mmap_state mmap_state) | |
465 | { | |
466 | struct pcidev_cookie *pcp = pdev->sysdata; | |
467 | struct pci_pbm_info *pbm; | |
468 | struct pci_controller_info *p; | |
469 | unsigned long space_size, user_offset, user_size; | |
470 | ||
471 | if (!pcp) | |
472 | return -ENXIO; | |
473 | pbm = pcp->pbm; | |
474 | if (!pbm) | |
475 | return -ENXIO; | |
476 | ||
477 | p = pbm->parent; | |
478 | if (p->pbms_same_domain) { | |
479 | unsigned long lowest, highest; | |
480 | ||
481 | lowest = ~0UL; highest = 0UL; | |
482 | if (mmap_state == pci_mmap_io) { | |
483 | if (p->pbm_A.io_space.flags) { | |
484 | lowest = p->pbm_A.io_space.start; | |
485 | highest = p->pbm_A.io_space.end + 1; | |
486 | } | |
487 | if (p->pbm_B.io_space.flags) { | |
488 | if (lowest > p->pbm_B.io_space.start) | |
489 | lowest = p->pbm_B.io_space.start; | |
490 | if (highest < p->pbm_B.io_space.end + 1) | |
491 | highest = p->pbm_B.io_space.end + 1; | |
492 | } | |
493 | space_size = highest - lowest; | |
494 | } else { | |
495 | if (p->pbm_A.mem_space.flags) { | |
496 | lowest = p->pbm_A.mem_space.start; | |
497 | highest = p->pbm_A.mem_space.end + 1; | |
498 | } | |
499 | if (p->pbm_B.mem_space.flags) { | |
500 | if (lowest > p->pbm_B.mem_space.start) | |
501 | lowest = p->pbm_B.mem_space.start; | |
502 | if (highest < p->pbm_B.mem_space.end + 1) | |
503 | highest = p->pbm_B.mem_space.end + 1; | |
504 | } | |
505 | space_size = highest - lowest; | |
506 | } | |
507 | } else { | |
508 | if (mmap_state == pci_mmap_io) { | |
509 | space_size = (pbm->io_space.end - | |
510 | pbm->io_space.start) + 1; | |
511 | } else { | |
512 | space_size = (pbm->mem_space.end - | |
513 | pbm->mem_space.start) + 1; | |
514 | } | |
515 | } | |
516 | ||
517 | /* Make sure the request is in range. */ | |
518 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
519 | user_size = vma->vm_end - vma->vm_start; | |
520 | ||
521 | if (user_offset >= space_size || | |
522 | (user_offset + user_size) > space_size) | |
523 | return -EINVAL; | |
524 | ||
525 | if (p->pbms_same_domain) { | |
526 | unsigned long lowest = ~0UL; | |
527 | ||
528 | if (mmap_state == pci_mmap_io) { | |
529 | if (p->pbm_A.io_space.flags) | |
530 | lowest = p->pbm_A.io_space.start; | |
531 | if (p->pbm_B.io_space.flags && | |
532 | lowest > p->pbm_B.io_space.start) | |
533 | lowest = p->pbm_B.io_space.start; | |
534 | } else { | |
535 | if (p->pbm_A.mem_space.flags) | |
536 | lowest = p->pbm_A.mem_space.start; | |
537 | if (p->pbm_B.mem_space.flags && | |
538 | lowest > p->pbm_B.mem_space.start) | |
539 | lowest = p->pbm_B.mem_space.start; | |
540 | } | |
541 | vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT; | |
542 | } else { | |
543 | if (mmap_state == pci_mmap_io) { | |
544 | vma->vm_pgoff = (pbm->io_space.start + | |
545 | user_offset) >> PAGE_SHIFT; | |
546 | } else { | |
547 | vma->vm_pgoff = (pbm->mem_space.start + | |
548 | user_offset) >> PAGE_SHIFT; | |
549 | } | |
550 | } | |
551 | ||
552 | return 0; | |
553 | } | |
554 | ||
555 | /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding | |
556 | * to the 32-bit pci bus offset for DEV requested by the user. | |
557 | * | |
558 | * Basically, the user finds the base address for his device which he wishes | |
559 | * to mmap. They read the 32-bit value from the config space base register, | |
560 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
561 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
562 | * | |
563 | * Returns negative error code on failure, zero on success. | |
564 | */ | |
565 | static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma, | |
566 | enum pci_mmap_state mmap_state) | |
567 | { | |
568 | unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
569 | unsigned long user32 = user_offset & pci_memspace_mask; | |
570 | unsigned long largest_base, this_base, addr32; | |
571 | int i; | |
572 | ||
573 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
574 | return __pci_mmap_make_offset_bus(dev, vma, mmap_state); | |
575 | ||
576 | /* Figure out which base address this is for. */ | |
577 | largest_base = 0UL; | |
578 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
579 | struct resource *rp = &dev->resource[i]; | |
580 | ||
581 | /* Active? */ | |
582 | if (!rp->flags) | |
583 | continue; | |
584 | ||
585 | /* Same type? */ | |
586 | if (i == PCI_ROM_RESOURCE) { | |
587 | if (mmap_state != pci_mmap_mem) | |
588 | continue; | |
589 | } else { | |
590 | if ((mmap_state == pci_mmap_io && | |
591 | (rp->flags & IORESOURCE_IO) == 0) || | |
592 | (mmap_state == pci_mmap_mem && | |
593 | (rp->flags & IORESOURCE_MEM) == 0)) | |
594 | continue; | |
595 | } | |
596 | ||
597 | this_base = rp->start; | |
598 | ||
599 | addr32 = (this_base & PAGE_MASK) & pci_memspace_mask; | |
600 | ||
601 | if (mmap_state == pci_mmap_io) | |
602 | addr32 &= 0xffffff; | |
603 | ||
604 | if (addr32 <= user32 && this_base > largest_base) | |
605 | largest_base = this_base; | |
606 | } | |
607 | ||
608 | if (largest_base == 0UL) | |
609 | return -EINVAL; | |
610 | ||
611 | /* Now construct the final physical address. */ | |
612 | if (mmap_state == pci_mmap_io) | |
613 | vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT); | |
614 | else | |
615 | vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT); | |
616 | ||
617 | return 0; | |
618 | } | |
619 | ||
620 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
621 | * mapping. | |
622 | */ | |
623 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
624 | enum pci_mmap_state mmap_state) | |
625 | { | |
626 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
627 | } | |
628 | ||
629 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
630 | * device mapping. | |
631 | */ | |
632 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
633 | enum pci_mmap_state mmap_state) | |
634 | { | |
a7a6cac2 | 635 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
636 | } |
637 | ||
638 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
639 | * for this architecture. The region in the process to map is described by vm_start | |
640 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
641 | * The pci device structure is provided so that architectures may make mapping | |
642 | * decisions on a per-device or per-bus basis. | |
643 | * | |
644 | * Returns a negative error code on failure, zero on success. | |
645 | */ | |
646 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
647 | enum pci_mmap_state mmap_state, | |
648 | int write_combine) | |
649 | { | |
650 | int ret; | |
651 | ||
652 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
653 | if (ret < 0) | |
654 | return ret; | |
655 | ||
656 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
657 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
658 | ||
659 | ret = io_remap_pfn_range(vma, vma->vm_start, | |
660 | vma->vm_pgoff, | |
661 | vma->vm_end - vma->vm_start, | |
662 | vma->vm_page_prot); | |
663 | if (ret) | |
664 | return ret; | |
665 | ||
666 | vma->vm_flags |= VM_IO; | |
667 | return 0; | |
668 | } | |
669 | ||
670 | /* Return the domain nuber for this pci bus */ | |
671 | ||
672 | int pci_domain_nr(struct pci_bus *pbus) | |
673 | { | |
674 | struct pci_pbm_info *pbm = pbus->sysdata; | |
675 | int ret; | |
676 | ||
677 | if (pbm == NULL || pbm->parent == NULL) { | |
678 | ret = -ENXIO; | |
679 | } else { | |
680 | struct pci_controller_info *p = pbm->parent; | |
681 | ||
682 | ret = p->index; | |
683 | if (p->pbms_same_domain == 0) | |
684 | ret = ((ret << 1) + | |
685 | ((pbm == &pbm->parent->pbm_B) ? 1 : 0)); | |
686 | } | |
687 | ||
688 | return ret; | |
689 | } | |
690 | EXPORT_SYMBOL(pci_domain_nr); | |
691 | ||
692 | int pcibios_prep_mwi(struct pci_dev *dev) | |
693 | { | |
694 | /* We set correct PCI_CACHE_LINE_SIZE register values for every | |
695 | * device probed on this platform. So there is nothing to check | |
696 | * and this always succeeds. | |
697 | */ | |
698 | return 0; | |
699 | } | |
700 | ||
701 | #endif /* !(CONFIG_PCI) */ |