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[SPARC64]: Probe PCI bus using OF device tree.
[linux-2.6-block.git] / arch / sparc64 / kernel / pci.c
CommitLineData
a2fb23af 1/* pci.c: UltraSparc PCI controller support.
1da177e4
LT		 2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
a2fb23af
DM		 6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
1da177e4
LT		 9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
17#include <linux/smp_lock.h>
35a17eb6
DM		 18#include <linux/msi.h>
19#include <linux/irq.h>
1da177e4
LT		 20#include <linux/init.h>
21
22#include <asm/uaccess.h>
23#include <asm/pbm.h>
24#include <asm/pgtable.h>
25#include <asm/irq.h>
26#include <asm/ebus.h>
27#include <asm/isa.h>
e87dc350 28#include <asm/prom.h>
1da177e4
LT		 29
30unsigned long pci_memspace_mask = 0xffffffffUL;
31
32#ifndef CONFIG_PCI
33/* A "nop" PCI implementation. */
34asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
35 unsigned long off, unsigned long len,
36 unsigned char *buf)
37{
38 return 0;
39}
40asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
41 unsigned long off, unsigned long len,
42 unsigned char *buf)
43{
44 return 0;
45}
46#else
47
48/* List of all PCI controllers found in the system. */
49struct pci_controller_info *pci_controller_root = NULL;
50
51/* Each PCI controller found gets a unique index. */
52int pci_num_controllers = 0;
53
1da177e4
LT		 54volatile int pci_poke_in_progress;
55volatile int pci_poke_cpu = -1;
56volatile int pci_poke_faulted;
57
58static DEFINE_SPINLOCK(pci_poke_lock);
59
60void pci_config_read8(u8 *addr, u8 *ret)
61{
62 unsigned long flags;
63 u8 byte;
64
65 spin_lock_irqsave(&pci_poke_lock, flags);
66 pci_poke_cpu = smp_processor_id();
67 pci_poke_in_progress = 1;
68 pci_poke_faulted = 0;
69 __asm__ __volatile__("membar #Sync\n\t"
70 "lduba [%1] %2, %0\n\t"
71 "membar #Sync"
72 : "=r" (byte)
73 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
74 : "memory");
75 pci_poke_in_progress = 0;
76 pci_poke_cpu = -1;
77 if (!pci_poke_faulted)
78 *ret = byte;
79 spin_unlock_irqrestore(&pci_poke_lock, flags);
80}
81
82void pci_config_read16(u16 *addr, u16 *ret)
83{
84 unsigned long flags;
85 u16 word;
86
87 spin_lock_irqsave(&pci_poke_lock, flags);
88 pci_poke_cpu = smp_processor_id();
89 pci_poke_in_progress = 1;
90 pci_poke_faulted = 0;
91 __asm__ __volatile__("membar #Sync\n\t"
92 "lduha [%1] %2, %0\n\t"
93 "membar #Sync"
94 : "=r" (word)
95 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
96 : "memory");
97 pci_poke_in_progress = 0;
98 pci_poke_cpu = -1;
99 if (!pci_poke_faulted)
100 *ret = word;
101 spin_unlock_irqrestore(&pci_poke_lock, flags);
102}
103
104void pci_config_read32(u32 *addr, u32 *ret)
105{
106 unsigned long flags;
107 u32 dword;
108
109 spin_lock_irqsave(&pci_poke_lock, flags);
110 pci_poke_cpu = smp_processor_id();
111 pci_poke_in_progress = 1;
112 pci_poke_faulted = 0;
113 __asm__ __volatile__("membar #Sync\n\t"
114 "lduwa [%1] %2, %0\n\t"
115 "membar #Sync"
116 : "=r" (dword)
117 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
118 : "memory");
119 pci_poke_in_progress = 0;
120 pci_poke_cpu = -1;
121 if (!pci_poke_faulted)
122 *ret = dword;
123 spin_unlock_irqrestore(&pci_poke_lock, flags);
124}
125
126void pci_config_write8(u8 *addr, u8 val)
127{
128 unsigned long flags;
129
130 spin_lock_irqsave(&pci_poke_lock, flags);
131 pci_poke_cpu = smp_processor_id();
132 pci_poke_in_progress = 1;
133 pci_poke_faulted = 0;
134 __asm__ __volatile__("membar #Sync\n\t"
135 "stba %0, [%1] %2\n\t"
136 "membar #Sync"
137 : /* no outputs */
138 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
139 : "memory");
140 pci_poke_in_progress = 0;
141 pci_poke_cpu = -1;
142 spin_unlock_irqrestore(&pci_poke_lock, flags);
143}
144
145void pci_config_write16(u16 *addr, u16 val)
146{
147 unsigned long flags;
148
149 spin_lock_irqsave(&pci_poke_lock, flags);
150 pci_poke_cpu = smp_processor_id();
151 pci_poke_in_progress = 1;
152 pci_poke_faulted = 0;
153 __asm__ __volatile__("membar #Sync\n\t"
154 "stha %0, [%1] %2\n\t"
155 "membar #Sync"
156 : /* no outputs */
157 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
158 : "memory");
159 pci_poke_in_progress = 0;
160 pci_poke_cpu = -1;
161 spin_unlock_irqrestore(&pci_poke_lock, flags);
162}
163
164void pci_config_write32(u32 *addr, u32 val)
165{
166 unsigned long flags;
167
168 spin_lock_irqsave(&pci_poke_lock, flags);
169 pci_poke_cpu = smp_processor_id();
170 pci_poke_in_progress = 1;
171 pci_poke_faulted = 0;
172 __asm__ __volatile__("membar #Sync\n\t"
173 "stwa %0, [%1] %2\n\t"
174 "membar #Sync"
175 : /* no outputs */
176 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
177 : "memory");
178 pci_poke_in_progress = 0;
179 pci_poke_cpu = -1;
180 spin_unlock_irqrestore(&pci_poke_lock, flags);
181}
182
183/* Probe for all PCI controllers in the system. */
e87dc350
DM		 184extern void sabre_init(struct device_node *, const char *);
185extern void psycho_init(struct device_node *, const char *);
186extern void schizo_init(struct device_node *, const char *);
187extern void schizo_plus_init(struct device_node *, const char *);
188extern void tomatillo_init(struct device_node *, const char *);
189extern void sun4v_pci_init(struct device_node *, const char *);
1da177e4
LT		 190
191static struct {
192 char *model_name;
e87dc350 193 void (*init)(struct device_node *, const char *);
1da177e4
LT		 194} pci_controller_table[] __initdata = {
195 { "SUNW,sabre", sabre_init },
196 { "pci108e,a000", sabre_init },
197 { "pci108e,a001", sabre_init },
198 { "SUNW,psycho", psycho_init },
199 { "pci108e,8000", psycho_init },
200 { "SUNW,schizo", schizo_init },
201 { "pci108e,8001", schizo_init },
202 { "SUNW,schizo+", schizo_plus_init },
203 { "pci108e,8002", schizo_plus_init },
204 { "SUNW,tomatillo", tomatillo_init },
205 { "pci108e,a801", tomatillo_init },
8f6a93a1 206 { "SUNW,sun4v-pci", sun4v_pci_init },
1da177e4
LT		 207};
208#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
209 sizeof(pci_controller_table[0]))
210
e87dc350 211static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 212{
213 int i;
214
215 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
216 if (!strncmp(model_name,
217 pci_controller_table[i].model_name,
218 namelen)) {
e87dc350 219 pci_controller_table[i].init(dp, model_name);
1da177e4
LT		 220 return 1;
221 }
222 }
1da177e4
LT		 223
224 return 0;
225}
226
e87dc350 227static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 228{
229 int i;
230
231 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
232 if (!strncmp(model_name,
233 pci_controller_table[i].model_name,
234 namelen)) {
235 return 1;
236 }
237 }
238 return 0;
239}
240
e87dc350 241static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
1da177e4 242{
e87dc350 243 struct device_node *dp;
1da177e4
LT		 244 int count = 0;
245
e87dc350
DM		 246 for_each_node_by_name(dp, "pci") {
247 struct property *prop;
1da177e4
LT		 248 int len;
249
e87dc350
DM		 250 prop = of_find_property(dp, "model", &len);
251 if (!prop)
252 prop = of_find_property(dp, "compatible", &len);
253
254 if (prop) {
255 const char *model = prop->value;
1da177e4
LT		 256 int item_len = 0;
257
258 /* Our value may be a multi-valued string in the
259 * case of some compatible properties. For sanity,
e87dc350
DM		 260 * only try the first one.
261 */
262 while (model[item_len] && len) {
1da177e4
LT		 263 len--;
264 item_len++;
265 }
266
e87dc350 267 if (handler(model, item_len, dp))
1da177e4
LT		 268 count++;
269 }
1da177e4
LT		 270 }
271
272 return count;
273}
274
275
276/* Is there some PCI controller in the system? */
277int __init pcic_present(void)
278{
279 return pci_controller_scan(pci_is_controller);
280}
281
8f6a93a1
DM		 282struct pci_iommu_ops *pci_iommu_ops;
283EXPORT_SYMBOL(pci_iommu_ops);
284
285extern struct pci_iommu_ops pci_sun4u_iommu_ops,
286 pci_sun4v_iommu_ops;
287
1da177e4
LT		 288/* Find each controller in the system, attach and initialize
289 * software state structure for each and link into the
290 * pci_controller_root. Setup the controller enough such
291 * that bus scanning can be done.
292 */
293static void __init pci_controller_probe(void)
294{
8f6a93a1
DM		 295 if (tlb_type == hypervisor)
296 pci_iommu_ops = &pci_sun4v_iommu_ops;
297 else
298 pci_iommu_ops = &pci_sun4u_iommu_ops;
299
1da177e4
LT		 300 printk("PCI: Probing for controllers.\n");
301
302 pci_controller_scan(pci_controller_init);
303}
304
a2fb23af
DM		 305static unsigned long pci_parse_of_flags(u32 addr0)
306{
307 unsigned long flags = 0;
308
309 if (addr0 & 0x02000000) {
310 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
311 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
312 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
313 if (addr0 & 0x40000000)
314 flags |= IORESOURCE_PREFETCH
315 | PCI_BASE_ADDRESS_MEM_PREFETCH;
316 } else if (addr0 & 0x01000000)
317 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
318 return flags;
319}
320
321/* The of_device layer has translated all of the assigned-address properties
322 * into physical address resources, we only have to figure out the register
323 * mapping.
324 */
325static void pci_parse_of_addrs(struct of_device *op,
326 struct device_node *node,
327 struct pci_dev *dev)
328{
329 struct resource *op_res;
330 const u32 *addrs;
331 int proplen;
332
333 addrs = of_get_property(node, "assigned-addresses", &proplen);
334 if (!addrs)
335 return;
336 printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
337 op_res = &op->resource[0];
338 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
339 struct resource *res;
340 unsigned long flags;
341 int i;
342
343 flags = pci_parse_of_flags(addrs[0]);
344 if (!flags)
345 continue;
346 i = addrs[0] & 0xff;
347 printk(" start: %lx, end: %lx, i: %x\n",
348 op_res->start, op_res->end, i);
349
350 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
351 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
352 } else if (i == dev->rom_base_reg) {
353 res = &dev->resource[PCI_ROM_RESOURCE];
354 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
355 } else {
356 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
357 continue;
358 }
359 res->start = op_res->start;
360 res->end = op_res->end;
361 res->flags = flags;
362 res->name = pci_name(dev);
363 }
364}
365
366struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
367 struct device_node *node,
368 struct pci_bus *bus, int devfn)
369{
370 struct dev_archdata *sd;
371 struct pci_dev *dev;
372 const char *type;
373
374 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
375 if (!dev)
376 return NULL;
377
378 sd = &dev->dev.archdata;
379 sd->iommu = pbm->iommu;
380 sd->stc = &pbm->stc;
381 sd->host_controller = pbm;
382 sd->prom_node = node;
383 sd->op = of_find_device_by_node(node);
384 sd->msi_num = 0xffffffff;
385
386 type = of_get_property(node, "device_type", NULL);
387 if (type == NULL)
388 type = "";
389
390 printk(" create device, devfn: %x, type: %s\n", devfn, type);
391
392 dev->bus = bus;
393 dev->sysdata = node;
394 dev->dev.parent = bus->bridge;
395 dev->dev.bus = &pci_bus_type;
396 dev->devfn = devfn;
397 dev->multifunction = 0; /* maybe a lie? */
398
399 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
400 dev->device = of_getintprop_default(node, "device-id", 0xffff);
401 dev->subsystem_vendor =
402 of_getintprop_default(node, "subsystem-vendor-id", 0);
403 dev->subsystem_device =
404 of_getintprop_default(node, "subsystem-id", 0);
405
406 dev->cfg_size = pci_cfg_space_size(dev);
407
408 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
409 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
410 dev->class = of_getintprop_default(node, "class-code", 0);
411
412 printk(" class: 0x%x\n", dev->class);
413
414 dev->current_state = 4; /* unknown power state */
415 dev->error_state = pci_channel_io_normal;
416
417 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
418 /* a PCI-PCI bridge */
419 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
420 dev->rom_base_reg = PCI_ROM_ADDRESS1;
421 } else if (!strcmp(type, "cardbus")) {
422 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
423 } else {
424 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
425 dev->rom_base_reg = PCI_ROM_ADDRESS;
426
427 dev->irq = sd->op->irqs[0];
428 if (dev->irq == 0xffffffff)
429 dev->irq = PCI_IRQ_NONE;
430 }
431
432 pci_parse_of_addrs(sd->op, node, dev);
433
434 printk(" adding to system ...\n");
435
436 pci_device_add(dev, bus);
437
438 return dev;
439}
440
441static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
442 struct device_node *node,
443 struct pci_bus *bus);
444
445#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
446
447void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
448 struct device_node *node,
449 struct pci_dev *dev)
450{
451 struct pci_bus *bus;
452 const u32 *busrange, *ranges;
453 int len, i;
454 struct resource *res;
455 unsigned int flags;
456 u64 size;
457
458 printk("of_scan_pci_bridge(%s)\n", node->full_name);
459
460 /* parse bus-range property */
461 busrange = of_get_property(node, "bus-range", &len);
462 if (busrange == NULL || len != 8) {
463 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
464 node->full_name);
465 return;
466 }
467 ranges = of_get_property(node, "ranges", &len);
468 if (ranges == NULL) {
469 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
470 node->full_name);
471 return;
472 }
473
474 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
475 if (!bus) {
476 printk(KERN_ERR "Failed to create pci bus for %s\n",
477 node->full_name);
478 return;
479 }
480
481 bus->primary = dev->bus->number;
482 bus->subordinate = busrange[1];
483 bus->bridge_ctl = 0;
484
485 /* parse ranges property */
486 /* PCI #address-cells == 3 and #size-cells == 2 always */
487 res = &dev->resource[PCI_BRIDGE_RESOURCES];
488 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
489 res->flags = 0;
490 bus->resource[i] = res;
491 ++res;
492 }
493 i = 1;
494 for (; len >= 32; len -= 32, ranges += 8) {
495 struct resource *root;
496
497 flags = pci_parse_of_flags(ranges[0]);
498 size = GET_64BIT(ranges, 6);
499 if (flags == 0 || size == 0)
500 continue;
501 if (flags & IORESOURCE_IO) {
502 res = bus->resource[0];
503 if (res->flags) {
504 printk(KERN_ERR "PCI: ignoring extra I/O range"
505 " for bridge %s\n", node->full_name);
506 continue;
507 }
508 root = &pbm->io_space;
509 } else {
510 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
511 printk(KERN_ERR "PCI: too many memory ranges"
512 " for bridge %s\n", node->full_name);
513 continue;
514 }
515 res = bus->resource[i];
516 ++i;
517 root = &pbm->mem_space;
518 }
519
520 res->start = GET_64BIT(ranges, 1);
521 res->end = res->start + size - 1;
522 res->flags = flags;
523
524 /* Another way to implement this would be to add an of_device
525 * layer routine that can calculate a resource for a given
526 * range property value in a PCI device.
527 */
528 pbm->parent->resource_adjust(dev, res, root);
529 }
530 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
531 bus->number);
532 printk(" bus name: %s\n", bus->name);
533
534 pci_of_scan_bus(pbm, node, bus);
535}
536
537static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
538 struct device_node *node,
539 struct pci_bus *bus)
540{
541 struct device_node *child;
542 const u32 *reg;
543 int reglen, devfn;
544 struct pci_dev *dev;
545
546 printk("PCI: scan_bus[%s] bus no %d\n",
547 node->full_name, bus->number);
548
549 child = NULL;
550 while ((child = of_get_next_child(node, child)) != NULL) {
551 printk(" * %s\n", child->full_name);
552 reg = of_get_property(child, "reg", &reglen);
553 if (reg == NULL || reglen < 20)
554 continue;
555 devfn = (reg[0] >> 8) & 0xff;
556
557 /* create a new pci_dev for this device */
558 dev = of_create_pci_dev(pbm, child, bus, devfn);
559 if (!dev)
560 continue;
561 printk("PCI: dev header type: %x\n", dev->hdr_type);
562
563 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
564 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
565 of_scan_pci_bridge(pbm, child, dev);
566 }
567}
568
569static ssize_t
570show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
571{
572 struct pci_dev *pdev;
573 struct device_node *dp;
574
575 pdev = to_pci_dev(dev);
576 dp = pdev->dev.archdata.prom_node;
577
578 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
579}
580
581static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
582
583static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
584{
585 struct pci_dev *dev;
586 int err;
587
588 list_for_each_entry(dev, &bus->devices, bus_list) {
589 /* we don't really care if we can create this file or
590 * not, but we need to assign the result of the call
591 * or the world will fall under alien invasion and
592 * everybody will be frozen on a spaceship ready to be
593 * eaten on alpha centauri by some green and jelly
594 * humanoid.
595 */
596 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
597 }
598}
599
600struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
601{
602 struct pci_controller_info *p = pbm->parent;
603 struct device_node *node = pbm->prom_node;
604 struct pci_bus *bus;
605
606 printk("PCI: Scanning PBM %s\n", node->full_name);
607
608 /* XXX parent device? XXX */
609 bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
610 if (!bus) {
611 printk(KERN_ERR "Failed to create bus for %s\n",
612 node->full_name);
613 return NULL;
614 }
615 bus->secondary = pbm->pci_first_busno;
616 bus->subordinate = pbm->pci_last_busno;
617
618 bus->resource[0] = &pbm->io_space;
619 bus->resource[1] = &pbm->mem_space;
620
621 pci_of_scan_bus(pbm, node, bus);
622 pci_bus_add_devices(bus);
623 pci_bus_register_of_sysfs(bus);
624
625 return bus;
626}
627
1da177e4
LT		 628static void __init pci_scan_each_controller_bus(void)
629{
630 struct pci_controller_info *p;
631
632 for (p = pci_controller_root; p; p = p->next)
633 p->scan_bus(p);
634}
635
1da177e4
LT		 636extern void power_init(void);
637
638static int __init pcibios_init(void)
639{
640 pci_controller_probe();
641 if (pci_controller_root == NULL)
642 return 0;
643
644 pci_scan_each_controller_bus();
645
1da177e4
LT		 646 isa_init();
647 ebus_init();
1da177e4
LT		 648 power_init();
649
650 return 0;
651}
652
653subsys_initcall(pcibios_init);
654
f6b45da1 655void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
1da177e4
LT		 656{
657 struct pci_pbm_info *pbm = pbus->sysdata;
658
659 /* Generic PCI bus probing sets these to point at
660 * &io{port,mem}_resouce which is wrong for us.
661 */
662 pbus->resource[0] = &pbm->io_space;
663 pbus->resource[1] = &pbm->mem_space;
664}
665
085ae41f 666struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
1da177e4
LT		 667{
668 struct pci_pbm_info *pbm = pdev->bus->sysdata;
085ae41f 669 struct resource *root = NULL;
1da177e4 670
085ae41f 671 if (r->flags & IORESOURCE_IO)
1da177e4 672 root = &pbm->io_space;
085ae41f 673 if (r->flags & IORESOURCE_MEM)
1da177e4
LT		 674 root = &pbm->mem_space;
675
085ae41f 676 return root;
1da177e4
LT		 677}
678
679void pcibios_update_irq(struct pci_dev *pdev, int irq)
680{
681}
682
683void pcibios_align_resource(void *data, struct resource *res,
e31dd6e4 684 resource_size_t size, resource_size_t align)
1da177e4
LT		 685{
686}
687
a2fb23af 688int pcibios_enable_device(struct pci_dev *dev, int mask)
1da177e4 689{
a2fb23af
DM		 690 u16 cmd, oldcmd;
691 int i;
692
693 pci_read_config_word(dev, PCI_COMMAND, &cmd);
694 oldcmd = cmd;
695
696 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
697 struct resource *res = &dev->resource[i];
698
699 /* Only set up the requested stuff */
700 if (!(mask & (1<<i)))
701 continue;
702
703 if (res->flags & IORESOURCE_IO)
704 cmd |= PCI_COMMAND_IO;
705 if (res->flags & IORESOURCE_MEM)
706 cmd |= PCI_COMMAND_MEMORY;
707 }
708
709 if (cmd != oldcmd) {
710 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
711 pci_name(dev), cmd);
712 /* Enable the appropriate bits in the PCI command register. */
713 pci_write_config_word(dev, PCI_COMMAND, cmd);
714 }
1da177e4
LT		 715 return 0;
716}
717
718void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
719 struct resource *res)
720{
721 struct pci_pbm_info *pbm = pdev->bus->sysdata;
722 struct resource zero_res, *root;
723
724 zero_res.start = 0;
725 zero_res.end = 0;
726 zero_res.flags = res->flags;
727
728 if (res->flags & IORESOURCE_IO)
729 root = &pbm->io_space;
730 else
731 root = &pbm->mem_space;
732
733 pbm->parent->resource_adjust(pdev, &zero_res, root);
734
735 region->start = res->start - zero_res.start;
736 region->end = res->end - zero_res.start;
737}
5fdfd42e 738EXPORT_SYMBOL(pcibios_resource_to_bus);
1da177e4
LT		 739
740void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
741 struct pci_bus_region *region)
742{
743 struct pci_pbm_info *pbm = pdev->bus->sysdata;
744 struct resource *root;
745
746 res->start = region->start;
747 res->end = region->end;
748
749 if (res->flags & IORESOURCE_IO)
750 root = &pbm->io_space;
751 else
752 root = &pbm->mem_space;
753
754 pbm->parent->resource_adjust(pdev, res, root);
755}
41290c14 756EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 757
f6b45da1 758char * __devinit pcibios_setup(char *str)
1da177e4 759{
1da177e4
LT		 760 return str;
761}
762
763/* Platform support for /proc/bus/pci/X/Y mmap()s. */
764
765/* If the user uses a host-bridge as the PCI device, he may use
766 * this to perform a raw mmap() of the I/O or MEM space behind
767 * that controller.
768 *
769 * This can be useful for execution of x86 PCI bios initialization code
770 * on a PCI card, like the xfree86 int10 stuff does.
771 */
772static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
773 enum pci_mmap_state mmap_state)
774{
a2fb23af 775 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1da177e4
LT		 776 struct pci_controller_info *p;
777 unsigned long space_size, user_offset, user_size;
778
1da177e4
LT		 779 p = pbm->parent;
780 if (p->pbms_same_domain) {
781 unsigned long lowest, highest;
782
783 lowest = ~0UL; highest = 0UL;
784 if (mmap_state == pci_mmap_io) {
785 if (p->pbm_A.io_space.flags) {
786 lowest = p->pbm_A.io_space.start;
787 highest = p->pbm_A.io_space.end + 1;
788 }
789 if (p->pbm_B.io_space.flags) {
790 if (lowest > p->pbm_B.io_space.start)
791 lowest = p->pbm_B.io_space.start;
792 if (highest < p->pbm_B.io_space.end + 1)
793 highest = p->pbm_B.io_space.end + 1;
794 }
795 space_size = highest - lowest;
796 } else {
797 if (p->pbm_A.mem_space.flags) {
798 lowest = p->pbm_A.mem_space.start;
799 highest = p->pbm_A.mem_space.end + 1;
800 }
801 if (p->pbm_B.mem_space.flags) {
802 if (lowest > p->pbm_B.mem_space.start)
803 lowest = p->pbm_B.mem_space.start;
804 if (highest < p->pbm_B.mem_space.end + 1)
805 highest = p->pbm_B.mem_space.end + 1;
806 }
807 space_size = highest - lowest;
808 }
809 } else {
810 if (mmap_state == pci_mmap_io) {
811 space_size = (pbm->io_space.end -
812 pbm->io_space.start) + 1;
813 } else {
814 space_size = (pbm->mem_space.end -
815 pbm->mem_space.start) + 1;
816 }
817 }
818
819 /* Make sure the request is in range. */
820 user_offset = vma->vm_pgoff << PAGE_SHIFT;
821 user_size = vma->vm_end - vma->vm_start;
822
823 if (user_offset >= space_size ||
824 (user_offset + user_size) > space_size)
825 return -EINVAL;
826
827 if (p->pbms_same_domain) {
828 unsigned long lowest = ~0UL;
829
830 if (mmap_state == pci_mmap_io) {
831 if (p->pbm_A.io_space.flags)
832 lowest = p->pbm_A.io_space.start;
833 if (p->pbm_B.io_space.flags &&
834 lowest > p->pbm_B.io_space.start)
835 lowest = p->pbm_B.io_space.start;
836 } else {
837 if (p->pbm_A.mem_space.flags)
838 lowest = p->pbm_A.mem_space.start;
839 if (p->pbm_B.mem_space.flags &&
840 lowest > p->pbm_B.mem_space.start)
841 lowest = p->pbm_B.mem_space.start;
842 }
843 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
844 } else {
845 if (mmap_state == pci_mmap_io) {
846 vma->vm_pgoff = (pbm->io_space.start +
847 user_offset) >> PAGE_SHIFT;
848 } else {
849 vma->vm_pgoff = (pbm->mem_space.start +
850 user_offset) >> PAGE_SHIFT;
851 }
852 }
853
854 return 0;
855}
856
857/* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
858 * to the 32-bit pci bus offset for DEV requested by the user.
859 *
860 * Basically, the user finds the base address for his device which he wishes
861 * to mmap. They read the 32-bit value from the config space base register,
862 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
863 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
864 *
865 * Returns negative error code on failure, zero on success.
866 */
867static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
868 enum pci_mmap_state mmap_state)
869{
870 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
871 unsigned long user32 = user_offset & pci_memspace_mask;
872 unsigned long largest_base, this_base, addr32;
873 int i;
874
875 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
876 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
877
878 /* Figure out which base address this is for. */
879 largest_base = 0UL;
880 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
881 struct resource *rp = &dev->resource[i];
882
883 /* Active? */
884 if (!rp->flags)
885 continue;
886
887 /* Same type? */
888 if (i == PCI_ROM_RESOURCE) {
889 if (mmap_state != pci_mmap_mem)
890 continue;
891 } else {
892 if ((mmap_state == pci_mmap_io &&
893 (rp->flags & IORESOURCE_IO) == 0) ||
894 (mmap_state == pci_mmap_mem &&
895 (rp->flags & IORESOURCE_MEM) == 0))
896 continue;
897 }
898
899 this_base = rp->start;
900
901 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
902
903 if (mmap_state == pci_mmap_io)
904 addr32 &= 0xffffff;
905
906 if (addr32 <= user32 && this_base > largest_base)
907 largest_base = this_base;
908 }
909
910 if (largest_base == 0UL)
911 return -EINVAL;
912
913 /* Now construct the final physical address. */
914 if (mmap_state == pci_mmap_io)
915 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
916 else
917 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
918
919 return 0;
920}
921
922/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
923 * mapping.
924 */
925static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
926 enum pci_mmap_state mmap_state)
927{
928 vma->vm_flags |= (VM_IO | VM_RESERVED);
929}
930
931/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
932 * device mapping.
933 */
934static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
935 enum pci_mmap_state mmap_state)
936{
a7a6cac2 937 /* Our io_remap_pfn_range takes care of this, do nothing. */
1da177e4
LT		 938}
939
940/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
941 * for this architecture. The region in the process to map is described by vm_start
942 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
943 * The pci device structure is provided so that architectures may make mapping
944 * decisions on a per-device or per-bus basis.
945 *
946 * Returns a negative error code on failure, zero on success.
947 */
948int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
949 enum pci_mmap_state mmap_state,
950 int write_combine)
951{
952 int ret;
953
954 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
955 if (ret < 0)
956 return ret;
957
958 __pci_mmap_set_flags(dev, vma, mmap_state);
959 __pci_mmap_set_pgprot(dev, vma, mmap_state);
960
14778d90 961 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1da177e4
LT		 962 ret = io_remap_pfn_range(vma, vma->vm_start,
963 vma->vm_pgoff,
964 vma->vm_end - vma->vm_start,
965 vma->vm_page_prot);
966 if (ret)
967 return ret;
968
1da177e4
LT		 969 return 0;
970}
971
972/* Return the domain nuber for this pci bus */
973
974int pci_domain_nr(struct pci_bus *pbus)
975{
976 struct pci_pbm_info *pbm = pbus->sysdata;
977 int ret;
978
979 if (pbm == NULL || pbm->parent == NULL) {
980 ret = -ENXIO;
981 } else {
982 struct pci_controller_info *p = pbm->parent;
983
984 ret = p->index;
985 if (p->pbms_same_domain == 0)
986 ret = ((ret << 1) +
987 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
988 }
989
990 return ret;
991}
992EXPORT_SYMBOL(pci_domain_nr);
993
35a17eb6
DM		 994#ifdef CONFIG_PCI_MSI
995int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
996{
a2fb23af 997 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6
DM		 998 struct pci_controller_info *p = pbm->parent;
999 int virt_irq, err;
1000
1001 if (!pbm->msi_num || !p->setup_msi_irq)
1002 return -EINVAL;
1003
1004 err = p->setup_msi_irq(&virt_irq, pdev, desc);
1005 if (err < 0)
1006 return err;
1007
1008 return virt_irq;
1009}
1010
1011void arch_teardown_msi_irq(unsigned int virt_irq)
1012{
abfd336c 1013 struct msi_desc *entry = get_irq_msi(virt_irq);
35a17eb6 1014 struct pci_dev *pdev = entry->dev;
a2fb23af 1015 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6
DM		 1016 struct pci_controller_info *p = pbm->parent;
1017
1018 if (!pbm->msi_num || !p->setup_msi_irq)
1019 return;
1020
1021 return p->teardown_msi_irq(virt_irq, pdev);
1022}
1023#endif /* !(CONFIG_PCI_MSI) */
1024
f6d0f9ea
DM		 1025struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1026{
a2fb23af 1027 return pdev->dev.archdata.prom_node;
f6d0f9ea
DM		 1028}
1029EXPORT_SYMBOL(pci_device_to_OF_node);
1030
1da177e4 1031#endif /* !(CONFIG_PCI) */
Linux 6.x block layer and io_uring tree(s)