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[SPARC64]: Kill pci_controller->base_address_update().
[linux-2.6-block.git] / arch / sparc64 / kernel / pci.c
CommitLineData
a2fb23af 1/* pci.c: UltraSparc PCI controller support.
1da177e4
LT		 2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
a2fb23af
DM		 6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
1da177e4
LT		 9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
17#include <linux/smp_lock.h>
35a17eb6
DM		 18#include <linux/msi.h>
19#include <linux/irq.h>
1da177e4
LT		 20#include <linux/init.h>
21
22#include <asm/uaccess.h>
23#include <asm/pbm.h>
24#include <asm/pgtable.h>
25#include <asm/irq.h>
26#include <asm/ebus.h>
27#include <asm/isa.h>
e87dc350 28#include <asm/prom.h>
01f94c4a 29#include <asm/apb.h>
1da177e4 30
1e8a8cc5
DM		 31#include "pci_impl.h"
32
1da177e4
LT		 33unsigned long pci_memspace_mask = 0xffffffffUL;
34
35#ifndef CONFIG_PCI
36/* A "nop" PCI implementation. */
37asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
38 unsigned long off, unsigned long len,
39 unsigned char *buf)
40{
41 return 0;
42}
43asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
44 unsigned long off, unsigned long len,
45 unsigned char *buf)
46{
47 return 0;
48}
49#else
50
51/* List of all PCI controllers found in the system. */
52struct pci_controller_info *pci_controller_root = NULL;
53
54/* Each PCI controller found gets a unique index. */
55int pci_num_controllers = 0;
56
1da177e4
LT		 57volatile int pci_poke_in_progress;
58volatile int pci_poke_cpu = -1;
59volatile int pci_poke_faulted;
60
61static DEFINE_SPINLOCK(pci_poke_lock);
62
63void pci_config_read8(u8 *addr, u8 *ret)
64{
65 unsigned long flags;
66 u8 byte;
67
68 spin_lock_irqsave(&pci_poke_lock, flags);
69 pci_poke_cpu = smp_processor_id();
70 pci_poke_in_progress = 1;
71 pci_poke_faulted = 0;
72 __asm__ __volatile__("membar #Sync\n\t"
73 "lduba [%1] %2, %0\n\t"
74 "membar #Sync"
75 : "=r" (byte)
76 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
77 : "memory");
78 pci_poke_in_progress = 0;
79 pci_poke_cpu = -1;
80 if (!pci_poke_faulted)
81 *ret = byte;
82 spin_unlock_irqrestore(&pci_poke_lock, flags);
83}
84
85void pci_config_read16(u16 *addr, u16 *ret)
86{
87 unsigned long flags;
88 u16 word;
89
90 spin_lock_irqsave(&pci_poke_lock, flags);
91 pci_poke_cpu = smp_processor_id();
92 pci_poke_in_progress = 1;
93 pci_poke_faulted = 0;
94 __asm__ __volatile__("membar #Sync\n\t"
95 "lduha [%1] %2, %0\n\t"
96 "membar #Sync"
97 : "=r" (word)
98 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
99 : "memory");
100 pci_poke_in_progress = 0;
101 pci_poke_cpu = -1;
102 if (!pci_poke_faulted)
103 *ret = word;
104 spin_unlock_irqrestore(&pci_poke_lock, flags);
105}
106
107void pci_config_read32(u32 *addr, u32 *ret)
108{
109 unsigned long flags;
110 u32 dword;
111
112 spin_lock_irqsave(&pci_poke_lock, flags);
113 pci_poke_cpu = smp_processor_id();
114 pci_poke_in_progress = 1;
115 pci_poke_faulted = 0;
116 __asm__ __volatile__("membar #Sync\n\t"
117 "lduwa [%1] %2, %0\n\t"
118 "membar #Sync"
119 : "=r" (dword)
120 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
121 : "memory");
122 pci_poke_in_progress = 0;
123 pci_poke_cpu = -1;
124 if (!pci_poke_faulted)
125 *ret = dword;
126 spin_unlock_irqrestore(&pci_poke_lock, flags);
127}
128
129void pci_config_write8(u8 *addr, u8 val)
130{
131 unsigned long flags;
132
133 spin_lock_irqsave(&pci_poke_lock, flags);
134 pci_poke_cpu = smp_processor_id();
135 pci_poke_in_progress = 1;
136 pci_poke_faulted = 0;
137 __asm__ __volatile__("membar #Sync\n\t"
138 "stba %0, [%1] %2\n\t"
139 "membar #Sync"
140 : /* no outputs */
141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 : "memory");
143 pci_poke_in_progress = 0;
144 pci_poke_cpu = -1;
145 spin_unlock_irqrestore(&pci_poke_lock, flags);
146}
147
148void pci_config_write16(u16 *addr, u16 val)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&pci_poke_lock, flags);
153 pci_poke_cpu = smp_processor_id();
154 pci_poke_in_progress = 1;
155 pci_poke_faulted = 0;
156 __asm__ __volatile__("membar #Sync\n\t"
157 "stha %0, [%1] %2\n\t"
158 "membar #Sync"
159 : /* no outputs */
160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 : "memory");
162 pci_poke_in_progress = 0;
163 pci_poke_cpu = -1;
164 spin_unlock_irqrestore(&pci_poke_lock, flags);
165}
166
167void pci_config_write32(u32 *addr, u32 val)
168{
169 unsigned long flags;
170
171 spin_lock_irqsave(&pci_poke_lock, flags);
172 pci_poke_cpu = smp_processor_id();
173 pci_poke_in_progress = 1;
174 pci_poke_faulted = 0;
175 __asm__ __volatile__("membar #Sync\n\t"
176 "stwa %0, [%1] %2\n\t"
177 "membar #Sync"
178 : /* no outputs */
179 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
180 : "memory");
181 pci_poke_in_progress = 0;
182 pci_poke_cpu = -1;
183 spin_unlock_irqrestore(&pci_poke_lock, flags);
184}
185
186/* Probe for all PCI controllers in the system. */
e87dc350
DM		 187extern void sabre_init(struct device_node *, const char *);
188extern void psycho_init(struct device_node *, const char *);
189extern void schizo_init(struct device_node *, const char *);
190extern void schizo_plus_init(struct device_node *, const char *);
191extern void tomatillo_init(struct device_node *, const char *);
192extern void sun4v_pci_init(struct device_node *, const char *);
1da177e4
LT		 193
194static struct {
195 char *model_name;
e87dc350 196 void (*init)(struct device_node *, const char *);
1da177e4
LT		 197} pci_controller_table[] __initdata = {
198 { "SUNW,sabre", sabre_init },
199 { "pci108e,a000", sabre_init },
200 { "pci108e,a001", sabre_init },
201 { "SUNW,psycho", psycho_init },
202 { "pci108e,8000", psycho_init },
203 { "SUNW,schizo", schizo_init },
204 { "pci108e,8001", schizo_init },
205 { "SUNW,schizo+", schizo_plus_init },
206 { "pci108e,8002", schizo_plus_init },
207 { "SUNW,tomatillo", tomatillo_init },
208 { "pci108e,a801", tomatillo_init },
8f6a93a1 209 { "SUNW,sun4v-pci", sun4v_pci_init },
1da177e4
LT		 210};
211#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
212 sizeof(pci_controller_table[0]))
213
e87dc350 214static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 215{
216 int i;
217
218 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
219 if (!strncmp(model_name,
220 pci_controller_table[i].model_name,
221 namelen)) {
e87dc350 222 pci_controller_table[i].init(dp, model_name);
1da177e4
LT		 223 return 1;
224 }
225 }
1da177e4
LT		 226
227 return 0;
228}
229
e87dc350 230static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 231{
232 int i;
233
234 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
235 if (!strncmp(model_name,
236 pci_controller_table[i].model_name,
237 namelen)) {
238 return 1;
239 }
240 }
241 return 0;
242}
243
e87dc350 244static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
1da177e4 245{
e87dc350 246 struct device_node *dp;
1da177e4
LT		 247 int count = 0;
248
e87dc350
DM		 249 for_each_node_by_name(dp, "pci") {
250 struct property *prop;
1da177e4
LT		 251 int len;
252
e87dc350
DM		 253 prop = of_find_property(dp, "model", &len);
254 if (!prop)
255 prop = of_find_property(dp, "compatible", &len);
256
257 if (prop) {
258 const char *model = prop->value;
1da177e4
LT		 259 int item_len = 0;
260
261 /* Our value may be a multi-valued string in the
262 * case of some compatible properties. For sanity,
e87dc350
DM		 263 * only try the first one.
264 */
265 while (model[item_len] && len) {
1da177e4
LT		 266 len--;
267 item_len++;
268 }
269
e87dc350 270 if (handler(model, item_len, dp))
1da177e4
LT		 271 count++;
272 }
1da177e4
LT		 273 }
274
275 return count;
276}
277
278
279/* Is there some PCI controller in the system? */
280int __init pcic_present(void)
281{
282 return pci_controller_scan(pci_is_controller);
283}
284
8f6a93a1
DM		 285struct pci_iommu_ops *pci_iommu_ops;
286EXPORT_SYMBOL(pci_iommu_ops);
287
288extern struct pci_iommu_ops pci_sun4u_iommu_ops,
289 pci_sun4v_iommu_ops;
290
1da177e4
LT		 291/* Find each controller in the system, attach and initialize
292 * software state structure for each and link into the
293 * pci_controller_root. Setup the controller enough such
294 * that bus scanning can be done.
295 */
296static void __init pci_controller_probe(void)
297{
8f6a93a1
DM		 298 if (tlb_type == hypervisor)
299 pci_iommu_ops = &pci_sun4v_iommu_ops;
300 else
301 pci_iommu_ops = &pci_sun4u_iommu_ops;
302
1da177e4
LT		 303 printk("PCI: Probing for controllers.\n");
304
305 pci_controller_scan(pci_controller_init);
306}
307
a2fb23af
DM		 308static unsigned long pci_parse_of_flags(u32 addr0)
309{
310 unsigned long flags = 0;
311
312 if (addr0 & 0x02000000) {
313 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
314 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
315 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
316 if (addr0 & 0x40000000)
317 flags |= IORESOURCE_PREFETCH
318 | PCI_BASE_ADDRESS_MEM_PREFETCH;
319 } else if (addr0 & 0x01000000)
320 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
321 return flags;
322}
323
324/* The of_device layer has translated all of the assigned-address properties
325 * into physical address resources, we only have to figure out the register
326 * mapping.
327 */
328static void pci_parse_of_addrs(struct of_device *op,
329 struct device_node *node,
330 struct pci_dev *dev)
331{
332 struct resource *op_res;
333 const u32 *addrs;
334 int proplen;
335
336 addrs = of_get_property(node, "assigned-addresses", &proplen);
337 if (!addrs)
338 return;
339 printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
340 op_res = &op->resource[0];
341 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
342 struct resource *res;
343 unsigned long flags;
344 int i;
345
346 flags = pci_parse_of_flags(addrs[0]);
347 if (!flags)
348 continue;
349 i = addrs[0] & 0xff;
350 printk(" start: %lx, end: %lx, i: %x\n",
351 op_res->start, op_res->end, i);
352
353 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
354 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
355 } else if (i == dev->rom_base_reg) {
356 res = &dev->resource[PCI_ROM_RESOURCE];
357 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
358 } else {
359 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
360 continue;
361 }
362 res->start = op_res->start;
363 res->end = op_res->end;
364 res->flags = flags;
365 res->name = pci_name(dev);
366 }
367}
368
369struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
370 struct device_node *node,
371 struct pci_bus *bus, int devfn)
372{
373 struct dev_archdata *sd;
374 struct pci_dev *dev;
375 const char *type;
01f94c4a 376 u32 class;
a2fb23af
DM		 377
378 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
379 if (!dev)
380 return NULL;
381
382 sd = &dev->dev.archdata;
383 sd->iommu = pbm->iommu;
384 sd->stc = &pbm->stc;
385 sd->host_controller = pbm;
386 sd->prom_node = node;
387 sd->op = of_find_device_by_node(node);
388 sd->msi_num = 0xffffffff;
389
390 type = of_get_property(node, "device_type", NULL);
391 if (type == NULL)
392 type = "";
393
394 printk(" create device, devfn: %x, type: %s\n", devfn, type);
395
396 dev->bus = bus;
397 dev->sysdata = node;
398 dev->dev.parent = bus->bridge;
399 dev->dev.bus = &pci_bus_type;
400 dev->devfn = devfn;
401 dev->multifunction = 0; /* maybe a lie? */
402
403 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
404 dev->device = of_getintprop_default(node, "device-id", 0xffff);
405 dev->subsystem_vendor =
406 of_getintprop_default(node, "subsystem-vendor-id", 0);
407 dev->subsystem_device =
408 of_getintprop_default(node, "subsystem-id", 0);
409
410 dev->cfg_size = pci_cfg_space_size(dev);
411
412 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
413 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
01f94c4a
DM		 414
415 /* dev->class = of_getintprop_default(node, "class-code", 0); */
416 /* We can't actually use the firmware value, we have to read what
417 * is in the register right now. One reason is that in the case
418 * of IDE interfaces the firmware can sample the value before the
419 * the IDE interface is programmed into native mode.
420 */
421 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
422 dev->class = class >> 8;
a2fb23af
DM		 423
424 printk(" class: 0x%x\n", dev->class);
425
426 dev->current_state = 4; /* unknown power state */
427 dev->error_state = pci_channel_io_normal;
428
429 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
430 /* a PCI-PCI bridge */
431 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
432 dev->rom_base_reg = PCI_ROM_ADDRESS1;
433 } else if (!strcmp(type, "cardbus")) {
434 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
435 } else {
436 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
437 dev->rom_base_reg = PCI_ROM_ADDRESS;
438
439 dev->irq = sd->op->irqs[0];
440 if (dev->irq == 0xffffffff)
441 dev->irq = PCI_IRQ_NONE;
442 }
443
444 pci_parse_of_addrs(sd->op, node, dev);
445
446 printk(" adding to system ...\n");
447
448 pci_device_add(dev, bus);
449
450 return dev;
451}
452
01f94c4a
DM		 453static void __init apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
454{
455 u32 idx, first, last;
456
457 first = 8;
458 last = 0;
459 for (idx = 0; idx < 8; idx++) {
460 if ((map & (1 << idx)) != 0) {
461 if (first > idx)
462 first = idx;
463 if (last < idx)
464 last = idx;
465 }
466 }
467
468 *first_p = first;
469 *last_p = last;
470}
471
0bae5f81
DM		 472static void __init pci_resource_adjust(struct resource *res,
473 struct resource *root)
474{
475 res->start += root->start;
476 res->end += root->start;
477}
478
01f94c4a
DM		 479/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
480 * a proper 'ranges' property.
481 */
482static void __init apb_fake_ranges(struct pci_dev *dev,
483 struct pci_bus *bus,
484 struct pci_pbm_info *pbm)
485{
486 struct resource *res;
487 u32 first, last;
488 u8 map;
489
490 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
491 apb_calc_first_last(map, &first, &last);
492 res = bus->resource[0];
493 res->start = (first << 21);
494 res->end = (last << 21) + ((1 << 21) - 1);
495 res->flags = IORESOURCE_IO;
0bae5f81 496 pci_resource_adjust(res, &pbm->io_space);
01f94c4a
DM		 497
498 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
499 apb_calc_first_last(map, &first, &last);
500 res = bus->resource[1];
501 res->start = (first << 21);
502 res->end = (last << 21) + ((1 << 21) - 1);
503 res->flags = IORESOURCE_MEM;
0bae5f81 504 pci_resource_adjust(res, &pbm->mem_space);
01f94c4a
DM		 505}
506
a2fb23af
DM		 507static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
508 struct device_node *node,
509 struct pci_bus *bus);
510
511#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
512
513void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
514 struct device_node *node,
515 struct pci_dev *dev)
516{
517 struct pci_bus *bus;
518 const u32 *busrange, *ranges;
01f94c4a 519 int len, i, simba;
a2fb23af
DM		 520 struct resource *res;
521 unsigned int flags;
522 u64 size;
523
524 printk("of_scan_pci_bridge(%s)\n", node->full_name);
525
526 /* parse bus-range property */
527 busrange = of_get_property(node, "bus-range", &len);
528 if (busrange == NULL || len != 8) {
529 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
530 node->full_name);
531 return;
532 }
533 ranges = of_get_property(node, "ranges", &len);
01f94c4a 534 simba = 0;
a2fb23af 535 if (ranges == NULL) {
01f94c4a
DM		 536 char *model = of_get_property(node, "model", NULL);
537 if (model && !strcmp(model, "SUNW,simba")) {
538 simba = 1;
539 } else {
540 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
541 node->full_name);
542 return;
543 }
a2fb23af
DM		 544 }
545
546 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
547 if (!bus) {
548 printk(KERN_ERR "Failed to create pci bus for %s\n",
549 node->full_name);
550 return;
551 }
552
553 bus->primary = dev->bus->number;
554 bus->subordinate = busrange[1];
555 bus->bridge_ctl = 0;
556
01f94c4a 557 /* parse ranges property, or cook one up by hand for Simba */
a2fb23af
DM		 558 /* PCI #address-cells == 3 and #size-cells == 2 always */
559 res = &dev->resource[PCI_BRIDGE_RESOURCES];
560 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
561 res->flags = 0;
562 bus->resource[i] = res;
563 ++res;
564 }
01f94c4a
DM		 565 if (simba) {
566 apb_fake_ranges(dev, bus, pbm);
567 goto simba_cont;
568 }
a2fb23af
DM		 569 i = 1;
570 for (; len >= 32; len -= 32, ranges += 8) {
571 struct resource *root;
572
573 flags = pci_parse_of_flags(ranges[0]);
574 size = GET_64BIT(ranges, 6);
575 if (flags == 0 || size == 0)
576 continue;
577 if (flags & IORESOURCE_IO) {
578 res = bus->resource[0];
579 if (res->flags) {
580 printk(KERN_ERR "PCI: ignoring extra I/O range"
581 " for bridge %s\n", node->full_name);
582 continue;
583 }
584 root = &pbm->io_space;
585 } else {
586 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
587 printk(KERN_ERR "PCI: too many memory ranges"
588 " for bridge %s\n", node->full_name);
589 continue;
590 }
591 res = bus->resource[i];
592 ++i;
593 root = &pbm->mem_space;
594 }
595
596 res->start = GET_64BIT(ranges, 1);
597 res->end = res->start + size - 1;
598 res->flags = flags;
599
600 /* Another way to implement this would be to add an of_device
601 * layer routine that can calculate a resource for a given
602 * range property value in a PCI device.
603 */
0bae5f81 604 pci_resource_adjust(res, root);
a2fb23af 605 }
01f94c4a 606simba_cont:
a2fb23af
DM		 607 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
608 bus->number);
609 printk(" bus name: %s\n", bus->name);
610
611 pci_of_scan_bus(pbm, node, bus);
612}
613
614static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
615 struct device_node *node,
616 struct pci_bus *bus)
617{
618 struct device_node *child;
619 const u32 *reg;
620 int reglen, devfn;
621 struct pci_dev *dev;
622
623 printk("PCI: scan_bus[%s] bus no %d\n",
624 node->full_name, bus->number);
625
626 child = NULL;
627 while ((child = of_get_next_child(node, child)) != NULL) {
628 printk(" * %s\n", child->full_name);
629 reg = of_get_property(child, "reg", &reglen);
630 if (reg == NULL || reglen < 20)
631 continue;
632 devfn = (reg[0] >> 8) & 0xff;
633
634 /* create a new pci_dev for this device */
635 dev = of_create_pci_dev(pbm, child, bus, devfn);
636 if (!dev)
637 continue;
638 printk("PCI: dev header type: %x\n", dev->hdr_type);
639
640 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
641 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
642 of_scan_pci_bridge(pbm, child, dev);
643 }
644}
645
646static ssize_t
647show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
648{
649 struct pci_dev *pdev;
650 struct device_node *dp;
651
652 pdev = to_pci_dev(dev);
653 dp = pdev->dev.archdata.prom_node;
654
655 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
656}
657
658static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
659
660static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
661{
662 struct pci_dev *dev;
a378fd0e 663 struct pci_bus *child_bus;
a2fb23af
DM		 664 int err;
665
666 list_for_each_entry(dev, &bus->devices, bus_list) {
667 /* we don't really care if we can create this file or
668 * not, but we need to assign the result of the call
669 * or the world will fall under alien invasion and
670 * everybody will be frozen on a spaceship ready to be
671 * eaten on alpha centauri by some green and jelly
672 * humanoid.
673 */
674 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
675 }
a378fd0e
DM		 676 list_for_each_entry(child_bus, &bus->children, node)
677 pci_bus_register_of_sysfs(child_bus);
a2fb23af
DM		 678}
679
680struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
681{
682 struct pci_controller_info *p = pbm->parent;
683 struct device_node *node = pbm->prom_node;
684 struct pci_bus *bus;
685
686 printk("PCI: Scanning PBM %s\n", node->full_name);
687
688 /* XXX parent device? XXX */
689 bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
690 if (!bus) {
691 printk(KERN_ERR "Failed to create bus for %s\n",
692 node->full_name);
693 return NULL;
694 }
695 bus->secondary = pbm->pci_first_busno;
696 bus->subordinate = pbm->pci_last_busno;
697
698 bus->resource[0] = &pbm->io_space;
699 bus->resource[1] = &pbm->mem_space;
700
701 pci_of_scan_bus(pbm, node, bus);
702 pci_bus_add_devices(bus);
703 pci_bus_register_of_sysfs(bus);
704
705 return bus;
706}
707
1da177e4
LT		 708static void __init pci_scan_each_controller_bus(void)
709{
710 struct pci_controller_info *p;
711
712 for (p = pci_controller_root; p; p = p->next)
713 p->scan_bus(p);
714}
715
1da177e4
LT		 716extern void power_init(void);
717
718static int __init pcibios_init(void)
719{
720 pci_controller_probe();
721 if (pci_controller_root == NULL)
722 return 0;
723
724 pci_scan_each_controller_bus();
725
1da177e4
LT		 726 isa_init();
727 ebus_init();
1da177e4
LT		 728 power_init();
729
730 return 0;
731}
732
733subsys_initcall(pcibios_init);
734
f6b45da1 735void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
1da177e4
LT		 736{
737 struct pci_pbm_info *pbm = pbus->sysdata;
738
739 /* Generic PCI bus probing sets these to point at
740 * &io{port,mem}_resouce which is wrong for us.
741 */
742 pbus->resource[0] = &pbm->io_space;
743 pbus->resource[1] = &pbm->mem_space;
744}
745
085ae41f 746struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
1da177e4
LT		 747{
748 struct pci_pbm_info *pbm = pdev->bus->sysdata;
085ae41f 749 struct resource *root = NULL;
1da177e4 750
085ae41f 751 if (r->flags & IORESOURCE_IO)
1da177e4 752 root = &pbm->io_space;
085ae41f 753 if (r->flags & IORESOURCE_MEM)
1da177e4
LT		 754 root = &pbm->mem_space;
755
085ae41f 756 return root;
1da177e4
LT		 757}
758
759void pcibios_update_irq(struct pci_dev *pdev, int irq)
760{
761}
762
763void pcibios_align_resource(void *data, struct resource *res,
e31dd6e4 764 resource_size_t size, resource_size_t align)
1da177e4
LT		 765{
766}
767
a2fb23af 768int pcibios_enable_device(struct pci_dev *dev, int mask)
1da177e4 769{
a2fb23af
DM		 770 u16 cmd, oldcmd;
771 int i;
772
773 pci_read_config_word(dev, PCI_COMMAND, &cmd);
774 oldcmd = cmd;
775
776 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
777 struct resource *res = &dev->resource[i];
778
779 /* Only set up the requested stuff */
780 if (!(mask & (1<<i)))
781 continue;
782
783 if (res->flags & IORESOURCE_IO)
784 cmd |= PCI_COMMAND_IO;
785 if (res->flags & IORESOURCE_MEM)
786 cmd |= PCI_COMMAND_MEMORY;
787 }
788
789 if (cmd != oldcmd) {
790 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
791 pci_name(dev), cmd);
792 /* Enable the appropriate bits in the PCI command register. */
793 pci_write_config_word(dev, PCI_COMMAND, cmd);
794 }
1da177e4
LT		 795 return 0;
796}
797
798void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
799 struct resource *res)
800{
801 struct pci_pbm_info *pbm = pdev->bus->sysdata;
802 struct resource zero_res, *root;
803
804 zero_res.start = 0;
805 zero_res.end = 0;
806 zero_res.flags = res->flags;
807
808 if (res->flags & IORESOURCE_IO)
809 root = &pbm->io_space;
810 else
811 root = &pbm->mem_space;
812
0bae5f81 813 pci_resource_adjust(&zero_res, root);
1da177e4
LT		 814
815 region->start = res->start - zero_res.start;
816 region->end = res->end - zero_res.start;
817}
5fdfd42e 818EXPORT_SYMBOL(pcibios_resource_to_bus);
1da177e4
LT		 819
820void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
821 struct pci_bus_region *region)
822{
823 struct pci_pbm_info *pbm = pdev->bus->sysdata;
824 struct resource *root;
825
826 res->start = region->start;
827 res->end = region->end;
828
829 if (res->flags & IORESOURCE_IO)
830 root = &pbm->io_space;
831 else
832 root = &pbm->mem_space;
833
0bae5f81 834 pci_resource_adjust(res, root);
1da177e4 835}
41290c14 836EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 837
f6b45da1 838char * __devinit pcibios_setup(char *str)
1da177e4 839{
1da177e4
LT		 840 return str;
841}
842
843/* Platform support for /proc/bus/pci/X/Y mmap()s. */
844
845/* If the user uses a host-bridge as the PCI device, he may use
846 * this to perform a raw mmap() of the I/O or MEM space behind
847 * that controller.
848 *
849 * This can be useful for execution of x86 PCI bios initialization code
850 * on a PCI card, like the xfree86 int10 stuff does.
851 */
852static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
853 enum pci_mmap_state mmap_state)
854{
a2fb23af 855 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1da177e4
LT		 856 struct pci_controller_info *p;
857 unsigned long space_size, user_offset, user_size;
858
1da177e4
LT		 859 p = pbm->parent;
860 if (p->pbms_same_domain) {
861 unsigned long lowest, highest;
862
863 lowest = ~0UL; highest = 0UL;
864 if (mmap_state == pci_mmap_io) {
865 if (p->pbm_A.io_space.flags) {
866 lowest = p->pbm_A.io_space.start;
867 highest = p->pbm_A.io_space.end + 1;
868 }
869 if (p->pbm_B.io_space.flags) {
870 if (lowest > p->pbm_B.io_space.start)
871 lowest = p->pbm_B.io_space.start;
872 if (highest < p->pbm_B.io_space.end + 1)
873 highest = p->pbm_B.io_space.end + 1;
874 }
875 space_size = highest - lowest;
876 } else {
877 if (p->pbm_A.mem_space.flags) {
878 lowest = p->pbm_A.mem_space.start;
879 highest = p->pbm_A.mem_space.end + 1;
880 }
881 if (p->pbm_B.mem_space.flags) {
882 if (lowest > p->pbm_B.mem_space.start)
883 lowest = p->pbm_B.mem_space.start;
884 if (highest < p->pbm_B.mem_space.end + 1)
885 highest = p->pbm_B.mem_space.end + 1;
886 }
887 space_size = highest - lowest;
888 }
889 } else {
890 if (mmap_state == pci_mmap_io) {
891 space_size = (pbm->io_space.end -
892 pbm->io_space.start) + 1;
893 } else {
894 space_size = (pbm->mem_space.end -
895 pbm->mem_space.start) + 1;
896 }
897 }
898
899 /* Make sure the request is in range. */
900 user_offset = vma->vm_pgoff << PAGE_SHIFT;
901 user_size = vma->vm_end - vma->vm_start;
902
903 if (user_offset >= space_size ||
904 (user_offset + user_size) > space_size)
905 return -EINVAL;
906
907 if (p->pbms_same_domain) {
908 unsigned long lowest = ~0UL;
909
910 if (mmap_state == pci_mmap_io) {
911 if (p->pbm_A.io_space.flags)
912 lowest = p->pbm_A.io_space.start;
913 if (p->pbm_B.io_space.flags &&
914 lowest > p->pbm_B.io_space.start)
915 lowest = p->pbm_B.io_space.start;
916 } else {
917 if (p->pbm_A.mem_space.flags)
918 lowest = p->pbm_A.mem_space.start;
919 if (p->pbm_B.mem_space.flags &&
920 lowest > p->pbm_B.mem_space.start)
921 lowest = p->pbm_B.mem_space.start;
922 }
923 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
924 } else {
925 if (mmap_state == pci_mmap_io) {
926 vma->vm_pgoff = (pbm->io_space.start +
927 user_offset) >> PAGE_SHIFT;
928 } else {
929 vma->vm_pgoff = (pbm->mem_space.start +
930 user_offset) >> PAGE_SHIFT;
931 }
932 }
933
934 return 0;
935}
936
937/* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
938 * to the 32-bit pci bus offset for DEV requested by the user.
939 *
940 * Basically, the user finds the base address for his device which he wishes
941 * to mmap. They read the 32-bit value from the config space base register,
942 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
943 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
944 *
945 * Returns negative error code on failure, zero on success.
946 */
947static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
948 enum pci_mmap_state mmap_state)
949{
950 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
951 unsigned long user32 = user_offset & pci_memspace_mask;
952 unsigned long largest_base, this_base, addr32;
953 int i;
954
955 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
956 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
957
958 /* Figure out which base address this is for. */
959 largest_base = 0UL;
960 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
961 struct resource *rp = &dev->resource[i];
962
963 /* Active? */
964 if (!rp->flags)
965 continue;
966
967 /* Same type? */
968 if (i == PCI_ROM_RESOURCE) {
969 if (mmap_state != pci_mmap_mem)
970 continue;
971 } else {
972 if ((mmap_state == pci_mmap_io &&
973 (rp->flags & IORESOURCE_IO) == 0) ||
974 (mmap_state == pci_mmap_mem &&
975 (rp->flags & IORESOURCE_MEM) == 0))
976 continue;
977 }
978
979 this_base = rp->start;
980
981 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
982
983 if (mmap_state == pci_mmap_io)
984 addr32 &= 0xffffff;
985
986 if (addr32 <= user32 && this_base > largest_base)
987 largest_base = this_base;
988 }
989
990 if (largest_base == 0UL)
991 return -EINVAL;
992
993 /* Now construct the final physical address. */
994 if (mmap_state == pci_mmap_io)
995 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
996 else
997 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
998
999 return 0;
1000}
1001
1002/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1003 * mapping.
1004 */
1005static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1006 enum pci_mmap_state mmap_state)
1007{
1008 vma->vm_flags |= (VM_IO | VM_RESERVED);
1009}
1010
1011/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1012 * device mapping.
1013 */
1014static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1015 enum pci_mmap_state mmap_state)
1016{
a7a6cac2 1017 /* Our io_remap_pfn_range takes care of this, do nothing. */
1da177e4
LT		 1018}
1019
1020/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1021 * for this architecture. The region in the process to map is described by vm_start
1022 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1023 * The pci device structure is provided so that architectures may make mapping
1024 * decisions on a per-device or per-bus basis.
1025 *
1026 * Returns a negative error code on failure, zero on success.
1027 */
1028int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1029 enum pci_mmap_state mmap_state,
1030 int write_combine)
1031{
1032 int ret;
1033
1034 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1035 if (ret < 0)
1036 return ret;
1037
1038 __pci_mmap_set_flags(dev, vma, mmap_state);
1039 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1040
14778d90 1041 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1da177e4
LT		 1042 ret = io_remap_pfn_range(vma, vma->vm_start,
1043 vma->vm_pgoff,
1044 vma->vm_end - vma->vm_start,
1045 vma->vm_page_prot);
1046 if (ret)
1047 return ret;
1048
1da177e4
LT		 1049 return 0;
1050}
1051
1052/* Return the domain nuber for this pci bus */
1053
1054int pci_domain_nr(struct pci_bus *pbus)
1055{
1056 struct pci_pbm_info *pbm = pbus->sysdata;
1057 int ret;
1058
1059 if (pbm == NULL || pbm->parent == NULL) {
1060 ret = -ENXIO;
1061 } else {
1062 struct pci_controller_info *p = pbm->parent;
1063
1064 ret = p->index;
1065 if (p->pbms_same_domain == 0)
1066 ret = ((ret << 1) +
1067 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
1068 }
1069
1070 return ret;
1071}
1072EXPORT_SYMBOL(pci_domain_nr);
1073
35a17eb6
DM		 1074#ifdef CONFIG_PCI_MSI
1075int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1076{
a2fb23af 1077 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6
DM		 1078 struct pci_controller_info *p = pbm->parent;
1079 int virt_irq, err;
1080
1081 if (!pbm->msi_num || !p->setup_msi_irq)
1082 return -EINVAL;
1083
1084 err = p->setup_msi_irq(&virt_irq, pdev, desc);
1085 if (err < 0)
1086 return err;
1087
1088 return virt_irq;
1089}
1090
1091void arch_teardown_msi_irq(unsigned int virt_irq)
1092{
abfd336c 1093 struct msi_desc *entry = get_irq_msi(virt_irq);
35a17eb6 1094 struct pci_dev *pdev = entry->dev;
a2fb23af 1095 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6
DM		 1096 struct pci_controller_info *p = pbm->parent;
1097
1098 if (!pbm->msi_num || !p->setup_msi_irq)
1099 return;
1100
1101 return p->teardown_msi_irq(virt_irq, pdev);
1102}
1103#endif /* !(CONFIG_PCI_MSI) */
1104
f6d0f9ea
DM		 1105struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1106{
a2fb23af 1107 return pdev->dev.archdata.prom_node;
f6d0f9ea
DM		 1108}
1109EXPORT_SYMBOL(pci_device_to_OF_node);
1110
1da177e4 1111#endif /* !(CONFIG_PCI) */
Linux 6.x block layer and io_uring tree(s)