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[SPARC64]: Use 'unsigned long' for port argument to I/O string ops.
[linux-2.6-block.git] / arch / sparc64 / kernel / pci.c
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1da177e4
LT		 1/* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $
2 * pci.c: UltraSparc PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 */
8
9#include <linux/config.h>
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/sched.h>
14#include <linux/capability.h>
15#include <linux/errno.h>
16#include <linux/smp_lock.h>
17#include <linux/init.h>
18
19#include <asm/uaccess.h>
20#include <asm/pbm.h>
21#include <asm/pgtable.h>
22#include <asm/irq.h>
23#include <asm/ebus.h>
24#include <asm/isa.h>
25
26unsigned long pci_memspace_mask = 0xffffffffUL;
27
28#ifndef CONFIG_PCI
29/* A "nop" PCI implementation. */
30asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
31 unsigned long off, unsigned long len,
32 unsigned char *buf)
33{
34 return 0;
35}
36asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
37 unsigned long off, unsigned long len,
38 unsigned char *buf)
39{
40 return 0;
41}
42#else
43
44/* List of all PCI controllers found in the system. */
45struct pci_controller_info *pci_controller_root = NULL;
46
47/* Each PCI controller found gets a unique index. */
48int pci_num_controllers = 0;
49
50/* At boot time the user can give the kernel a command
51 * line option which controls if and how PCI devices
52 * are reordered at PCI bus probing time.
53 */
54int pci_device_reorder = 0;
55
56volatile int pci_poke_in_progress;
57volatile int pci_poke_cpu = -1;
58volatile int pci_poke_faulted;
59
60static DEFINE_SPINLOCK(pci_poke_lock);
61
62void pci_config_read8(u8 *addr, u8 *ret)
63{
64 unsigned long flags;
65 u8 byte;
66
67 spin_lock_irqsave(&pci_poke_lock, flags);
68 pci_poke_cpu = smp_processor_id();
69 pci_poke_in_progress = 1;
70 pci_poke_faulted = 0;
71 __asm__ __volatile__("membar #Sync\n\t"
72 "lduba [%1] %2, %0\n\t"
73 "membar #Sync"
74 : "=r" (byte)
75 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
76 : "memory");
77 pci_poke_in_progress = 0;
78 pci_poke_cpu = -1;
79 if (!pci_poke_faulted)
80 *ret = byte;
81 spin_unlock_irqrestore(&pci_poke_lock, flags);
82}
83
84void pci_config_read16(u16 *addr, u16 *ret)
85{
86 unsigned long flags;
87 u16 word;
88
89 spin_lock_irqsave(&pci_poke_lock, flags);
90 pci_poke_cpu = smp_processor_id();
91 pci_poke_in_progress = 1;
92 pci_poke_faulted = 0;
93 __asm__ __volatile__("membar #Sync\n\t"
94 "lduha [%1] %2, %0\n\t"
95 "membar #Sync"
96 : "=r" (word)
97 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
98 : "memory");
99 pci_poke_in_progress = 0;
100 pci_poke_cpu = -1;
101 if (!pci_poke_faulted)
102 *ret = word;
103 spin_unlock_irqrestore(&pci_poke_lock, flags);
104}
105
106void pci_config_read32(u32 *addr, u32 *ret)
107{
108 unsigned long flags;
109 u32 dword;
110
111 spin_lock_irqsave(&pci_poke_lock, flags);
112 pci_poke_cpu = smp_processor_id();
113 pci_poke_in_progress = 1;
114 pci_poke_faulted = 0;
115 __asm__ __volatile__("membar #Sync\n\t"
116 "lduwa [%1] %2, %0\n\t"
117 "membar #Sync"
118 : "=r" (dword)
119 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
120 : "memory");
121 pci_poke_in_progress = 0;
122 pci_poke_cpu = -1;
123 if (!pci_poke_faulted)
124 *ret = dword;
125 spin_unlock_irqrestore(&pci_poke_lock, flags);
126}
127
128void pci_config_write8(u8 *addr, u8 val)
129{
130 unsigned long flags;
131
132 spin_lock_irqsave(&pci_poke_lock, flags);
133 pci_poke_cpu = smp_processor_id();
134 pci_poke_in_progress = 1;
135 pci_poke_faulted = 0;
136 __asm__ __volatile__("membar #Sync\n\t"
137 "stba %0, [%1] %2\n\t"
138 "membar #Sync"
139 : /* no outputs */
140 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
141 : "memory");
142 pci_poke_in_progress = 0;
143 pci_poke_cpu = -1;
144 spin_unlock_irqrestore(&pci_poke_lock, flags);
145}
146
147void pci_config_write16(u16 *addr, u16 val)
148{
149 unsigned long flags;
150
151 spin_lock_irqsave(&pci_poke_lock, flags);
152 pci_poke_cpu = smp_processor_id();
153 pci_poke_in_progress = 1;
154 pci_poke_faulted = 0;
155 __asm__ __volatile__("membar #Sync\n\t"
156 "stha %0, [%1] %2\n\t"
157 "membar #Sync"
158 : /* no outputs */
159 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
160 : "memory");
161 pci_poke_in_progress = 0;
162 pci_poke_cpu = -1;
163 spin_unlock_irqrestore(&pci_poke_lock, flags);
164}
165
166void pci_config_write32(u32 *addr, u32 val)
167{
168 unsigned long flags;
169
170 spin_lock_irqsave(&pci_poke_lock, flags);
171 pci_poke_cpu = smp_processor_id();
172 pci_poke_in_progress = 1;
173 pci_poke_faulted = 0;
174 __asm__ __volatile__("membar #Sync\n\t"
175 "stwa %0, [%1] %2\n\t"
176 "membar #Sync"
177 : /* no outputs */
178 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
179 : "memory");
180 pci_poke_in_progress = 0;
181 pci_poke_cpu = -1;
182 spin_unlock_irqrestore(&pci_poke_lock, flags);
183}
184
185/* Probe for all PCI controllers in the system. */
186extern void sabre_init(int, char *);
187extern void psycho_init(int, char *);
188extern void schizo_init(int, char *);
189extern void schizo_plus_init(int, char *);
190extern void tomatillo_init(int, char *);
191
192static struct {
193 char *model_name;
194 void (*init)(int, char *);
195} pci_controller_table[] __initdata = {
196 { "SUNW,sabre", sabre_init },
197 { "pci108e,a000", sabre_init },
198 { "pci108e,a001", sabre_init },
199 { "SUNW,psycho", psycho_init },
200 { "pci108e,8000", psycho_init },
201 { "SUNW,schizo", schizo_init },
202 { "pci108e,8001", schizo_init },
203 { "SUNW,schizo+", schizo_plus_init },
204 { "pci108e,8002", schizo_plus_init },
205 { "SUNW,tomatillo", tomatillo_init },
206 { "pci108e,a801", tomatillo_init },
207};
208#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
209 sizeof(pci_controller_table[0]))
210
211static int __init pci_controller_init(char *model_name, int namelen, int node)
212{
213 int i;
214
215 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
216 if (!strncmp(model_name,
217 pci_controller_table[i].model_name,
218 namelen)) {
219 pci_controller_table[i].init(node, model_name);
220 return 1;
221 }
222 }
223 printk("PCI: Warning unknown controller, model name [%s]\n",
224 model_name);
225 printk("PCI: Ignoring controller...\n");
226
227 return 0;
228}
229
230static int __init pci_is_controller(char *model_name, int namelen, int node)
231{
232 int i;
233
234 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
235 if (!strncmp(model_name,
236 pci_controller_table[i].model_name,
237 namelen)) {
238 return 1;
239 }
240 }
241 return 0;
242}
243
244static int __init pci_controller_scan(int (*handler)(char *, int, int))
245{
246 char namebuf[64];
247 int node;
248 int count = 0;
249
250 node = prom_getchild(prom_root_node);
251 while ((node = prom_searchsiblings(node, "pci")) != 0) {
252 int len;
253
254 if ((len = prom_getproperty(node, "model", namebuf, sizeof(namebuf))) > 0 ||
255 (len = prom_getproperty(node, "compatible", namebuf, sizeof(namebuf))) > 0) {
256 int item_len = 0;
257
258 /* Our value may be a multi-valued string in the
259 * case of some compatible properties. For sanity,
260 * only try the first one. */
261
262 while (namebuf[item_len] && len) {
263 len--;
264 item_len++;
265 }
266
267 if (handler(namebuf, item_len, node))
268 count++;
269 }
270
271 node = prom_getsibling(node);
272 if (!node)
273 break;
274 }
275
276 return count;
277}
278
279
280/* Is there some PCI controller in the system? */
281int __init pcic_present(void)
282{
283 return pci_controller_scan(pci_is_controller);
284}
285
286/* Find each controller in the system, attach and initialize
287 * software state structure for each and link into the
288 * pci_controller_root. Setup the controller enough such
289 * that bus scanning can be done.
290 */
291static void __init pci_controller_probe(void)
292{
293 printk("PCI: Probing for controllers.\n");
294
295 pci_controller_scan(pci_controller_init);
296}
297
298static void __init pci_scan_each_controller_bus(void)
299{
300 struct pci_controller_info *p;
301
302 for (p = pci_controller_root; p; p = p->next)
303 p->scan_bus(p);
304}
305
306/* Reorder the pci_dev chain, so that onboard devices come first
307 * and then come the pluggable cards.
308 */
309static void __init pci_reorder_devs(void)
310{
311 struct list_head *pci_onboard = &pci_devices;
312 struct list_head *walk = pci_onboard->next;
313
314 while (walk != pci_onboard) {
315 struct pci_dev *pdev = pci_dev_g(walk);
316 struct list_head *walk_next = walk->next;
317
318 if (pdev->irq && (__irq_ino(pdev->irq) & 0x20)) {
319 list_del(walk);
320 list_add(walk, pci_onboard);
321 }
322
323 walk = walk_next;
324 }
325}
326
327extern void clock_probe(void);
328extern void power_init(void);
329
330static int __init pcibios_init(void)
331{
332 pci_controller_probe();
333 if (pci_controller_root == NULL)
334 return 0;
335
336 pci_scan_each_controller_bus();
337
338 if (pci_device_reorder)
339 pci_reorder_devs();
340
341 isa_init();
342 ebus_init();
343 clock_probe();
344 power_init();
345
346 return 0;
347}
348
349subsys_initcall(pcibios_init);
350
351void pcibios_fixup_bus(struct pci_bus *pbus)
352{
353 struct pci_pbm_info *pbm = pbus->sysdata;
354
355 /* Generic PCI bus probing sets these to point at
356 * &io{port,mem}_resouce which is wrong for us.
357 */
358 pbus->resource[0] = &pbm->io_space;
359 pbus->resource[1] = &pbm->mem_space;
360}
361
362int pci_claim_resource(struct pci_dev *pdev, int resource)
363{
364 struct pci_pbm_info *pbm = pdev->bus->sysdata;
365 struct resource *res = &pdev->resource[resource];
366 struct resource *root;
367
368 if (!pbm)
369 return -EINVAL;
370
371 if (res->flags & IORESOURCE_IO)
372 root = &pbm->io_space;
373 else
374 root = &pbm->mem_space;
375
376 pbm->parent->resource_adjust(pdev, res, root);
377
378 return request_resource(root, res);
379}
380
381/*
382 * Given the PCI bus a device resides on, try to
383 * find an acceptable resource allocation for a
384 * specific device resource..
385 */
386static int pci_assign_bus_resource(const struct pci_bus *bus,
387 struct pci_dev *dev,
388 struct resource *res,
389 unsigned long size,
390 unsigned long min,
391 int resno)
392{
393 unsigned int type_mask;
394 int i;
395
396 type_mask = IORESOURCE_IO | IORESOURCE_MEM;
397 for (i = 0 ; i < 4; i++) {
398 struct resource *r = bus->resource[i];
399 if (!r)
400 continue;
401
402 /* type_mask must match */
403 if ((res->flags ^ r->flags) & type_mask)
404 continue;
405
406 /* Ok, try it out.. */
407 if (allocate_resource(r, res, size, min, -1, size, NULL, NULL) < 0)
408 continue;
409
410 /* PCI config space updated by caller. */
411 return 0;
412 }
413 return -EBUSY;
414}
415
416int pci_assign_resource(struct pci_dev *pdev, int resource)
417{
418 struct pcidev_cookie *pcp = pdev->sysdata;
419 struct pci_pbm_info *pbm = pcp->pbm;
420 struct resource *res = &pdev->resource[resource];
421 unsigned long min, size;
422 int err;
423
424 if (res->flags & IORESOURCE_IO)
425 min = pbm->io_space.start + 0x400UL;
426 else
427 min = pbm->mem_space.start;
428
429 size = res->end - res->start + 1;
430
431 err = pci_assign_bus_resource(pdev->bus, pdev, res, size, min, resource);
432
433 if (err < 0) {
434 printk("PCI: Failed to allocate resource %d for %s\n",
435 resource, pci_name(pdev));
436 } else {
437 /* Update PCI config space. */
438 pbm->parent->base_address_update(pdev, resource);
439 }
440
441 return err;
442}
443
444/* Sort resources by alignment */
445void pdev_sort_resources(struct pci_dev *dev, struct resource_list *head)
446{
447 int i;
448
449 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
450 struct resource *r;
451 struct resource_list *list, *tmp;
452 unsigned long r_align;
453
454 r = &dev->resource[i];
455 r_align = r->end - r->start;
456
457 if (!(r->flags) || r->parent)
458 continue;
459 if (!r_align) {
460 printk(KERN_WARNING "PCI: Ignore bogus resource %d "
461 "[%lx:%lx] of %s\n",
462 i, r->start, r->end, pci_name(dev));
463 continue;
464 }
465 r_align = (i < PCI_BRIDGE_RESOURCES) ? r_align + 1 : r->start;
466 for (list = head; ; list = list->next) {
467 unsigned long align = 0;
468 struct resource_list *ln = list->next;
469 int idx;
470
471 if (ln) {
472 idx = ln->res - &ln->dev->resource[0];
473 align = (idx < PCI_BRIDGE_RESOURCES) ?
474 ln->res->end - ln->res->start + 1 :
475 ln->res->start;
476 }
477 if (r_align > align) {
478 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
479 if (!tmp)
480 panic("pdev_sort_resources(): "
481 "kmalloc() failed!\n");
482 tmp->next = ln;
483 tmp->res = r;
484 tmp->dev = dev;
485 list->next = tmp;
486 break;
487 }
488 }
489 }
490}
491
492void pcibios_update_irq(struct pci_dev *pdev, int irq)
493{
494}
495
496void pcibios_align_resource(void *data, struct resource *res,
497 unsigned long size, unsigned long align)
498{
499}
500
501int pcibios_enable_device(struct pci_dev *pdev, int mask)
502{
503 return 0;
504}
505
506void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
507 struct resource *res)
508{
509 struct pci_pbm_info *pbm = pdev->bus->sysdata;
510 struct resource zero_res, *root;
511
512 zero_res.start = 0;
513 zero_res.end = 0;
514 zero_res.flags = res->flags;
515
516 if (res->flags & IORESOURCE_IO)
517 root = &pbm->io_space;
518 else
519 root = &pbm->mem_space;
520
521 pbm->parent->resource_adjust(pdev, &zero_res, root);
522
523 region->start = res->start - zero_res.start;
524 region->end = res->end - zero_res.start;
525}
526
527void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
528 struct pci_bus_region *region)
529{
530 struct pci_pbm_info *pbm = pdev->bus->sysdata;
531 struct resource *root;
532
533 res->start = region->start;
534 res->end = region->end;
535
536 if (res->flags & IORESOURCE_IO)
537 root = &pbm->io_space;
538 else
539 root = &pbm->mem_space;
540
541 pbm->parent->resource_adjust(pdev, res, root);
542}
41290c14 543EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4
LT		 544
545char * __init pcibios_setup(char *str)
546{
547 if (!strcmp(str, "onboardfirst")) {
548 pci_device_reorder = 1;
549 return NULL;
550 }
551 if (!strcmp(str, "noreorder")) {
552 pci_device_reorder = 0;
553 return NULL;
554 }
555 return str;
556}
557
558/* Platform support for /proc/bus/pci/X/Y mmap()s. */
559
560/* If the user uses a host-bridge as the PCI device, he may use
561 * this to perform a raw mmap() of the I/O or MEM space behind
562 * that controller.
563 *
564 * This can be useful for execution of x86 PCI bios initialization code
565 * on a PCI card, like the xfree86 int10 stuff does.
566 */
567static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
568 enum pci_mmap_state mmap_state)
569{
570 struct pcidev_cookie *pcp = pdev->sysdata;
571 struct pci_pbm_info *pbm;
572 struct pci_controller_info *p;
573 unsigned long space_size, user_offset, user_size;
574
575 if (!pcp)
576 return -ENXIO;
577 pbm = pcp->pbm;
578 if (!pbm)
579 return -ENXIO;
580
581 p = pbm->parent;
582 if (p->pbms_same_domain) {
583 unsigned long lowest, highest;
584
585 lowest = ~0UL; highest = 0UL;
586 if (mmap_state == pci_mmap_io) {
587 if (p->pbm_A.io_space.flags) {
588 lowest = p->pbm_A.io_space.start;
589 highest = p->pbm_A.io_space.end + 1;
590 }
591 if (p->pbm_B.io_space.flags) {
592 if (lowest > p->pbm_B.io_space.start)
593 lowest = p->pbm_B.io_space.start;
594 if (highest < p->pbm_B.io_space.end + 1)
595 highest = p->pbm_B.io_space.end + 1;
596 }
597 space_size = highest - lowest;
598 } else {
599 if (p->pbm_A.mem_space.flags) {
600 lowest = p->pbm_A.mem_space.start;
601 highest = p->pbm_A.mem_space.end + 1;
602 }
603 if (p->pbm_B.mem_space.flags) {
604 if (lowest > p->pbm_B.mem_space.start)
605 lowest = p->pbm_B.mem_space.start;
606 if (highest < p->pbm_B.mem_space.end + 1)
607 highest = p->pbm_B.mem_space.end + 1;
608 }
609 space_size = highest - lowest;
610 }
611 } else {
612 if (mmap_state == pci_mmap_io) {
613 space_size = (pbm->io_space.end -
614 pbm->io_space.start) + 1;
615 } else {
616 space_size = (pbm->mem_space.end -
617 pbm->mem_space.start) + 1;
618 }
619 }
620
621 /* Make sure the request is in range. */
622 user_offset = vma->vm_pgoff << PAGE_SHIFT;
623 user_size = vma->vm_end - vma->vm_start;
624
625 if (user_offset >= space_size ||
626 (user_offset + user_size) > space_size)
627 return -EINVAL;
628
629 if (p->pbms_same_domain) {
630 unsigned long lowest = ~0UL;
631
632 if (mmap_state == pci_mmap_io) {
633 if (p->pbm_A.io_space.flags)
634 lowest = p->pbm_A.io_space.start;
635 if (p->pbm_B.io_space.flags &&
636 lowest > p->pbm_B.io_space.start)
637 lowest = p->pbm_B.io_space.start;
638 } else {
639 if (p->pbm_A.mem_space.flags)
640 lowest = p->pbm_A.mem_space.start;
641 if (p->pbm_B.mem_space.flags &&
642 lowest > p->pbm_B.mem_space.start)
643 lowest = p->pbm_B.mem_space.start;
644 }
645 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
646 } else {
647 if (mmap_state == pci_mmap_io) {
648 vma->vm_pgoff = (pbm->io_space.start +
649 user_offset) >> PAGE_SHIFT;
650 } else {
651 vma->vm_pgoff = (pbm->mem_space.start +
652 user_offset) >> PAGE_SHIFT;
653 }
654 }
655
656 return 0;
657}
658
659/* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
660 * to the 32-bit pci bus offset for DEV requested by the user.
661 *
662 * Basically, the user finds the base address for his device which he wishes
663 * to mmap. They read the 32-bit value from the config space base register,
664 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
665 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
666 *
667 * Returns negative error code on failure, zero on success.
668 */
669static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
670 enum pci_mmap_state mmap_state)
671{
672 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
673 unsigned long user32 = user_offset & pci_memspace_mask;
674 unsigned long largest_base, this_base, addr32;
675 int i;
676
677 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
678 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
679
680 /* Figure out which base address this is for. */
681 largest_base = 0UL;
682 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
683 struct resource *rp = &dev->resource[i];
684
685 /* Active? */
686 if (!rp->flags)
687 continue;
688
689 /* Same type? */
690 if (i == PCI_ROM_RESOURCE) {
691 if (mmap_state != pci_mmap_mem)
692 continue;
693 } else {
694 if ((mmap_state == pci_mmap_io &&
695 (rp->flags & IORESOURCE_IO) == 0) ||
696 (mmap_state == pci_mmap_mem &&
697 (rp->flags & IORESOURCE_MEM) == 0))
698 continue;
699 }
700
701 this_base = rp->start;
702
703 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
704
705 if (mmap_state == pci_mmap_io)
706 addr32 &= 0xffffff;
707
708 if (addr32 <= user32 && this_base > largest_base)
709 largest_base = this_base;
710 }
711
712 if (largest_base == 0UL)
713 return -EINVAL;
714
715 /* Now construct the final physical address. */
716 if (mmap_state == pci_mmap_io)
717 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
718 else
719 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
720
721 return 0;
722}
723
724/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
725 * mapping.
726 */
727static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
728 enum pci_mmap_state mmap_state)
729{
730 vma->vm_flags |= (VM_IO | VM_RESERVED);
731}
732
733/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
734 * device mapping.
735 */
736static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
737 enum pci_mmap_state mmap_state)
738{
739 /* Our io_remap_page_range/io_remap_pfn_range takes care of this,
740 do nothing. */
741}
742
743/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
744 * for this architecture. The region in the process to map is described by vm_start
745 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
746 * The pci device structure is provided so that architectures may make mapping
747 * decisions on a per-device or per-bus basis.
748 *
749 * Returns a negative error code on failure, zero on success.
750 */
751int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
752 enum pci_mmap_state mmap_state,
753 int write_combine)
754{
755 int ret;
756
757 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
758 if (ret < 0)
759 return ret;
760
761 __pci_mmap_set_flags(dev, vma, mmap_state);
762 __pci_mmap_set_pgprot(dev, vma, mmap_state);
763
764 ret = io_remap_pfn_range(vma, vma->vm_start,
765 vma->vm_pgoff,
766 vma->vm_end - vma->vm_start,
767 vma->vm_page_prot);
768 if (ret)
769 return ret;
770
771 vma->vm_flags |= VM_IO;
772 return 0;
773}
774
775/* Return the domain nuber for this pci bus */
776
777int pci_domain_nr(struct pci_bus *pbus)
778{
779 struct pci_pbm_info *pbm = pbus->sysdata;
780 int ret;
781
782 if (pbm == NULL || pbm->parent == NULL) {
783 ret = -ENXIO;
784 } else {
785 struct pci_controller_info *p = pbm->parent;
786
787 ret = p->index;
788 if (p->pbms_same_domain == 0)
789 ret = ((ret << 1) +
790 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
791 }
792
793 return ret;
794}
795EXPORT_SYMBOL(pci_domain_nr);
796
797int pcibios_prep_mwi(struct pci_dev *dev)
798{
799 /* We set correct PCI_CACHE_LINE_SIZE register values for every
800 * device probed on this platform. So there is nothing to check
801 * and this always succeeds.
802 */
803 return 0;
804}
805
806#endif /* !(CONFIG_PCI) */
Linux 6.x block layer and io_uring tree(s)