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[SPARC64]: Consolidate MSI support code.
[linux-2.6-block.git] / arch / sparc64 / kernel / pci.c
CommitLineData
a2fb23af 1/* pci.c: UltraSparc PCI controller support.
1da177e4
LT		 2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
a2fb23af
DM		 6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
1da177e4
LT		 9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
c57c2ffb 17#include <linux/pci.h>
35a17eb6
DM		 18#include <linux/msi.h>
19#include <linux/irq.h>
1da177e4
LT		 20#include <linux/init.h>
21
22#include <asm/uaccess.h>
1da177e4
LT		 23#include <asm/pgtable.h>
24#include <asm/irq.h>
25#include <asm/ebus.h>
26#include <asm/isa.h>
e87dc350 27#include <asm/prom.h>
01f94c4a 28#include <asm/apb.h>
1da177e4 29
1e8a8cc5
DM		 30#include "pci_impl.h"
31
1da177e4
LT		 32unsigned long pci_memspace_mask = 0xffffffffUL;
33
34#ifndef CONFIG_PCI
35/* A "nop" PCI implementation. */
36asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
37 unsigned long off, unsigned long len,
38 unsigned char *buf)
39{
40 return 0;
41}
42asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
43 unsigned long off, unsigned long len,
44 unsigned char *buf)
45{
46 return 0;
47}
48#else
49
50/* List of all PCI controllers found in the system. */
34768bc8 51struct pci_pbm_info *pci_pbm_root = NULL;
1da177e4 52
6c108f12
DM		 53/* Each PBM found gets a unique index. */
54int pci_num_pbms = 0;
1da177e4 55
1da177e4
LT		 56volatile int pci_poke_in_progress;
57volatile int pci_poke_cpu = -1;
58volatile int pci_poke_faulted;
59
60static DEFINE_SPINLOCK(pci_poke_lock);
61
62void pci_config_read8(u8 *addr, u8 *ret)
63{
64 unsigned long flags;
65 u8 byte;
66
67 spin_lock_irqsave(&pci_poke_lock, flags);
68 pci_poke_cpu = smp_processor_id();
69 pci_poke_in_progress = 1;
70 pci_poke_faulted = 0;
71 __asm__ __volatile__("membar #Sync\n\t"
72 "lduba [%1] %2, %0\n\t"
73 "membar #Sync"
74 : "=r" (byte)
75 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
76 : "memory");
77 pci_poke_in_progress = 0;
78 pci_poke_cpu = -1;
79 if (!pci_poke_faulted)
80 *ret = byte;
81 spin_unlock_irqrestore(&pci_poke_lock, flags);
82}
83
84void pci_config_read16(u16 *addr, u16 *ret)
85{
86 unsigned long flags;
87 u16 word;
88
89 spin_lock_irqsave(&pci_poke_lock, flags);
90 pci_poke_cpu = smp_processor_id();
91 pci_poke_in_progress = 1;
92 pci_poke_faulted = 0;
93 __asm__ __volatile__("membar #Sync\n\t"
94 "lduha [%1] %2, %0\n\t"
95 "membar #Sync"
96 : "=r" (word)
97 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
98 : "memory");
99 pci_poke_in_progress = 0;
100 pci_poke_cpu = -1;
101 if (!pci_poke_faulted)
102 *ret = word;
103 spin_unlock_irqrestore(&pci_poke_lock, flags);
104}
105
106void pci_config_read32(u32 *addr, u32 *ret)
107{
108 unsigned long flags;
109 u32 dword;
110
111 spin_lock_irqsave(&pci_poke_lock, flags);
112 pci_poke_cpu = smp_processor_id();
113 pci_poke_in_progress = 1;
114 pci_poke_faulted = 0;
115 __asm__ __volatile__("membar #Sync\n\t"
116 "lduwa [%1] %2, %0\n\t"
117 "membar #Sync"
118 : "=r" (dword)
119 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
120 : "memory");
121 pci_poke_in_progress = 0;
122 pci_poke_cpu = -1;
123 if (!pci_poke_faulted)
124 *ret = dword;
125 spin_unlock_irqrestore(&pci_poke_lock, flags);
126}
127
128void pci_config_write8(u8 *addr, u8 val)
129{
130 unsigned long flags;
131
132 spin_lock_irqsave(&pci_poke_lock, flags);
133 pci_poke_cpu = smp_processor_id();
134 pci_poke_in_progress = 1;
135 pci_poke_faulted = 0;
136 __asm__ __volatile__("membar #Sync\n\t"
137 "stba %0, [%1] %2\n\t"
138 "membar #Sync"
139 : /* no outputs */
140 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
141 : "memory");
142 pci_poke_in_progress = 0;
143 pci_poke_cpu = -1;
144 spin_unlock_irqrestore(&pci_poke_lock, flags);
145}
146
147void pci_config_write16(u16 *addr, u16 val)
148{
149 unsigned long flags;
150
151 spin_lock_irqsave(&pci_poke_lock, flags);
152 pci_poke_cpu = smp_processor_id();
153 pci_poke_in_progress = 1;
154 pci_poke_faulted = 0;
155 __asm__ __volatile__("membar #Sync\n\t"
156 "stha %0, [%1] %2\n\t"
157 "membar #Sync"
158 : /* no outputs */
159 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
160 : "memory");
161 pci_poke_in_progress = 0;
162 pci_poke_cpu = -1;
163 spin_unlock_irqrestore(&pci_poke_lock, flags);
164}
165
166void pci_config_write32(u32 *addr, u32 val)
167{
168 unsigned long flags;
169
170 spin_lock_irqsave(&pci_poke_lock, flags);
171 pci_poke_cpu = smp_processor_id();
172 pci_poke_in_progress = 1;
173 pci_poke_faulted = 0;
174 __asm__ __volatile__("membar #Sync\n\t"
175 "stwa %0, [%1] %2\n\t"
176 "membar #Sync"
177 : /* no outputs */
178 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
179 : "memory");
180 pci_poke_in_progress = 0;
181 pci_poke_cpu = -1;
182 spin_unlock_irqrestore(&pci_poke_lock, flags);
183}
184
185/* Probe for all PCI controllers in the system. */
e87dc350
DM		 186extern void sabre_init(struct device_node *, const char *);
187extern void psycho_init(struct device_node *, const char *);
188extern void schizo_init(struct device_node *, const char *);
189extern void schizo_plus_init(struct device_node *, const char *);
190extern void tomatillo_init(struct device_node *, const char *);
191extern void sun4v_pci_init(struct device_node *, const char *);
861fe906 192extern void fire_pci_init(struct device_node *, const char *);
1da177e4
LT		 193
194static struct {
195 char *model_name;
e87dc350 196 void (*init)(struct device_node *, const char *);
1da177e4
LT		 197} pci_controller_table[] __initdata = {
198 { "SUNW,sabre", sabre_init },
199 { "pci108e,a000", sabre_init },
200 { "pci108e,a001", sabre_init },
201 { "SUNW,psycho", psycho_init },
202 { "pci108e,8000", psycho_init },
203 { "SUNW,schizo", schizo_init },
204 { "pci108e,8001", schizo_init },
205 { "SUNW,schizo+", schizo_plus_init },
206 { "pci108e,8002", schizo_plus_init },
207 { "SUNW,tomatillo", tomatillo_init },
208 { "pci108e,a801", tomatillo_init },
8f6a93a1 209 { "SUNW,sun4v-pci", sun4v_pci_init },
861fe906 210 { "pciex108e,80f0", fire_pci_init },
1da177e4
LT		 211};
212#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
213 sizeof(pci_controller_table[0]))
214
e87dc350 215static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 216{
217 int i;
218
219 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
220 if (!strncmp(model_name,
221 pci_controller_table[i].model_name,
222 namelen)) {
e87dc350 223 pci_controller_table[i].init(dp, model_name);
1da177e4
LT		 224 return 1;
225 }
226 }
1da177e4
LT		 227
228 return 0;
229}
230
e87dc350 231static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 232{
233 int i;
234
235 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
236 if (!strncmp(model_name,
237 pci_controller_table[i].model_name,
238 namelen)) {
239 return 1;
240 }
241 }
242 return 0;
243}
244
e87dc350 245static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
1da177e4 246{
e87dc350 247 struct device_node *dp;
1da177e4
LT		 248 int count = 0;
249
e87dc350
DM		 250 for_each_node_by_name(dp, "pci") {
251 struct property *prop;
1da177e4
LT		 252 int len;
253
e87dc350
DM		 254 prop = of_find_property(dp, "model", &len);
255 if (!prop)
256 prop = of_find_property(dp, "compatible", &len);
257
258 if (prop) {
259 const char *model = prop->value;
1da177e4
LT		 260 int item_len = 0;
261
262 /* Our value may be a multi-valued string in the
263 * case of some compatible properties. For sanity,
e87dc350
DM		 264 * only try the first one.
265 */
266 while (model[item_len] && len) {
1da177e4
LT		 267 len--;
268 item_len++;
269 }
270
e87dc350 271 if (handler(model, item_len, dp))
1da177e4
LT		 272 count++;
273 }
1da177e4
LT		 274 }
275
276 return count;
277}
278
279
280/* Is there some PCI controller in the system? */
281int __init pcic_present(void)
282{
283 return pci_controller_scan(pci_is_controller);
284}
285
286/* Find each controller in the system, attach and initialize
287 * software state structure for each and link into the
34768bc8 288 * pci_pbm_root. Setup the controller enough such
1da177e4
LT		 289 * that bus scanning can be done.
290 */
291static void __init pci_controller_probe(void)
292{
293 printk("PCI: Probing for controllers.\n");
294
295 pci_controller_scan(pci_controller_init);
296}
297
5840fc66
DM		 298static int ofpci_verbose;
299
300static int __init ofpci_debug(char *str)
301{
302 int val = 0;
303
304 get_option(&str, &val);
305 if (val)
306 ofpci_verbose = 1;
307 return 1;
308}
309
310__setup("ofpci_debug=", ofpci_debug);
311
a2fb23af
DM		 312static unsigned long pci_parse_of_flags(u32 addr0)
313{
314 unsigned long flags = 0;
315
316 if (addr0 & 0x02000000) {
317 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
318 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
319 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
320 if (addr0 & 0x40000000)
321 flags |= IORESOURCE_PREFETCH
322 | PCI_BASE_ADDRESS_MEM_PREFETCH;
323 } else if (addr0 & 0x01000000)
324 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
325 return flags;
326}
327
328/* The of_device layer has translated all of the assigned-address properties
329 * into physical address resources, we only have to figure out the register
330 * mapping.
331 */
332static void pci_parse_of_addrs(struct of_device *op,
333 struct device_node *node,
334 struct pci_dev *dev)
335{
336 struct resource *op_res;
337 const u32 *addrs;
338 int proplen;
339
340 addrs = of_get_property(node, "assigned-addresses", &proplen);
341 if (!addrs)
342 return;
5840fc66
DM		 343 if (ofpci_verbose)
344 printk(" parse addresses (%d bytes) @ %p\n",
345 proplen, addrs);
a2fb23af
DM		 346 op_res = &op->resource[0];
347 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
348 struct resource *res;
349 unsigned long flags;
350 int i;
351
352 flags = pci_parse_of_flags(addrs[0]);
353 if (!flags)
354 continue;
355 i = addrs[0] & 0xff;
5840fc66
DM		 356 if (ofpci_verbose)
357 printk(" start: %lx, end: %lx, i: %x\n",
358 op_res->start, op_res->end, i);
a2fb23af
DM		 359
360 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
361 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
362 } else if (i == dev->rom_base_reg) {
363 res = &dev->resource[PCI_ROM_RESOURCE];
364 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
365 } else {
366 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
367 continue;
368 }
369 res->start = op_res->start;
370 res->end = op_res->end;
371 res->flags = flags;
372 res->name = pci_name(dev);
373 }
374}
375
376struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
377 struct device_node *node,
97b3cf05
DM		 378 struct pci_bus *bus, int devfn,
379 int host_controller)
a2fb23af
DM		 380{
381 struct dev_archdata *sd;
382 struct pci_dev *dev;
383 const char *type;
01f94c4a 384 u32 class;
a2fb23af 385
26e6385f 386 dev = alloc_pci_dev();
a2fb23af
DM		 387 if (!dev)
388 return NULL;
389
390 sd = &dev->dev.archdata;
391 sd->iommu = pbm->iommu;
392 sd->stc = &pbm->stc;
393 sd->host_controller = pbm;
394 sd->prom_node = node;
395 sd->op = of_find_device_by_node(node);
a2fb23af 396
ad7ad57c
DM		 397 sd = &sd->op->dev.archdata;
398 sd->iommu = pbm->iommu;
399 sd->stc = &pbm->stc;
400
a2fb23af
DM		 401 type = of_get_property(node, "device_type", NULL);
402 if (type == NULL)
403 type = "";
404
5840fc66
DM		 405 if (ofpci_verbose)
406 printk(" create device, devfn: %x, type: %s\n",
407 devfn, type);
a2fb23af
DM		 408
409 dev->bus = bus;
410 dev->sysdata = node;
411 dev->dev.parent = bus->bridge;
412 dev->dev.bus = &pci_bus_type;
413 dev->devfn = devfn;
414 dev->multifunction = 0; /* maybe a lie? */
415
97b3cf05 416 if (host_controller) {
a2d6ea01
DM		 417 if (tlb_type != hypervisor) {
418 pci_read_config_word(dev, PCI_VENDOR_ID,
419 &dev->vendor);
420 pci_read_config_word(dev, PCI_DEVICE_ID,
421 &dev->device);
422 } else {
423 dev->vendor = PCI_VENDOR_ID_SUN;
424 dev->device = 0x80f0;
425 }
97b3cf05 426 dev->cfg_size = 256;
28f57e77
DM		 427 dev->class = PCI_CLASS_BRIDGE_HOST << 8;
428 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
429 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
97b3cf05
DM		 430 } else {
431 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
432 dev->device = of_getintprop_default(node, "device-id", 0xffff);
433 dev->subsystem_vendor =
434 of_getintprop_default(node, "subsystem-vendor-id", 0);
435 dev->subsystem_device =
436 of_getintprop_default(node, "subsystem-id", 0);
437
438 dev->cfg_size = pci_cfg_space_size(dev);
01f94c4a 439
97b3cf05
DM		 440 /* We can't actually use the firmware value, we have
441 * to read what is in the register right now. One
442 * reason is that in the case of IDE interfaces the
443 * firmware can sample the value before the the IDE
444 * interface is programmed into native mode.
445 */
446 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
447 dev->class = class >> 8;
b8a3a521 448 dev->revision = class & 0xff;
28f57e77
DM		 449
450 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
451 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
97b3cf05 452 }
5840fc66
DM		 453 if (ofpci_verbose)
454 printk(" class: 0x%x device name: %s\n",
455 dev->class, pci_name(dev));
a2fb23af 456
861fe906
DM		 457 /* I have seen IDE devices which will not respond to
458 * the bmdma simplex check reads if bus mastering is
459 * disabled.
460 */
461 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
462 pci_set_master(dev);
463
a2fb23af
DM		 464 dev->current_state = 4; /* unknown power state */
465 dev->error_state = pci_channel_io_normal;
466
97b3cf05 467 if (host_controller) {
a2fb23af
DM		 468 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
469 dev->rom_base_reg = PCI_ROM_ADDRESS1;
97b3cf05 470 dev->irq = PCI_IRQ_NONE;
a2fb23af 471 } else {
97b3cf05
DM		 472 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
473 /* a PCI-PCI bridge */
474 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
475 dev->rom_base_reg = PCI_ROM_ADDRESS1;
476 } else if (!strcmp(type, "cardbus")) {
477 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
478 } else {
479 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
480 dev->rom_base_reg = PCI_ROM_ADDRESS;
a2fb23af 481
97b3cf05
DM		 482 dev->irq = sd->op->irqs[0];
483 if (dev->irq == 0xffffffff)
484 dev->irq = PCI_IRQ_NONE;
485 }
a2fb23af 486 }
a2fb23af
DM		 487 pci_parse_of_addrs(sd->op, node, dev);
488
5840fc66
DM		 489 if (ofpci_verbose)
490 printk(" adding to system ...\n");
a2fb23af
DM		 491
492 pci_device_add(dev, bus);
493
494 return dev;
495}
496
a6009dda 497static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
01f94c4a
DM		 498{
499 u32 idx, first, last;
500
501 first = 8;
502 last = 0;
503 for (idx = 0; idx < 8; idx++) {
504 if ((map & (1 << idx)) != 0) {
505 if (first > idx)
506 first = idx;
507 if (last < idx)
508 last = idx;
509 }
510 }
511
512 *first_p = first;
513 *last_p = last;
514}
515
f16537ba
DM		 516static void pci_resource_adjust(struct resource *res,
517 struct resource *root)
0bae5f81
DM		 518{
519 res->start += root->start;
520 res->end += root->start;
521}
522
8c2786cf
DM		 523/* For PCI bus devices which lack a 'ranges' property we interrogate
524 * the config space values to set the resources, just like the generic
525 * Linux PCI probing code does.
526 */
527static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
528 struct pci_bus *bus,
529 struct pci_pbm_info *pbm)
530{
531 struct resource *res;
532 u8 io_base_lo, io_limit_lo;
533 u16 mem_base_lo, mem_limit_lo;
534 unsigned long base, limit;
535
536 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
537 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
538 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
539 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
540
541 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
542 u16 io_base_hi, io_limit_hi;
543
544 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
545 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
546 base |= (io_base_hi << 16);
547 limit |= (io_limit_hi << 16);
548 }
549
550 res = bus->resource[0];
551 if (base <= limit) {
552 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
553 if (!res->start)
554 res->start = base;
555 if (!res->end)
556 res->end = limit + 0xfff;
557 pci_resource_adjust(res, &pbm->io_space);
558 }
559
560 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
561 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
562 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
563 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
564
565 res = bus->resource[1];
566 if (base <= limit) {
567 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
568 IORESOURCE_MEM);
569 res->start = base;
570 res->end = limit + 0xfffff;
571 pci_resource_adjust(res, &pbm->mem_space);
572 }
573
574 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
575 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
576 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
577 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
578
579 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
580 u32 mem_base_hi, mem_limit_hi;
581
582 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
583 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
584
585 /*
586 * Some bridges set the base > limit by default, and some
587 * (broken) BIOSes do not initialize them. If we find
588 * this, just assume they are not being used.
589 */
590 if (mem_base_hi <= mem_limit_hi) {
591 base |= ((long) mem_base_hi) << 32;
592 limit |= ((long) mem_limit_hi) << 32;
593 }
594 }
595
596 res = bus->resource[2];
597 if (base <= limit) {
598 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
599 IORESOURCE_MEM | IORESOURCE_PREFETCH);
600 res->start = base;
601 res->end = limit + 0xfffff;
602 pci_resource_adjust(res, &pbm->mem_space);
603 }
604}
605
01f94c4a
DM		 606/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
607 * a proper 'ranges' property.
608 */
a6009dda
DM		 609static void __devinit apb_fake_ranges(struct pci_dev *dev,
610 struct pci_bus *bus,
611 struct pci_pbm_info *pbm)
01f94c4a
DM		 612{
613 struct resource *res;
614 u32 first, last;
615 u8 map;
616
617 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
618 apb_calc_first_last(map, &first, &last);
619 res = bus->resource[0];
620 res->start = (first << 21);
621 res->end = (last << 21) + ((1 << 21) - 1);
622 res->flags = IORESOURCE_IO;
0bae5f81 623 pci_resource_adjust(res, &pbm->io_space);
01f94c4a
DM		 624
625 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
626 apb_calc_first_last(map, &first, &last);
627 res = bus->resource[1];
628 res->start = (first << 21);
629 res->end = (last << 21) + ((1 << 21) - 1);
630 res->flags = IORESOURCE_MEM;
0bae5f81 631 pci_resource_adjust(res, &pbm->mem_space);
01f94c4a
DM		 632}
633
a6009dda
DM		 634static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
635 struct device_node *node,
636 struct pci_bus *bus);
a2fb23af
DM		 637
638#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
639
a6009dda
DM		 640static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
641 struct device_node *node,
642 struct pci_dev *dev)
a2fb23af
DM		 643{
644 struct pci_bus *bus;
645 const u32 *busrange, *ranges;
01f94c4a 646 int len, i, simba;
a2fb23af
DM		 647 struct resource *res;
648 unsigned int flags;
649 u64 size;
650
5840fc66
DM		 651 if (ofpci_verbose)
652 printk("of_scan_pci_bridge(%s)\n", node->full_name);
a2fb23af
DM		 653
654 /* parse bus-range property */
655 busrange = of_get_property(node, "bus-range", &len);
656 if (busrange == NULL || len != 8) {
657 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
658 node->full_name);
659 return;
660 }
661 ranges = of_get_property(node, "ranges", &len);
01f94c4a 662 simba = 0;
a2fb23af 663 if (ranges == NULL) {
a165b420 664 const char *model = of_get_property(node, "model", NULL);
8c2786cf 665 if (model && !strcmp(model, "SUNW,simba"))
01f94c4a 666 simba = 1;
a2fb23af
DM		 667 }
668
669 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
670 if (!bus) {
671 printk(KERN_ERR "Failed to create pci bus for %s\n",
672 node->full_name);
673 return;
674 }
675
676 bus->primary = dev->bus->number;
677 bus->subordinate = busrange[1];
678 bus->bridge_ctl = 0;
679
01f94c4a 680 /* parse ranges property, or cook one up by hand for Simba */
a2fb23af
DM		 681 /* PCI #address-cells == 3 and #size-cells == 2 always */
682 res = &dev->resource[PCI_BRIDGE_RESOURCES];
683 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
684 res->flags = 0;
685 bus->resource[i] = res;
686 ++res;
687 }
01f94c4a
DM		 688 if (simba) {
689 apb_fake_ranges(dev, bus, pbm);
8c2786cf
DM		 690 goto after_ranges;
691 } else if (ranges == NULL) {
692 pci_cfg_fake_ranges(dev, bus, pbm);
693 goto after_ranges;
01f94c4a 694 }
a2fb23af
DM		 695 i = 1;
696 for (; len >= 32; len -= 32, ranges += 8) {
697 struct resource *root;
698
699 flags = pci_parse_of_flags(ranges[0]);
700 size = GET_64BIT(ranges, 6);
701 if (flags == 0 || size == 0)
702 continue;
703 if (flags & IORESOURCE_IO) {
704 res = bus->resource[0];
705 if (res->flags) {
706 printk(KERN_ERR "PCI: ignoring extra I/O range"
707 " for bridge %s\n", node->full_name);
708 continue;
709 }
710 root = &pbm->io_space;
711 } else {
712 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
713 printk(KERN_ERR "PCI: too many memory ranges"
714 " for bridge %s\n", node->full_name);
715 continue;
716 }
717 res = bus->resource[i];
718 ++i;
719 root = &pbm->mem_space;
720 }
721
722 res->start = GET_64BIT(ranges, 1);
723 res->end = res->start + size - 1;
724 res->flags = flags;
725
726 /* Another way to implement this would be to add an of_device
727 * layer routine that can calculate a resource for a given
728 * range property value in a PCI device.
729 */
0bae5f81 730 pci_resource_adjust(res, root);
a2fb23af 731 }
8c2786cf 732after_ranges:
a2fb23af
DM		 733 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
734 bus->number);
5840fc66
DM		 735 if (ofpci_verbose)
736 printk(" bus name: %s\n", bus->name);
a2fb23af
DM		 737
738 pci_of_scan_bus(pbm, node, bus);
739}
740
a6009dda
DM		 741static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
742 struct device_node *node,
743 struct pci_bus *bus)
a2fb23af
DM		 744{
745 struct device_node *child;
746 const u32 *reg;
2cc7345f 747 int reglen, devfn, prev_devfn;
a2fb23af
DM		 748 struct pci_dev *dev;
749
5840fc66
DM		 750 if (ofpci_verbose)
751 printk("PCI: scan_bus[%s] bus no %d\n",
752 node->full_name, bus->number);
a2fb23af
DM		 753
754 child = NULL;
2cc7345f 755 prev_devfn = -1;
a2fb23af 756 while ((child = of_get_next_child(node, child)) != NULL) {
5840fc66
DM		 757 if (ofpci_verbose)
758 printk(" * %s\n", child->full_name);
a2fb23af
DM		 759 reg = of_get_property(child, "reg", &reglen);
760 if (reg == NULL || reglen < 20)
761 continue;
2cc7345f 762
a2fb23af
DM		 763 devfn = (reg[0] >> 8) & 0xff;
764
2cc7345f
DM		 765 /* This is a workaround for some device trees
766 * which list PCI devices twice. On the V100
767 * for example, device number 3 is listed twice.
768 * Once as "pm" and once again as "lomp".
769 */
770 if (devfn == prev_devfn)
771 continue;
772 prev_devfn = devfn;
773
a2fb23af 774 /* create a new pci_dev for this device */
97b3cf05 775 dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
a2fb23af
DM		 776 if (!dev)
777 continue;
5840fc66
DM		 778 if (ofpci_verbose)
779 printk("PCI: dev header type: %x\n",
780 dev->hdr_type);
a2fb23af
DM		 781
782 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
783 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
784 of_scan_pci_bridge(pbm, child, dev);
785 }
786}
787
788static ssize_t
789show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
790{
791 struct pci_dev *pdev;
792 struct device_node *dp;
793
794 pdev = to_pci_dev(dev);
795 dp = pdev->dev.archdata.prom_node;
796
797 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
798}
799
800static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
801
802static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
803{
804 struct pci_dev *dev;
a378fd0e 805 struct pci_bus *child_bus;
a2fb23af
DM		 806 int err;
807
808 list_for_each_entry(dev, &bus->devices, bus_list) {
809 /* we don't really care if we can create this file or
810 * not, but we need to assign the result of the call
811 * or the world will fall under alien invasion and
812 * everybody will be frozen on a spaceship ready to be
813 * eaten on alpha centauri by some green and jelly
814 * humanoid.
815 */
816 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
817 }
a378fd0e
DM		 818 list_for_each_entry(child_bus, &bus->children, node)
819 pci_bus_register_of_sysfs(child_bus);
a2fb23af
DM		 820}
821
97b3cf05
DM		 822int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
823 unsigned int devfn,
824 int where, int size,
825 u32 *value)
826{
827 static u8 fake_pci_config[] = {
828 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
a2d6ea01 829 0xf0, 0x80, /* Device: 0x80f0 (Fire) */
97b3cf05
DM		 830 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
831 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
832 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
833 0x00, /* Cacheline: 0x00 */
834 0x40, /* Latency: 0x40 */
835 0x00, /* Header-Type: 0x00 normal */
836 };
837
838 *value = 0;
839 if (where >= 0 && where < sizeof(fake_pci_config) &&
840 (where + size) >= 0 &&
841 (where + size) < sizeof(fake_pci_config) &&
842 size <= sizeof(u32)) {
843 while (size--) {
844 *value <<= 8;
845 *value |= fake_pci_config[where + size];
846 }
847 }
848
849 return PCIBIOS_SUCCESSFUL;
850}
851
852int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
853 unsigned int devfn,
854 int where, int size,
855 u32 value)
856{
857 return PCIBIOS_SUCCESSFUL;
858}
859
a6009dda 860struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
a2fb23af 861{
a2fb23af 862 struct device_node *node = pbm->prom_node;
97b3cf05 863 struct pci_dev *host_pdev;
a2fb23af
DM		 864 struct pci_bus *bus;
865
866 printk("PCI: Scanning PBM %s\n", node->full_name);
867
868 /* XXX parent device? XXX */
f1cd8de2 869 bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm);
a2fb23af
DM		 870 if (!bus) {
871 printk(KERN_ERR "Failed to create bus for %s\n",
872 node->full_name);
873 return NULL;
874 }
875 bus->secondary = pbm->pci_first_busno;
876 bus->subordinate = pbm->pci_last_busno;
877
878 bus->resource[0] = &pbm->io_space;
879 bus->resource[1] = &pbm->mem_space;
880
97b3cf05
DM		 881 /* Create the dummy host bridge and link it in. */
882 host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
883 bus->self = host_pdev;
884
a2fb23af
DM		 885 pci_of_scan_bus(pbm, node, bus);
886 pci_bus_add_devices(bus);
887 pci_bus_register_of_sysfs(bus);
888
889 return bus;
890}
891
1da177e4
LT		 892static void __init pci_scan_each_controller_bus(void)
893{
34768bc8 894 struct pci_pbm_info *pbm;
1da177e4 895
34768bc8
DM		 896 for (pbm = pci_pbm_root; pbm; pbm = pbm->next)
897 pbm->scan_bus(pbm);
1da177e4
LT		 898}
899
1da177e4
LT		 900extern void power_init(void);
901
902static int __init pcibios_init(void)
903{
904 pci_controller_probe();
34768bc8 905 if (pci_pbm_root == NULL)
1da177e4
LT		 906 return 0;
907
908 pci_scan_each_controller_bus();
909
1da177e4
LT		 910 isa_init();
911 ebus_init();
1da177e4
LT		 912 power_init();
913
914 return 0;
915}
916
917subsys_initcall(pcibios_init);
918
f6b45da1 919void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
1da177e4
LT		 920{
921 struct pci_pbm_info *pbm = pbus->sysdata;
922
923 /* Generic PCI bus probing sets these to point at
924 * &io{port,mem}_resouce which is wrong for us.
925 */
926 pbus->resource[0] = &pbm->io_space;
927 pbus->resource[1] = &pbm->mem_space;
928}
929
085ae41f 930struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
1da177e4
LT		 931{
932 struct pci_pbm_info *pbm = pdev->bus->sysdata;
085ae41f 933 struct resource *root = NULL;
1da177e4 934
085ae41f 935 if (r->flags & IORESOURCE_IO)
1da177e4 936 root = &pbm->io_space;
085ae41f 937 if (r->flags & IORESOURCE_MEM)
1da177e4
LT		 938 root = &pbm->mem_space;
939
085ae41f 940 return root;
1da177e4
LT		 941}
942
943void pcibios_update_irq(struct pci_dev *pdev, int irq)
944{
945}
946
947void pcibios_align_resource(void *data, struct resource *res,
e31dd6e4 948 resource_size_t size, resource_size_t align)
1da177e4
LT		 949{
950}
951
a2fb23af 952int pcibios_enable_device(struct pci_dev *dev, int mask)
1da177e4 953{
a2fb23af
DM		 954 u16 cmd, oldcmd;
955 int i;
956
957 pci_read_config_word(dev, PCI_COMMAND, &cmd);
958 oldcmd = cmd;
959
960 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
961 struct resource *res = &dev->resource[i];
962
963 /* Only set up the requested stuff */
964 if (!(mask & (1<<i)))
965 continue;
966
967 if (res->flags & IORESOURCE_IO)
968 cmd |= PCI_COMMAND_IO;
969 if (res->flags & IORESOURCE_MEM)
970 cmd |= PCI_COMMAND_MEMORY;
971 }
972
973 if (cmd != oldcmd) {
974 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
975 pci_name(dev), cmd);
976 /* Enable the appropriate bits in the PCI command register. */
977 pci_write_config_word(dev, PCI_COMMAND, cmd);
978 }
1da177e4
LT		 979 return 0;
980}
981
982void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
983 struct resource *res)
984{
985 struct pci_pbm_info *pbm = pdev->bus->sysdata;
986 struct resource zero_res, *root;
987
988 zero_res.start = 0;
989 zero_res.end = 0;
990 zero_res.flags = res->flags;
991
992 if (res->flags & IORESOURCE_IO)
993 root = &pbm->io_space;
994 else
995 root = &pbm->mem_space;
996
0bae5f81 997 pci_resource_adjust(&zero_res, root);
1da177e4
LT		 998
999 region->start = res->start - zero_res.start;
1000 region->end = res->end - zero_res.start;
1001}
5fdfd42e 1002EXPORT_SYMBOL(pcibios_resource_to_bus);
1da177e4
LT		 1003
1004void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
1005 struct pci_bus_region *region)
1006{
1007 struct pci_pbm_info *pbm = pdev->bus->sysdata;
1008 struct resource *root;
1009
1010 res->start = region->start;
1011 res->end = region->end;
1012
1013 if (res->flags & IORESOURCE_IO)
1014 root = &pbm->io_space;
1015 else
1016 root = &pbm->mem_space;
1017
0bae5f81 1018 pci_resource_adjust(res, root);
1da177e4 1019}
41290c14 1020EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 1021
f6b45da1 1022char * __devinit pcibios_setup(char *str)
1da177e4 1023{
1da177e4
LT		 1024 return str;
1025}
1026
1027/* Platform support for /proc/bus/pci/X/Y mmap()s. */
1028
1029/* If the user uses a host-bridge as the PCI device, he may use
1030 * this to perform a raw mmap() of the I/O or MEM space behind
1031 * that controller.
1032 *
1033 * This can be useful for execution of x86 PCI bios initialization code
1034 * on a PCI card, like the xfree86 int10 stuff does.
1035 */
1036static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
1037 enum pci_mmap_state mmap_state)
1038{
a2fb23af 1039 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1da177e4
LT		 1040 unsigned long space_size, user_offset, user_size;
1041
3875c5c0
DM		 1042 if (mmap_state == pci_mmap_io) {
1043 space_size = (pbm->io_space.end -
1044 pbm->io_space.start) + 1;
1da177e4 1045 } else {
3875c5c0
DM		 1046 space_size = (pbm->mem_space.end -
1047 pbm->mem_space.start) + 1;
1da177e4
LT		 1048 }
1049
1050 /* Make sure the request is in range. */
1051 user_offset = vma->vm_pgoff << PAGE_SHIFT;
1052 user_size = vma->vm_end - vma->vm_start;
1053
1054 if (user_offset >= space_size ||
1055 (user_offset + user_size) > space_size)
1056 return -EINVAL;
1057
3875c5c0
DM		 1058 if (mmap_state == pci_mmap_io) {
1059 vma->vm_pgoff = (pbm->io_space.start +
1060 user_offset) >> PAGE_SHIFT;
1da177e4 1061 } else {
3875c5c0
DM		 1062 vma->vm_pgoff = (pbm->mem_space.start +
1063 user_offset) >> PAGE_SHIFT;
1da177e4
LT		 1064 }
1065
1066 return 0;
1067}
1068
1069/* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
1070 * to the 32-bit pci bus offset for DEV requested by the user.
1071 *
1072 * Basically, the user finds the base address for his device which he wishes
1073 * to mmap. They read the 32-bit value from the config space base register,
1074 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1075 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1076 *
1077 * Returns negative error code on failure, zero on success.
1078 */
1079static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
1080 enum pci_mmap_state mmap_state)
1081{
1082 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
1083 unsigned long user32 = user_offset & pci_memspace_mask;
1084 unsigned long largest_base, this_base, addr32;
1085 int i;
1086
1087 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
1088 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
1089
1090 /* Figure out which base address this is for. */
1091 largest_base = 0UL;
1092 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
1093 struct resource *rp = &dev->resource[i];
1094
1095 /* Active? */
1096 if (!rp->flags)
1097 continue;
1098
1099 /* Same type? */
1100 if (i == PCI_ROM_RESOURCE) {
1101 if (mmap_state != pci_mmap_mem)
1102 continue;
1103 } else {
1104 if ((mmap_state == pci_mmap_io &&
1105 (rp->flags & IORESOURCE_IO) == 0) ||
1106 (mmap_state == pci_mmap_mem &&
1107 (rp->flags & IORESOURCE_MEM) == 0))
1108 continue;
1109 }
1110
1111 this_base = rp->start;
1112
1113 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
1114
1115 if (mmap_state == pci_mmap_io)
1116 addr32 &= 0xffffff;
1117
1118 if (addr32 <= user32 && this_base > largest_base)
1119 largest_base = this_base;
1120 }
1121
1122 if (largest_base == 0UL)
1123 return -EINVAL;
1124
1125 /* Now construct the final physical address. */
1126 if (mmap_state == pci_mmap_io)
1127 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
1128 else
1129 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
1130
1131 return 0;
1132}
1133
1134/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1135 * mapping.
1136 */
1137static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
1138 enum pci_mmap_state mmap_state)
1139{
1140 vma->vm_flags |= (VM_IO | VM_RESERVED);
1141}
1142
1143/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1144 * device mapping.
1145 */
1146static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1147 enum pci_mmap_state mmap_state)
1148{
a7a6cac2 1149 /* Our io_remap_pfn_range takes care of this, do nothing. */
1da177e4
LT		 1150}
1151
1152/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1153 * for this architecture. The region in the process to map is described by vm_start
1154 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1155 * The pci device structure is provided so that architectures may make mapping
1156 * decisions on a per-device or per-bus basis.
1157 *
1158 * Returns a negative error code on failure, zero on success.
1159 */
1160int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1161 enum pci_mmap_state mmap_state,
1162 int write_combine)
1163{
1164 int ret;
1165
1166 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1167 if (ret < 0)
1168 return ret;
1169
1170 __pci_mmap_set_flags(dev, vma, mmap_state);
1171 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1172
14778d90 1173 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1da177e4
LT		 1174 ret = io_remap_pfn_range(vma, vma->vm_start,
1175 vma->vm_pgoff,
1176 vma->vm_end - vma->vm_start,
1177 vma->vm_page_prot);
1178 if (ret)
1179 return ret;
1180
1da177e4
LT		 1181 return 0;
1182}
1183
1184/* Return the domain nuber for this pci bus */
1185
1186int pci_domain_nr(struct pci_bus *pbus)
1187{
1188 struct pci_pbm_info *pbm = pbus->sysdata;
1189 int ret;
1190
1191 if (pbm == NULL || pbm->parent == NULL) {
1192 ret = -ENXIO;
1193 } else {
6c108f12 1194 ret = pbm->index;
1da177e4
LT		 1195 }
1196
1197 return ret;
1198}
1199EXPORT_SYMBOL(pci_domain_nr);
1200
35a17eb6
DM		 1201#ifdef CONFIG_PCI_MSI
1202int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1203{
a2fb23af 1204 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
e9870c4c 1205 int virt_irq;
35a17eb6 1206
e9870c4c 1207 if (!pbm->setup_msi_irq)
35a17eb6
DM		 1208 return -EINVAL;
1209
e9870c4c 1210 return pbm->setup_msi_irq(&virt_irq, pdev, desc);
35a17eb6
DM		 1211}
1212
1213void arch_teardown_msi_irq(unsigned int virt_irq)
1214{
abfd336c 1215 struct msi_desc *entry = get_irq_msi(virt_irq);
35a17eb6 1216 struct pci_dev *pdev = entry->dev;
a2fb23af 1217 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6 1218
e9870c4c 1219 if (!pbm->teardown_msi_irq)
35a17eb6
DM		 1220 return;
1221
e9870c4c 1222 return pbm->teardown_msi_irq(virt_irq, pdev);
35a17eb6
DM		 1223}
1224#endif /* !(CONFIG_PCI_MSI) */
1225
f6d0f9ea
DM		 1226struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1227{
a2fb23af 1228 return pdev->dev.archdata.prom_node;
f6d0f9ea
DM		 1229}
1230EXPORT_SYMBOL(pci_device_to_OF_node);
1231
ad7ad57c
DM		 1232static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
1233{
1234 struct pci_dev *ali_isa_bridge;
1235 u8 val;
1236
1237 /* ALI sound chips generate 31-bits of DMA, a special register
1238 * determines what bit 31 is emitted as.
1239 */
1240 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
1241 PCI_DEVICE_ID_AL_M1533,
1242 NULL);
1243
1244 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
1245 if (set_bit)
1246 val |= 0x01;
1247 else
1248 val &= ~0x01;
1249 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
1250 pci_dev_put(ali_isa_bridge);
1251}
1252
1253int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
1254{
1255 u64 dma_addr_mask;
1256
1257 if (pdev == NULL) {
1258 dma_addr_mask = 0xffffffff;
1259 } else {
1260 struct iommu *iommu = pdev->dev.archdata.iommu;
1261
1262 dma_addr_mask = iommu->dma_addr_mask;
1263
1264 if (pdev->vendor == PCI_VENDOR_ID_AL &&
1265 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
1266 device_mask == 0x7fffffff) {
1267 ali_sound_dma_hack(pdev,
1268 (dma_addr_mask & 0x80000000) != 0);
1269 return 1;
1270 }
1271 }
1272
1273 if (device_mask >= (1UL << 32UL))
1274 return 0;
1275
1276 return (device_mask & dma_addr_mask) == dma_addr_mask;
1277}
1278
1da177e4 1279#endif /* !(CONFIG_PCI) */
Linux 6.x block layer and io_uring tree(s)