Commit | Line | Data |
---|---|---|
a2fb23af | 1 | /* pci.c: UltraSparc PCI controller support. |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
a2fb23af DM |
6 | * |
7 | * OF tree based PCI bus probing taken from the PowerPC port | |
8 | * with minor modifications, see there for credits. | |
1da177e4 LT |
9 | */ |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/string.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/capability.h> | |
16 | #include <linux/errno.h> | |
c57c2ffb | 17 | #include <linux/pci.h> |
35a17eb6 DM |
18 | #include <linux/msi.h> |
19 | #include <linux/irq.h> | |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | ||
22 | #include <asm/uaccess.h> | |
1da177e4 LT |
23 | #include <asm/pgtable.h> |
24 | #include <asm/irq.h> | |
25 | #include <asm/ebus.h> | |
26 | #include <asm/isa.h> | |
e87dc350 | 27 | #include <asm/prom.h> |
01f94c4a | 28 | #include <asm/apb.h> |
1da177e4 | 29 | |
1e8a8cc5 DM |
30 | #include "pci_impl.h" |
31 | ||
1da177e4 LT |
32 | unsigned long pci_memspace_mask = 0xffffffffUL; |
33 | ||
34 | #ifndef CONFIG_PCI | |
35 | /* A "nop" PCI implementation. */ | |
36 | asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn, | |
37 | unsigned long off, unsigned long len, | |
38 | unsigned char *buf) | |
39 | { | |
40 | return 0; | |
41 | } | |
42 | asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn, | |
43 | unsigned long off, unsigned long len, | |
44 | unsigned char *buf) | |
45 | { | |
46 | return 0; | |
47 | } | |
48 | #else | |
49 | ||
50 | /* List of all PCI controllers found in the system. */ | |
34768bc8 | 51 | struct pci_pbm_info *pci_pbm_root = NULL; |
1da177e4 | 52 | |
6c108f12 DM |
53 | /* Each PBM found gets a unique index. */ |
54 | int pci_num_pbms = 0; | |
1da177e4 | 55 | |
1da177e4 LT |
56 | volatile int pci_poke_in_progress; |
57 | volatile int pci_poke_cpu = -1; | |
58 | volatile int pci_poke_faulted; | |
59 | ||
60 | static DEFINE_SPINLOCK(pci_poke_lock); | |
61 | ||
62 | void pci_config_read8(u8 *addr, u8 *ret) | |
63 | { | |
64 | unsigned long flags; | |
65 | u8 byte; | |
66 | ||
67 | spin_lock_irqsave(&pci_poke_lock, flags); | |
68 | pci_poke_cpu = smp_processor_id(); | |
69 | pci_poke_in_progress = 1; | |
70 | pci_poke_faulted = 0; | |
71 | __asm__ __volatile__("membar #Sync\n\t" | |
72 | "lduba [%1] %2, %0\n\t" | |
73 | "membar #Sync" | |
74 | : "=r" (byte) | |
75 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
76 | : "memory"); | |
77 | pci_poke_in_progress = 0; | |
78 | pci_poke_cpu = -1; | |
79 | if (!pci_poke_faulted) | |
80 | *ret = byte; | |
81 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
82 | } | |
83 | ||
84 | void pci_config_read16(u16 *addr, u16 *ret) | |
85 | { | |
86 | unsigned long flags; | |
87 | u16 word; | |
88 | ||
89 | spin_lock_irqsave(&pci_poke_lock, flags); | |
90 | pci_poke_cpu = smp_processor_id(); | |
91 | pci_poke_in_progress = 1; | |
92 | pci_poke_faulted = 0; | |
93 | __asm__ __volatile__("membar #Sync\n\t" | |
94 | "lduha [%1] %2, %0\n\t" | |
95 | "membar #Sync" | |
96 | : "=r" (word) | |
97 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
98 | : "memory"); | |
99 | pci_poke_in_progress = 0; | |
100 | pci_poke_cpu = -1; | |
101 | if (!pci_poke_faulted) | |
102 | *ret = word; | |
103 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
104 | } | |
105 | ||
106 | void pci_config_read32(u32 *addr, u32 *ret) | |
107 | { | |
108 | unsigned long flags; | |
109 | u32 dword; | |
110 | ||
111 | spin_lock_irqsave(&pci_poke_lock, flags); | |
112 | pci_poke_cpu = smp_processor_id(); | |
113 | pci_poke_in_progress = 1; | |
114 | pci_poke_faulted = 0; | |
115 | __asm__ __volatile__("membar #Sync\n\t" | |
116 | "lduwa [%1] %2, %0\n\t" | |
117 | "membar #Sync" | |
118 | : "=r" (dword) | |
119 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
120 | : "memory"); | |
121 | pci_poke_in_progress = 0; | |
122 | pci_poke_cpu = -1; | |
123 | if (!pci_poke_faulted) | |
124 | *ret = dword; | |
125 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
126 | } | |
127 | ||
128 | void pci_config_write8(u8 *addr, u8 val) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&pci_poke_lock, flags); | |
133 | pci_poke_cpu = smp_processor_id(); | |
134 | pci_poke_in_progress = 1; | |
135 | pci_poke_faulted = 0; | |
136 | __asm__ __volatile__("membar #Sync\n\t" | |
137 | "stba %0, [%1] %2\n\t" | |
138 | "membar #Sync" | |
139 | : /* no outputs */ | |
140 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
141 | : "memory"); | |
142 | pci_poke_in_progress = 0; | |
143 | pci_poke_cpu = -1; | |
144 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
145 | } | |
146 | ||
147 | void pci_config_write16(u16 *addr, u16 val) | |
148 | { | |
149 | unsigned long flags; | |
150 | ||
151 | spin_lock_irqsave(&pci_poke_lock, flags); | |
152 | pci_poke_cpu = smp_processor_id(); | |
153 | pci_poke_in_progress = 1; | |
154 | pci_poke_faulted = 0; | |
155 | __asm__ __volatile__("membar #Sync\n\t" | |
156 | "stha %0, [%1] %2\n\t" | |
157 | "membar #Sync" | |
158 | : /* no outputs */ | |
159 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
160 | : "memory"); | |
161 | pci_poke_in_progress = 0; | |
162 | pci_poke_cpu = -1; | |
163 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
164 | } | |
165 | ||
166 | void pci_config_write32(u32 *addr, u32 val) | |
167 | { | |
168 | unsigned long flags; | |
169 | ||
170 | spin_lock_irqsave(&pci_poke_lock, flags); | |
171 | pci_poke_cpu = smp_processor_id(); | |
172 | pci_poke_in_progress = 1; | |
173 | pci_poke_faulted = 0; | |
174 | __asm__ __volatile__("membar #Sync\n\t" | |
175 | "stwa %0, [%1] %2\n\t" | |
176 | "membar #Sync" | |
177 | : /* no outputs */ | |
178 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
179 | : "memory"); | |
180 | pci_poke_in_progress = 0; | |
181 | pci_poke_cpu = -1; | |
182 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
183 | } | |
184 | ||
185 | /* Probe for all PCI controllers in the system. */ | |
e87dc350 DM |
186 | extern void sabre_init(struct device_node *, const char *); |
187 | extern void psycho_init(struct device_node *, const char *); | |
188 | extern void schizo_init(struct device_node *, const char *); | |
189 | extern void schizo_plus_init(struct device_node *, const char *); | |
190 | extern void tomatillo_init(struct device_node *, const char *); | |
191 | extern void sun4v_pci_init(struct device_node *, const char *); | |
861fe906 | 192 | extern void fire_pci_init(struct device_node *, const char *); |
1da177e4 LT |
193 | |
194 | static struct { | |
195 | char *model_name; | |
e87dc350 | 196 | void (*init)(struct device_node *, const char *); |
1da177e4 LT |
197 | } pci_controller_table[] __initdata = { |
198 | { "SUNW,sabre", sabre_init }, | |
199 | { "pci108e,a000", sabre_init }, | |
200 | { "pci108e,a001", sabre_init }, | |
201 | { "SUNW,psycho", psycho_init }, | |
202 | { "pci108e,8000", psycho_init }, | |
203 | { "SUNW,schizo", schizo_init }, | |
204 | { "pci108e,8001", schizo_init }, | |
205 | { "SUNW,schizo+", schizo_plus_init }, | |
206 | { "pci108e,8002", schizo_plus_init }, | |
207 | { "SUNW,tomatillo", tomatillo_init }, | |
208 | { "pci108e,a801", tomatillo_init }, | |
8f6a93a1 | 209 | { "SUNW,sun4v-pci", sun4v_pci_init }, |
861fe906 | 210 | { "pciex108e,80f0", fire_pci_init }, |
1da177e4 LT |
211 | }; |
212 | #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \ | |
213 | sizeof(pci_controller_table[0])) | |
214 | ||
e87dc350 | 215 | static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
216 | { |
217 | int i; | |
218 | ||
219 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
220 | if (!strncmp(model_name, | |
221 | pci_controller_table[i].model_name, | |
222 | namelen)) { | |
e87dc350 | 223 | pci_controller_table[i].init(dp, model_name); |
1da177e4 LT |
224 | return 1; |
225 | } | |
226 | } | |
1da177e4 LT |
227 | |
228 | return 0; | |
229 | } | |
230 | ||
e87dc350 | 231 | static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
232 | { |
233 | int i; | |
234 | ||
235 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
236 | if (!strncmp(model_name, | |
237 | pci_controller_table[i].model_name, | |
238 | namelen)) { | |
239 | return 1; | |
240 | } | |
241 | } | |
242 | return 0; | |
243 | } | |
244 | ||
e87dc350 | 245 | static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *)) |
1da177e4 | 246 | { |
e87dc350 | 247 | struct device_node *dp; |
1da177e4 LT |
248 | int count = 0; |
249 | ||
e87dc350 DM |
250 | for_each_node_by_name(dp, "pci") { |
251 | struct property *prop; | |
1da177e4 LT |
252 | int len; |
253 | ||
e87dc350 DM |
254 | prop = of_find_property(dp, "model", &len); |
255 | if (!prop) | |
256 | prop = of_find_property(dp, "compatible", &len); | |
257 | ||
258 | if (prop) { | |
259 | const char *model = prop->value; | |
1da177e4 LT |
260 | int item_len = 0; |
261 | ||
262 | /* Our value may be a multi-valued string in the | |
263 | * case of some compatible properties. For sanity, | |
e87dc350 DM |
264 | * only try the first one. |
265 | */ | |
266 | while (model[item_len] && len) { | |
1da177e4 LT |
267 | len--; |
268 | item_len++; | |
269 | } | |
270 | ||
e87dc350 | 271 | if (handler(model, item_len, dp)) |
1da177e4 LT |
272 | count++; |
273 | } | |
1da177e4 LT |
274 | } |
275 | ||
276 | return count; | |
277 | } | |
278 | ||
279 | ||
280 | /* Is there some PCI controller in the system? */ | |
281 | int __init pcic_present(void) | |
282 | { | |
283 | return pci_controller_scan(pci_is_controller); | |
284 | } | |
285 | ||
286 | /* Find each controller in the system, attach and initialize | |
287 | * software state structure for each and link into the | |
34768bc8 | 288 | * pci_pbm_root. Setup the controller enough such |
1da177e4 LT |
289 | * that bus scanning can be done. |
290 | */ | |
291 | static void __init pci_controller_probe(void) | |
292 | { | |
293 | printk("PCI: Probing for controllers.\n"); | |
294 | ||
295 | pci_controller_scan(pci_controller_init); | |
296 | } | |
297 | ||
5840fc66 DM |
298 | static int ofpci_verbose; |
299 | ||
300 | static int __init ofpci_debug(char *str) | |
301 | { | |
302 | int val = 0; | |
303 | ||
304 | get_option(&str, &val); | |
305 | if (val) | |
306 | ofpci_verbose = 1; | |
307 | return 1; | |
308 | } | |
309 | ||
310 | __setup("ofpci_debug=", ofpci_debug); | |
311 | ||
a2fb23af DM |
312 | static unsigned long pci_parse_of_flags(u32 addr0) |
313 | { | |
314 | unsigned long flags = 0; | |
315 | ||
316 | if (addr0 & 0x02000000) { | |
317 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; | |
318 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
319 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
320 | if (addr0 & 0x40000000) | |
321 | flags |= IORESOURCE_PREFETCH | |
322 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
323 | } else if (addr0 & 0x01000000) | |
324 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; | |
325 | return flags; | |
326 | } | |
327 | ||
328 | /* The of_device layer has translated all of the assigned-address properties | |
329 | * into physical address resources, we only have to figure out the register | |
330 | * mapping. | |
331 | */ | |
332 | static void pci_parse_of_addrs(struct of_device *op, | |
333 | struct device_node *node, | |
334 | struct pci_dev *dev) | |
335 | { | |
336 | struct resource *op_res; | |
337 | const u32 *addrs; | |
338 | int proplen; | |
339 | ||
340 | addrs = of_get_property(node, "assigned-addresses", &proplen); | |
341 | if (!addrs) | |
342 | return; | |
5840fc66 DM |
343 | if (ofpci_verbose) |
344 | printk(" parse addresses (%d bytes) @ %p\n", | |
345 | proplen, addrs); | |
a2fb23af DM |
346 | op_res = &op->resource[0]; |
347 | for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { | |
348 | struct resource *res; | |
349 | unsigned long flags; | |
350 | int i; | |
351 | ||
352 | flags = pci_parse_of_flags(addrs[0]); | |
353 | if (!flags) | |
354 | continue; | |
355 | i = addrs[0] & 0xff; | |
5840fc66 DM |
356 | if (ofpci_verbose) |
357 | printk(" start: %lx, end: %lx, i: %x\n", | |
358 | op_res->start, op_res->end, i); | |
a2fb23af DM |
359 | |
360 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
361 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
362 | } else if (i == dev->rom_base_reg) { | |
363 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
364 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
365 | } else { | |
366 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
367 | continue; | |
368 | } | |
369 | res->start = op_res->start; | |
370 | res->end = op_res->end; | |
371 | res->flags = flags; | |
372 | res->name = pci_name(dev); | |
373 | } | |
374 | } | |
375 | ||
376 | struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, | |
377 | struct device_node *node, | |
97b3cf05 DM |
378 | struct pci_bus *bus, int devfn, |
379 | int host_controller) | |
a2fb23af DM |
380 | { |
381 | struct dev_archdata *sd; | |
382 | struct pci_dev *dev; | |
383 | const char *type; | |
01f94c4a | 384 | u32 class; |
a2fb23af | 385 | |
26e6385f | 386 | dev = alloc_pci_dev(); |
a2fb23af DM |
387 | if (!dev) |
388 | return NULL; | |
389 | ||
390 | sd = &dev->dev.archdata; | |
391 | sd->iommu = pbm->iommu; | |
392 | sd->stc = &pbm->stc; | |
393 | sd->host_controller = pbm; | |
394 | sd->prom_node = node; | |
395 | sd->op = of_find_device_by_node(node); | |
a2fb23af | 396 | |
ad7ad57c DM |
397 | sd = &sd->op->dev.archdata; |
398 | sd->iommu = pbm->iommu; | |
399 | sd->stc = &pbm->stc; | |
400 | ||
a2fb23af DM |
401 | type = of_get_property(node, "device_type", NULL); |
402 | if (type == NULL) | |
403 | type = ""; | |
404 | ||
5840fc66 DM |
405 | if (ofpci_verbose) |
406 | printk(" create device, devfn: %x, type: %s\n", | |
407 | devfn, type); | |
a2fb23af DM |
408 | |
409 | dev->bus = bus; | |
410 | dev->sysdata = node; | |
411 | dev->dev.parent = bus->bridge; | |
412 | dev->dev.bus = &pci_bus_type; | |
413 | dev->devfn = devfn; | |
414 | dev->multifunction = 0; /* maybe a lie? */ | |
415 | ||
97b3cf05 | 416 | if (host_controller) { |
a2d6ea01 DM |
417 | if (tlb_type != hypervisor) { |
418 | pci_read_config_word(dev, PCI_VENDOR_ID, | |
419 | &dev->vendor); | |
420 | pci_read_config_word(dev, PCI_DEVICE_ID, | |
421 | &dev->device); | |
422 | } else { | |
423 | dev->vendor = PCI_VENDOR_ID_SUN; | |
424 | dev->device = 0x80f0; | |
425 | } | |
97b3cf05 | 426 | dev->cfg_size = 256; |
28f57e77 DM |
427 | dev->class = PCI_CLASS_BRIDGE_HOST << 8; |
428 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
429 | 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 DM |
430 | } else { |
431 | dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); | |
432 | dev->device = of_getintprop_default(node, "device-id", 0xffff); | |
433 | dev->subsystem_vendor = | |
434 | of_getintprop_default(node, "subsystem-vendor-id", 0); | |
435 | dev->subsystem_device = | |
436 | of_getintprop_default(node, "subsystem-id", 0); | |
437 | ||
438 | dev->cfg_size = pci_cfg_space_size(dev); | |
01f94c4a | 439 | |
97b3cf05 DM |
440 | /* We can't actually use the firmware value, we have |
441 | * to read what is in the register right now. One | |
442 | * reason is that in the case of IDE interfaces the | |
443 | * firmware can sample the value before the the IDE | |
444 | * interface is programmed into native mode. | |
445 | */ | |
446 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
447 | dev->class = class >> 8; | |
b8a3a521 | 448 | dev->revision = class & 0xff; |
28f57e77 DM |
449 | |
450 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
451 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 | 452 | } |
5840fc66 DM |
453 | if (ofpci_verbose) |
454 | printk(" class: 0x%x device name: %s\n", | |
455 | dev->class, pci_name(dev)); | |
a2fb23af | 456 | |
861fe906 DM |
457 | /* I have seen IDE devices which will not respond to |
458 | * the bmdma simplex check reads if bus mastering is | |
459 | * disabled. | |
460 | */ | |
461 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
462 | pci_set_master(dev); | |
463 | ||
a2fb23af DM |
464 | dev->current_state = 4; /* unknown power state */ |
465 | dev->error_state = pci_channel_io_normal; | |
466 | ||
97b3cf05 | 467 | if (host_controller) { |
a2fb23af DM |
468 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; |
469 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
97b3cf05 | 470 | dev->irq = PCI_IRQ_NONE; |
a2fb23af | 471 | } else { |
97b3cf05 DM |
472 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
473 | /* a PCI-PCI bridge */ | |
474 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
475 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
476 | } else if (!strcmp(type, "cardbus")) { | |
477 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
478 | } else { | |
479 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
480 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
a2fb23af | 481 | |
97b3cf05 DM |
482 | dev->irq = sd->op->irqs[0]; |
483 | if (dev->irq == 0xffffffff) | |
484 | dev->irq = PCI_IRQ_NONE; | |
485 | } | |
a2fb23af | 486 | } |
a2fb23af DM |
487 | pci_parse_of_addrs(sd->op, node, dev); |
488 | ||
5840fc66 DM |
489 | if (ofpci_verbose) |
490 | printk(" adding to system ...\n"); | |
a2fb23af DM |
491 | |
492 | pci_device_add(dev, bus); | |
493 | ||
494 | return dev; | |
495 | } | |
496 | ||
a6009dda | 497 | static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) |
01f94c4a DM |
498 | { |
499 | u32 idx, first, last; | |
500 | ||
501 | first = 8; | |
502 | last = 0; | |
503 | for (idx = 0; idx < 8; idx++) { | |
504 | if ((map & (1 << idx)) != 0) { | |
505 | if (first > idx) | |
506 | first = idx; | |
507 | if (last < idx) | |
508 | last = idx; | |
509 | } | |
510 | } | |
511 | ||
512 | *first_p = first; | |
513 | *last_p = last; | |
514 | } | |
515 | ||
f16537ba DM |
516 | static void pci_resource_adjust(struct resource *res, |
517 | struct resource *root) | |
0bae5f81 DM |
518 | { |
519 | res->start += root->start; | |
520 | res->end += root->start; | |
521 | } | |
522 | ||
8c2786cf DM |
523 | /* For PCI bus devices which lack a 'ranges' property we interrogate |
524 | * the config space values to set the resources, just like the generic | |
525 | * Linux PCI probing code does. | |
526 | */ | |
527 | static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev, | |
528 | struct pci_bus *bus, | |
529 | struct pci_pbm_info *pbm) | |
530 | { | |
531 | struct resource *res; | |
532 | u8 io_base_lo, io_limit_lo; | |
533 | u16 mem_base_lo, mem_limit_lo; | |
534 | unsigned long base, limit; | |
535 | ||
536 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
537 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
538 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
539 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
540 | ||
541 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
542 | u16 io_base_hi, io_limit_hi; | |
543 | ||
544 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
545 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
546 | base |= (io_base_hi << 16); | |
547 | limit |= (io_limit_hi << 16); | |
548 | } | |
549 | ||
550 | res = bus->resource[0]; | |
551 | if (base <= limit) { | |
552 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
553 | if (!res->start) | |
554 | res->start = base; | |
555 | if (!res->end) | |
556 | res->end = limit + 0xfff; | |
557 | pci_resource_adjust(res, &pbm->io_space); | |
558 | } | |
559 | ||
560 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
561 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
562 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
563 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
564 | ||
565 | res = bus->resource[1]; | |
566 | if (base <= limit) { | |
567 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
568 | IORESOURCE_MEM); | |
569 | res->start = base; | |
570 | res->end = limit + 0xfffff; | |
571 | pci_resource_adjust(res, &pbm->mem_space); | |
572 | } | |
573 | ||
574 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
575 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
576 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
577 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
578 | ||
579 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
580 | u32 mem_base_hi, mem_limit_hi; | |
581 | ||
582 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
583 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
584 | ||
585 | /* | |
586 | * Some bridges set the base > limit by default, and some | |
587 | * (broken) BIOSes do not initialize them. If we find | |
588 | * this, just assume they are not being used. | |
589 | */ | |
590 | if (mem_base_hi <= mem_limit_hi) { | |
591 | base |= ((long) mem_base_hi) << 32; | |
592 | limit |= ((long) mem_limit_hi) << 32; | |
593 | } | |
594 | } | |
595 | ||
596 | res = bus->resource[2]; | |
597 | if (base <= limit) { | |
598 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
599 | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
600 | res->start = base; | |
601 | res->end = limit + 0xfffff; | |
602 | pci_resource_adjust(res, &pbm->mem_space); | |
603 | } | |
604 | } | |
605 | ||
01f94c4a DM |
606 | /* Cook up fake bus resources for SUNW,simba PCI bridges which lack |
607 | * a proper 'ranges' property. | |
608 | */ | |
a6009dda DM |
609 | static void __devinit apb_fake_ranges(struct pci_dev *dev, |
610 | struct pci_bus *bus, | |
611 | struct pci_pbm_info *pbm) | |
01f94c4a DM |
612 | { |
613 | struct resource *res; | |
614 | u32 first, last; | |
615 | u8 map; | |
616 | ||
617 | pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); | |
618 | apb_calc_first_last(map, &first, &last); | |
619 | res = bus->resource[0]; | |
620 | res->start = (first << 21); | |
621 | res->end = (last << 21) + ((1 << 21) - 1); | |
622 | res->flags = IORESOURCE_IO; | |
0bae5f81 | 623 | pci_resource_adjust(res, &pbm->io_space); |
01f94c4a DM |
624 | |
625 | pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); | |
626 | apb_calc_first_last(map, &first, &last); | |
627 | res = bus->resource[1]; | |
628 | res->start = (first << 21); | |
629 | res->end = (last << 21) + ((1 << 21) - 1); | |
630 | res->flags = IORESOURCE_MEM; | |
0bae5f81 | 631 | pci_resource_adjust(res, &pbm->mem_space); |
01f94c4a DM |
632 | } |
633 | ||
a6009dda DM |
634 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
635 | struct device_node *node, | |
636 | struct pci_bus *bus); | |
a2fb23af DM |
637 | |
638 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
639 | ||
a6009dda DM |
640 | static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, |
641 | struct device_node *node, | |
642 | struct pci_dev *dev) | |
a2fb23af DM |
643 | { |
644 | struct pci_bus *bus; | |
645 | const u32 *busrange, *ranges; | |
01f94c4a | 646 | int len, i, simba; |
a2fb23af DM |
647 | struct resource *res; |
648 | unsigned int flags; | |
649 | u64 size; | |
650 | ||
5840fc66 DM |
651 | if (ofpci_verbose) |
652 | printk("of_scan_pci_bridge(%s)\n", node->full_name); | |
a2fb23af DM |
653 | |
654 | /* parse bus-range property */ | |
655 | busrange = of_get_property(node, "bus-range", &len); | |
656 | if (busrange == NULL || len != 8) { | |
657 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", | |
658 | node->full_name); | |
659 | return; | |
660 | } | |
661 | ranges = of_get_property(node, "ranges", &len); | |
01f94c4a | 662 | simba = 0; |
a2fb23af | 663 | if (ranges == NULL) { |
a165b420 | 664 | const char *model = of_get_property(node, "model", NULL); |
8c2786cf | 665 | if (model && !strcmp(model, "SUNW,simba")) |
01f94c4a | 666 | simba = 1; |
a2fb23af DM |
667 | } |
668 | ||
669 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
670 | if (!bus) { | |
671 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
672 | node->full_name); | |
673 | return; | |
674 | } | |
675 | ||
676 | bus->primary = dev->bus->number; | |
677 | bus->subordinate = busrange[1]; | |
678 | bus->bridge_ctl = 0; | |
679 | ||
01f94c4a | 680 | /* parse ranges property, or cook one up by hand for Simba */ |
a2fb23af DM |
681 | /* PCI #address-cells == 3 and #size-cells == 2 always */ |
682 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
683 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
684 | res->flags = 0; | |
685 | bus->resource[i] = res; | |
686 | ++res; | |
687 | } | |
01f94c4a DM |
688 | if (simba) { |
689 | apb_fake_ranges(dev, bus, pbm); | |
8c2786cf DM |
690 | goto after_ranges; |
691 | } else if (ranges == NULL) { | |
692 | pci_cfg_fake_ranges(dev, bus, pbm); | |
693 | goto after_ranges; | |
01f94c4a | 694 | } |
a2fb23af DM |
695 | i = 1; |
696 | for (; len >= 32; len -= 32, ranges += 8) { | |
697 | struct resource *root; | |
698 | ||
699 | flags = pci_parse_of_flags(ranges[0]); | |
700 | size = GET_64BIT(ranges, 6); | |
701 | if (flags == 0 || size == 0) | |
702 | continue; | |
703 | if (flags & IORESOURCE_IO) { | |
704 | res = bus->resource[0]; | |
705 | if (res->flags) { | |
706 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
707 | " for bridge %s\n", node->full_name); | |
708 | continue; | |
709 | } | |
710 | root = &pbm->io_space; | |
711 | } else { | |
712 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
713 | printk(KERN_ERR "PCI: too many memory ranges" | |
714 | " for bridge %s\n", node->full_name); | |
715 | continue; | |
716 | } | |
717 | res = bus->resource[i]; | |
718 | ++i; | |
719 | root = &pbm->mem_space; | |
720 | } | |
721 | ||
722 | res->start = GET_64BIT(ranges, 1); | |
723 | res->end = res->start + size - 1; | |
724 | res->flags = flags; | |
725 | ||
726 | /* Another way to implement this would be to add an of_device | |
727 | * layer routine that can calculate a resource for a given | |
728 | * range property value in a PCI device. | |
729 | */ | |
0bae5f81 | 730 | pci_resource_adjust(res, root); |
a2fb23af | 731 | } |
8c2786cf | 732 | after_ranges: |
a2fb23af DM |
733 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), |
734 | bus->number); | |
5840fc66 DM |
735 | if (ofpci_verbose) |
736 | printk(" bus name: %s\n", bus->name); | |
a2fb23af DM |
737 | |
738 | pci_of_scan_bus(pbm, node, bus); | |
739 | } | |
740 | ||
a6009dda DM |
741 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
742 | struct device_node *node, | |
743 | struct pci_bus *bus) | |
a2fb23af DM |
744 | { |
745 | struct device_node *child; | |
746 | const u32 *reg; | |
747 | int reglen, devfn; | |
748 | struct pci_dev *dev; | |
749 | ||
5840fc66 DM |
750 | if (ofpci_verbose) |
751 | printk("PCI: scan_bus[%s] bus no %d\n", | |
752 | node->full_name, bus->number); | |
a2fb23af DM |
753 | |
754 | child = NULL; | |
755 | while ((child = of_get_next_child(node, child)) != NULL) { | |
5840fc66 DM |
756 | if (ofpci_verbose) |
757 | printk(" * %s\n", child->full_name); | |
a2fb23af DM |
758 | reg = of_get_property(child, "reg", ®len); |
759 | if (reg == NULL || reglen < 20) | |
760 | continue; | |
761 | devfn = (reg[0] >> 8) & 0xff; | |
762 | ||
763 | /* create a new pci_dev for this device */ | |
97b3cf05 | 764 | dev = of_create_pci_dev(pbm, child, bus, devfn, 0); |
a2fb23af DM |
765 | if (!dev) |
766 | continue; | |
5840fc66 DM |
767 | if (ofpci_verbose) |
768 | printk("PCI: dev header type: %x\n", | |
769 | dev->hdr_type); | |
a2fb23af DM |
770 | |
771 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
772 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
773 | of_scan_pci_bridge(pbm, child, dev); | |
774 | } | |
775 | } | |
776 | ||
777 | static ssize_t | |
778 | show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) | |
779 | { | |
780 | struct pci_dev *pdev; | |
781 | struct device_node *dp; | |
782 | ||
783 | pdev = to_pci_dev(dev); | |
784 | dp = pdev->dev.archdata.prom_node; | |
785 | ||
786 | return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); | |
787 | } | |
788 | ||
789 | static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); | |
790 | ||
791 | static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) | |
792 | { | |
793 | struct pci_dev *dev; | |
a378fd0e | 794 | struct pci_bus *child_bus; |
a2fb23af DM |
795 | int err; |
796 | ||
797 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
798 | /* we don't really care if we can create this file or | |
799 | * not, but we need to assign the result of the call | |
800 | * or the world will fall under alien invasion and | |
801 | * everybody will be frozen on a spaceship ready to be | |
802 | * eaten on alpha centauri by some green and jelly | |
803 | * humanoid. | |
804 | */ | |
805 | err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); | |
806 | } | |
a378fd0e DM |
807 | list_for_each_entry(child_bus, &bus->children, node) |
808 | pci_bus_register_of_sysfs(child_bus); | |
a2fb23af DM |
809 | } |
810 | ||
97b3cf05 DM |
811 | int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev, |
812 | unsigned int devfn, | |
813 | int where, int size, | |
814 | u32 *value) | |
815 | { | |
816 | static u8 fake_pci_config[] = { | |
817 | 0x8e, 0x10, /* Vendor: 0x108e (Sun) */ | |
a2d6ea01 | 818 | 0xf0, 0x80, /* Device: 0x80f0 (Fire) */ |
97b3cf05 DM |
819 | 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */ |
820 | 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */ | |
821 | 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */ | |
822 | 0x00, /* Cacheline: 0x00 */ | |
823 | 0x40, /* Latency: 0x40 */ | |
824 | 0x00, /* Header-Type: 0x00 normal */ | |
825 | }; | |
826 | ||
827 | *value = 0; | |
828 | if (where >= 0 && where < sizeof(fake_pci_config) && | |
829 | (where + size) >= 0 && | |
830 | (where + size) < sizeof(fake_pci_config) && | |
831 | size <= sizeof(u32)) { | |
832 | while (size--) { | |
833 | *value <<= 8; | |
834 | *value |= fake_pci_config[where + size]; | |
835 | } | |
836 | } | |
837 | ||
838 | return PCIBIOS_SUCCESSFUL; | |
839 | } | |
840 | ||
841 | int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev, | |
842 | unsigned int devfn, | |
843 | int where, int size, | |
844 | u32 value) | |
845 | { | |
846 | return PCIBIOS_SUCCESSFUL; | |
847 | } | |
848 | ||
a6009dda | 849 | struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm) |
a2fb23af | 850 | { |
a2fb23af | 851 | struct device_node *node = pbm->prom_node; |
97b3cf05 | 852 | struct pci_dev *host_pdev; |
a2fb23af DM |
853 | struct pci_bus *bus; |
854 | ||
855 | printk("PCI: Scanning PBM %s\n", node->full_name); | |
856 | ||
857 | /* XXX parent device? XXX */ | |
f1cd8de2 | 858 | bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm); |
a2fb23af DM |
859 | if (!bus) { |
860 | printk(KERN_ERR "Failed to create bus for %s\n", | |
861 | node->full_name); | |
862 | return NULL; | |
863 | } | |
864 | bus->secondary = pbm->pci_first_busno; | |
865 | bus->subordinate = pbm->pci_last_busno; | |
866 | ||
867 | bus->resource[0] = &pbm->io_space; | |
868 | bus->resource[1] = &pbm->mem_space; | |
869 | ||
97b3cf05 DM |
870 | /* Create the dummy host bridge and link it in. */ |
871 | host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1); | |
872 | bus->self = host_pdev; | |
873 | ||
a2fb23af DM |
874 | pci_of_scan_bus(pbm, node, bus); |
875 | pci_bus_add_devices(bus); | |
876 | pci_bus_register_of_sysfs(bus); | |
877 | ||
878 | return bus; | |
879 | } | |
880 | ||
1da177e4 LT |
881 | static void __init pci_scan_each_controller_bus(void) |
882 | { | |
34768bc8 | 883 | struct pci_pbm_info *pbm; |
1da177e4 | 884 | |
34768bc8 DM |
885 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) |
886 | pbm->scan_bus(pbm); | |
1da177e4 LT |
887 | } |
888 | ||
1da177e4 LT |
889 | extern void power_init(void); |
890 | ||
891 | static int __init pcibios_init(void) | |
892 | { | |
893 | pci_controller_probe(); | |
34768bc8 | 894 | if (pci_pbm_root == NULL) |
1da177e4 LT |
895 | return 0; |
896 | ||
897 | pci_scan_each_controller_bus(); | |
898 | ||
1da177e4 LT |
899 | isa_init(); |
900 | ebus_init(); | |
1da177e4 LT |
901 | power_init(); |
902 | ||
903 | return 0; | |
904 | } | |
905 | ||
906 | subsys_initcall(pcibios_init); | |
907 | ||
f6b45da1 | 908 | void __devinit pcibios_fixup_bus(struct pci_bus *pbus) |
1da177e4 LT |
909 | { |
910 | struct pci_pbm_info *pbm = pbus->sysdata; | |
911 | ||
912 | /* Generic PCI bus probing sets these to point at | |
913 | * &io{port,mem}_resouce which is wrong for us. | |
914 | */ | |
915 | pbus->resource[0] = &pbm->io_space; | |
916 | pbus->resource[1] = &pbm->mem_space; | |
917 | } | |
918 | ||
085ae41f | 919 | struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r) |
1da177e4 LT |
920 | { |
921 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
085ae41f | 922 | struct resource *root = NULL; |
1da177e4 | 923 | |
085ae41f | 924 | if (r->flags & IORESOURCE_IO) |
1da177e4 | 925 | root = &pbm->io_space; |
085ae41f | 926 | if (r->flags & IORESOURCE_MEM) |
1da177e4 LT |
927 | root = &pbm->mem_space; |
928 | ||
085ae41f | 929 | return root; |
1da177e4 LT |
930 | } |
931 | ||
932 | void pcibios_update_irq(struct pci_dev *pdev, int irq) | |
933 | { | |
934 | } | |
935 | ||
936 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 937 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
938 | { |
939 | } | |
940 | ||
a2fb23af | 941 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1da177e4 | 942 | { |
a2fb23af DM |
943 | u16 cmd, oldcmd; |
944 | int i; | |
945 | ||
946 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
947 | oldcmd = cmd; | |
948 | ||
949 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
950 | struct resource *res = &dev->resource[i]; | |
951 | ||
952 | /* Only set up the requested stuff */ | |
953 | if (!(mask & (1<<i))) | |
954 | continue; | |
955 | ||
956 | if (res->flags & IORESOURCE_IO) | |
957 | cmd |= PCI_COMMAND_IO; | |
958 | if (res->flags & IORESOURCE_MEM) | |
959 | cmd |= PCI_COMMAND_MEMORY; | |
960 | } | |
961 | ||
962 | if (cmd != oldcmd) { | |
963 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
964 | pci_name(dev), cmd); | |
965 | /* Enable the appropriate bits in the PCI command register. */ | |
966 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
967 | } | |
1da177e4 LT |
968 | return 0; |
969 | } | |
970 | ||
971 | void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, | |
972 | struct resource *res) | |
973 | { | |
974 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
975 | struct resource zero_res, *root; | |
976 | ||
977 | zero_res.start = 0; | |
978 | zero_res.end = 0; | |
979 | zero_res.flags = res->flags; | |
980 | ||
981 | if (res->flags & IORESOURCE_IO) | |
982 | root = &pbm->io_space; | |
983 | else | |
984 | root = &pbm->mem_space; | |
985 | ||
0bae5f81 | 986 | pci_resource_adjust(&zero_res, root); |
1da177e4 LT |
987 | |
988 | region->start = res->start - zero_res.start; | |
989 | region->end = res->end - zero_res.start; | |
990 | } | |
5fdfd42e | 991 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
1da177e4 LT |
992 | |
993 | void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, | |
994 | struct pci_bus_region *region) | |
995 | { | |
996 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
997 | struct resource *root; | |
998 | ||
999 | res->start = region->start; | |
1000 | res->end = region->end; | |
1001 | ||
1002 | if (res->flags & IORESOURCE_IO) | |
1003 | root = &pbm->io_space; | |
1004 | else | |
1005 | root = &pbm->mem_space; | |
1006 | ||
0bae5f81 | 1007 | pci_resource_adjust(res, root); |
1da177e4 | 1008 | } |
41290c14 | 1009 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 1010 | |
f6b45da1 | 1011 | char * __devinit pcibios_setup(char *str) |
1da177e4 | 1012 | { |
1da177e4 LT |
1013 | return str; |
1014 | } | |
1015 | ||
1016 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
1017 | ||
1018 | /* If the user uses a host-bridge as the PCI device, he may use | |
1019 | * this to perform a raw mmap() of the I/O or MEM space behind | |
1020 | * that controller. | |
1021 | * | |
1022 | * This can be useful for execution of x86 PCI bios initialization code | |
1023 | * on a PCI card, like the xfree86 int10 stuff does. | |
1024 | */ | |
1025 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
1026 | enum pci_mmap_state mmap_state) | |
1027 | { | |
a2fb23af | 1028 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
1da177e4 LT |
1029 | unsigned long space_size, user_offset, user_size; |
1030 | ||
3875c5c0 DM |
1031 | if (mmap_state == pci_mmap_io) { |
1032 | space_size = (pbm->io_space.end - | |
1033 | pbm->io_space.start) + 1; | |
1da177e4 | 1034 | } else { |
3875c5c0 DM |
1035 | space_size = (pbm->mem_space.end - |
1036 | pbm->mem_space.start) + 1; | |
1da177e4 LT |
1037 | } |
1038 | ||
1039 | /* Make sure the request is in range. */ | |
1040 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
1041 | user_size = vma->vm_end - vma->vm_start; | |
1042 | ||
1043 | if (user_offset >= space_size || | |
1044 | (user_offset + user_size) > space_size) | |
1045 | return -EINVAL; | |
1046 | ||
3875c5c0 DM |
1047 | if (mmap_state == pci_mmap_io) { |
1048 | vma->vm_pgoff = (pbm->io_space.start + | |
1049 | user_offset) >> PAGE_SHIFT; | |
1da177e4 | 1050 | } else { |
3875c5c0 DM |
1051 | vma->vm_pgoff = (pbm->mem_space.start + |
1052 | user_offset) >> PAGE_SHIFT; | |
1da177e4 LT |
1053 | } |
1054 | ||
1055 | return 0; | |
1056 | } | |
1057 | ||
1058 | /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding | |
1059 | * to the 32-bit pci bus offset for DEV requested by the user. | |
1060 | * | |
1061 | * Basically, the user finds the base address for his device which he wishes | |
1062 | * to mmap. They read the 32-bit value from the config space base register, | |
1063 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
1064 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
1065 | * | |
1066 | * Returns negative error code on failure, zero on success. | |
1067 | */ | |
1068 | static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma, | |
1069 | enum pci_mmap_state mmap_state) | |
1070 | { | |
1071 | unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
1072 | unsigned long user32 = user_offset & pci_memspace_mask; | |
1073 | unsigned long largest_base, this_base, addr32; | |
1074 | int i; | |
1075 | ||
1076 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
1077 | return __pci_mmap_make_offset_bus(dev, vma, mmap_state); | |
1078 | ||
1079 | /* Figure out which base address this is for. */ | |
1080 | largest_base = 0UL; | |
1081 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
1082 | struct resource *rp = &dev->resource[i]; | |
1083 | ||
1084 | /* Active? */ | |
1085 | if (!rp->flags) | |
1086 | continue; | |
1087 | ||
1088 | /* Same type? */ | |
1089 | if (i == PCI_ROM_RESOURCE) { | |
1090 | if (mmap_state != pci_mmap_mem) | |
1091 | continue; | |
1092 | } else { | |
1093 | if ((mmap_state == pci_mmap_io && | |
1094 | (rp->flags & IORESOURCE_IO) == 0) || | |
1095 | (mmap_state == pci_mmap_mem && | |
1096 | (rp->flags & IORESOURCE_MEM) == 0)) | |
1097 | continue; | |
1098 | } | |
1099 | ||
1100 | this_base = rp->start; | |
1101 | ||
1102 | addr32 = (this_base & PAGE_MASK) & pci_memspace_mask; | |
1103 | ||
1104 | if (mmap_state == pci_mmap_io) | |
1105 | addr32 &= 0xffffff; | |
1106 | ||
1107 | if (addr32 <= user32 && this_base > largest_base) | |
1108 | largest_base = this_base; | |
1109 | } | |
1110 | ||
1111 | if (largest_base == 0UL) | |
1112 | return -EINVAL; | |
1113 | ||
1114 | /* Now construct the final physical address. */ | |
1115 | if (mmap_state == pci_mmap_io) | |
1116 | vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT); | |
1117 | else | |
1118 | vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT); | |
1119 | ||
1120 | return 0; | |
1121 | } | |
1122 | ||
1123 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
1124 | * mapping. | |
1125 | */ | |
1126 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
1127 | enum pci_mmap_state mmap_state) | |
1128 | { | |
1129 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
1130 | } | |
1131 | ||
1132 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
1133 | * device mapping. | |
1134 | */ | |
1135 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
1136 | enum pci_mmap_state mmap_state) | |
1137 | { | |
a7a6cac2 | 1138 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
1139 | } |
1140 | ||
1141 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
1142 | * for this architecture. The region in the process to map is described by vm_start | |
1143 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
1144 | * The pci device structure is provided so that architectures may make mapping | |
1145 | * decisions on a per-device or per-bus basis. | |
1146 | * | |
1147 | * Returns a negative error code on failure, zero on success. | |
1148 | */ | |
1149 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
1150 | enum pci_mmap_state mmap_state, | |
1151 | int write_combine) | |
1152 | { | |
1153 | int ret; | |
1154 | ||
1155 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
1156 | if (ret < 0) | |
1157 | return ret; | |
1158 | ||
1159 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
1160 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
1161 | ||
14778d90 | 1162 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1da177e4 LT |
1163 | ret = io_remap_pfn_range(vma, vma->vm_start, |
1164 | vma->vm_pgoff, | |
1165 | vma->vm_end - vma->vm_start, | |
1166 | vma->vm_page_prot); | |
1167 | if (ret) | |
1168 | return ret; | |
1169 | ||
1da177e4 LT |
1170 | return 0; |
1171 | } | |
1172 | ||
1173 | /* Return the domain nuber for this pci bus */ | |
1174 | ||
1175 | int pci_domain_nr(struct pci_bus *pbus) | |
1176 | { | |
1177 | struct pci_pbm_info *pbm = pbus->sysdata; | |
1178 | int ret; | |
1179 | ||
1180 | if (pbm == NULL || pbm->parent == NULL) { | |
1181 | ret = -ENXIO; | |
1182 | } else { | |
6c108f12 | 1183 | ret = pbm->index; |
1da177e4 LT |
1184 | } |
1185 | ||
1186 | return ret; | |
1187 | } | |
1188 | EXPORT_SYMBOL(pci_domain_nr); | |
1189 | ||
35a17eb6 DM |
1190 | #ifdef CONFIG_PCI_MSI |
1191 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
1192 | { | |
a2fb23af | 1193 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
e9870c4c | 1194 | int virt_irq; |
35a17eb6 | 1195 | |
e9870c4c | 1196 | if (!pbm->setup_msi_irq) |
35a17eb6 DM |
1197 | return -EINVAL; |
1198 | ||
e9870c4c | 1199 | return pbm->setup_msi_irq(&virt_irq, pdev, desc); |
35a17eb6 DM |
1200 | } |
1201 | ||
1202 | void arch_teardown_msi_irq(unsigned int virt_irq) | |
1203 | { | |
abfd336c | 1204 | struct msi_desc *entry = get_irq_msi(virt_irq); |
35a17eb6 | 1205 | struct pci_dev *pdev = entry->dev; |
a2fb23af | 1206 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 | 1207 | |
e9870c4c | 1208 | if (!pbm->teardown_msi_irq) |
35a17eb6 DM |
1209 | return; |
1210 | ||
e9870c4c | 1211 | return pbm->teardown_msi_irq(virt_irq, pdev); |
35a17eb6 DM |
1212 | } |
1213 | #endif /* !(CONFIG_PCI_MSI) */ | |
1214 | ||
f6d0f9ea DM |
1215 | struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) |
1216 | { | |
a2fb23af | 1217 | return pdev->dev.archdata.prom_node; |
f6d0f9ea DM |
1218 | } |
1219 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
1220 | ||
ad7ad57c DM |
1221 | static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) |
1222 | { | |
1223 | struct pci_dev *ali_isa_bridge; | |
1224 | u8 val; | |
1225 | ||
1226 | /* ALI sound chips generate 31-bits of DMA, a special register | |
1227 | * determines what bit 31 is emitted as. | |
1228 | */ | |
1229 | ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, | |
1230 | PCI_DEVICE_ID_AL_M1533, | |
1231 | NULL); | |
1232 | ||
1233 | pci_read_config_byte(ali_isa_bridge, 0x7e, &val); | |
1234 | if (set_bit) | |
1235 | val |= 0x01; | |
1236 | else | |
1237 | val &= ~0x01; | |
1238 | pci_write_config_byte(ali_isa_bridge, 0x7e, val); | |
1239 | pci_dev_put(ali_isa_bridge); | |
1240 | } | |
1241 | ||
1242 | int pci_dma_supported(struct pci_dev *pdev, u64 device_mask) | |
1243 | { | |
1244 | u64 dma_addr_mask; | |
1245 | ||
1246 | if (pdev == NULL) { | |
1247 | dma_addr_mask = 0xffffffff; | |
1248 | } else { | |
1249 | struct iommu *iommu = pdev->dev.archdata.iommu; | |
1250 | ||
1251 | dma_addr_mask = iommu->dma_addr_mask; | |
1252 | ||
1253 | if (pdev->vendor == PCI_VENDOR_ID_AL && | |
1254 | pdev->device == PCI_DEVICE_ID_AL_M5451 && | |
1255 | device_mask == 0x7fffffff) { | |
1256 | ali_sound_dma_hack(pdev, | |
1257 | (dma_addr_mask & 0x80000000) != 0); | |
1258 | return 1; | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | if (device_mask >= (1UL << 32UL)) | |
1263 | return 0; | |
1264 | ||
1265 | return (device_mask & dma_addr_mask) == dma_addr_mask; | |
1266 | } | |
1267 | ||
1da177e4 | 1268 | #endif /* !(CONFIG_PCI) */ |