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[SPARC64]: Kill PBM ranges software state.
[linux-2.6-block.git] / arch / sparc64 / kernel / pci.c
CommitLineData
a2fb23af 1/* pci.c: UltraSparc PCI controller support.
1da177e4
LT		 2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
a2fb23af
DM		 6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
1da177e4
LT		 9 */
10
1da177e4
LT		 11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
17#include <linux/smp_lock.h>
35a17eb6
DM		 18#include <linux/msi.h>
19#include <linux/irq.h>
1da177e4
LT		 20#include <linux/init.h>
21
22#include <asm/uaccess.h>
23#include <asm/pbm.h>
24#include <asm/pgtable.h>
25#include <asm/irq.h>
26#include <asm/ebus.h>
27#include <asm/isa.h>
e87dc350 28#include <asm/prom.h>
01f94c4a 29#include <asm/apb.h>
1da177e4 30
1e8a8cc5
DM		 31#include "pci_impl.h"
32
1da177e4
LT		 33unsigned long pci_memspace_mask = 0xffffffffUL;
34
35#ifndef CONFIG_PCI
36/* A "nop" PCI implementation. */
37asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn,
38 unsigned long off, unsigned long len,
39 unsigned char *buf)
40{
41 return 0;
42}
43asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn,
44 unsigned long off, unsigned long len,
45 unsigned char *buf)
46{
47 return 0;
48}
49#else
50
51/* List of all PCI controllers found in the system. */
52struct pci_controller_info *pci_controller_root = NULL;
53
54/* Each PCI controller found gets a unique index. */
55int pci_num_controllers = 0;
56
1da177e4
LT		 57volatile int pci_poke_in_progress;
58volatile int pci_poke_cpu = -1;
59volatile int pci_poke_faulted;
60
61static DEFINE_SPINLOCK(pci_poke_lock);
62
63void pci_config_read8(u8 *addr, u8 *ret)
64{
65 unsigned long flags;
66 u8 byte;
67
68 spin_lock_irqsave(&pci_poke_lock, flags);
69 pci_poke_cpu = smp_processor_id();
70 pci_poke_in_progress = 1;
71 pci_poke_faulted = 0;
72 __asm__ __volatile__("membar #Sync\n\t"
73 "lduba [%1] %2, %0\n\t"
74 "membar #Sync"
75 : "=r" (byte)
76 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
77 : "memory");
78 pci_poke_in_progress = 0;
79 pci_poke_cpu = -1;
80 if (!pci_poke_faulted)
81 *ret = byte;
82 spin_unlock_irqrestore(&pci_poke_lock, flags);
83}
84
85void pci_config_read16(u16 *addr, u16 *ret)
86{
87 unsigned long flags;
88 u16 word;
89
90 spin_lock_irqsave(&pci_poke_lock, flags);
91 pci_poke_cpu = smp_processor_id();
92 pci_poke_in_progress = 1;
93 pci_poke_faulted = 0;
94 __asm__ __volatile__("membar #Sync\n\t"
95 "lduha [%1] %2, %0\n\t"
96 "membar #Sync"
97 : "=r" (word)
98 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
99 : "memory");
100 pci_poke_in_progress = 0;
101 pci_poke_cpu = -1;
102 if (!pci_poke_faulted)
103 *ret = word;
104 spin_unlock_irqrestore(&pci_poke_lock, flags);
105}
106
107void pci_config_read32(u32 *addr, u32 *ret)
108{
109 unsigned long flags;
110 u32 dword;
111
112 spin_lock_irqsave(&pci_poke_lock, flags);
113 pci_poke_cpu = smp_processor_id();
114 pci_poke_in_progress = 1;
115 pci_poke_faulted = 0;
116 __asm__ __volatile__("membar #Sync\n\t"
117 "lduwa [%1] %2, %0\n\t"
118 "membar #Sync"
119 : "=r" (dword)
120 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
121 : "memory");
122 pci_poke_in_progress = 0;
123 pci_poke_cpu = -1;
124 if (!pci_poke_faulted)
125 *ret = dword;
126 spin_unlock_irqrestore(&pci_poke_lock, flags);
127}
128
129void pci_config_write8(u8 *addr, u8 val)
130{
131 unsigned long flags;
132
133 spin_lock_irqsave(&pci_poke_lock, flags);
134 pci_poke_cpu = smp_processor_id();
135 pci_poke_in_progress = 1;
136 pci_poke_faulted = 0;
137 __asm__ __volatile__("membar #Sync\n\t"
138 "stba %0, [%1] %2\n\t"
139 "membar #Sync"
140 : /* no outputs */
141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 : "memory");
143 pci_poke_in_progress = 0;
144 pci_poke_cpu = -1;
145 spin_unlock_irqrestore(&pci_poke_lock, flags);
146}
147
148void pci_config_write16(u16 *addr, u16 val)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&pci_poke_lock, flags);
153 pci_poke_cpu = smp_processor_id();
154 pci_poke_in_progress = 1;
155 pci_poke_faulted = 0;
156 __asm__ __volatile__("membar #Sync\n\t"
157 "stha %0, [%1] %2\n\t"
158 "membar #Sync"
159 : /* no outputs */
160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 : "memory");
162 pci_poke_in_progress = 0;
163 pci_poke_cpu = -1;
164 spin_unlock_irqrestore(&pci_poke_lock, flags);
165}
166
167void pci_config_write32(u32 *addr, u32 val)
168{
169 unsigned long flags;
170
171 spin_lock_irqsave(&pci_poke_lock, flags);
172 pci_poke_cpu = smp_processor_id();
173 pci_poke_in_progress = 1;
174 pci_poke_faulted = 0;
175 __asm__ __volatile__("membar #Sync\n\t"
176 "stwa %0, [%1] %2\n\t"
177 "membar #Sync"
178 : /* no outputs */
179 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
180 : "memory");
181 pci_poke_in_progress = 0;
182 pci_poke_cpu = -1;
183 spin_unlock_irqrestore(&pci_poke_lock, flags);
184}
185
186/* Probe for all PCI controllers in the system. */
e87dc350
DM		 187extern void sabre_init(struct device_node *, const char *);
188extern void psycho_init(struct device_node *, const char *);
189extern void schizo_init(struct device_node *, const char *);
190extern void schizo_plus_init(struct device_node *, const char *);
191extern void tomatillo_init(struct device_node *, const char *);
192extern void sun4v_pci_init(struct device_node *, const char *);
1da177e4
LT		 193
194static struct {
195 char *model_name;
e87dc350 196 void (*init)(struct device_node *, const char *);
1da177e4
LT		 197} pci_controller_table[] __initdata = {
198 { "SUNW,sabre", sabre_init },
199 { "pci108e,a000", sabre_init },
200 { "pci108e,a001", sabre_init },
201 { "SUNW,psycho", psycho_init },
202 { "pci108e,8000", psycho_init },
203 { "SUNW,schizo", schizo_init },
204 { "pci108e,8001", schizo_init },
205 { "SUNW,schizo+", schizo_plus_init },
206 { "pci108e,8002", schizo_plus_init },
207 { "SUNW,tomatillo", tomatillo_init },
208 { "pci108e,a801", tomatillo_init },
8f6a93a1 209 { "SUNW,sun4v-pci", sun4v_pci_init },
1da177e4
LT		 210};
211#define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \
212 sizeof(pci_controller_table[0]))
213
e87dc350 214static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 215{
216 int i;
217
218 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
219 if (!strncmp(model_name,
220 pci_controller_table[i].model_name,
221 namelen)) {
e87dc350 222 pci_controller_table[i].init(dp, model_name);
1da177e4
LT		 223 return 1;
224 }
225 }
1da177e4
LT		 226
227 return 0;
228}
229
e87dc350 230static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp)
1da177e4
LT		 231{
232 int i;
233
234 for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) {
235 if (!strncmp(model_name,
236 pci_controller_table[i].model_name,
237 namelen)) {
238 return 1;
239 }
240 }
241 return 0;
242}
243
e87dc350 244static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *))
1da177e4 245{
e87dc350 246 struct device_node *dp;
1da177e4
LT		 247 int count = 0;
248
e87dc350
DM		 249 for_each_node_by_name(dp, "pci") {
250 struct property *prop;
1da177e4
LT		 251 int len;
252
e87dc350
DM		 253 prop = of_find_property(dp, "model", &len);
254 if (!prop)
255 prop = of_find_property(dp, "compatible", &len);
256
257 if (prop) {
258 const char *model = prop->value;
1da177e4
LT		 259 int item_len = 0;
260
261 /* Our value may be a multi-valued string in the
262 * case of some compatible properties. For sanity,
e87dc350
DM		 263 * only try the first one.
264 */
265 while (model[item_len] && len) {
1da177e4
LT		 266 len--;
267 item_len++;
268 }
269
e87dc350 270 if (handler(model, item_len, dp))
1da177e4
LT		 271 count++;
272 }
1da177e4
LT		 273 }
274
275 return count;
276}
277
278
279/* Is there some PCI controller in the system? */
280int __init pcic_present(void)
281{
282 return pci_controller_scan(pci_is_controller);
283}
284
8f6a93a1
DM		 285struct pci_iommu_ops *pci_iommu_ops;
286EXPORT_SYMBOL(pci_iommu_ops);
287
288extern struct pci_iommu_ops pci_sun4u_iommu_ops,
289 pci_sun4v_iommu_ops;
290
1da177e4
LT		 291/* Find each controller in the system, attach and initialize
292 * software state structure for each and link into the
293 * pci_controller_root. Setup the controller enough such
294 * that bus scanning can be done.
295 */
296static void __init pci_controller_probe(void)
297{
8f6a93a1
DM		 298 if (tlb_type == hypervisor)
299 pci_iommu_ops = &pci_sun4v_iommu_ops;
300 else
301 pci_iommu_ops = &pci_sun4u_iommu_ops;
302
1da177e4
LT		 303 printk("PCI: Probing for controllers.\n");
304
305 pci_controller_scan(pci_controller_init);
306}
307
a2fb23af
DM		 308static unsigned long pci_parse_of_flags(u32 addr0)
309{
310 unsigned long flags = 0;
311
312 if (addr0 & 0x02000000) {
313 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
314 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
315 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
316 if (addr0 & 0x40000000)
317 flags |= IORESOURCE_PREFETCH
318 | PCI_BASE_ADDRESS_MEM_PREFETCH;
319 } else if (addr0 & 0x01000000)
320 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
321 return flags;
322}
323
324/* The of_device layer has translated all of the assigned-address properties
325 * into physical address resources, we only have to figure out the register
326 * mapping.
327 */
328static void pci_parse_of_addrs(struct of_device *op,
329 struct device_node *node,
330 struct pci_dev *dev)
331{
332 struct resource *op_res;
333 const u32 *addrs;
334 int proplen;
335
336 addrs = of_get_property(node, "assigned-addresses", &proplen);
337 if (!addrs)
338 return;
339 printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs);
340 op_res = &op->resource[0];
341 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
342 struct resource *res;
343 unsigned long flags;
344 int i;
345
346 flags = pci_parse_of_flags(addrs[0]);
347 if (!flags)
348 continue;
349 i = addrs[0] & 0xff;
350 printk(" start: %lx, end: %lx, i: %x\n",
351 op_res->start, op_res->end, i);
352
353 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
354 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
355 } else if (i == dev->rom_base_reg) {
356 res = &dev->resource[PCI_ROM_RESOURCE];
357 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
358 } else {
359 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
360 continue;
361 }
362 res->start = op_res->start;
363 res->end = op_res->end;
364 res->flags = flags;
365 res->name = pci_name(dev);
366 }
367}
368
369struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
370 struct device_node *node,
371 struct pci_bus *bus, int devfn)
372{
373 struct dev_archdata *sd;
374 struct pci_dev *dev;
375 const char *type;
01f94c4a 376 u32 class;
a2fb23af
DM		 377
378 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
379 if (!dev)
380 return NULL;
381
382 sd = &dev->dev.archdata;
383 sd->iommu = pbm->iommu;
384 sd->stc = &pbm->stc;
385 sd->host_controller = pbm;
386 sd->prom_node = node;
387 sd->op = of_find_device_by_node(node);
388 sd->msi_num = 0xffffffff;
389
390 type = of_get_property(node, "device_type", NULL);
391 if (type == NULL)
392 type = "";
393
394 printk(" create device, devfn: %x, type: %s\n", devfn, type);
395
396 dev->bus = bus;
397 dev->sysdata = node;
398 dev->dev.parent = bus->bridge;
399 dev->dev.bus = &pci_bus_type;
400 dev->devfn = devfn;
401 dev->multifunction = 0; /* maybe a lie? */
402
403 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
404 dev->device = of_getintprop_default(node, "device-id", 0xffff);
405 dev->subsystem_vendor =
406 of_getintprop_default(node, "subsystem-vendor-id", 0);
407 dev->subsystem_device =
408 of_getintprop_default(node, "subsystem-id", 0);
409
410 dev->cfg_size = pci_cfg_space_size(dev);
411
412 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
413 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
01f94c4a
DM		 414
415 /* dev->class = of_getintprop_default(node, "class-code", 0); */
416 /* We can't actually use the firmware value, we have to read what
417 * is in the register right now. One reason is that in the case
418 * of IDE interfaces the firmware can sample the value before the
419 * the IDE interface is programmed into native mode.
420 */
421 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
422 dev->class = class >> 8;
a2fb23af
DM		 423
424 printk(" class: 0x%x\n", dev->class);
425
426 dev->current_state = 4; /* unknown power state */
427 dev->error_state = pci_channel_io_normal;
428
429 if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
430 /* a PCI-PCI bridge */
431 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
432 dev->rom_base_reg = PCI_ROM_ADDRESS1;
433 } else if (!strcmp(type, "cardbus")) {
434 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
435 } else {
436 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
437 dev->rom_base_reg = PCI_ROM_ADDRESS;
438
439 dev->irq = sd->op->irqs[0];
440 if (dev->irq == 0xffffffff)
441 dev->irq = PCI_IRQ_NONE;
442 }
443
444 pci_parse_of_addrs(sd->op, node, dev);
445
446 printk(" adding to system ...\n");
447
448 pci_device_add(dev, bus);
449
450 return dev;
451}
452
01f94c4a
DM		 453static void __init apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
454{
455 u32 idx, first, last;
456
457 first = 8;
458 last = 0;
459 for (idx = 0; idx < 8; idx++) {
460 if ((map & (1 << idx)) != 0) {
461 if (first > idx)
462 first = idx;
463 if (last < idx)
464 last = idx;
465 }
466 }
467
468 *first_p = first;
469 *last_p = last;
470}
471
472/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
473 * a proper 'ranges' property.
474 */
475static void __init apb_fake_ranges(struct pci_dev *dev,
476 struct pci_bus *bus,
477 struct pci_pbm_info *pbm)
478{
479 struct resource *res;
480 u32 first, last;
481 u8 map;
482
483 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
484 apb_calc_first_last(map, &first, &last);
485 res = bus->resource[0];
486 res->start = (first << 21);
487 res->end = (last << 21) + ((1 << 21) - 1);
488 res->flags = IORESOURCE_IO;
489 pbm->parent->resource_adjust(dev, res, &pbm->io_space);
490
491 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
492 apb_calc_first_last(map, &first, &last);
493 res = bus->resource[1];
494 res->start = (first << 21);
495 res->end = (last << 21) + ((1 << 21) - 1);
496 res->flags = IORESOURCE_MEM;
497 pbm->parent->resource_adjust(dev, res, &pbm->mem_space);
498}
499
a2fb23af
DM		 500static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
501 struct device_node *node,
502 struct pci_bus *bus);
503
504#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
505
506void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
507 struct device_node *node,
508 struct pci_dev *dev)
509{
510 struct pci_bus *bus;
511 const u32 *busrange, *ranges;
01f94c4a 512 int len, i, simba;
a2fb23af
DM		 513 struct resource *res;
514 unsigned int flags;
515 u64 size;
516
517 printk("of_scan_pci_bridge(%s)\n", node->full_name);
518
519 /* parse bus-range property */
520 busrange = of_get_property(node, "bus-range", &len);
521 if (busrange == NULL || len != 8) {
522 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
523 node->full_name);
524 return;
525 }
526 ranges = of_get_property(node, "ranges", &len);
01f94c4a 527 simba = 0;
a2fb23af 528 if (ranges == NULL) {
01f94c4a
DM		 529 char *model = of_get_property(node, "model", NULL);
530 if (model && !strcmp(model, "SUNW,simba")) {
531 simba = 1;
532 } else {
533 printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n",
534 node->full_name);
535 return;
536 }
a2fb23af
DM		 537 }
538
539 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
540 if (!bus) {
541 printk(KERN_ERR "Failed to create pci bus for %s\n",
542 node->full_name);
543 return;
544 }
545
546 bus->primary = dev->bus->number;
547 bus->subordinate = busrange[1];
548 bus->bridge_ctl = 0;
549
01f94c4a 550 /* parse ranges property, or cook one up by hand for Simba */
a2fb23af
DM		 551 /* PCI #address-cells == 3 and #size-cells == 2 always */
552 res = &dev->resource[PCI_BRIDGE_RESOURCES];
553 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
554 res->flags = 0;
555 bus->resource[i] = res;
556 ++res;
557 }
01f94c4a
DM		 558 if (simba) {
559 apb_fake_ranges(dev, bus, pbm);
560 goto simba_cont;
561 }
a2fb23af
DM		 562 i = 1;
563 for (; len >= 32; len -= 32, ranges += 8) {
564 struct resource *root;
565
566 flags = pci_parse_of_flags(ranges[0]);
567 size = GET_64BIT(ranges, 6);
568 if (flags == 0 || size == 0)
569 continue;
570 if (flags & IORESOURCE_IO) {
571 res = bus->resource[0];
572 if (res->flags) {
573 printk(KERN_ERR "PCI: ignoring extra I/O range"
574 " for bridge %s\n", node->full_name);
575 continue;
576 }
577 root = &pbm->io_space;
578 } else {
579 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
580 printk(KERN_ERR "PCI: too many memory ranges"
581 " for bridge %s\n", node->full_name);
582 continue;
583 }
584 res = bus->resource[i];
585 ++i;
586 root = &pbm->mem_space;
587 }
588
589 res->start = GET_64BIT(ranges, 1);
590 res->end = res->start + size - 1;
591 res->flags = flags;
592
593 /* Another way to implement this would be to add an of_device
594 * layer routine that can calculate a resource for a given
595 * range property value in a PCI device.
596 */
597 pbm->parent->resource_adjust(dev, res, root);
598 }
01f94c4a 599simba_cont:
a2fb23af
DM		 600 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
601 bus->number);
602 printk(" bus name: %s\n", bus->name);
603
604 pci_of_scan_bus(pbm, node, bus);
605}
606
607static void __init pci_of_scan_bus(struct pci_pbm_info *pbm,
608 struct device_node *node,
609 struct pci_bus *bus)
610{
611 struct device_node *child;
612 const u32 *reg;
613 int reglen, devfn;
614 struct pci_dev *dev;
615
616 printk("PCI: scan_bus[%s] bus no %d\n",
617 node->full_name, bus->number);
618
619 child = NULL;
620 while ((child = of_get_next_child(node, child)) != NULL) {
621 printk(" * %s\n", child->full_name);
622 reg = of_get_property(child, "reg", &reglen);
623 if (reg == NULL || reglen < 20)
624 continue;
625 devfn = (reg[0] >> 8) & 0xff;
626
627 /* create a new pci_dev for this device */
628 dev = of_create_pci_dev(pbm, child, bus, devfn);
629 if (!dev)
630 continue;
631 printk("PCI: dev header type: %x\n", dev->hdr_type);
632
633 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
634 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
635 of_scan_pci_bridge(pbm, child, dev);
636 }
637}
638
639static ssize_t
640show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
641{
642 struct pci_dev *pdev;
643 struct device_node *dp;
644
645 pdev = to_pci_dev(dev);
646 dp = pdev->dev.archdata.prom_node;
647
648 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
649}
650
651static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
652
653static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
654{
655 struct pci_dev *dev;
a378fd0e 656 struct pci_bus *child_bus;
a2fb23af
DM		 657 int err;
658
659 list_for_each_entry(dev, &bus->devices, bus_list) {
660 /* we don't really care if we can create this file or
661 * not, but we need to assign the result of the call
662 * or the world will fall under alien invasion and
663 * everybody will be frozen on a spaceship ready to be
664 * eaten on alpha centauri by some green and jelly
665 * humanoid.
666 */
667 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
668 }
a378fd0e
DM		 669 list_for_each_entry(child_bus, &bus->children, node)
670 pci_bus_register_of_sysfs(child_bus);
a2fb23af
DM		 671}
672
673struct pci_bus * __init pci_scan_one_pbm(struct pci_pbm_info *pbm)
674{
675 struct pci_controller_info *p = pbm->parent;
676 struct device_node *node = pbm->prom_node;
677 struct pci_bus *bus;
678
679 printk("PCI: Scanning PBM %s\n", node->full_name);
680
681 /* XXX parent device? XXX */
682 bus = pci_create_bus(NULL, pbm->pci_first_busno, p->pci_ops, pbm);
683 if (!bus) {
684 printk(KERN_ERR "Failed to create bus for %s\n",
685 node->full_name);
686 return NULL;
687 }
688 bus->secondary = pbm->pci_first_busno;
689 bus->subordinate = pbm->pci_last_busno;
690
691 bus->resource[0] = &pbm->io_space;
692 bus->resource[1] = &pbm->mem_space;
693
694 pci_of_scan_bus(pbm, node, bus);
695 pci_bus_add_devices(bus);
696 pci_bus_register_of_sysfs(bus);
697
698 return bus;
699}
700
1da177e4
LT		 701static void __init pci_scan_each_controller_bus(void)
702{
703 struct pci_controller_info *p;
704
705 for (p = pci_controller_root; p; p = p->next)
706 p->scan_bus(p);
707}
708
1da177e4
LT		 709extern void power_init(void);
710
711static int __init pcibios_init(void)
712{
713 pci_controller_probe();
714 if (pci_controller_root == NULL)
715 return 0;
716
717 pci_scan_each_controller_bus();
718
1da177e4
LT		 719 isa_init();
720 ebus_init();
1da177e4
LT		 721 power_init();
722
723 return 0;
724}
725
726subsys_initcall(pcibios_init);
727
f6b45da1 728void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
1da177e4
LT		 729{
730 struct pci_pbm_info *pbm = pbus->sysdata;
731
732 /* Generic PCI bus probing sets these to point at
733 * &io{port,mem}_resouce which is wrong for us.
734 */
735 pbus->resource[0] = &pbm->io_space;
736 pbus->resource[1] = &pbm->mem_space;
737}
738
085ae41f 739struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r)
1da177e4
LT		 740{
741 struct pci_pbm_info *pbm = pdev->bus->sysdata;
085ae41f 742 struct resource *root = NULL;
1da177e4 743
085ae41f 744 if (r->flags & IORESOURCE_IO)
1da177e4 745 root = &pbm->io_space;
085ae41f 746 if (r->flags & IORESOURCE_MEM)
1da177e4
LT		 747 root = &pbm->mem_space;
748
085ae41f 749 return root;
1da177e4
LT		 750}
751
752void pcibios_update_irq(struct pci_dev *pdev, int irq)
753{
754}
755
756void pcibios_align_resource(void *data, struct resource *res,
e31dd6e4 757 resource_size_t size, resource_size_t align)
1da177e4
LT		 758{
759}
760
a2fb23af 761int pcibios_enable_device(struct pci_dev *dev, int mask)
1da177e4 762{
a2fb23af
DM		 763 u16 cmd, oldcmd;
764 int i;
765
766 pci_read_config_word(dev, PCI_COMMAND, &cmd);
767 oldcmd = cmd;
768
769 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
770 struct resource *res = &dev->resource[i];
771
772 /* Only set up the requested stuff */
773 if (!(mask & (1<<i)))
774 continue;
775
776 if (res->flags & IORESOURCE_IO)
777 cmd |= PCI_COMMAND_IO;
778 if (res->flags & IORESOURCE_MEM)
779 cmd |= PCI_COMMAND_MEMORY;
780 }
781
782 if (cmd != oldcmd) {
783 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
784 pci_name(dev), cmd);
785 /* Enable the appropriate bits in the PCI command register. */
786 pci_write_config_word(dev, PCI_COMMAND, cmd);
787 }
1da177e4
LT		 788 return 0;
789}
790
791void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region,
792 struct resource *res)
793{
794 struct pci_pbm_info *pbm = pdev->bus->sysdata;
795 struct resource zero_res, *root;
796
797 zero_res.start = 0;
798 zero_res.end = 0;
799 zero_res.flags = res->flags;
800
801 if (res->flags & IORESOURCE_IO)
802 root = &pbm->io_space;
803 else
804 root = &pbm->mem_space;
805
806 pbm->parent->resource_adjust(pdev, &zero_res, root);
807
808 region->start = res->start - zero_res.start;
809 region->end = res->end - zero_res.start;
810}
5fdfd42e 811EXPORT_SYMBOL(pcibios_resource_to_bus);
1da177e4
LT		 812
813void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res,
814 struct pci_bus_region *region)
815{
816 struct pci_pbm_info *pbm = pdev->bus->sysdata;
817 struct resource *root;
818
819 res->start = region->start;
820 res->end = region->end;
821
822 if (res->flags & IORESOURCE_IO)
823 root = &pbm->io_space;
824 else
825 root = &pbm->mem_space;
826
827 pbm->parent->resource_adjust(pdev, res, root);
828}
41290c14 829EXPORT_SYMBOL(pcibios_bus_to_resource);
1da177e4 830
f6b45da1 831char * __devinit pcibios_setup(char *str)
1da177e4 832{
1da177e4
LT		 833 return str;
834}
835
836/* Platform support for /proc/bus/pci/X/Y mmap()s. */
837
838/* If the user uses a host-bridge as the PCI device, he may use
839 * this to perform a raw mmap() of the I/O or MEM space behind
840 * that controller.
841 *
842 * This can be useful for execution of x86 PCI bios initialization code
843 * on a PCI card, like the xfree86 int10 stuff does.
844 */
845static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
846 enum pci_mmap_state mmap_state)
847{
a2fb23af 848 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1da177e4
LT		 849 struct pci_controller_info *p;
850 unsigned long space_size, user_offset, user_size;
851
1da177e4
LT		 852 p = pbm->parent;
853 if (p->pbms_same_domain) {
854 unsigned long lowest, highest;
855
856 lowest = ~0UL; highest = 0UL;
857 if (mmap_state == pci_mmap_io) {
858 if (p->pbm_A.io_space.flags) {
859 lowest = p->pbm_A.io_space.start;
860 highest = p->pbm_A.io_space.end + 1;
861 }
862 if (p->pbm_B.io_space.flags) {
863 if (lowest > p->pbm_B.io_space.start)
864 lowest = p->pbm_B.io_space.start;
865 if (highest < p->pbm_B.io_space.end + 1)
866 highest = p->pbm_B.io_space.end + 1;
867 }
868 space_size = highest - lowest;
869 } else {
870 if (p->pbm_A.mem_space.flags) {
871 lowest = p->pbm_A.mem_space.start;
872 highest = p->pbm_A.mem_space.end + 1;
873 }
874 if (p->pbm_B.mem_space.flags) {
875 if (lowest > p->pbm_B.mem_space.start)
876 lowest = p->pbm_B.mem_space.start;
877 if (highest < p->pbm_B.mem_space.end + 1)
878 highest = p->pbm_B.mem_space.end + 1;
879 }
880 space_size = highest - lowest;
881 }
882 } else {
883 if (mmap_state == pci_mmap_io) {
884 space_size = (pbm->io_space.end -
885 pbm->io_space.start) + 1;
886 } else {
887 space_size = (pbm->mem_space.end -
888 pbm->mem_space.start) + 1;
889 }
890 }
891
892 /* Make sure the request is in range. */
893 user_offset = vma->vm_pgoff << PAGE_SHIFT;
894 user_size = vma->vm_end - vma->vm_start;
895
896 if (user_offset >= space_size ||
897 (user_offset + user_size) > space_size)
898 return -EINVAL;
899
900 if (p->pbms_same_domain) {
901 unsigned long lowest = ~0UL;
902
903 if (mmap_state == pci_mmap_io) {
904 if (p->pbm_A.io_space.flags)
905 lowest = p->pbm_A.io_space.start;
906 if (p->pbm_B.io_space.flags &&
907 lowest > p->pbm_B.io_space.start)
908 lowest = p->pbm_B.io_space.start;
909 } else {
910 if (p->pbm_A.mem_space.flags)
911 lowest = p->pbm_A.mem_space.start;
912 if (p->pbm_B.mem_space.flags &&
913 lowest > p->pbm_B.mem_space.start)
914 lowest = p->pbm_B.mem_space.start;
915 }
916 vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT;
917 } else {
918 if (mmap_state == pci_mmap_io) {
919 vma->vm_pgoff = (pbm->io_space.start +
920 user_offset) >> PAGE_SHIFT;
921 } else {
922 vma->vm_pgoff = (pbm->mem_space.start +
923 user_offset) >> PAGE_SHIFT;
924 }
925 }
926
927 return 0;
928}
929
930/* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding
931 * to the 32-bit pci bus offset for DEV requested by the user.
932 *
933 * Basically, the user finds the base address for his device which he wishes
934 * to mmap. They read the 32-bit value from the config space base register,
935 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
936 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
937 *
938 * Returns negative error code on failure, zero on success.
939 */
940static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
941 enum pci_mmap_state mmap_state)
942{
943 unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT;
944 unsigned long user32 = user_offset & pci_memspace_mask;
945 unsigned long largest_base, this_base, addr32;
946 int i;
947
948 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
949 return __pci_mmap_make_offset_bus(dev, vma, mmap_state);
950
951 /* Figure out which base address this is for. */
952 largest_base = 0UL;
953 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
954 struct resource *rp = &dev->resource[i];
955
956 /* Active? */
957 if (!rp->flags)
958 continue;
959
960 /* Same type? */
961 if (i == PCI_ROM_RESOURCE) {
962 if (mmap_state != pci_mmap_mem)
963 continue;
964 } else {
965 if ((mmap_state == pci_mmap_io &&
966 (rp->flags & IORESOURCE_IO) == 0) ||
967 (mmap_state == pci_mmap_mem &&
968 (rp->flags & IORESOURCE_MEM) == 0))
969 continue;
970 }
971
972 this_base = rp->start;
973
974 addr32 = (this_base & PAGE_MASK) & pci_memspace_mask;
975
976 if (mmap_state == pci_mmap_io)
977 addr32 &= 0xffffff;
978
979 if (addr32 <= user32 && this_base > largest_base)
980 largest_base = this_base;
981 }
982
983 if (largest_base == 0UL)
984 return -EINVAL;
985
986 /* Now construct the final physical address. */
987 if (mmap_state == pci_mmap_io)
988 vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT);
989 else
990 vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT);
991
992 return 0;
993}
994
995/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
996 * mapping.
997 */
998static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
999 enum pci_mmap_state mmap_state)
1000{
1001 vma->vm_flags |= (VM_IO | VM_RESERVED);
1002}
1003
1004/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1005 * device mapping.
1006 */
1007static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
1008 enum pci_mmap_state mmap_state)
1009{
a7a6cac2 1010 /* Our io_remap_pfn_range takes care of this, do nothing. */
1da177e4
LT		 1011}
1012
1013/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
1014 * for this architecture. The region in the process to map is described by vm_start
1015 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
1016 * The pci device structure is provided so that architectures may make mapping
1017 * decisions on a per-device or per-bus basis.
1018 *
1019 * Returns a negative error code on failure, zero on success.
1020 */
1021int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
1022 enum pci_mmap_state mmap_state,
1023 int write_combine)
1024{
1025 int ret;
1026
1027 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
1028 if (ret < 0)
1029 return ret;
1030
1031 __pci_mmap_set_flags(dev, vma, mmap_state);
1032 __pci_mmap_set_pgprot(dev, vma, mmap_state);
1033
14778d90 1034 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1da177e4
LT		 1035 ret = io_remap_pfn_range(vma, vma->vm_start,
1036 vma->vm_pgoff,
1037 vma->vm_end - vma->vm_start,
1038 vma->vm_page_prot);
1039 if (ret)
1040 return ret;
1041
1da177e4
LT		 1042 return 0;
1043}
1044
1045/* Return the domain nuber for this pci bus */
1046
1047int pci_domain_nr(struct pci_bus *pbus)
1048{
1049 struct pci_pbm_info *pbm = pbus->sysdata;
1050 int ret;
1051
1052 if (pbm == NULL || pbm->parent == NULL) {
1053 ret = -ENXIO;
1054 } else {
1055 struct pci_controller_info *p = pbm->parent;
1056
1057 ret = p->index;
1058 if (p->pbms_same_domain == 0)
1059 ret = ((ret << 1) +
1060 ((pbm == &pbm->parent->pbm_B) ? 1 : 0));
1061 }
1062
1063 return ret;
1064}
1065EXPORT_SYMBOL(pci_domain_nr);
1066
35a17eb6
DM		 1067#ifdef CONFIG_PCI_MSI
1068int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
1069{
a2fb23af 1070 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6
DM		 1071 struct pci_controller_info *p = pbm->parent;
1072 int virt_irq, err;
1073
1074 if (!pbm->msi_num || !p->setup_msi_irq)
1075 return -EINVAL;
1076
1077 err = p->setup_msi_irq(&virt_irq, pdev, desc);
1078 if (err < 0)
1079 return err;
1080
1081 return virt_irq;
1082}
1083
1084void arch_teardown_msi_irq(unsigned int virt_irq)
1085{
abfd336c 1086 struct msi_desc *entry = get_irq_msi(virt_irq);
35a17eb6 1087 struct pci_dev *pdev = entry->dev;
a2fb23af 1088 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
35a17eb6
DM		 1089 struct pci_controller_info *p = pbm->parent;
1090
1091 if (!pbm->msi_num || !p->setup_msi_irq)
1092 return;
1093
1094 return p->teardown_msi_irq(virt_irq, pdev);
1095}
1096#endif /* !(CONFIG_PCI_MSI) */
1097
f6d0f9ea
DM		 1098struct device_node *pci_device_to_OF_node(struct pci_dev *pdev)
1099{
a2fb23af 1100 return pdev->dev.archdata.prom_node;
f6d0f9ea
DM		 1101}
1102EXPORT_SYMBOL(pci_device_to_OF_node);
1103
1da177e4 1104#endif /* !(CONFIG_PCI) */
Linux 6.x block layer and io_uring tree(s)