Commit | Line | Data |
---|---|---|
a2fb23af | 1 | /* pci.c: UltraSparc PCI controller support. |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
a2fb23af DM |
6 | * |
7 | * OF tree based PCI bus probing taken from the PowerPC port | |
8 | * with minor modifications, see there for credits. | |
1da177e4 LT |
9 | */ |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/string.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/capability.h> | |
16 | #include <linux/errno.h> | |
c57c2ffb | 17 | #include <linux/pci.h> |
35a17eb6 DM |
18 | #include <linux/msi.h> |
19 | #include <linux/irq.h> | |
1da177e4 LT |
20 | #include <linux/init.h> |
21 | ||
22 | #include <asm/uaccess.h> | |
1da177e4 LT |
23 | #include <asm/pgtable.h> |
24 | #include <asm/irq.h> | |
25 | #include <asm/ebus.h> | |
26 | #include <asm/isa.h> | |
e87dc350 | 27 | #include <asm/prom.h> |
01f94c4a | 28 | #include <asm/apb.h> |
1da177e4 | 29 | |
1e8a8cc5 DM |
30 | #include "pci_impl.h" |
31 | ||
1da177e4 LT |
32 | #ifndef CONFIG_PCI |
33 | /* A "nop" PCI implementation. */ | |
34 | asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn, | |
35 | unsigned long off, unsigned long len, | |
36 | unsigned char *buf) | |
37 | { | |
38 | return 0; | |
39 | } | |
40 | asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn, | |
41 | unsigned long off, unsigned long len, | |
42 | unsigned char *buf) | |
43 | { | |
44 | return 0; | |
45 | } | |
46 | #else | |
47 | ||
48 | /* List of all PCI controllers found in the system. */ | |
34768bc8 | 49 | struct pci_pbm_info *pci_pbm_root = NULL; |
1da177e4 | 50 | |
6c108f12 DM |
51 | /* Each PBM found gets a unique index. */ |
52 | int pci_num_pbms = 0; | |
1da177e4 | 53 | |
1da177e4 LT |
54 | volatile int pci_poke_in_progress; |
55 | volatile int pci_poke_cpu = -1; | |
56 | volatile int pci_poke_faulted; | |
57 | ||
58 | static DEFINE_SPINLOCK(pci_poke_lock); | |
59 | ||
60 | void pci_config_read8(u8 *addr, u8 *ret) | |
61 | { | |
62 | unsigned long flags; | |
63 | u8 byte; | |
64 | ||
65 | spin_lock_irqsave(&pci_poke_lock, flags); | |
66 | pci_poke_cpu = smp_processor_id(); | |
67 | pci_poke_in_progress = 1; | |
68 | pci_poke_faulted = 0; | |
69 | __asm__ __volatile__("membar #Sync\n\t" | |
70 | "lduba [%1] %2, %0\n\t" | |
71 | "membar #Sync" | |
72 | : "=r" (byte) | |
73 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
74 | : "memory"); | |
75 | pci_poke_in_progress = 0; | |
76 | pci_poke_cpu = -1; | |
77 | if (!pci_poke_faulted) | |
78 | *ret = byte; | |
79 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
80 | } | |
81 | ||
82 | void pci_config_read16(u16 *addr, u16 *ret) | |
83 | { | |
84 | unsigned long flags; | |
85 | u16 word; | |
86 | ||
87 | spin_lock_irqsave(&pci_poke_lock, flags); | |
88 | pci_poke_cpu = smp_processor_id(); | |
89 | pci_poke_in_progress = 1; | |
90 | pci_poke_faulted = 0; | |
91 | __asm__ __volatile__("membar #Sync\n\t" | |
92 | "lduha [%1] %2, %0\n\t" | |
93 | "membar #Sync" | |
94 | : "=r" (word) | |
95 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
96 | : "memory"); | |
97 | pci_poke_in_progress = 0; | |
98 | pci_poke_cpu = -1; | |
99 | if (!pci_poke_faulted) | |
100 | *ret = word; | |
101 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
102 | } | |
103 | ||
104 | void pci_config_read32(u32 *addr, u32 *ret) | |
105 | { | |
106 | unsigned long flags; | |
107 | u32 dword; | |
108 | ||
109 | spin_lock_irqsave(&pci_poke_lock, flags); | |
110 | pci_poke_cpu = smp_processor_id(); | |
111 | pci_poke_in_progress = 1; | |
112 | pci_poke_faulted = 0; | |
113 | __asm__ __volatile__("membar #Sync\n\t" | |
114 | "lduwa [%1] %2, %0\n\t" | |
115 | "membar #Sync" | |
116 | : "=r" (dword) | |
117 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
118 | : "memory"); | |
119 | pci_poke_in_progress = 0; | |
120 | pci_poke_cpu = -1; | |
121 | if (!pci_poke_faulted) | |
122 | *ret = dword; | |
123 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
124 | } | |
125 | ||
126 | void pci_config_write8(u8 *addr, u8 val) | |
127 | { | |
128 | unsigned long flags; | |
129 | ||
130 | spin_lock_irqsave(&pci_poke_lock, flags); | |
131 | pci_poke_cpu = smp_processor_id(); | |
132 | pci_poke_in_progress = 1; | |
133 | pci_poke_faulted = 0; | |
134 | __asm__ __volatile__("membar #Sync\n\t" | |
135 | "stba %0, [%1] %2\n\t" | |
136 | "membar #Sync" | |
137 | : /* no outputs */ | |
138 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
139 | : "memory"); | |
140 | pci_poke_in_progress = 0; | |
141 | pci_poke_cpu = -1; | |
142 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
143 | } | |
144 | ||
145 | void pci_config_write16(u16 *addr, u16 val) | |
146 | { | |
147 | unsigned long flags; | |
148 | ||
149 | spin_lock_irqsave(&pci_poke_lock, flags); | |
150 | pci_poke_cpu = smp_processor_id(); | |
151 | pci_poke_in_progress = 1; | |
152 | pci_poke_faulted = 0; | |
153 | __asm__ __volatile__("membar #Sync\n\t" | |
154 | "stha %0, [%1] %2\n\t" | |
155 | "membar #Sync" | |
156 | : /* no outputs */ | |
157 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
158 | : "memory"); | |
159 | pci_poke_in_progress = 0; | |
160 | pci_poke_cpu = -1; | |
161 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
162 | } | |
163 | ||
164 | void pci_config_write32(u32 *addr, u32 val) | |
165 | { | |
166 | unsigned long flags; | |
167 | ||
168 | spin_lock_irqsave(&pci_poke_lock, flags); | |
169 | pci_poke_cpu = smp_processor_id(); | |
170 | pci_poke_in_progress = 1; | |
171 | pci_poke_faulted = 0; | |
172 | __asm__ __volatile__("membar #Sync\n\t" | |
173 | "stwa %0, [%1] %2\n\t" | |
174 | "membar #Sync" | |
175 | : /* no outputs */ | |
176 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
177 | : "memory"); | |
178 | pci_poke_in_progress = 0; | |
179 | pci_poke_cpu = -1; | |
180 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
181 | } | |
182 | ||
183 | /* Probe for all PCI controllers in the system. */ | |
e87dc350 DM |
184 | extern void sabre_init(struct device_node *, const char *); |
185 | extern void psycho_init(struct device_node *, const char *); | |
186 | extern void schizo_init(struct device_node *, const char *); | |
187 | extern void schizo_plus_init(struct device_node *, const char *); | |
188 | extern void tomatillo_init(struct device_node *, const char *); | |
189 | extern void sun4v_pci_init(struct device_node *, const char *); | |
861fe906 | 190 | extern void fire_pci_init(struct device_node *, const char *); |
1da177e4 LT |
191 | |
192 | static struct { | |
193 | char *model_name; | |
e87dc350 | 194 | void (*init)(struct device_node *, const char *); |
1da177e4 LT |
195 | } pci_controller_table[] __initdata = { |
196 | { "SUNW,sabre", sabre_init }, | |
197 | { "pci108e,a000", sabre_init }, | |
198 | { "pci108e,a001", sabre_init }, | |
199 | { "SUNW,psycho", psycho_init }, | |
200 | { "pci108e,8000", psycho_init }, | |
201 | { "SUNW,schizo", schizo_init }, | |
202 | { "pci108e,8001", schizo_init }, | |
203 | { "SUNW,schizo+", schizo_plus_init }, | |
204 | { "pci108e,8002", schizo_plus_init }, | |
205 | { "SUNW,tomatillo", tomatillo_init }, | |
206 | { "pci108e,a801", tomatillo_init }, | |
8f6a93a1 | 207 | { "SUNW,sun4v-pci", sun4v_pci_init }, |
861fe906 | 208 | { "pciex108e,80f0", fire_pci_init }, |
1da177e4 | 209 | }; |
29f139ce | 210 | #define PCI_NUM_CONTROLLER_TYPES ARRAY_SIZE(pci_controller_table) |
1da177e4 | 211 | |
e87dc350 | 212 | static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
213 | { |
214 | int i; | |
215 | ||
216 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
217 | if (!strncmp(model_name, | |
218 | pci_controller_table[i].model_name, | |
219 | namelen)) { | |
e87dc350 | 220 | pci_controller_table[i].init(dp, model_name); |
1da177e4 LT |
221 | return 1; |
222 | } | |
223 | } | |
1da177e4 LT |
224 | |
225 | return 0; | |
226 | } | |
227 | ||
e87dc350 | 228 | static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *)) |
1da177e4 | 229 | { |
e87dc350 | 230 | struct device_node *dp; |
1da177e4 LT |
231 | int count = 0; |
232 | ||
e87dc350 DM |
233 | for_each_node_by_name(dp, "pci") { |
234 | struct property *prop; | |
1da177e4 LT |
235 | int len; |
236 | ||
e87dc350 DM |
237 | prop = of_find_property(dp, "model", &len); |
238 | if (!prop) | |
239 | prop = of_find_property(dp, "compatible", &len); | |
240 | ||
241 | if (prop) { | |
242 | const char *model = prop->value; | |
1da177e4 LT |
243 | int item_len = 0; |
244 | ||
245 | /* Our value may be a multi-valued string in the | |
246 | * case of some compatible properties. For sanity, | |
e87dc350 DM |
247 | * only try the first one. |
248 | */ | |
249 | while (model[item_len] && len) { | |
1da177e4 LT |
250 | len--; |
251 | item_len++; | |
252 | } | |
253 | ||
e87dc350 | 254 | if (handler(model, item_len, dp)) |
1da177e4 LT |
255 | count++; |
256 | } | |
1da177e4 LT |
257 | } |
258 | ||
259 | return count; | |
260 | } | |
261 | ||
1da177e4 LT |
262 | /* Find each controller in the system, attach and initialize |
263 | * software state structure for each and link into the | |
34768bc8 | 264 | * pci_pbm_root. Setup the controller enough such |
1da177e4 LT |
265 | * that bus scanning can be done. |
266 | */ | |
267 | static void __init pci_controller_probe(void) | |
268 | { | |
269 | printk("PCI: Probing for controllers.\n"); | |
270 | ||
271 | pci_controller_scan(pci_controller_init); | |
272 | } | |
273 | ||
5840fc66 DM |
274 | static int ofpci_verbose; |
275 | ||
276 | static int __init ofpci_debug(char *str) | |
277 | { | |
278 | int val = 0; | |
279 | ||
280 | get_option(&str, &val); | |
281 | if (val) | |
282 | ofpci_verbose = 1; | |
283 | return 1; | |
284 | } | |
285 | ||
286 | __setup("ofpci_debug=", ofpci_debug); | |
287 | ||
a2fb23af DM |
288 | static unsigned long pci_parse_of_flags(u32 addr0) |
289 | { | |
290 | unsigned long flags = 0; | |
291 | ||
292 | if (addr0 & 0x02000000) { | |
293 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; | |
294 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
295 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
296 | if (addr0 & 0x40000000) | |
297 | flags |= IORESOURCE_PREFETCH | |
298 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
299 | } else if (addr0 & 0x01000000) | |
300 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; | |
301 | return flags; | |
302 | } | |
303 | ||
304 | /* The of_device layer has translated all of the assigned-address properties | |
305 | * into physical address resources, we only have to figure out the register | |
306 | * mapping. | |
307 | */ | |
308 | static void pci_parse_of_addrs(struct of_device *op, | |
309 | struct device_node *node, | |
310 | struct pci_dev *dev) | |
311 | { | |
312 | struct resource *op_res; | |
313 | const u32 *addrs; | |
314 | int proplen; | |
315 | ||
316 | addrs = of_get_property(node, "assigned-addresses", &proplen); | |
317 | if (!addrs) | |
318 | return; | |
5840fc66 DM |
319 | if (ofpci_verbose) |
320 | printk(" parse addresses (%d bytes) @ %p\n", | |
321 | proplen, addrs); | |
a2fb23af DM |
322 | op_res = &op->resource[0]; |
323 | for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { | |
324 | struct resource *res; | |
325 | unsigned long flags; | |
326 | int i; | |
327 | ||
328 | flags = pci_parse_of_flags(addrs[0]); | |
329 | if (!flags) | |
330 | continue; | |
331 | i = addrs[0] & 0xff; | |
5840fc66 DM |
332 | if (ofpci_verbose) |
333 | printk(" start: %lx, end: %lx, i: %x\n", | |
334 | op_res->start, op_res->end, i); | |
a2fb23af DM |
335 | |
336 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
337 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
338 | } else if (i == dev->rom_base_reg) { | |
339 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
340 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
341 | } else { | |
342 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
343 | continue; | |
344 | } | |
345 | res->start = op_res->start; | |
346 | res->end = op_res->end; | |
347 | res->flags = flags; | |
348 | res->name = pci_name(dev); | |
349 | } | |
350 | } | |
351 | ||
352 | struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, | |
353 | struct device_node *node, | |
97b3cf05 DM |
354 | struct pci_bus *bus, int devfn, |
355 | int host_controller) | |
a2fb23af DM |
356 | { |
357 | struct dev_archdata *sd; | |
358 | struct pci_dev *dev; | |
359 | const char *type; | |
01f94c4a | 360 | u32 class; |
a2fb23af | 361 | |
26e6385f | 362 | dev = alloc_pci_dev(); |
a2fb23af DM |
363 | if (!dev) |
364 | return NULL; | |
365 | ||
366 | sd = &dev->dev.archdata; | |
367 | sd->iommu = pbm->iommu; | |
368 | sd->stc = &pbm->stc; | |
369 | sd->host_controller = pbm; | |
370 | sd->prom_node = node; | |
371 | sd->op = of_find_device_by_node(node); | |
a2fb23af | 372 | |
ad7ad57c DM |
373 | sd = &sd->op->dev.archdata; |
374 | sd->iommu = pbm->iommu; | |
375 | sd->stc = &pbm->stc; | |
376 | ||
a2fb23af DM |
377 | type = of_get_property(node, "device_type", NULL); |
378 | if (type == NULL) | |
379 | type = ""; | |
380 | ||
5840fc66 DM |
381 | if (ofpci_verbose) |
382 | printk(" create device, devfn: %x, type: %s\n", | |
383 | devfn, type); | |
a2fb23af DM |
384 | |
385 | dev->bus = bus; | |
386 | dev->sysdata = node; | |
387 | dev->dev.parent = bus->bridge; | |
388 | dev->dev.bus = &pci_bus_type; | |
389 | dev->devfn = devfn; | |
390 | dev->multifunction = 0; /* maybe a lie? */ | |
391 | ||
97b3cf05 | 392 | if (host_controller) { |
a2d6ea01 DM |
393 | if (tlb_type != hypervisor) { |
394 | pci_read_config_word(dev, PCI_VENDOR_ID, | |
395 | &dev->vendor); | |
396 | pci_read_config_word(dev, PCI_DEVICE_ID, | |
397 | &dev->device); | |
398 | } else { | |
399 | dev->vendor = PCI_VENDOR_ID_SUN; | |
400 | dev->device = 0x80f0; | |
401 | } | |
97b3cf05 | 402 | dev->cfg_size = 256; |
28f57e77 DM |
403 | dev->class = PCI_CLASS_BRIDGE_HOST << 8; |
404 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
405 | 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 DM |
406 | } else { |
407 | dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); | |
408 | dev->device = of_getintprop_default(node, "device-id", 0xffff); | |
409 | dev->subsystem_vendor = | |
410 | of_getintprop_default(node, "subsystem-vendor-id", 0); | |
411 | dev->subsystem_device = | |
412 | of_getintprop_default(node, "subsystem-id", 0); | |
413 | ||
414 | dev->cfg_size = pci_cfg_space_size(dev); | |
01f94c4a | 415 | |
97b3cf05 DM |
416 | /* We can't actually use the firmware value, we have |
417 | * to read what is in the register right now. One | |
418 | * reason is that in the case of IDE interfaces the | |
419 | * firmware can sample the value before the the IDE | |
420 | * interface is programmed into native mode. | |
421 | */ | |
422 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
423 | dev->class = class >> 8; | |
b8a3a521 | 424 | dev->revision = class & 0xff; |
28f57e77 DM |
425 | |
426 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
427 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 | 428 | } |
5840fc66 DM |
429 | if (ofpci_verbose) |
430 | printk(" class: 0x%x device name: %s\n", | |
431 | dev->class, pci_name(dev)); | |
a2fb23af | 432 | |
861fe906 DM |
433 | /* I have seen IDE devices which will not respond to |
434 | * the bmdma simplex check reads if bus mastering is | |
435 | * disabled. | |
436 | */ | |
437 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
438 | pci_set_master(dev); | |
439 | ||
a2fb23af DM |
440 | dev->current_state = 4; /* unknown power state */ |
441 | dev->error_state = pci_channel_io_normal; | |
442 | ||
97b3cf05 | 443 | if (host_controller) { |
a2fb23af DM |
444 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; |
445 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
97b3cf05 | 446 | dev->irq = PCI_IRQ_NONE; |
a2fb23af | 447 | } else { |
97b3cf05 DM |
448 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
449 | /* a PCI-PCI bridge */ | |
450 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
451 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
452 | } else if (!strcmp(type, "cardbus")) { | |
453 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
454 | } else { | |
455 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
456 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
a2fb23af | 457 | |
97b3cf05 DM |
458 | dev->irq = sd->op->irqs[0]; |
459 | if (dev->irq == 0xffffffff) | |
460 | dev->irq = PCI_IRQ_NONE; | |
461 | } | |
a2fb23af | 462 | } |
a2fb23af DM |
463 | pci_parse_of_addrs(sd->op, node, dev); |
464 | ||
5840fc66 DM |
465 | if (ofpci_verbose) |
466 | printk(" adding to system ...\n"); | |
a2fb23af DM |
467 | |
468 | pci_device_add(dev, bus); | |
469 | ||
470 | return dev; | |
471 | } | |
472 | ||
a6009dda | 473 | static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) |
01f94c4a DM |
474 | { |
475 | u32 idx, first, last; | |
476 | ||
477 | first = 8; | |
478 | last = 0; | |
479 | for (idx = 0; idx < 8; idx++) { | |
480 | if ((map & (1 << idx)) != 0) { | |
481 | if (first > idx) | |
482 | first = idx; | |
483 | if (last < idx) | |
484 | last = idx; | |
485 | } | |
486 | } | |
487 | ||
488 | *first_p = first; | |
489 | *last_p = last; | |
490 | } | |
491 | ||
f16537ba DM |
492 | static void pci_resource_adjust(struct resource *res, |
493 | struct resource *root) | |
0bae5f81 DM |
494 | { |
495 | res->start += root->start; | |
496 | res->end += root->start; | |
497 | } | |
498 | ||
8c2786cf DM |
499 | /* For PCI bus devices which lack a 'ranges' property we interrogate |
500 | * the config space values to set the resources, just like the generic | |
501 | * Linux PCI probing code does. | |
502 | */ | |
503 | static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev, | |
504 | struct pci_bus *bus, | |
505 | struct pci_pbm_info *pbm) | |
506 | { | |
507 | struct resource *res; | |
508 | u8 io_base_lo, io_limit_lo; | |
509 | u16 mem_base_lo, mem_limit_lo; | |
510 | unsigned long base, limit; | |
511 | ||
512 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); | |
513 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); | |
514 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; | |
515 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; | |
516 | ||
517 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { | |
518 | u16 io_base_hi, io_limit_hi; | |
519 | ||
520 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); | |
521 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); | |
522 | base |= (io_base_hi << 16); | |
523 | limit |= (io_limit_hi << 16); | |
524 | } | |
525 | ||
526 | res = bus->resource[0]; | |
527 | if (base <= limit) { | |
528 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; | |
529 | if (!res->start) | |
530 | res->start = base; | |
531 | if (!res->end) | |
532 | res->end = limit + 0xfff; | |
533 | pci_resource_adjust(res, &pbm->io_space); | |
534 | } | |
535 | ||
536 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); | |
537 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); | |
538 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
539 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; | |
540 | ||
541 | res = bus->resource[1]; | |
542 | if (base <= limit) { | |
543 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
544 | IORESOURCE_MEM); | |
545 | res->start = base; | |
546 | res->end = limit + 0xfffff; | |
547 | pci_resource_adjust(res, &pbm->mem_space); | |
548 | } | |
549 | ||
550 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); | |
551 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); | |
552 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; | |
553 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; | |
554 | ||
555 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { | |
556 | u32 mem_base_hi, mem_limit_hi; | |
557 | ||
558 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); | |
559 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); | |
560 | ||
561 | /* | |
562 | * Some bridges set the base > limit by default, and some | |
563 | * (broken) BIOSes do not initialize them. If we find | |
564 | * this, just assume they are not being used. | |
565 | */ | |
566 | if (mem_base_hi <= mem_limit_hi) { | |
567 | base |= ((long) mem_base_hi) << 32; | |
568 | limit |= ((long) mem_limit_hi) << 32; | |
569 | } | |
570 | } | |
571 | ||
572 | res = bus->resource[2]; | |
573 | if (base <= limit) { | |
574 | res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | | |
575 | IORESOURCE_MEM | IORESOURCE_PREFETCH); | |
576 | res->start = base; | |
577 | res->end = limit + 0xfffff; | |
578 | pci_resource_adjust(res, &pbm->mem_space); | |
579 | } | |
580 | } | |
581 | ||
01f94c4a DM |
582 | /* Cook up fake bus resources for SUNW,simba PCI bridges which lack |
583 | * a proper 'ranges' property. | |
584 | */ | |
a6009dda DM |
585 | static void __devinit apb_fake_ranges(struct pci_dev *dev, |
586 | struct pci_bus *bus, | |
587 | struct pci_pbm_info *pbm) | |
01f94c4a DM |
588 | { |
589 | struct resource *res; | |
590 | u32 first, last; | |
591 | u8 map; | |
592 | ||
593 | pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); | |
594 | apb_calc_first_last(map, &first, &last); | |
595 | res = bus->resource[0]; | |
596 | res->start = (first << 21); | |
597 | res->end = (last << 21) + ((1 << 21) - 1); | |
598 | res->flags = IORESOURCE_IO; | |
0bae5f81 | 599 | pci_resource_adjust(res, &pbm->io_space); |
01f94c4a DM |
600 | |
601 | pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); | |
602 | apb_calc_first_last(map, &first, &last); | |
603 | res = bus->resource[1]; | |
604 | res->start = (first << 21); | |
605 | res->end = (last << 21) + ((1 << 21) - 1); | |
606 | res->flags = IORESOURCE_MEM; | |
0bae5f81 | 607 | pci_resource_adjust(res, &pbm->mem_space); |
01f94c4a DM |
608 | } |
609 | ||
a6009dda DM |
610 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
611 | struct device_node *node, | |
612 | struct pci_bus *bus); | |
a2fb23af DM |
613 | |
614 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
615 | ||
a6009dda DM |
616 | static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, |
617 | struct device_node *node, | |
618 | struct pci_dev *dev) | |
a2fb23af DM |
619 | { |
620 | struct pci_bus *bus; | |
621 | const u32 *busrange, *ranges; | |
01f94c4a | 622 | int len, i, simba; |
a2fb23af DM |
623 | struct resource *res; |
624 | unsigned int flags; | |
625 | u64 size; | |
626 | ||
5840fc66 DM |
627 | if (ofpci_verbose) |
628 | printk("of_scan_pci_bridge(%s)\n", node->full_name); | |
a2fb23af DM |
629 | |
630 | /* parse bus-range property */ | |
631 | busrange = of_get_property(node, "bus-range", &len); | |
632 | if (busrange == NULL || len != 8) { | |
633 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", | |
634 | node->full_name); | |
635 | return; | |
636 | } | |
637 | ranges = of_get_property(node, "ranges", &len); | |
01f94c4a | 638 | simba = 0; |
a2fb23af | 639 | if (ranges == NULL) { |
a165b420 | 640 | const char *model = of_get_property(node, "model", NULL); |
8c2786cf | 641 | if (model && !strcmp(model, "SUNW,simba")) |
01f94c4a | 642 | simba = 1; |
a2fb23af DM |
643 | } |
644 | ||
645 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
646 | if (!bus) { | |
647 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
648 | node->full_name); | |
649 | return; | |
650 | } | |
651 | ||
652 | bus->primary = dev->bus->number; | |
653 | bus->subordinate = busrange[1]; | |
654 | bus->bridge_ctl = 0; | |
655 | ||
01f94c4a | 656 | /* parse ranges property, or cook one up by hand for Simba */ |
a2fb23af DM |
657 | /* PCI #address-cells == 3 and #size-cells == 2 always */ |
658 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
659 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
660 | res->flags = 0; | |
661 | bus->resource[i] = res; | |
662 | ++res; | |
663 | } | |
01f94c4a DM |
664 | if (simba) { |
665 | apb_fake_ranges(dev, bus, pbm); | |
8c2786cf DM |
666 | goto after_ranges; |
667 | } else if (ranges == NULL) { | |
668 | pci_cfg_fake_ranges(dev, bus, pbm); | |
669 | goto after_ranges; | |
01f94c4a | 670 | } |
a2fb23af DM |
671 | i = 1; |
672 | for (; len >= 32; len -= 32, ranges += 8) { | |
673 | struct resource *root; | |
674 | ||
675 | flags = pci_parse_of_flags(ranges[0]); | |
676 | size = GET_64BIT(ranges, 6); | |
677 | if (flags == 0 || size == 0) | |
678 | continue; | |
679 | if (flags & IORESOURCE_IO) { | |
680 | res = bus->resource[0]; | |
681 | if (res->flags) { | |
682 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
683 | " for bridge %s\n", node->full_name); | |
684 | continue; | |
685 | } | |
686 | root = &pbm->io_space; | |
687 | } else { | |
688 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
689 | printk(KERN_ERR "PCI: too many memory ranges" | |
690 | " for bridge %s\n", node->full_name); | |
691 | continue; | |
692 | } | |
693 | res = bus->resource[i]; | |
694 | ++i; | |
695 | root = &pbm->mem_space; | |
696 | } | |
697 | ||
698 | res->start = GET_64BIT(ranges, 1); | |
699 | res->end = res->start + size - 1; | |
700 | res->flags = flags; | |
701 | ||
702 | /* Another way to implement this would be to add an of_device | |
703 | * layer routine that can calculate a resource for a given | |
704 | * range property value in a PCI device. | |
705 | */ | |
0bae5f81 | 706 | pci_resource_adjust(res, root); |
a2fb23af | 707 | } |
8c2786cf | 708 | after_ranges: |
a2fb23af DM |
709 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), |
710 | bus->number); | |
5840fc66 DM |
711 | if (ofpci_verbose) |
712 | printk(" bus name: %s\n", bus->name); | |
a2fb23af DM |
713 | |
714 | pci_of_scan_bus(pbm, node, bus); | |
715 | } | |
716 | ||
a6009dda DM |
717 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
718 | struct device_node *node, | |
719 | struct pci_bus *bus) | |
a2fb23af DM |
720 | { |
721 | struct device_node *child; | |
722 | const u32 *reg; | |
2cc7345f | 723 | int reglen, devfn, prev_devfn; |
a2fb23af DM |
724 | struct pci_dev *dev; |
725 | ||
5840fc66 DM |
726 | if (ofpci_verbose) |
727 | printk("PCI: scan_bus[%s] bus no %d\n", | |
728 | node->full_name, bus->number); | |
a2fb23af DM |
729 | |
730 | child = NULL; | |
2cc7345f | 731 | prev_devfn = -1; |
a2fb23af | 732 | while ((child = of_get_next_child(node, child)) != NULL) { |
5840fc66 DM |
733 | if (ofpci_verbose) |
734 | printk(" * %s\n", child->full_name); | |
a2fb23af DM |
735 | reg = of_get_property(child, "reg", ®len); |
736 | if (reg == NULL || reglen < 20) | |
737 | continue; | |
2cc7345f | 738 | |
a2fb23af DM |
739 | devfn = (reg[0] >> 8) & 0xff; |
740 | ||
2cc7345f DM |
741 | /* This is a workaround for some device trees |
742 | * which list PCI devices twice. On the V100 | |
743 | * for example, device number 3 is listed twice. | |
744 | * Once as "pm" and once again as "lomp". | |
745 | */ | |
746 | if (devfn == prev_devfn) | |
747 | continue; | |
748 | prev_devfn = devfn; | |
749 | ||
a2fb23af | 750 | /* create a new pci_dev for this device */ |
97b3cf05 | 751 | dev = of_create_pci_dev(pbm, child, bus, devfn, 0); |
a2fb23af DM |
752 | if (!dev) |
753 | continue; | |
5840fc66 DM |
754 | if (ofpci_verbose) |
755 | printk("PCI: dev header type: %x\n", | |
756 | dev->hdr_type); | |
a2fb23af DM |
757 | |
758 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
759 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
760 | of_scan_pci_bridge(pbm, child, dev); | |
761 | } | |
762 | } | |
763 | ||
764 | static ssize_t | |
765 | show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) | |
766 | { | |
767 | struct pci_dev *pdev; | |
768 | struct device_node *dp; | |
769 | ||
770 | pdev = to_pci_dev(dev); | |
771 | dp = pdev->dev.archdata.prom_node; | |
772 | ||
773 | return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); | |
774 | } | |
775 | ||
776 | static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); | |
777 | ||
778 | static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) | |
779 | { | |
780 | struct pci_dev *dev; | |
a378fd0e | 781 | struct pci_bus *child_bus; |
a2fb23af DM |
782 | int err; |
783 | ||
784 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
785 | /* we don't really care if we can create this file or | |
786 | * not, but we need to assign the result of the call | |
787 | * or the world will fall under alien invasion and | |
788 | * everybody will be frozen on a spaceship ready to be | |
789 | * eaten on alpha centauri by some green and jelly | |
790 | * humanoid. | |
791 | */ | |
792 | err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); | |
793 | } | |
a378fd0e DM |
794 | list_for_each_entry(child_bus, &bus->children, node) |
795 | pci_bus_register_of_sysfs(child_bus); | |
a2fb23af DM |
796 | } |
797 | ||
97b3cf05 DM |
798 | int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev, |
799 | unsigned int devfn, | |
800 | int where, int size, | |
801 | u32 *value) | |
802 | { | |
803 | static u8 fake_pci_config[] = { | |
804 | 0x8e, 0x10, /* Vendor: 0x108e (Sun) */ | |
a2d6ea01 | 805 | 0xf0, 0x80, /* Device: 0x80f0 (Fire) */ |
97b3cf05 DM |
806 | 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */ |
807 | 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */ | |
808 | 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */ | |
809 | 0x00, /* Cacheline: 0x00 */ | |
810 | 0x40, /* Latency: 0x40 */ | |
811 | 0x00, /* Header-Type: 0x00 normal */ | |
812 | }; | |
813 | ||
814 | *value = 0; | |
815 | if (where >= 0 && where < sizeof(fake_pci_config) && | |
816 | (where + size) >= 0 && | |
817 | (where + size) < sizeof(fake_pci_config) && | |
818 | size <= sizeof(u32)) { | |
819 | while (size--) { | |
820 | *value <<= 8; | |
821 | *value |= fake_pci_config[where + size]; | |
822 | } | |
823 | } | |
824 | ||
825 | return PCIBIOS_SUCCESSFUL; | |
826 | } | |
827 | ||
828 | int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev, | |
829 | unsigned int devfn, | |
830 | int where, int size, | |
831 | u32 value) | |
832 | { | |
833 | return PCIBIOS_SUCCESSFUL; | |
834 | } | |
835 | ||
a6009dda | 836 | struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm) |
a2fb23af | 837 | { |
a2fb23af | 838 | struct device_node *node = pbm->prom_node; |
97b3cf05 | 839 | struct pci_dev *host_pdev; |
a2fb23af DM |
840 | struct pci_bus *bus; |
841 | ||
842 | printk("PCI: Scanning PBM %s\n", node->full_name); | |
843 | ||
844 | /* XXX parent device? XXX */ | |
f1cd8de2 | 845 | bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm); |
a2fb23af DM |
846 | if (!bus) { |
847 | printk(KERN_ERR "Failed to create bus for %s\n", | |
848 | node->full_name); | |
849 | return NULL; | |
850 | } | |
851 | bus->secondary = pbm->pci_first_busno; | |
852 | bus->subordinate = pbm->pci_last_busno; | |
853 | ||
854 | bus->resource[0] = &pbm->io_space; | |
855 | bus->resource[1] = &pbm->mem_space; | |
856 | ||
97b3cf05 DM |
857 | /* Create the dummy host bridge and link it in. */ |
858 | host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1); | |
859 | bus->self = host_pdev; | |
860 | ||
a2fb23af DM |
861 | pci_of_scan_bus(pbm, node, bus); |
862 | pci_bus_add_devices(bus); | |
863 | pci_bus_register_of_sysfs(bus); | |
864 | ||
865 | return bus; | |
866 | } | |
867 | ||
1da177e4 LT |
868 | static void __init pci_scan_each_controller_bus(void) |
869 | { | |
34768bc8 | 870 | struct pci_pbm_info *pbm; |
1da177e4 | 871 | |
34768bc8 DM |
872 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) |
873 | pbm->scan_bus(pbm); | |
1da177e4 LT |
874 | } |
875 | ||
1da177e4 LT |
876 | extern void power_init(void); |
877 | ||
878 | static int __init pcibios_init(void) | |
879 | { | |
880 | pci_controller_probe(); | |
34768bc8 | 881 | if (pci_pbm_root == NULL) |
1da177e4 LT |
882 | return 0; |
883 | ||
884 | pci_scan_each_controller_bus(); | |
885 | ||
1da177e4 LT |
886 | isa_init(); |
887 | ebus_init(); | |
1da177e4 LT |
888 | power_init(); |
889 | ||
890 | return 0; | |
891 | } | |
892 | ||
893 | subsys_initcall(pcibios_init); | |
894 | ||
f6b45da1 | 895 | void __devinit pcibios_fixup_bus(struct pci_bus *pbus) |
1da177e4 LT |
896 | { |
897 | struct pci_pbm_info *pbm = pbus->sysdata; | |
898 | ||
899 | /* Generic PCI bus probing sets these to point at | |
900 | * &io{port,mem}_resouce which is wrong for us. | |
901 | */ | |
902 | pbus->resource[0] = &pbm->io_space; | |
903 | pbus->resource[1] = &pbm->mem_space; | |
904 | } | |
905 | ||
085ae41f | 906 | struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r) |
1da177e4 LT |
907 | { |
908 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
085ae41f | 909 | struct resource *root = NULL; |
1da177e4 | 910 | |
085ae41f | 911 | if (r->flags & IORESOURCE_IO) |
1da177e4 | 912 | root = &pbm->io_space; |
085ae41f | 913 | if (r->flags & IORESOURCE_MEM) |
1da177e4 LT |
914 | root = &pbm->mem_space; |
915 | ||
085ae41f | 916 | return root; |
1da177e4 LT |
917 | } |
918 | ||
919 | void pcibios_update_irq(struct pci_dev *pdev, int irq) | |
920 | { | |
921 | } | |
922 | ||
923 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 924 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
925 | { |
926 | } | |
927 | ||
a2fb23af | 928 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1da177e4 | 929 | { |
a2fb23af DM |
930 | u16 cmd, oldcmd; |
931 | int i; | |
932 | ||
933 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
934 | oldcmd = cmd; | |
935 | ||
936 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
937 | struct resource *res = &dev->resource[i]; | |
938 | ||
939 | /* Only set up the requested stuff */ | |
940 | if (!(mask & (1<<i))) | |
941 | continue; | |
942 | ||
943 | if (res->flags & IORESOURCE_IO) | |
944 | cmd |= PCI_COMMAND_IO; | |
945 | if (res->flags & IORESOURCE_MEM) | |
946 | cmd |= PCI_COMMAND_MEMORY; | |
947 | } | |
948 | ||
949 | if (cmd != oldcmd) { | |
950 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
951 | pci_name(dev), cmd); | |
952 | /* Enable the appropriate bits in the PCI command register. */ | |
953 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
954 | } | |
1da177e4 LT |
955 | return 0; |
956 | } | |
957 | ||
958 | void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, | |
959 | struct resource *res) | |
960 | { | |
961 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
962 | struct resource zero_res, *root; | |
963 | ||
964 | zero_res.start = 0; | |
965 | zero_res.end = 0; | |
966 | zero_res.flags = res->flags; | |
967 | ||
968 | if (res->flags & IORESOURCE_IO) | |
969 | root = &pbm->io_space; | |
970 | else | |
971 | root = &pbm->mem_space; | |
972 | ||
0bae5f81 | 973 | pci_resource_adjust(&zero_res, root); |
1da177e4 LT |
974 | |
975 | region->start = res->start - zero_res.start; | |
976 | region->end = res->end - zero_res.start; | |
977 | } | |
5fdfd42e | 978 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
1da177e4 LT |
979 | |
980 | void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, | |
981 | struct pci_bus_region *region) | |
982 | { | |
983 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
984 | struct resource *root; | |
985 | ||
986 | res->start = region->start; | |
987 | res->end = region->end; | |
988 | ||
989 | if (res->flags & IORESOURCE_IO) | |
990 | root = &pbm->io_space; | |
991 | else | |
992 | root = &pbm->mem_space; | |
993 | ||
0bae5f81 | 994 | pci_resource_adjust(res, root); |
1da177e4 | 995 | } |
41290c14 | 996 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 997 | |
f6b45da1 | 998 | char * __devinit pcibios_setup(char *str) |
1da177e4 | 999 | { |
1da177e4 LT |
1000 | return str; |
1001 | } | |
1002 | ||
1003 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
1004 | ||
1005 | /* If the user uses a host-bridge as the PCI device, he may use | |
1006 | * this to perform a raw mmap() of the I/O or MEM space behind | |
1007 | * that controller. | |
1008 | * | |
1009 | * This can be useful for execution of x86 PCI bios initialization code | |
1010 | * on a PCI card, like the xfree86 int10 stuff does. | |
1011 | */ | |
1012 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
1013 | enum pci_mmap_state mmap_state) | |
1014 | { | |
a2fb23af | 1015 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
1da177e4 LT |
1016 | unsigned long space_size, user_offset, user_size; |
1017 | ||
3875c5c0 DM |
1018 | if (mmap_state == pci_mmap_io) { |
1019 | space_size = (pbm->io_space.end - | |
1020 | pbm->io_space.start) + 1; | |
1da177e4 | 1021 | } else { |
3875c5c0 DM |
1022 | space_size = (pbm->mem_space.end - |
1023 | pbm->mem_space.start) + 1; | |
1da177e4 LT |
1024 | } |
1025 | ||
1026 | /* Make sure the request is in range. */ | |
1027 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
1028 | user_size = vma->vm_end - vma->vm_start; | |
1029 | ||
1030 | if (user_offset >= space_size || | |
1031 | (user_offset + user_size) > space_size) | |
1032 | return -EINVAL; | |
1033 | ||
3875c5c0 DM |
1034 | if (mmap_state == pci_mmap_io) { |
1035 | vma->vm_pgoff = (pbm->io_space.start + | |
1036 | user_offset) >> PAGE_SHIFT; | |
1da177e4 | 1037 | } else { |
3875c5c0 DM |
1038 | vma->vm_pgoff = (pbm->mem_space.start + |
1039 | user_offset) >> PAGE_SHIFT; | |
1da177e4 LT |
1040 | } |
1041 | ||
1042 | return 0; | |
1043 | } | |
1044 | ||
bbe0b5eb DM |
1045 | /* Adjust vm_pgoff of VMA such that it is the physical page offset |
1046 | * corresponding to the 32-bit pci bus offset for DEV requested by the user. | |
1da177e4 LT |
1047 | * |
1048 | * Basically, the user finds the base address for his device which he wishes | |
1049 | * to mmap. They read the 32-bit value from the config space base register, | |
1050 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
1051 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
1052 | * | |
1053 | * Returns negative error code on failure, zero on success. | |
1054 | */ | |
bbe0b5eb DM |
1055 | static int __pci_mmap_make_offset(struct pci_dev *pdev, |
1056 | struct vm_area_struct *vma, | |
1da177e4 LT |
1057 | enum pci_mmap_state mmap_state) |
1058 | { | |
bbe0b5eb DM |
1059 | unsigned long user_paddr, user_size; |
1060 | int i, err; | |
1da177e4 | 1061 | |
bbe0b5eb DM |
1062 | /* First compute the physical address in vma->vm_pgoff, |
1063 | * making sure the user offset is within range in the | |
1064 | * appropriate PCI space. | |
1065 | */ | |
1066 | err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state); | |
1067 | if (err) | |
1068 | return err; | |
1069 | ||
1070 | /* If this is a mapping on a host bridge, any address | |
1071 | * is OK. | |
1072 | */ | |
1073 | if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
1074 | return err; | |
1075 | ||
1076 | /* Otherwise make sure it's in the range for one of the | |
1077 | * device's resources. | |
1078 | */ | |
1079 | user_paddr = vma->vm_pgoff << PAGE_SHIFT; | |
1080 | user_size = vma->vm_end - vma->vm_start; | |
1da177e4 | 1081 | |
1da177e4 | 1082 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { |
bbe0b5eb | 1083 | struct resource *rp = &pdev->resource[i]; |
1da177e4 LT |
1084 | |
1085 | /* Active? */ | |
1086 | if (!rp->flags) | |
1087 | continue; | |
1088 | ||
1089 | /* Same type? */ | |
1090 | if (i == PCI_ROM_RESOURCE) { | |
1091 | if (mmap_state != pci_mmap_mem) | |
1092 | continue; | |
1093 | } else { | |
1094 | if ((mmap_state == pci_mmap_io && | |
1095 | (rp->flags & IORESOURCE_IO) == 0) || | |
1096 | (mmap_state == pci_mmap_mem && | |
1097 | (rp->flags & IORESOURCE_MEM) == 0)) | |
1098 | continue; | |
1099 | } | |
1100 | ||
bbe0b5eb DM |
1101 | if ((rp->start <= user_paddr) && |
1102 | (user_paddr + user_size) <= (rp->end + 1UL)) | |
1103 | break; | |
1da177e4 LT |
1104 | } |
1105 | ||
bbe0b5eb | 1106 | if (i > PCI_ROM_RESOURCE) |
1da177e4 LT |
1107 | return -EINVAL; |
1108 | ||
1da177e4 LT |
1109 | return 0; |
1110 | } | |
1111 | ||
1112 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
1113 | * mapping. | |
1114 | */ | |
1115 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
1116 | enum pci_mmap_state mmap_state) | |
1117 | { | |
1118 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
1119 | } | |
1120 | ||
1121 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
1122 | * device mapping. | |
1123 | */ | |
1124 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
1125 | enum pci_mmap_state mmap_state) | |
1126 | { | |
a7a6cac2 | 1127 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
1128 | } |
1129 | ||
1130 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
1131 | * for this architecture. The region in the process to map is described by vm_start | |
1132 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
1133 | * The pci device structure is provided so that architectures may make mapping | |
1134 | * decisions on a per-device or per-bus basis. | |
1135 | * | |
1136 | * Returns a negative error code on failure, zero on success. | |
1137 | */ | |
1138 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
1139 | enum pci_mmap_state mmap_state, | |
1140 | int write_combine) | |
1141 | { | |
1142 | int ret; | |
1143 | ||
1144 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
1145 | if (ret < 0) | |
1146 | return ret; | |
1147 | ||
1148 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
1149 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
1150 | ||
14778d90 | 1151 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1da177e4 LT |
1152 | ret = io_remap_pfn_range(vma, vma->vm_start, |
1153 | vma->vm_pgoff, | |
1154 | vma->vm_end - vma->vm_start, | |
1155 | vma->vm_page_prot); | |
1156 | if (ret) | |
1157 | return ret; | |
1158 | ||
1da177e4 LT |
1159 | return 0; |
1160 | } | |
1161 | ||
1162 | /* Return the domain nuber for this pci bus */ | |
1163 | ||
1164 | int pci_domain_nr(struct pci_bus *pbus) | |
1165 | { | |
1166 | struct pci_pbm_info *pbm = pbus->sysdata; | |
1167 | int ret; | |
1168 | ||
1169 | if (pbm == NULL || pbm->parent == NULL) { | |
1170 | ret = -ENXIO; | |
1171 | } else { | |
6c108f12 | 1172 | ret = pbm->index; |
1da177e4 LT |
1173 | } |
1174 | ||
1175 | return ret; | |
1176 | } | |
1177 | EXPORT_SYMBOL(pci_domain_nr); | |
1178 | ||
35a17eb6 DM |
1179 | #ifdef CONFIG_PCI_MSI |
1180 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
1181 | { | |
a2fb23af | 1182 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
e9870c4c | 1183 | int virt_irq; |
35a17eb6 | 1184 | |
e9870c4c | 1185 | if (!pbm->setup_msi_irq) |
35a17eb6 DM |
1186 | return -EINVAL; |
1187 | ||
e9870c4c | 1188 | return pbm->setup_msi_irq(&virt_irq, pdev, desc); |
35a17eb6 DM |
1189 | } |
1190 | ||
1191 | void arch_teardown_msi_irq(unsigned int virt_irq) | |
1192 | { | |
abfd336c | 1193 | struct msi_desc *entry = get_irq_msi(virt_irq); |
35a17eb6 | 1194 | struct pci_dev *pdev = entry->dev; |
a2fb23af | 1195 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 | 1196 | |
e9870c4c | 1197 | if (!pbm->teardown_msi_irq) |
35a17eb6 DM |
1198 | return; |
1199 | ||
e9870c4c | 1200 | return pbm->teardown_msi_irq(virt_irq, pdev); |
35a17eb6 DM |
1201 | } |
1202 | #endif /* !(CONFIG_PCI_MSI) */ | |
1203 | ||
f6d0f9ea DM |
1204 | struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) |
1205 | { | |
a2fb23af | 1206 | return pdev->dev.archdata.prom_node; |
f6d0f9ea DM |
1207 | } |
1208 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
1209 | ||
ad7ad57c DM |
1210 | static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit) |
1211 | { | |
1212 | struct pci_dev *ali_isa_bridge; | |
1213 | u8 val; | |
1214 | ||
1215 | /* ALI sound chips generate 31-bits of DMA, a special register | |
1216 | * determines what bit 31 is emitted as. | |
1217 | */ | |
1218 | ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL, | |
1219 | PCI_DEVICE_ID_AL_M1533, | |
1220 | NULL); | |
1221 | ||
1222 | pci_read_config_byte(ali_isa_bridge, 0x7e, &val); | |
1223 | if (set_bit) | |
1224 | val |= 0x01; | |
1225 | else | |
1226 | val &= ~0x01; | |
1227 | pci_write_config_byte(ali_isa_bridge, 0x7e, val); | |
1228 | pci_dev_put(ali_isa_bridge); | |
1229 | } | |
1230 | ||
1231 | int pci_dma_supported(struct pci_dev *pdev, u64 device_mask) | |
1232 | { | |
1233 | u64 dma_addr_mask; | |
1234 | ||
1235 | if (pdev == NULL) { | |
1236 | dma_addr_mask = 0xffffffff; | |
1237 | } else { | |
1238 | struct iommu *iommu = pdev->dev.archdata.iommu; | |
1239 | ||
1240 | dma_addr_mask = iommu->dma_addr_mask; | |
1241 | ||
1242 | if (pdev->vendor == PCI_VENDOR_ID_AL && | |
1243 | pdev->device == PCI_DEVICE_ID_AL_M5451 && | |
1244 | device_mask == 0x7fffffff) { | |
1245 | ali_sound_dma_hack(pdev, | |
1246 | (dma_addr_mask & 0x80000000) != 0); | |
1247 | return 1; | |
1248 | } | |
1249 | } | |
1250 | ||
1251 | if (device_mask >= (1UL << 32UL)) | |
1252 | return 0; | |
1253 | ||
1254 | return (device_mask & dma_addr_mask) == dma_addr_mask; | |
1255 | } | |
1256 | ||
bcea1db1 DM |
1257 | void pci_resource_to_user(const struct pci_dev *pdev, int bar, |
1258 | const struct resource *rp, resource_size_t *start, | |
1259 | resource_size_t *end) | |
1260 | { | |
1261 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | |
1262 | unsigned long offset; | |
1263 | ||
1264 | if (rp->flags & IORESOURCE_IO) | |
1265 | offset = pbm->io_space.start; | |
1266 | else | |
1267 | offset = pbm->mem_space.start; | |
1268 | ||
1269 | *start = rp->start - offset; | |
1270 | *end = rp->end - offset; | |
1271 | } | |
1272 | ||
1da177e4 | 1273 | #endif /* !(CONFIG_PCI) */ |