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1da177e4 LT |
1 | /* $Id: pci.c,v 1.39 2002/01/05 01:13:43 davem Exp $ |
2 | * pci.c: UltraSparc PCI controller support. | |
3 | * | |
4 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
5 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
9 | #include <linux/config.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/string.h> | |
13 | #include <linux/sched.h> | |
14 | #include <linux/capability.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/smp_lock.h> | |
17 | #include <linux/init.h> | |
18 | ||
19 | #include <asm/uaccess.h> | |
20 | #include <asm/pbm.h> | |
21 | #include <asm/pgtable.h> | |
22 | #include <asm/irq.h> | |
23 | #include <asm/ebus.h> | |
24 | #include <asm/isa.h> | |
25 | ||
26 | unsigned long pci_memspace_mask = 0xffffffffUL; | |
27 | ||
28 | #ifndef CONFIG_PCI | |
29 | /* A "nop" PCI implementation. */ | |
30 | asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn, | |
31 | unsigned long off, unsigned long len, | |
32 | unsigned char *buf) | |
33 | { | |
34 | return 0; | |
35 | } | |
36 | asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn, | |
37 | unsigned long off, unsigned long len, | |
38 | unsigned char *buf) | |
39 | { | |
40 | return 0; | |
41 | } | |
42 | #else | |
43 | ||
44 | /* List of all PCI controllers found in the system. */ | |
45 | struct pci_controller_info *pci_controller_root = NULL; | |
46 | ||
47 | /* Each PCI controller found gets a unique index. */ | |
48 | int pci_num_controllers = 0; | |
49 | ||
50 | /* At boot time the user can give the kernel a command | |
51 | * line option which controls if and how PCI devices | |
52 | * are reordered at PCI bus probing time. | |
53 | */ | |
54 | int pci_device_reorder = 0; | |
55 | ||
56 | volatile int pci_poke_in_progress; | |
57 | volatile int pci_poke_cpu = -1; | |
58 | volatile int pci_poke_faulted; | |
59 | ||
60 | static DEFINE_SPINLOCK(pci_poke_lock); | |
61 | ||
62 | void pci_config_read8(u8 *addr, u8 *ret) | |
63 | { | |
64 | unsigned long flags; | |
65 | u8 byte; | |
66 | ||
67 | spin_lock_irqsave(&pci_poke_lock, flags); | |
68 | pci_poke_cpu = smp_processor_id(); | |
69 | pci_poke_in_progress = 1; | |
70 | pci_poke_faulted = 0; | |
71 | __asm__ __volatile__("membar #Sync\n\t" | |
72 | "lduba [%1] %2, %0\n\t" | |
73 | "membar #Sync" | |
74 | : "=r" (byte) | |
75 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
76 | : "memory"); | |
77 | pci_poke_in_progress = 0; | |
78 | pci_poke_cpu = -1; | |
79 | if (!pci_poke_faulted) | |
80 | *ret = byte; | |
81 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
82 | } | |
83 | ||
84 | void pci_config_read16(u16 *addr, u16 *ret) | |
85 | { | |
86 | unsigned long flags; | |
87 | u16 word; | |
88 | ||
89 | spin_lock_irqsave(&pci_poke_lock, flags); | |
90 | pci_poke_cpu = smp_processor_id(); | |
91 | pci_poke_in_progress = 1; | |
92 | pci_poke_faulted = 0; | |
93 | __asm__ __volatile__("membar #Sync\n\t" | |
94 | "lduha [%1] %2, %0\n\t" | |
95 | "membar #Sync" | |
96 | : "=r" (word) | |
97 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
98 | : "memory"); | |
99 | pci_poke_in_progress = 0; | |
100 | pci_poke_cpu = -1; | |
101 | if (!pci_poke_faulted) | |
102 | *ret = word; | |
103 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
104 | } | |
105 | ||
106 | void pci_config_read32(u32 *addr, u32 *ret) | |
107 | { | |
108 | unsigned long flags; | |
109 | u32 dword; | |
110 | ||
111 | spin_lock_irqsave(&pci_poke_lock, flags); | |
112 | pci_poke_cpu = smp_processor_id(); | |
113 | pci_poke_in_progress = 1; | |
114 | pci_poke_faulted = 0; | |
115 | __asm__ __volatile__("membar #Sync\n\t" | |
116 | "lduwa [%1] %2, %0\n\t" | |
117 | "membar #Sync" | |
118 | : "=r" (dword) | |
119 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
120 | : "memory"); | |
121 | pci_poke_in_progress = 0; | |
122 | pci_poke_cpu = -1; | |
123 | if (!pci_poke_faulted) | |
124 | *ret = dword; | |
125 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
126 | } | |
127 | ||
128 | void pci_config_write8(u8 *addr, u8 val) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&pci_poke_lock, flags); | |
133 | pci_poke_cpu = smp_processor_id(); | |
134 | pci_poke_in_progress = 1; | |
135 | pci_poke_faulted = 0; | |
136 | __asm__ __volatile__("membar #Sync\n\t" | |
137 | "stba %0, [%1] %2\n\t" | |
138 | "membar #Sync" | |
139 | : /* no outputs */ | |
140 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
141 | : "memory"); | |
142 | pci_poke_in_progress = 0; | |
143 | pci_poke_cpu = -1; | |
144 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
145 | } | |
146 | ||
147 | void pci_config_write16(u16 *addr, u16 val) | |
148 | { | |
149 | unsigned long flags; | |
150 | ||
151 | spin_lock_irqsave(&pci_poke_lock, flags); | |
152 | pci_poke_cpu = smp_processor_id(); | |
153 | pci_poke_in_progress = 1; | |
154 | pci_poke_faulted = 0; | |
155 | __asm__ __volatile__("membar #Sync\n\t" | |
156 | "stha %0, [%1] %2\n\t" | |
157 | "membar #Sync" | |
158 | : /* no outputs */ | |
159 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
160 | : "memory"); | |
161 | pci_poke_in_progress = 0; | |
162 | pci_poke_cpu = -1; | |
163 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
164 | } | |
165 | ||
166 | void pci_config_write32(u32 *addr, u32 val) | |
167 | { | |
168 | unsigned long flags; | |
169 | ||
170 | spin_lock_irqsave(&pci_poke_lock, flags); | |
171 | pci_poke_cpu = smp_processor_id(); | |
172 | pci_poke_in_progress = 1; | |
173 | pci_poke_faulted = 0; | |
174 | __asm__ __volatile__("membar #Sync\n\t" | |
175 | "stwa %0, [%1] %2\n\t" | |
176 | "membar #Sync" | |
177 | : /* no outputs */ | |
178 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
179 | : "memory"); | |
180 | pci_poke_in_progress = 0; | |
181 | pci_poke_cpu = -1; | |
182 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
183 | } | |
184 | ||
185 | /* Probe for all PCI controllers in the system. */ | |
186 | extern void sabre_init(int, char *); | |
187 | extern void psycho_init(int, char *); | |
188 | extern void schizo_init(int, char *); | |
189 | extern void schizo_plus_init(int, char *); | |
190 | extern void tomatillo_init(int, char *); | |
191 | ||
192 | static struct { | |
193 | char *model_name; | |
194 | void (*init)(int, char *); | |
195 | } pci_controller_table[] __initdata = { | |
196 | { "SUNW,sabre", sabre_init }, | |
197 | { "pci108e,a000", sabre_init }, | |
198 | { "pci108e,a001", sabre_init }, | |
199 | { "SUNW,psycho", psycho_init }, | |
200 | { "pci108e,8000", psycho_init }, | |
201 | { "SUNW,schizo", schizo_init }, | |
202 | { "pci108e,8001", schizo_init }, | |
203 | { "SUNW,schizo+", schizo_plus_init }, | |
204 | { "pci108e,8002", schizo_plus_init }, | |
205 | { "SUNW,tomatillo", tomatillo_init }, | |
206 | { "pci108e,a801", tomatillo_init }, | |
207 | }; | |
208 | #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \ | |
209 | sizeof(pci_controller_table[0])) | |
210 | ||
211 | static int __init pci_controller_init(char *model_name, int namelen, int node) | |
212 | { | |
213 | int i; | |
214 | ||
215 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
216 | if (!strncmp(model_name, | |
217 | pci_controller_table[i].model_name, | |
218 | namelen)) { | |
219 | pci_controller_table[i].init(node, model_name); | |
220 | return 1; | |
221 | } | |
222 | } | |
223 | printk("PCI: Warning unknown controller, model name [%s]\n", | |
224 | model_name); | |
225 | printk("PCI: Ignoring controller...\n"); | |
226 | ||
227 | return 0; | |
228 | } | |
229 | ||
230 | static int __init pci_is_controller(char *model_name, int namelen, int node) | |
231 | { | |
232 | int i; | |
233 | ||
234 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
235 | if (!strncmp(model_name, | |
236 | pci_controller_table[i].model_name, | |
237 | namelen)) { | |
238 | return 1; | |
239 | } | |
240 | } | |
241 | return 0; | |
242 | } | |
243 | ||
244 | static int __init pci_controller_scan(int (*handler)(char *, int, int)) | |
245 | { | |
246 | char namebuf[64]; | |
247 | int node; | |
248 | int count = 0; | |
249 | ||
250 | node = prom_getchild(prom_root_node); | |
251 | while ((node = prom_searchsiblings(node, "pci")) != 0) { | |
252 | int len; | |
253 | ||
254 | if ((len = prom_getproperty(node, "model", namebuf, sizeof(namebuf))) > 0 || | |
255 | (len = prom_getproperty(node, "compatible", namebuf, sizeof(namebuf))) > 0) { | |
256 | int item_len = 0; | |
257 | ||
258 | /* Our value may be a multi-valued string in the | |
259 | * case of some compatible properties. For sanity, | |
260 | * only try the first one. */ | |
261 | ||
262 | while (namebuf[item_len] && len) { | |
263 | len--; | |
264 | item_len++; | |
265 | } | |
266 | ||
267 | if (handler(namebuf, item_len, node)) | |
268 | count++; | |
269 | } | |
270 | ||
271 | node = prom_getsibling(node); | |
272 | if (!node) | |
273 | break; | |
274 | } | |
275 | ||
276 | return count; | |
277 | } | |
278 | ||
279 | ||
280 | /* Is there some PCI controller in the system? */ | |
281 | int __init pcic_present(void) | |
282 | { | |
283 | return pci_controller_scan(pci_is_controller); | |
284 | } | |
285 | ||
286 | /* Find each controller in the system, attach and initialize | |
287 | * software state structure for each and link into the | |
288 | * pci_controller_root. Setup the controller enough such | |
289 | * that bus scanning can be done. | |
290 | */ | |
291 | static void __init pci_controller_probe(void) | |
292 | { | |
293 | printk("PCI: Probing for controllers.\n"); | |
294 | ||
295 | pci_controller_scan(pci_controller_init); | |
296 | } | |
297 | ||
298 | static void __init pci_scan_each_controller_bus(void) | |
299 | { | |
300 | struct pci_controller_info *p; | |
301 | ||
302 | for (p = pci_controller_root; p; p = p->next) | |
303 | p->scan_bus(p); | |
304 | } | |
305 | ||
306 | /* Reorder the pci_dev chain, so that onboard devices come first | |
307 | * and then come the pluggable cards. | |
308 | */ | |
309 | static void __init pci_reorder_devs(void) | |
310 | { | |
311 | struct list_head *pci_onboard = &pci_devices; | |
312 | struct list_head *walk = pci_onboard->next; | |
313 | ||
314 | while (walk != pci_onboard) { | |
315 | struct pci_dev *pdev = pci_dev_g(walk); | |
316 | struct list_head *walk_next = walk->next; | |
317 | ||
318 | if (pdev->irq && (__irq_ino(pdev->irq) & 0x20)) { | |
319 | list_del(walk); | |
320 | list_add(walk, pci_onboard); | |
321 | } | |
322 | ||
323 | walk = walk_next; | |
324 | } | |
325 | } | |
326 | ||
327 | extern void clock_probe(void); | |
328 | extern void power_init(void); | |
329 | ||
330 | static int __init pcibios_init(void) | |
331 | { | |
332 | pci_controller_probe(); | |
333 | if (pci_controller_root == NULL) | |
334 | return 0; | |
335 | ||
336 | pci_scan_each_controller_bus(); | |
337 | ||
338 | if (pci_device_reorder) | |
339 | pci_reorder_devs(); | |
340 | ||
341 | isa_init(); | |
342 | ebus_init(); | |
343 | clock_probe(); | |
344 | power_init(); | |
345 | ||
346 | return 0; | |
347 | } | |
348 | ||
349 | subsys_initcall(pcibios_init); | |
350 | ||
351 | void pcibios_fixup_bus(struct pci_bus *pbus) | |
352 | { | |
353 | struct pci_pbm_info *pbm = pbus->sysdata; | |
354 | ||
355 | /* Generic PCI bus probing sets these to point at | |
356 | * &io{port,mem}_resouce which is wrong for us. | |
357 | */ | |
358 | pbus->resource[0] = &pbm->io_space; | |
359 | pbus->resource[1] = &pbm->mem_space; | |
360 | } | |
361 | ||
085ae41f | 362 | struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r) |
1da177e4 LT |
363 | { |
364 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
085ae41f | 365 | struct resource *root = NULL; |
1da177e4 | 366 | |
085ae41f | 367 | if (r->flags & IORESOURCE_IO) |
1da177e4 | 368 | root = &pbm->io_space; |
085ae41f | 369 | if (r->flags & IORESOURCE_MEM) |
1da177e4 LT |
370 | root = &pbm->mem_space; |
371 | ||
085ae41f | 372 | return root; |
1da177e4 LT |
373 | } |
374 | ||
375 | void pcibios_update_irq(struct pci_dev *pdev, int irq) | |
376 | { | |
377 | } | |
378 | ||
379 | void pcibios_align_resource(void *data, struct resource *res, | |
380 | unsigned long size, unsigned long align) | |
381 | { | |
382 | } | |
383 | ||
384 | int pcibios_enable_device(struct pci_dev *pdev, int mask) | |
385 | { | |
386 | return 0; | |
387 | } | |
388 | ||
389 | void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, | |
390 | struct resource *res) | |
391 | { | |
392 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
393 | struct resource zero_res, *root; | |
394 | ||
395 | zero_res.start = 0; | |
396 | zero_res.end = 0; | |
397 | zero_res.flags = res->flags; | |
398 | ||
399 | if (res->flags & IORESOURCE_IO) | |
400 | root = &pbm->io_space; | |
401 | else | |
402 | root = &pbm->mem_space; | |
403 | ||
404 | pbm->parent->resource_adjust(pdev, &zero_res, root); | |
405 | ||
406 | region->start = res->start - zero_res.start; | |
407 | region->end = res->end - zero_res.start; | |
408 | } | |
409 | ||
410 | void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, | |
411 | struct pci_bus_region *region) | |
412 | { | |
413 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
414 | struct resource *root; | |
415 | ||
416 | res->start = region->start; | |
417 | res->end = region->end; | |
418 | ||
419 | if (res->flags & IORESOURCE_IO) | |
420 | root = &pbm->io_space; | |
421 | else | |
422 | root = &pbm->mem_space; | |
423 | ||
424 | pbm->parent->resource_adjust(pdev, res, root); | |
425 | } | |
41290c14 | 426 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 LT |
427 | |
428 | char * __init pcibios_setup(char *str) | |
429 | { | |
430 | if (!strcmp(str, "onboardfirst")) { | |
431 | pci_device_reorder = 1; | |
432 | return NULL; | |
433 | } | |
434 | if (!strcmp(str, "noreorder")) { | |
435 | pci_device_reorder = 0; | |
436 | return NULL; | |
437 | } | |
438 | return str; | |
439 | } | |
440 | ||
441 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
442 | ||
443 | /* If the user uses a host-bridge as the PCI device, he may use | |
444 | * this to perform a raw mmap() of the I/O or MEM space behind | |
445 | * that controller. | |
446 | * | |
447 | * This can be useful for execution of x86 PCI bios initialization code | |
448 | * on a PCI card, like the xfree86 int10 stuff does. | |
449 | */ | |
450 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
451 | enum pci_mmap_state mmap_state) | |
452 | { | |
453 | struct pcidev_cookie *pcp = pdev->sysdata; | |
454 | struct pci_pbm_info *pbm; | |
455 | struct pci_controller_info *p; | |
456 | unsigned long space_size, user_offset, user_size; | |
457 | ||
458 | if (!pcp) | |
459 | return -ENXIO; | |
460 | pbm = pcp->pbm; | |
461 | if (!pbm) | |
462 | return -ENXIO; | |
463 | ||
464 | p = pbm->parent; | |
465 | if (p->pbms_same_domain) { | |
466 | unsigned long lowest, highest; | |
467 | ||
468 | lowest = ~0UL; highest = 0UL; | |
469 | if (mmap_state == pci_mmap_io) { | |
470 | if (p->pbm_A.io_space.flags) { | |
471 | lowest = p->pbm_A.io_space.start; | |
472 | highest = p->pbm_A.io_space.end + 1; | |
473 | } | |
474 | if (p->pbm_B.io_space.flags) { | |
475 | if (lowest > p->pbm_B.io_space.start) | |
476 | lowest = p->pbm_B.io_space.start; | |
477 | if (highest < p->pbm_B.io_space.end + 1) | |
478 | highest = p->pbm_B.io_space.end + 1; | |
479 | } | |
480 | space_size = highest - lowest; | |
481 | } else { | |
482 | if (p->pbm_A.mem_space.flags) { | |
483 | lowest = p->pbm_A.mem_space.start; | |
484 | highest = p->pbm_A.mem_space.end + 1; | |
485 | } | |
486 | if (p->pbm_B.mem_space.flags) { | |
487 | if (lowest > p->pbm_B.mem_space.start) | |
488 | lowest = p->pbm_B.mem_space.start; | |
489 | if (highest < p->pbm_B.mem_space.end + 1) | |
490 | highest = p->pbm_B.mem_space.end + 1; | |
491 | } | |
492 | space_size = highest - lowest; | |
493 | } | |
494 | } else { | |
495 | if (mmap_state == pci_mmap_io) { | |
496 | space_size = (pbm->io_space.end - | |
497 | pbm->io_space.start) + 1; | |
498 | } else { | |
499 | space_size = (pbm->mem_space.end - | |
500 | pbm->mem_space.start) + 1; | |
501 | } | |
502 | } | |
503 | ||
504 | /* Make sure the request is in range. */ | |
505 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
506 | user_size = vma->vm_end - vma->vm_start; | |
507 | ||
508 | if (user_offset >= space_size || | |
509 | (user_offset + user_size) > space_size) | |
510 | return -EINVAL; | |
511 | ||
512 | if (p->pbms_same_domain) { | |
513 | unsigned long lowest = ~0UL; | |
514 | ||
515 | if (mmap_state == pci_mmap_io) { | |
516 | if (p->pbm_A.io_space.flags) | |
517 | lowest = p->pbm_A.io_space.start; | |
518 | if (p->pbm_B.io_space.flags && | |
519 | lowest > p->pbm_B.io_space.start) | |
520 | lowest = p->pbm_B.io_space.start; | |
521 | } else { | |
522 | if (p->pbm_A.mem_space.flags) | |
523 | lowest = p->pbm_A.mem_space.start; | |
524 | if (p->pbm_B.mem_space.flags && | |
525 | lowest > p->pbm_B.mem_space.start) | |
526 | lowest = p->pbm_B.mem_space.start; | |
527 | } | |
528 | vma->vm_pgoff = (lowest + user_offset) >> PAGE_SHIFT; | |
529 | } else { | |
530 | if (mmap_state == pci_mmap_io) { | |
531 | vma->vm_pgoff = (pbm->io_space.start + | |
532 | user_offset) >> PAGE_SHIFT; | |
533 | } else { | |
534 | vma->vm_pgoff = (pbm->mem_space.start + | |
535 | user_offset) >> PAGE_SHIFT; | |
536 | } | |
537 | } | |
538 | ||
539 | return 0; | |
540 | } | |
541 | ||
542 | /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding | |
543 | * to the 32-bit pci bus offset for DEV requested by the user. | |
544 | * | |
545 | * Basically, the user finds the base address for his device which he wishes | |
546 | * to mmap. They read the 32-bit value from the config space base register, | |
547 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
548 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
549 | * | |
550 | * Returns negative error code on failure, zero on success. | |
551 | */ | |
552 | static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma, | |
553 | enum pci_mmap_state mmap_state) | |
554 | { | |
555 | unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
556 | unsigned long user32 = user_offset & pci_memspace_mask; | |
557 | unsigned long largest_base, this_base, addr32; | |
558 | int i; | |
559 | ||
560 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
561 | return __pci_mmap_make_offset_bus(dev, vma, mmap_state); | |
562 | ||
563 | /* Figure out which base address this is for. */ | |
564 | largest_base = 0UL; | |
565 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
566 | struct resource *rp = &dev->resource[i]; | |
567 | ||
568 | /* Active? */ | |
569 | if (!rp->flags) | |
570 | continue; | |
571 | ||
572 | /* Same type? */ | |
573 | if (i == PCI_ROM_RESOURCE) { | |
574 | if (mmap_state != pci_mmap_mem) | |
575 | continue; | |
576 | } else { | |
577 | if ((mmap_state == pci_mmap_io && | |
578 | (rp->flags & IORESOURCE_IO) == 0) || | |
579 | (mmap_state == pci_mmap_mem && | |
580 | (rp->flags & IORESOURCE_MEM) == 0)) | |
581 | continue; | |
582 | } | |
583 | ||
584 | this_base = rp->start; | |
585 | ||
586 | addr32 = (this_base & PAGE_MASK) & pci_memspace_mask; | |
587 | ||
588 | if (mmap_state == pci_mmap_io) | |
589 | addr32 &= 0xffffff; | |
590 | ||
591 | if (addr32 <= user32 && this_base > largest_base) | |
592 | largest_base = this_base; | |
593 | } | |
594 | ||
595 | if (largest_base == 0UL) | |
596 | return -EINVAL; | |
597 | ||
598 | /* Now construct the final physical address. */ | |
599 | if (mmap_state == pci_mmap_io) | |
600 | vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT); | |
601 | else | |
602 | vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT); | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
607 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
608 | * mapping. | |
609 | */ | |
610 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
611 | enum pci_mmap_state mmap_state) | |
612 | { | |
613 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
614 | } | |
615 | ||
616 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
617 | * device mapping. | |
618 | */ | |
619 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
620 | enum pci_mmap_state mmap_state) | |
621 | { | |
a7a6cac2 | 622 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
623 | } |
624 | ||
625 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
626 | * for this architecture. The region in the process to map is described by vm_start | |
627 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
628 | * The pci device structure is provided so that architectures may make mapping | |
629 | * decisions on a per-device or per-bus basis. | |
630 | * | |
631 | * Returns a negative error code on failure, zero on success. | |
632 | */ | |
633 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
634 | enum pci_mmap_state mmap_state, | |
635 | int write_combine) | |
636 | { | |
637 | int ret; | |
638 | ||
639 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
640 | if (ret < 0) | |
641 | return ret; | |
642 | ||
643 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
644 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
645 | ||
646 | ret = io_remap_pfn_range(vma, vma->vm_start, | |
647 | vma->vm_pgoff, | |
648 | vma->vm_end - vma->vm_start, | |
649 | vma->vm_page_prot); | |
650 | if (ret) | |
651 | return ret; | |
652 | ||
653 | vma->vm_flags |= VM_IO; | |
654 | return 0; | |
655 | } | |
656 | ||
657 | /* Return the domain nuber for this pci bus */ | |
658 | ||
659 | int pci_domain_nr(struct pci_bus *pbus) | |
660 | { | |
661 | struct pci_pbm_info *pbm = pbus->sysdata; | |
662 | int ret; | |
663 | ||
664 | if (pbm == NULL || pbm->parent == NULL) { | |
665 | ret = -ENXIO; | |
666 | } else { | |
667 | struct pci_controller_info *p = pbm->parent; | |
668 | ||
669 | ret = p->index; | |
670 | if (p->pbms_same_domain == 0) | |
671 | ret = ((ret << 1) + | |
672 | ((pbm == &pbm->parent->pbm_B) ? 1 : 0)); | |
673 | } | |
674 | ||
675 | return ret; | |
676 | } | |
677 | EXPORT_SYMBOL(pci_domain_nr); | |
678 | ||
679 | int pcibios_prep_mwi(struct pci_dev *dev) | |
680 | { | |
681 | /* We set correct PCI_CACHE_LINE_SIZE register values for every | |
682 | * device probed on this platform. So there is nothing to check | |
683 | * and this always succeeds. | |
684 | */ | |
685 | return 0; | |
686 | } | |
687 | ||
688 | #endif /* !(CONFIG_PCI) */ |