[linux-2.6-block.git] / arch / sparc64 / kernel / chmc.c

/* chmc.c: Driver for UltraSPARC-III memory controller.
 *
 * Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/string.h>
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <asm/spitfire.h>
#include <asm/chmctrl.h>
#include <asm/cpudata.h>
#include <asm/oplib.h>
#include <asm/prom.h>
#include <asm/head.h>
#include <asm/io.h>
#include <asm/memctrl.h>

#define DRV_MODULE_NAME		"chmc"
#define PFX DRV_MODULE_NAME	": "
#define DRV_MODULE_VERSION	"0.2"

MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_MODULE_VERSION);

#define CHMCTRL_NDGRPS	2
#define CHMCTRL_NDIMMS	4

#define CHMC_DIMMS_PER_MC	(CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)

/* OBP memory-layout property format. */
struct chmc_obp_map {
	unsigned char	dimm_map[144];
	unsigned char	pin_map[576];
};

#define DIMM_LABEL_SZ	8

struct chmc_obp_mem_layout {
	/* One max 8-byte string label per DIMM.  Usually
	 * this matches the label on the motherboard where
	 * that DIMM resides.
	 */
	char			dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ];

	/* If symmetric use map[0], else it is
	 * asymmetric and map[1] should be used.
	 */
	char			symmetric;

	struct chmc_obp_map	map[2];
};

#define CHMCTRL_NBANKS	4

struct chmc_bank_info {
	struct chmc		*p;
	int			bank_id;

	u64			raw_reg;
	int			valid;
	int			uk;
	int			um;
	int			lk;
	int			lm;
	int			interleave;
	unsigned long		base;
	unsigned long		size;
};

struct chmc {
	struct list_head		list;
	int				portid;

	struct chmc_obp_mem_layout	layout_prop;
	int				layout_size;

	void __iomem			*regs;

	u64				timing_control1;
	u64				timing_control2;
	u64				timing_control3;
	u64				timing_control4;
	u64				memaddr_control;

	struct chmc_bank_info		logical_banks[CHMCTRL_NBANKS];
};

static LIST_HEAD(mctrl_list);

/* Does BANK decode PHYS_ADDR? */
static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr)
{
	unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
	unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;

	/* Bank must be enabled to match. */
	if (bp->valid == 0)
		return 0;

	/* Would BANK match upper bits? */
	upper_bits ^= bp->um;		/* What bits are different? */
	upper_bits  = ~upper_bits;	/* Invert. */
	upper_bits |= bp->uk;		/* What bits don't matter for matching? */
	upper_bits  = ~upper_bits;	/* Invert. */

	if (upper_bits)
		return 0;

	/* Would BANK match lower bits? */
	lower_bits ^= bp->lm;		/* What bits are different? */
	lower_bits  = ~lower_bits;	/* Invert. */
	lower_bits |= bp->lk;		/* What bits don't matter for matching? */
	lower_bits  = ~lower_bits;	/* Invert. */

	if (lower_bits)
		return 0;

	/* I always knew you'd be the one. */
	return 1;
}

/* Given PHYS_ADDR, search memory controller banks for a match. */
static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr)
{
	struct list_head *mctrl_head = &mctrl_list;
	struct list_head *mctrl_entry = mctrl_head->next;

	for (;;) {
		struct chmc *p = list_entry(mctrl_entry, struct chmc, list);
		int bank_no;

		if (mctrl_entry == mctrl_head)
			break;
		mctrl_entry = mctrl_entry->next;

		for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
			struct chmc_bank_info *bp;

			bp = &p->logical_banks[bank_no];
			if (chmc_bank_match(bp, phys_addr))
				return bp;
		}
	}

	return NULL;
}

/* This is the main purpose of this driver. */
#define SYNDROME_MIN	-1
#define SYNDROME_MAX	144
static int chmc_print_dimm(int syndrome_code,
			   unsigned long phys_addr,
			   char *buf, int buflen)
{
	struct chmc_bank_info *bp;
	struct chmc_obp_mem_layout *prop;
	int bank_in_controller, first_dimm;

	bp = chmc_find_bank(phys_addr);
	if (bp == NULL ||
	    syndrome_code < SYNDROME_MIN ||
	    syndrome_code > SYNDROME_MAX) {
		buf[0] = '?';
		buf[1] = '?';
		buf[2] = '?';
		buf[3] = '\0';
		return 0;
	}

	prop = &bp->p->layout_prop;
	bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
	first_dimm  = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
	first_dimm *= CHMCTRL_NDIMMS;

	if (syndrome_code != SYNDROME_MIN) {
		struct chmc_obp_map *map;
		int qword, where_in_line, where, map_index, map_offset;
		unsigned int map_val;

		/* Yaay, single bit error so we can figure out
		 * the exact dimm.
		 */
		if (prop->symmetric)
			map = &prop->map[0];
		else
			map = &prop->map[1];

		/* Covert syndrome code into the way the bits are
		 * positioned on the bus.
		 */
		if (syndrome_code < 144 - 16)
			syndrome_code += 16;
		else if (syndrome_code < 144)
			syndrome_code -= (144 - 7);
		else if (syndrome_code < (144 + 3))
			syndrome_code -= (144 + 3 - 4);
		else
			syndrome_code -= 144 + 3;

		/* All this magic has to do with how a cache line
		 * comes over the wire on Safari.  A 64-bit line
		 * comes over in 4 quadword cycles, each of which
		 * transmit ECC/MTAG info as well as the actual
		 * data.  144 bits per quadword, 576 total.
		 */
#define LINE_SIZE	64
#define LINE_ADDR_MSK	(LINE_SIZE - 1)
#define QW_PER_LINE	4
#define QW_BYTES	(LINE_SIZE / QW_PER_LINE)
#define QW_BITS		144
#define LAST_BIT	(576 - 1)

		qword = (phys_addr & LINE_ADDR_MSK) / QW_BYTES;
		where_in_line = ((3 - qword) * QW_BITS) + syndrome_code;
		where = (LAST_BIT - where_in_line);
		map_index = where >> 2;
		map_offset = where & 0x3;
		map_val = map->dimm_map[map_index];
		map_val = ((map_val >> ((3 - map_offset) << 1)) & (2 - 1));

		sprintf(buf, "%s, pin %3d",
			prop->dimm_labels[first_dimm + map_val],
			map->pin_map[where_in_line]);
	} else {
		int dimm;

		/* Multi-bit error, we just dump out all the
		 * dimm labels associated with this bank.
		 */
		for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) {
			sprintf(buf, "%s ",
				prop->dimm_labels[first_dimm + dimm]);
			buf += strlen(buf);
		}
	}
	return 0;
}

/* Accessing the registers is slightly complicated.  If you want
 * to get at the memory controller which is on the same processor
 * the code is executing, you must use special ASI load/store else
 * you go through the global mapping.
 */
static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset)
{
	unsigned long ret, this_cpu;

	preempt_disable();

	this_cpu = real_hard_smp_processor_id();

	if (p->portid == this_cpu) {
		__asm__ __volatile__("ldxa	[%1] %2, %0"
				     : "=r" (ret)
				     : "r" (offset), "i" (ASI_MCU_CTRL_REG));
	} else {
		__asm__ __volatile__("ldxa	[%1] %2, %0"
				     : "=r" (ret)
				     : "r" (p->regs + offset),
				       "i" (ASI_PHYS_BYPASS_EC_E));
	}

	preempt_enable();

	return ret;
}

#if 0 /* currently unused */
static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val)
{
	if (p->portid == smp_processor_id()) {
		__asm__ __volatile__("stxa	%0, [%1] %2"
				     : : "r" (val),
				         "r" (offset), "i" (ASI_MCU_CTRL_REG));
	} else {
		__asm__ __volatile__("ldxa	%0, [%1] %2"
				     : : "r" (val),
				         "r" (p->regs + offset),
				         "i" (ASI_PHYS_BYPASS_EC_E));
	}
}
#endif

static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val)
{
	struct chmc_bank_info *bp = &p->logical_banks[which_bank];

	bp->p = p;
	bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank;
	bp->raw_reg = val;
	bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
	bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
	bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
	bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
	bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;

	bp->base  =  (bp->um);
	bp->base &= ~(bp->uk);
	bp->base <<= PA_UPPER_BITS_SHIFT;

	switch(bp->lk) {
	case 0xf:
	default:
		bp->interleave = 1;
		break;

	case 0xe:
		bp->interleave = 2;
		break;

	case 0xc:
		bp->interleave = 4;
		break;

	case 0x8:
		bp->interleave = 8;
		break;

	case 0x0:
		bp->interleave = 16;
		break;
	};

	/* UK[10] is reserved, and UK[11] is not set for the SDRAM
	 * bank size definition.
	 */
	bp->size = (((unsigned long)bp->uk &
		     ((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
	bp->size /= bp->interleave;
}

static void chmc_fetch_decode_regs(struct chmc *p)
{
	if (p->layout_size == 0)
		return;

	chmc_interpret_one_decode_reg(p, 0,
				      chmc_read_mcreg(p, CHMCTRL_DECODE1));
	chmc_interpret_one_decode_reg(p, 1,
				      chmc_read_mcreg(p, CHMCTRL_DECODE2));
	chmc_interpret_one_decode_reg(p, 2,
				      chmc_read_mcreg(p, CHMCTRL_DECODE3));
	chmc_interpret_one_decode_reg(p, 3,
				      chmc_read_mcreg(p, CHMCTRL_DECODE4));
}

static int __devinit chmc_probe(struct of_device *op,
				const struct of_device_id *match)
{
	struct device_node *dp = op->node;
	unsigned long ver;
	const void *pval;
	int len, portid;
	struct chmc *p;
	int err;

	err = -ENODEV;
	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
	if ((ver >> 32UL) == __JALAPENO_ID ||
	    (ver >> 32UL) == __SERRANO_ID)
		goto out;

	portid = of_getintprop_default(dp, "portid", -1);
	if (portid == -1)
		goto out;

	pval = of_get_property(dp, "memory-layout", &len);
	if (pval && len > sizeof(p->layout_prop)) {
		printk(KERN_ERR PFX "Unexpected memory-layout property "
		       "size %d.\n", len);
		goto out;
	}

	err = -ENOMEM;
	p = kzalloc(sizeof(*p), GFP_KERNEL);
	if (!p) {
		printk(KERN_ERR PFX "Could not allocate struct chmc.\n");
		goto out;
	}

	p->portid = portid;
	p->layout_size = len;
	if (!pval)
		p->layout_size = 0;
	else
		memcpy(&p->layout_prop, pval, len);

	p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
	if (!p->regs) {
		printk(KERN_ERR PFX "Could not map registers.\n");
		goto out_free;
	}

	if (p->layout_size != 0UL) {
		p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1);
		p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2);
		p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3);
		p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4);
		p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL);
	}

	chmc_fetch_decode_regs(p);

	list_add(&p->list, &mctrl_list);

	/* Report the device. */
	printk(KERN_INFO PFX "UltraSPARC-III memory controller at %s [%s]\n",
	       dp->full_name,
	       (p->layout_size ? "ACTIVE" : "INACTIVE"));

	dev_set_drvdata(&op->dev, p);

	err = 0;

out:
	return err;

out_free:
	kfree(p);
	goto out;
}

static int __devexit chmc_remove(struct of_device *op)
{
	struct chmc *p = dev_get_drvdata(&op->dev);

	if (p) {
		list_del(&p->list);
		of_iounmap(&op->resource[0], p->regs, 0x48);
		kfree(p);
	}
	return 0;
}

static struct of_device_id chmc_match[] = {
	{
		.name = "memory-controller",
	},
	{},
};
MODULE_DEVICE_TABLE(of, chmc_match);

static struct of_platform_driver chmc_driver = {
	.name		= "chmc",
	.match_table	= chmc_match,
	.probe		= chmc_probe,
	.remove		= __devexit_p(chmc_remove),
};

static inline bool chmc_platform(void)
{
	if (tlb_type == cheetah || tlb_type == cheetah_plus)
		return true;
	return false;
}

static int __init chmc_init(void)
{
	int ret;

	if (!chmc_platform())
		return -ENODEV;

	ret = register_dimm_printer(chmc_print_dimm);
	if (!ret) {
		ret = of_register_driver(&chmc_driver, &of_bus_type);
		if (ret)
			unregister_dimm_printer(chmc_print_dimm);
	}
	return ret;
}

static void __exit chmc_cleanup(void)
{
	if (chmc_platform()) {
		unregister_dimm_printer(chmc_print_dimm);
		of_unregister_driver(&chmc_driver);
	}
}

module_init(chmc_init);
module_exit(chmc_cleanup);
Commit	Line	Data
b28422e3	1	/* chmc.c: Driver for UltraSPARC-III memory controller.
1da177e4	2	*
b28422e3	3	* Copyright (C) 2001, 2007, 2008 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	*/
	5
	6	#include <linux/module.h>
	7	#include <linux/kernel.h>
	8	#include <linux/types.h>
	9	#include <linux/slab.h>
	10	#include <linux/list.h>
	11	#include <linux/string.h>
	12	#include <linux/sched.h>
	13	#include <linux/smp.h>
	14	#include <linux/errno.h>
	15	#include <linux/init.h>
b28422e3 DM	16	#include <linux/of.h>
b28422e3 DM	17	#include <linux/of_device.h>
1da177e4 LT	18	#include <asm/spitfire.h>
1da177e4 LT	19	#include <asm/chmctrl.h>
b332b8bc	20	#include <asm/cpudata.h>
1da177e4	21	#include <asm/oplib.h>
44bdef5e	22	#include <asm/prom.h>
b28422e3	23	#include <asm/head.h>
1da177e4	24	#include <asm/io.h>
881d021a	25	#include <asm/memctrl.h>
1da177e4	26
b28422e3 DM	27	#define DRV_MODULE_NAME "chmc"
	28	#define PFX DRV_MODULE_NAME ": "
	29	#define DRV_MODULE_VERSION "0.2"
	30
	31	MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
	32	MODULE_DESCRIPTION("UltraSPARC-III memory controller driver");
	33	MODULE_LICENSE("GPL");
	34	MODULE_VERSION(DRV_MODULE_VERSION);
	35
1da177e4 LT	36	#define CHMCTRL_NDGRPS 2
	37	#define CHMCTRL_NDIMMS 4
	38
83ef64b9	39	#define CHMC_DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
1da177e4 LT	40
1da177e4 LT	41	/* OBP memory-layout property format. */
83ef64b9	42	struct chmc_obp_map {
1da177e4 LT	43	unsigned char dimm_map[144];
	44	unsigned char pin_map[576];
	45	};
	46
	47	#define DIMM_LABEL_SZ 8
	48
83ef64b9	49	struct chmc_obp_mem_layout {
1da177e4 LT	50	/* One max 8-byte string label per DIMM. Usually
	51	* this matches the label on the motherboard where
	52	* that DIMM resides.
	53	*/
83ef64b9	54	char dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ];
1da177e4 LT	55
	56	/* If symmetric use map[0], else it is
	57	* asymmetric and map[1] should be used.
	58	*/
83ef64b9	59	char symmetric;
1da177e4	60
83ef64b9	61	struct chmc_obp_map map[2];
1da177e4 LT	62	};
	63
	64	#define CHMCTRL_NBANKS 4
	65
83ef64b9 DM	66	struct chmc_bank_info {
83ef64b9 DM	67	struct chmc *p;
1da177e4 LT	68	int bank_id;
	69
	70	u64 raw_reg;
	71	int valid;
	72	int uk;
	73	int um;
	74	int lk;
	75	int lm;
	76	int interleave;
	77	unsigned long base;
	78	unsigned long size;
	79	};
	80
83ef64b9 DM	81	struct chmc {
	82	struct list_head list;
	83	int portid;
1da177e4	84
83ef64b9 DM	85	struct chmc_obp_mem_layout layout_prop;
83ef64b9 DM	86	int layout_size;
1da177e4	87
83ef64b9	88	void __iomem *regs;
1da177e4	89
83ef64b9 DM	90	u64 timing_control1;
	91	u64 timing_control2;
	92	u64 timing_control3;
	93	u64 timing_control4;
	94	u64 memaddr_control;
1da177e4	95
83ef64b9	96	struct chmc_bank_info logical_banks[CHMCTRL_NBANKS];
1da177e4 LT	97	};
	98
	99	static LIST_HEAD(mctrl_list);
	100
	101	/* Does BANK decode PHYS_ADDR? */
83ef64b9	102	static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr)
1da177e4 LT	103	{
	104	unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
	105	unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;
	106
	107	/* Bank must be enabled to match. */
	108	if (bp->valid == 0)
	109	return 0;
	110
	111	/* Would BANK match upper bits? */
	112	upper_bits ^= bp->um; /* What bits are different? */
	113	upper_bits = ~upper_bits; /* Invert. */
	114	upper_bits \|= bp->uk; /* What bits don't matter for matching? */
	115	upper_bits = ~upper_bits; /* Invert. */
	116
	117	if (upper_bits)
	118	return 0;
	119
	120	/* Would BANK match lower bits? */
	121	lower_bits ^= bp->lm; /* What bits are different? */
	122	lower_bits = ~lower_bits; /* Invert. */
	123	lower_bits \|= bp->lk; /* What bits don't matter for matching? */
	124	lower_bits = ~lower_bits; /* Invert. */
	125
	126	if (lower_bits)
	127	return 0;
	128
	129	/* I always knew you'd be the one. */
	130	return 1;
	131	}
	132
	133	/* Given PHYS_ADDR, search memory controller banks for a match. */
83ef64b9	134	static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr)
1da177e4 LT	135	{
	136	struct list_head *mctrl_head = &mctrl_list;
	137	struct list_head *mctrl_entry = mctrl_head->next;
	138
	139	for (;;) {
83ef64b9	140	struct chmc *p = list_entry(mctrl_entry, struct chmc, list);
1da177e4 LT	141	int bank_no;
	142
	143	if (mctrl_entry == mctrl_head)
	144	break;
	145	mctrl_entry = mctrl_entry->next;
	146
	147	for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
83ef64b9	148	struct chmc_bank_info *bp;
1da177e4	149
83ef64b9 DM	150	bp = &p->logical_banks[bank_no];
83ef64b9 DM	151	if (chmc_bank_match(bp, phys_addr))
1da177e4 LT	152	return bp;
	153	}
	154	}
	155
	156	return NULL;
	157	}
	158
	159	/* This is the main purpose of this driver. */
	160	#define SYNDROME_MIN -1
	161	#define SYNDROME_MAX 144
881d021a DM	162	static int chmc_print_dimm(int syndrome_code,
	163	unsigned long phys_addr,
	164	char *buf, int buflen)
1da177e4	165	{
83ef64b9 DM	166	struct chmc_bank_info *bp;
83ef64b9 DM	167	struct chmc_obp_mem_layout *prop;
1da177e4 LT	168	int bank_in_controller, first_dimm;
1da177e4 LT	169
83ef64b9	170	bp = chmc_find_bank(phys_addr);
1da177e4 LT	171	if (bp == NULL \|\|
	172	syndrome_code < SYNDROME_MIN \|\|
	173	syndrome_code > SYNDROME_MAX) {
	174	buf[0] = '?';
	175	buf[1] = '?';
	176	buf[2] = '?';
	177	buf[3] = '\0';
	178	return 0;
	179	}
	180
83ef64b9	181	prop = &bp->p->layout_prop;
1da177e4 LT	182	bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
	183	first_dimm = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
	184	first_dimm *= CHMCTRL_NDIMMS;
	185
	186	if (syndrome_code != SYNDROME_MIN) {
83ef64b9	187	struct chmc_obp_map *map;
1da177e4 LT	188	int qword, where_in_line, where, map_index, map_offset;
	189	unsigned int map_val;
	190
	191	/* Yaay, single bit error so we can figure out
	192	* the exact dimm.
	193	*/
	194	if (prop->symmetric)
	195	map = &prop->map[0];
	196	else
	197	map = &prop->map[1];
	198
	199	/* Covert syndrome code into the way the bits are
	200	* positioned on the bus.
	201	*/
	202	if (syndrome_code < 144 - 16)
	203	syndrome_code += 16;
	204	else if (syndrome_code < 144)
	205	syndrome_code -= (144 - 7);
	206	else if (syndrome_code < (144 + 3))
	207	syndrome_code -= (144 + 3 - 4);
	208	else
	209	syndrome_code -= 144 + 3;
	210
	211	/* All this magic has to do with how a cache line
	212	* comes over the wire on Safari. A 64-bit line
	213	* comes over in 4 quadword cycles, each of which
	214	* transmit ECC/MTAG info as well as the actual
	215	* data. 144 bits per quadword, 576 total.
	216	*/
	217	#define LINE_SIZE 64
	218	#define LINE_ADDR_MSK (LINE_SIZE - 1)
	219	#define QW_PER_LINE 4
	220	#define QW_BYTES (LINE_SIZE / QW_PER_LINE)
	221	#define QW_BITS 144
	222	#define LAST_BIT (576 - 1)
	223
	224	qword = (phys_addr & LINE_ADDR_MSK) / QW_BYTES;
	225	where_in_line = ((3 - qword) * QW_BITS) + syndrome_code;
	226	where = (LAST_BIT - where_in_line);
	227	map_index = where >> 2;
	228	map_offset = where & 0x3;
	229	map_val = map->dimm_map[map_index];
	230	map_val = ((map_val >> ((3 - map_offset) << 1)) & (2 - 1));
	231
	232	sprintf(buf, "%s, pin %3d",
	233	prop->dimm_labels[first_dimm + map_val],
	234	map->pin_map[where_in_line]);
	235	} else {
	236	int dimm;
	237
	238	/* Multi-bit error, we just dump out all the
	239	* dimm labels associated with this bank.
	240	*/
	241	for (dimm = 0; dimm < CHMCTRL_NDIMMS; dimm++) {
	242	sprintf(buf, "%s ",
	243	prop->dimm_labels[first_dimm + dimm]);
	244	buf += strlen(buf);
	245	}
	246	}
	247	return 0;
	248	}
	249
	250	/* Accessing the registers is slightly complicated. If you want
	251	* to get at the memory controller which is on the same processor
252	* the code is executing, you must use special ASI load/store else
253	* you go through the global mapping.
254	*/
83ef64b9	255	static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset)
1da177e4	256	{
b332b8bc DM	257	unsigned long ret, this_cpu;
	258
	259	preempt_disable();
	260
	261	this_cpu = real_hard_smp_processor_id();
1da177e4	262
83ef64b9	263	if (p->portid == this_cpu) {
1da177e4 LT	264	__asm__ __volatile__("ldxa [%1] %2, %0"
	265	: "=r" (ret)
	266	: "r" (offset), "i" (ASI_MCU_CTRL_REG));
	267	} else {
	268	__asm__ __volatile__("ldxa [%1] %2, %0"
	269	: "=r" (ret)
83ef64b9	270	: "r" (p->regs + offset),
1da177e4 LT	271	"i" (ASI_PHYS_BYPASS_EC_E));
1da177e4 LT	272	}
b332b8bc DM	273
b332b8bc DM	274	preempt_enable();
1da177e4 LT	275
	276	return ret;
	277	}
	278
	279	#if 0 /* currently unused */
83ef64b9	280	static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val)
1da177e4	281	{
83ef64b9	282	if (p->portid == smp_processor_id()) {
1da177e4 LT	283	__asm__ __volatile__("stxa %0, [%1] %2"
	284	: : "r" (val),
	285	"r" (offset), "i" (ASI_MCU_CTRL_REG));
	286	} else {
	287	__asm__ __volatile__("ldxa %0, [%1] %2"
	288	: : "r" (val),
83ef64b9	289	"r" (p->regs + offset),
1da177e4 LT	290	"i" (ASI_PHYS_BYPASS_EC_E));
	291	}
	292	}
	293	#endif
	294
83ef64b9	295	static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val)
1da177e4	296	{
83ef64b9 DM	297	struct chmc_bank_info *bp = &p->logical_banks[which_bank];
	298
	299	bp->p = p;
	300	bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank;
	301	bp->raw_reg = val;
	302	bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
	303	bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
	304	bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
	305	bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
	306	bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
	307
	308	bp->base = (bp->um);
	309	bp->base &= ~(bp->uk);
	310	bp->base <<= PA_UPPER_BITS_SHIFT;
	311
	312	switch(bp->lk) {
1da177e4 LT	313	case 0xf:
1da177e4 LT	314	default:
83ef64b9	315	bp->interleave = 1;
1da177e4 LT	316	break;
	317
	318	case 0xe:
83ef64b9	319	bp->interleave = 2;
1da177e4 LT	320	break;
	321
	322	case 0xc:
83ef64b9	323	bp->interleave = 4;
1da177e4 LT	324	break;
	325
	326	case 0x8:
83ef64b9	327	bp->interleave = 8;
1da177e4 LT	328	break;
	329
	330	case 0x0:
83ef64b9	331	bp->interleave = 16;
1da177e4 LT	332	break;
	333	};
	334
	335	/* UK[10] is reserved, and UK[11] is not set for the SDRAM
	336	* bank size definition.
	337	*/
83ef64b9 DM	338	bp->size = (((unsigned long)bp->uk &
	339	((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
	340	bp->size /= bp->interleave;
1da177e4 LT	341	}
1da177e4 LT	342
83ef64b9	343	static void chmc_fetch_decode_regs(struct chmc *p)
1da177e4	344	{
83ef64b9	345	if (p->layout_size == 0)
1da177e4 LT	346	return;
1da177e4 LT	347
83ef64b9 DM	348	chmc_interpret_one_decode_reg(p, 0,
	349	chmc_read_mcreg(p, CHMCTRL_DECODE1));
	350	chmc_interpret_one_decode_reg(p, 1,
	351	chmc_read_mcreg(p, CHMCTRL_DECODE2));
	352	chmc_interpret_one_decode_reg(p, 2,
	353	chmc_read_mcreg(p, CHMCTRL_DECODE3));
	354	chmc_interpret_one_decode_reg(p, 3,
	355	chmc_read_mcreg(p, CHMCTRL_DECODE4));
1da177e4 LT	356	}
1da177e4 LT	357
b28422e3 DM	358	static int __devinit chmc_probe(struct of_device *op,
b28422e3 DM	359	const struct of_device_id *match)
1da177e4	360	{
b28422e3	361	struct device_node *dp = op->node;
b28422e3	362	unsigned long ver;
6a23acf3	363	const void *pval;
b28422e3	364	int len, portid;
83ef64b9 DM	365	struct chmc *p;
83ef64b9 DM	366	int err;
b28422e3	367
83ef64b9	368	err = -ENODEV;
b28422e3 DM	369	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
	370	if ((ver >> 32UL) == __JALAPENO_ID \|\|
	371	(ver >> 32UL) == __SERRANO_ID)
83ef64b9	372	goto out;
b28422e3 DM	373
b28422e3 DM	374	portid = of_getintprop_default(dp, "portid", -1);
1da177e4	375	if (portid == -1)
83ef64b9	376	goto out;
1da177e4	377
44bdef5e	378	pval = of_get_property(dp, "memory-layout", &len);
83ef64b9 DM	379	if (pval && len > sizeof(p->layout_prop)) {
	380	printk(KERN_ERR PFX "Unexpected memory-layout property "
	381	"size %d.\n", len);
	382	goto out;
	383	}
	384
	385	err = -ENOMEM;
	386	p = kzalloc(sizeof(*p), GFP_KERNEL);
	387	if (!p) {
	388	printk(KERN_ERR PFX "Could not allocate struct chmc.\n");
	389	goto out;
44bdef5e	390	}
1da177e4	391
83ef64b9 DM	392	p->portid = portid;
	393	p->layout_size = len;
	394	if (!pval)
	395	p->layout_size = 0;
	396	else
	397	memcpy(&p->layout_prop, pval, len);
	398
	399	p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
	400	if (!p->regs) {
b28422e3	401	printk(KERN_ERR PFX "Could not map registers.\n");
83ef64b9	402	goto out_free;
b28422e3	403	}
1da177e4	404
83ef64b9 DM	405	if (p->layout_size != 0UL) {
	406	p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1);
	407	p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2);
	408	p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3);
	409	p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4);
	410	p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL);
1da177e4 LT	411	}
1da177e4 LT	412
83ef64b9	413	chmc_fetch_decode_regs(p);
1da177e4	414
83ef64b9	415	list_add(&p->list, &mctrl_list);
1da177e4 LT	416
1da177e4 LT	417	/* Report the device. */
b28422e3	418	printk(KERN_INFO PFX "UltraSPARC-III memory controller at %s [%s]\n",
44bdef5e	419	dp->full_name,
83ef64b9	420	(p->layout_size ? "ACTIVE" : "INACTIVE"));
b28422e3	421
83ef64b9	422	dev_set_drvdata(&op->dev, p);
1da177e4	423
83ef64b9	424	err = 0;
1da177e4	425
83ef64b9 DM	426	out:
	427	return err;
	428
	429	out_free:
	430	kfree(p);
	431	goto out;
1da177e4 LT	432	}
1da177e4 LT	433
b28422e3	434	static int __devexit chmc_remove(struct of_device *op)
1da177e4	435	{
83ef64b9	436	struct chmc *p = dev_get_drvdata(&op->dev);
1da177e4	437
83ef64b9 DM	438	if (p) {
	439	list_del(&p->list);
	440	of_iounmap(&op->resource[0], p->regs, 0x48);
	441	kfree(p);
b28422e3 DM	442	}
	443	return 0;
	444	}
1da177e4	445
b28422e3 DM	446	static struct of_device_id chmc_match[] = {
	447	{
	448	.name = "memory-controller",
	449	},
	450	{},
	451	};
	452	MODULE_DEVICE_TABLE(of, chmc_match);
44bdef5e	453
b28422e3 DM	454	static struct of_platform_driver chmc_driver = {
	455	.name = "chmc",
	456	.match_table = chmc_match,
	457	.probe = chmc_probe,
	458	.remove = __devexit_p(chmc_remove),
	459	};
1da177e4	460
b28422e3 DM	461	static inline bool chmc_platform(void)
	462	{
	463	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	464	return true;
	465	return false;
1da177e4 LT	466	}
1da177e4 LT	467
b28422e3	468	static int __init chmc_init(void)
1da177e4	469	{
881d021a DM	470	int ret;
881d021a DM	471
b28422e3 DM	472	if (!chmc_platform())
b28422e3 DM	473	return -ENODEV;
1da177e4	474
881d021a DM	475	ret = register_dimm_printer(chmc_print_dimm);
	476	if (!ret) {
	477	ret = of_register_driver(&chmc_driver, &of_bus_type);
	478	if (ret)
	479	unregister_dimm_printer(chmc_print_dimm);
	480	}
	481	return ret;
b28422e3	482	}
1da177e4	483
b28422e3 DM	484	static void __exit chmc_cleanup(void)
b28422e3 DM	485	{
881d021a DM	486	if (chmc_platform()) {
881d021a DM	487	unregister_dimm_printer(chmc_print_dimm);
b28422e3	488	of_unregister_driver(&chmc_driver);
881d021a	489	}
1da177e4 LT	490	}
	491
	492	module_init(chmc_init);
	493	module_exit(chmc_cleanup);