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74bf4312 DM |
1 | /* arch/sparc64/mm/tsb.c |
2 | * | |
a3cf5e6b | 3 | * Copyright (C) 2006, 2008 David S. Miller <davem@davemloft.net> |
74bf4312 DM |
4 | */ |
5 | ||
6 | #include <linux/kernel.h> | |
a3cf5e6b | 7 | #include <linux/preempt.h> |
5a0e3ad6 | 8 | #include <linux/slab.h> |
74bf4312 | 9 | #include <asm/page.h> |
98c5584c | 10 | #include <asm/pgtable.h> |
f36391d2 | 11 | #include <asm/mmu_context.h> |
8c7260c0 | 12 | #include <asm/setup.h> |
bd40791e | 13 | #include <asm/tsb.h> |
f36391d2 | 14 | #include <asm/tlb.h> |
9b4006dc | 15 | #include <asm/oplib.h> |
74bf4312 | 16 | |
74bf4312 DM |
17 | extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; |
18 | ||
dcc1e8dd | 19 | static inline unsigned long tsb_hash(unsigned long vaddr, unsigned long hash_shift, unsigned long nentries) |
74bf4312 | 20 | { |
dcc1e8dd | 21 | vaddr >>= hash_shift; |
98c5584c | 22 | return vaddr & (nentries - 1); |
74bf4312 DM |
23 | } |
24 | ||
8b234274 | 25 | static inline int tag_compare(unsigned long tag, unsigned long vaddr) |
74bf4312 | 26 | { |
8b234274 | 27 | return (tag == (vaddr >> 22)); |
74bf4312 DM |
28 | } |
29 | ||
30 | /* TSB flushes need only occur on the processor initiating the address | |
31 | * space modification, not on each cpu the address space has run on. | |
32 | * Only the TLB flush needs that treatment. | |
33 | */ | |
34 | ||
35 | void flush_tsb_kernel_range(unsigned long start, unsigned long end) | |
36 | { | |
37 | unsigned long v; | |
38 | ||
39 | for (v = start; v < end; v += PAGE_SIZE) { | |
dcc1e8dd DM |
40 | unsigned long hash = tsb_hash(v, PAGE_SHIFT, |
41 | KERNEL_TSB_NENTRIES); | |
98c5584c | 42 | struct tsb *ent = &swapper_tsb[hash]; |
74bf4312 | 43 | |
293666b7 | 44 | if (tag_compare(ent->tag, v)) |
8b234274 | 45 | ent->tag = (1UL << TSB_TAG_INVALID_BIT); |
74bf4312 DM |
46 | } |
47 | } | |
48 | ||
f36391d2 DM |
49 | static void __flush_tsb_one_entry(unsigned long tsb, unsigned long v, |
50 | unsigned long hash_shift, | |
51 | unsigned long nentries) | |
74bf4312 | 52 | { |
f36391d2 | 53 | unsigned long tag, ent, hash; |
7a1ac526 | 54 | |
f36391d2 DM |
55 | v &= ~0x1UL; |
56 | hash = tsb_hash(v, hash_shift, nentries); | |
57 | ent = tsb + (hash * sizeof(struct tsb)); | |
58 | tag = (v >> 22UL); | |
74bf4312 | 59 | |
f36391d2 DM |
60 | tsb_flush(ent, tag); |
61 | } | |
74bf4312 | 62 | |
f36391d2 DM |
63 | static void __flush_tsb_one(struct tlb_batch *tb, unsigned long hash_shift, |
64 | unsigned long tsb, unsigned long nentries) | |
65 | { | |
66 | unsigned long i; | |
517af332 | 67 | |
f36391d2 DM |
68 | for (i = 0; i < tb->tlb_nr; i++) |
69 | __flush_tsb_one_entry(tsb, tb->vaddrs[i], hash_shift, nentries); | |
dcc1e8dd DM |
70 | } |
71 | ||
90f08e39 | 72 | void flush_tsb_user(struct tlb_batch *tb) |
dcc1e8dd | 73 | { |
90f08e39 | 74 | struct mm_struct *mm = tb->mm; |
dcc1e8dd DM |
75 | unsigned long nentries, base, flags; |
76 | ||
77 | spin_lock_irqsave(&mm->context.lock, flags); | |
7a1ac526 | 78 | |
dcc1e8dd DM |
79 | base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb; |
80 | nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries; | |
81 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) | |
82 | base = __pa(base); | |
90f08e39 | 83 | __flush_tsb_one(tb, PAGE_SHIFT, base, nentries); |
dcc1e8dd | 84 | |
9e695d2e | 85 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
86 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb) { |
87 | base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb; | |
88 | nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries; | |
89 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) | |
90 | base = __pa(base); | |
37b3a8ff | 91 | __flush_tsb_one(tb, REAL_HPAGE_SHIFT, base, nentries); |
dcc1e8dd DM |
92 | } |
93 | #endif | |
7a1ac526 | 94 | spin_unlock_irqrestore(&mm->context.lock, flags); |
74bf4312 | 95 | } |
09f94287 | 96 | |
f36391d2 DM |
97 | void flush_tsb_user_page(struct mm_struct *mm, unsigned long vaddr) |
98 | { | |
99 | unsigned long nentries, base, flags; | |
100 | ||
101 | spin_lock_irqsave(&mm->context.lock, flags); | |
102 | ||
103 | base = (unsigned long) mm->context.tsb_block[MM_TSB_BASE].tsb; | |
104 | nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries; | |
105 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) | |
106 | base = __pa(base); | |
107 | __flush_tsb_one_entry(base, vaddr, PAGE_SHIFT, nentries); | |
108 | ||
109 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) | |
110 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb) { | |
111 | base = (unsigned long) mm->context.tsb_block[MM_TSB_HUGE].tsb; | |
112 | nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries; | |
113 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) | |
114 | base = __pa(base); | |
37b3a8ff | 115 | __flush_tsb_one_entry(base, vaddr, REAL_HPAGE_SHIFT, nentries); |
f36391d2 DM |
116 | } |
117 | #endif | |
118 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
119 | } | |
120 | ||
dcc1e8dd DM |
121 | #define HV_PGSZ_IDX_BASE HV_PGSZ_IDX_8K |
122 | #define HV_PGSZ_MASK_BASE HV_PGSZ_MASK_8K | |
dcc1e8dd | 123 | |
9e695d2e | 124 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
125 | #define HV_PGSZ_IDX_HUGE HV_PGSZ_IDX_4MB |
126 | #define HV_PGSZ_MASK_HUGE HV_PGSZ_MASK_4MB | |
dcc1e8dd DM |
127 | #endif |
128 | ||
129 | static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_idx, unsigned long tsb_bytes) | |
98c5584c DM |
130 | { |
131 | unsigned long tsb_reg, base, tsb_paddr; | |
132 | unsigned long page_sz, tte; | |
133 | ||
dcc1e8dd DM |
134 | mm->context.tsb_block[tsb_idx].tsb_nentries = |
135 | tsb_bytes / sizeof(struct tsb); | |
98c5584c | 136 | |
b18eb2d7 DM |
137 | switch (tsb_idx) { |
138 | case MM_TSB_BASE: | |
139 | base = TSBMAP_8K_BASE; | |
140 | break; | |
141 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) | |
142 | case MM_TSB_HUGE: | |
143 | base = TSBMAP_4M_BASE; | |
144 | break; | |
145 | #endif | |
146 | default: | |
147 | BUG(); | |
148 | } | |
149 | ||
c4bce90e | 150 | tte = pgprot_val(PAGE_KERNEL_LOCKED); |
dcc1e8dd | 151 | tsb_paddr = __pa(mm->context.tsb_block[tsb_idx].tsb); |
517af332 | 152 | BUG_ON(tsb_paddr & (tsb_bytes - 1UL)); |
98c5584c DM |
153 | |
154 | /* Use the smallest page size that can map the whole TSB | |
155 | * in one TLB entry. | |
156 | */ | |
157 | switch (tsb_bytes) { | |
158 | case 8192 << 0: | |
159 | tsb_reg = 0x0UL; | |
160 | #ifdef DCACHE_ALIASING_POSSIBLE | |
161 | base += (tsb_paddr & 8192); | |
162 | #endif | |
98c5584c DM |
163 | page_sz = 8192; |
164 | break; | |
165 | ||
166 | case 8192 << 1: | |
167 | tsb_reg = 0x1UL; | |
98c5584c DM |
168 | page_sz = 64 * 1024; |
169 | break; | |
170 | ||
171 | case 8192 << 2: | |
172 | tsb_reg = 0x2UL; | |
98c5584c DM |
173 | page_sz = 64 * 1024; |
174 | break; | |
175 | ||
176 | case 8192 << 3: | |
177 | tsb_reg = 0x3UL; | |
98c5584c DM |
178 | page_sz = 64 * 1024; |
179 | break; | |
180 | ||
181 | case 8192 << 4: | |
182 | tsb_reg = 0x4UL; | |
98c5584c DM |
183 | page_sz = 512 * 1024; |
184 | break; | |
185 | ||
186 | case 8192 << 5: | |
187 | tsb_reg = 0x5UL; | |
98c5584c DM |
188 | page_sz = 512 * 1024; |
189 | break; | |
190 | ||
191 | case 8192 << 6: | |
192 | tsb_reg = 0x6UL; | |
98c5584c DM |
193 | page_sz = 512 * 1024; |
194 | break; | |
195 | ||
196 | case 8192 << 7: | |
197 | tsb_reg = 0x7UL; | |
98c5584c DM |
198 | page_sz = 4 * 1024 * 1024; |
199 | break; | |
bd40791e DM |
200 | |
201 | default: | |
7e5766fa DM |
202 | printk(KERN_ERR "TSB[%s:%d]: Impossible TSB size %lu, killing process.\n", |
203 | current->comm, current->pid, tsb_bytes); | |
204 | do_exit(SIGSEGV); | |
6cb79b3f | 205 | } |
c4bce90e | 206 | tte |= pte_sz_bits(page_sz); |
98c5584c | 207 | |
618e9ed9 | 208 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) { |
517af332 DM |
209 | /* Physical mapping, no locked TLB entry for TSB. */ |
210 | tsb_reg |= tsb_paddr; | |
211 | ||
dcc1e8dd DM |
212 | mm->context.tsb_block[tsb_idx].tsb_reg_val = tsb_reg; |
213 | mm->context.tsb_block[tsb_idx].tsb_map_vaddr = 0; | |
214 | mm->context.tsb_block[tsb_idx].tsb_map_pte = 0; | |
517af332 DM |
215 | } else { |
216 | tsb_reg |= base; | |
217 | tsb_reg |= (tsb_paddr & (page_sz - 1UL)); | |
218 | tte |= (tsb_paddr & ~(page_sz - 1UL)); | |
219 | ||
dcc1e8dd DM |
220 | mm->context.tsb_block[tsb_idx].tsb_reg_val = tsb_reg; |
221 | mm->context.tsb_block[tsb_idx].tsb_map_vaddr = base; | |
222 | mm->context.tsb_block[tsb_idx].tsb_map_pte = tte; | |
517af332 | 223 | } |
98c5584c | 224 | |
618e9ed9 DM |
225 | /* Setup the Hypervisor TSB descriptor. */ |
226 | if (tlb_type == hypervisor) { | |
dcc1e8dd | 227 | struct hv_tsb_descr *hp = &mm->context.tsb_descr[tsb_idx]; |
618e9ed9 | 228 | |
dcc1e8dd DM |
229 | switch (tsb_idx) { |
230 | case MM_TSB_BASE: | |
231 | hp->pgsz_idx = HV_PGSZ_IDX_BASE; | |
618e9ed9 | 232 | break; |
9e695d2e | 233 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
234 | case MM_TSB_HUGE: |
235 | hp->pgsz_idx = HV_PGSZ_IDX_HUGE; | |
618e9ed9 | 236 | break; |
dcc1e8dd DM |
237 | #endif |
238 | default: | |
239 | BUG(); | |
6cb79b3f | 240 | } |
618e9ed9 DM |
241 | hp->assoc = 1; |
242 | hp->num_ttes = tsb_bytes / 16; | |
243 | hp->ctx_idx = 0; | |
dcc1e8dd DM |
244 | switch (tsb_idx) { |
245 | case MM_TSB_BASE: | |
246 | hp->pgsz_mask = HV_PGSZ_MASK_BASE; | |
618e9ed9 | 247 | break; |
9e695d2e | 248 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
249 | case MM_TSB_HUGE: |
250 | hp->pgsz_mask = HV_PGSZ_MASK_HUGE; | |
618e9ed9 | 251 | break; |
dcc1e8dd DM |
252 | #endif |
253 | default: | |
254 | BUG(); | |
6cb79b3f | 255 | } |
618e9ed9 DM |
256 | hp->tsb_base = tsb_paddr; |
257 | hp->resv = 0; | |
258 | } | |
98c5584c DM |
259 | } |
260 | ||
4dedbf8d DM |
261 | struct kmem_cache *pgtable_cache __read_mostly; |
262 | ||
e18b890b | 263 | static struct kmem_cache *tsb_caches[8] __read_mostly; |
9b4006dc DM |
264 | |
265 | static const char *tsb_cache_names[8] = { | |
266 | "tsb_8KB", | |
267 | "tsb_16KB", | |
268 | "tsb_32KB", | |
269 | "tsb_64KB", | |
270 | "tsb_128KB", | |
271 | "tsb_256KB", | |
272 | "tsb_512KB", | |
273 | "tsb_1MB", | |
274 | }; | |
275 | ||
3a2cba99 | 276 | void __init pgtable_cache_init(void) |
9b4006dc DM |
277 | { |
278 | unsigned long i; | |
279 | ||
4dedbf8d DM |
280 | pgtable_cache = kmem_cache_create("pgtable_cache", |
281 | PAGE_SIZE, PAGE_SIZE, | |
282 | 0, | |
283 | _clear_page); | |
284 | if (!pgtable_cache) { | |
285 | prom_printf("pgtable_cache_init(): Could not create!\n"); | |
286 | prom_halt(); | |
287 | } | |
288 | ||
151b628f | 289 | for (i = 0; i < ARRAY_SIZE(tsb_cache_names); i++) { |
9b4006dc DM |
290 | unsigned long size = 8192 << i; |
291 | const char *name = tsb_cache_names[i]; | |
292 | ||
293 | tsb_caches[i] = kmem_cache_create(name, | |
294 | size, size, | |
20c2df83 | 295 | 0, NULL); |
9b4006dc DM |
296 | if (!tsb_caches[i]) { |
297 | prom_printf("Could not create %s cache\n", name); | |
298 | prom_halt(); | |
299 | } | |
300 | } | |
301 | } | |
302 | ||
0871420f DM |
303 | int sysctl_tsb_ratio = -2; |
304 | ||
305 | static unsigned long tsb_size_to_rss_limit(unsigned long new_size) | |
306 | { | |
307 | unsigned long num_ents = (new_size / sizeof(struct tsb)); | |
308 | ||
309 | if (sysctl_tsb_ratio < 0) | |
310 | return num_ents - (num_ents >> -sysctl_tsb_ratio); | |
311 | else | |
312 | return num_ents + (num_ents >> sysctl_tsb_ratio); | |
313 | } | |
314 | ||
dcc1e8dd DM |
315 | /* When the RSS of an address space exceeds tsb_rss_limit for a TSB, |
316 | * do_sparc64_fault() invokes this routine to try and grow it. | |
7a1ac526 | 317 | * |
bd40791e | 318 | * When we reach the maximum TSB size supported, we stick ~0UL into |
dcc1e8dd | 319 | * tsb_rss_limit for that TSB so the grow checks in do_sparc64_fault() |
bd40791e DM |
320 | * will not trigger any longer. |
321 | * | |
322 | * The TSB can be anywhere from 8K to 1MB in size, in increasing powers | |
323 | * of two. The TSB must be aligned to it's size, so f.e. a 512K TSB | |
b52439c2 DM |
324 | * must be 512K aligned. It also must be physically contiguous, so we |
325 | * cannot use vmalloc(). | |
bd40791e DM |
326 | * |
327 | * The idea here is to grow the TSB when the RSS of the process approaches | |
328 | * the number of entries that the current TSB can hold at once. Currently, | |
329 | * we trigger when the RSS hits 3/4 of the TSB capacity. | |
330 | */ | |
dcc1e8dd | 331 | void tsb_grow(struct mm_struct *mm, unsigned long tsb_index, unsigned long rss) |
bd40791e DM |
332 | { |
333 | unsigned long max_tsb_size = 1 * 1024 * 1024; | |
9b4006dc | 334 | unsigned long new_size, old_size, flags; |
7a1ac526 | 335 | struct tsb *old_tsb, *new_tsb; |
9b4006dc DM |
336 | unsigned long new_cache_index, old_cache_index; |
337 | unsigned long new_rss_limit; | |
b52439c2 | 338 | gfp_t gfp_flags; |
bd40791e DM |
339 | |
340 | if (max_tsb_size > (PAGE_SIZE << MAX_ORDER)) | |
341 | max_tsb_size = (PAGE_SIZE << MAX_ORDER); | |
342 | ||
9b4006dc DM |
343 | new_cache_index = 0; |
344 | for (new_size = 8192; new_size < max_tsb_size; new_size <<= 1UL) { | |
0871420f DM |
345 | new_rss_limit = tsb_size_to_rss_limit(new_size); |
346 | if (new_rss_limit > rss) | |
bd40791e | 347 | break; |
9b4006dc | 348 | new_cache_index++; |
bd40791e DM |
349 | } |
350 | ||
9b4006dc | 351 | if (new_size == max_tsb_size) |
b52439c2 | 352 | new_rss_limit = ~0UL; |
b52439c2 | 353 | |
9b4006dc | 354 | retry_tsb_alloc: |
b52439c2 | 355 | gfp_flags = GFP_KERNEL; |
9b4006dc | 356 | if (new_size > (PAGE_SIZE * 2)) |
a55ee1ff | 357 | gfp_flags |= __GFP_NOWARN | __GFP_NORETRY; |
b52439c2 | 358 | |
1f261ef5 DM |
359 | new_tsb = kmem_cache_alloc_node(tsb_caches[new_cache_index], |
360 | gfp_flags, numa_node_id()); | |
9b4006dc | 361 | if (unlikely(!new_tsb)) { |
b52439c2 DM |
362 | /* Not being able to fork due to a high-order TSB |
363 | * allocation failure is very bad behavior. Just back | |
364 | * down to a 0-order allocation and force no TSB | |
365 | * growing for this address space. | |
366 | */ | |
dcc1e8dd DM |
367 | if (mm->context.tsb_block[tsb_index].tsb == NULL && |
368 | new_cache_index > 0) { | |
9b4006dc DM |
369 | new_cache_index = 0; |
370 | new_size = 8192; | |
b52439c2 | 371 | new_rss_limit = ~0UL; |
9b4006dc | 372 | goto retry_tsb_alloc; |
b52439c2 DM |
373 | } |
374 | ||
375 | /* If we failed on a TSB grow, we are under serious | |
376 | * memory pressure so don't try to grow any more. | |
377 | */ | |
dcc1e8dd DM |
378 | if (mm->context.tsb_block[tsb_index].tsb != NULL) |
379 | mm->context.tsb_block[tsb_index].tsb_rss_limit = ~0UL; | |
bd40791e | 380 | return; |
b52439c2 | 381 | } |
bd40791e | 382 | |
8b234274 | 383 | /* Mark all tags as invalid. */ |
bb8646d8 | 384 | tsb_init(new_tsb, new_size); |
7a1ac526 DM |
385 | |
386 | /* Ok, we are about to commit the changes. If we are | |
387 | * growing an existing TSB the locking is very tricky, | |
388 | * so WATCH OUT! | |
389 | * | |
390 | * We have to hold mm->context.lock while committing to the | |
391 | * new TSB, this synchronizes us with processors in | |
392 | * flush_tsb_user() and switch_mm() for this address space. | |
393 | * | |
394 | * But even with that lock held, processors run asynchronously | |
395 | * accessing the old TSB via TLB miss handling. This is OK | |
396 | * because those actions are just propagating state from the | |
397 | * Linux page tables into the TSB, page table mappings are not | |
398 | * being changed. If a real fault occurs, the processor will | |
399 | * synchronize with us when it hits flush_tsb_user(), this is | |
400 | * also true for the case where vmscan is modifying the page | |
401 | * tables. The only thing we need to be careful with is to | |
402 | * skip any locked TSB entries during copy_tsb(). | |
403 | * | |
404 | * When we finish committing to the new TSB, we have to drop | |
405 | * the lock and ask all other cpus running this address space | |
406 | * to run tsb_context_switch() to see the new TSB table. | |
407 | */ | |
408 | spin_lock_irqsave(&mm->context.lock, flags); | |
409 | ||
dcc1e8dd DM |
410 | old_tsb = mm->context.tsb_block[tsb_index].tsb; |
411 | old_cache_index = | |
412 | (mm->context.tsb_block[tsb_index].tsb_reg_val & 0x7UL); | |
413 | old_size = (mm->context.tsb_block[tsb_index].tsb_nentries * | |
414 | sizeof(struct tsb)); | |
7a1ac526 | 415 | |
9b4006dc | 416 | |
7a1ac526 DM |
417 | /* Handle multiple threads trying to grow the TSB at the same time. |
418 | * One will get in here first, and bump the size and the RSS limit. | |
419 | * The others will get in here next and hit this check. | |
420 | */ | |
dcc1e8dd DM |
421 | if (unlikely(old_tsb && |
422 | (rss < mm->context.tsb_block[tsb_index].tsb_rss_limit))) { | |
7a1ac526 DM |
423 | spin_unlock_irqrestore(&mm->context.lock, flags); |
424 | ||
9b4006dc | 425 | kmem_cache_free(tsb_caches[new_cache_index], new_tsb); |
7a1ac526 DM |
426 | return; |
427 | } | |
8b234274 | 428 | |
dcc1e8dd | 429 | mm->context.tsb_block[tsb_index].tsb_rss_limit = new_rss_limit; |
bd40791e | 430 | |
7a1ac526 DM |
431 | if (old_tsb) { |
432 | extern void copy_tsb(unsigned long old_tsb_base, | |
433 | unsigned long old_tsb_size, | |
434 | unsigned long new_tsb_base, | |
435 | unsigned long new_tsb_size); | |
436 | unsigned long old_tsb_base = (unsigned long) old_tsb; | |
437 | unsigned long new_tsb_base = (unsigned long) new_tsb; | |
438 | ||
439 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) { | |
440 | old_tsb_base = __pa(old_tsb_base); | |
441 | new_tsb_base = __pa(new_tsb_base); | |
442 | } | |
9b4006dc | 443 | copy_tsb(old_tsb_base, old_size, new_tsb_base, new_size); |
7a1ac526 | 444 | } |
bd40791e | 445 | |
dcc1e8dd DM |
446 | mm->context.tsb_block[tsb_index].tsb = new_tsb; |
447 | setup_tsb_params(mm, tsb_index, new_size); | |
bd40791e | 448 | |
7a1ac526 DM |
449 | spin_unlock_irqrestore(&mm->context.lock, flags); |
450 | ||
bd40791e DM |
451 | /* If old_tsb is NULL, we're being invoked for the first time |
452 | * from init_new_context(). | |
453 | */ | |
454 | if (old_tsb) { | |
7a1ac526 | 455 | /* Reload it on the local cpu. */ |
bd40791e DM |
456 | tsb_context_switch(mm); |
457 | ||
7a1ac526 | 458 | /* Now force other processors to do the same. */ |
a3cf5e6b | 459 | preempt_disable(); |
7a1ac526 | 460 | smp_tsb_sync(mm); |
a3cf5e6b | 461 | preempt_enable(); |
7a1ac526 DM |
462 | |
463 | /* Now it is safe to free the old tsb. */ | |
9b4006dc | 464 | kmem_cache_free(tsb_caches[old_cache_index], old_tsb); |
bd40791e DM |
465 | } |
466 | } | |
467 | ||
09f94287 DM |
468 | int init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
469 | { | |
9e695d2e | 470 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
471 | unsigned long huge_pte_count; |
472 | #endif | |
473 | unsigned int i; | |
474 | ||
a77754b4 | 475 | spin_lock_init(&mm->context.lock); |
09f94287 DM |
476 | |
477 | mm->context.sparc64_ctx_val = 0UL; | |
09f94287 | 478 | |
9e695d2e | 479 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
480 | /* We reset it to zero because the fork() page copying |
481 | * will re-increment the counters as the parent PTEs are | |
482 | * copied into the child address space. | |
483 | */ | |
484 | huge_pte_count = mm->context.huge_pte_count; | |
485 | mm->context.huge_pte_count = 0; | |
486 | #endif | |
487 | ||
bd40791e DM |
488 | /* copy_mm() copies over the parent's mm_struct before calling |
489 | * us, so we need to zero out the TSB pointer or else tsb_grow() | |
490 | * will be confused and think there is an older TSB to free up. | |
491 | */ | |
dcc1e8dd DM |
492 | for (i = 0; i < MM_NUM_TSBS; i++) |
493 | mm->context.tsb_block[i].tsb = NULL; | |
7a1ac526 DM |
494 | |
495 | /* If this is fork, inherit the parent's TSB size. We would | |
496 | * grow it to that size on the first page fault anyways. | |
497 | */ | |
dcc1e8dd | 498 | tsb_grow(mm, MM_TSB_BASE, get_mm_rss(mm)); |
bd40791e | 499 | |
9e695d2e | 500 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
dcc1e8dd DM |
501 | if (unlikely(huge_pte_count)) |
502 | tsb_grow(mm, MM_TSB_HUGE, huge_pte_count); | |
503 | #endif | |
504 | ||
505 | if (unlikely(!mm->context.tsb_block[MM_TSB_BASE].tsb)) | |
bd40791e | 506 | return -ENOMEM; |
09f94287 DM |
507 | |
508 | return 0; | |
509 | } | |
510 | ||
dcc1e8dd | 511 | static void tsb_destroy_one(struct tsb_config *tp) |
09f94287 | 512 | { |
dcc1e8dd | 513 | unsigned long cache_index; |
bd40791e | 514 | |
dcc1e8dd DM |
515 | if (!tp->tsb) |
516 | return; | |
517 | cache_index = tp->tsb_reg_val & 0x7UL; | |
518 | kmem_cache_free(tsb_caches[cache_index], tp->tsb); | |
519 | tp->tsb = NULL; | |
520 | tp->tsb_reg_val = 0UL; | |
521 | } | |
98c5584c | 522 | |
dcc1e8dd DM |
523 | void destroy_context(struct mm_struct *mm) |
524 | { | |
525 | unsigned long flags, i; | |
526 | ||
527 | for (i = 0; i < MM_NUM_TSBS; i++) | |
528 | tsb_destroy_one(&mm->context.tsb_block[i]); | |
09f94287 | 529 | |
77b838fa | 530 | spin_lock_irqsave(&ctx_alloc_lock, flags); |
09f94287 DM |
531 | |
532 | if (CTX_VALID(mm->context)) { | |
533 | unsigned long nr = CTX_NRBITS(mm->context); | |
534 | mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63)); | |
535 | } | |
536 | ||
77b838fa | 537 | spin_unlock_irqrestore(&ctx_alloc_lock, flags); |
09f94287 | 538 | } |