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sparc32: Pass -mcpu=v7 explicitly to gcc.
[linux-block.git] / arch / sparc / mm / srmmu.c
CommitLineData
1da177e4
LT		 1/*
2 * srmmu.c: SRMMU specific routines for memory management.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
9 */
10
1da177e4
LT		 11#include <linux/kernel.h>
12#include <linux/mm.h>
1da177e4
LT		 13#include <linux/vmalloc.h>
14#include <linux/pagemap.h>
15#include <linux/init.h>
16#include <linux/spinlock.h>
17#include <linux/bootmem.h>
18#include <linux/fs.h>
19#include <linux/seq_file.h>
1eeb66a1 20#include <linux/kdebug.h>
949e8274 21#include <linux/log2.h>
5a0e3ad6 22#include <linux/gfp.h>
1da177e4
LT		 23
24#include <asm/bitext.h>
25#include <asm/page.h>
26#include <asm/pgalloc.h>
27#include <asm/pgtable.h>
28#include <asm/io.h>
1da177e4
LT		 29#include <asm/vaddrs.h>
30#include <asm/traps.h>
31#include <asm/smp.h>
32#include <asm/mbus.h>
33#include <asm/cache.h>
34#include <asm/oplib.h>
1da177e4
LT		 35#include <asm/asi.h>
36#include <asm/msi.h>
1da177e4
LT		 37#include <asm/mmu_context.h>
38#include <asm/io-unit.h>
39#include <asm/cacheflush.h>
40#include <asm/tlbflush.h>
41
42/* Now the cpu specific definitions. */
43#include <asm/viking.h>
44#include <asm/mxcc.h>
45#include <asm/ross.h>
46#include <asm/tsunami.h>
47#include <asm/swift.h>
48#include <asm/turbosparc.h>
75d9e346 49#include <asm/leon.h>
1da177e4
LT		 50
51#include <asm/btfixup.h>
52
53enum mbus_module srmmu_modtype;
50215d65 54static unsigned int hwbug_bitmask;
1da177e4
LT		 55int vac_cache_size;
56int vac_line_size;
57
a3c5c663
SR		 58struct ctx_list *ctx_list_pool;
59struct ctx_list ctx_free;
60struct ctx_list ctx_used;
61
1da177e4
LT		 62extern struct resource sparc_iomap;
63
64extern unsigned long last_valid_pfn;
65
50215d65 66static pgd_t *srmmu_swapper_pg_dir;
1da177e4
LT		 67
68#ifdef CONFIG_SMP
69#define FLUSH_BEGIN(mm)
70#define FLUSH_END
71#else
72#define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
73#define FLUSH_END }
74#endif
75
76BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
77#define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
78
79int flush_page_for_dma_global = 1;
80
81#ifdef CONFIG_SMP
82BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
83#define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
84#endif
85
86char *srmmu_name;
87
88ctxd_t *srmmu_ctx_table_phys;
50215d65 89static ctxd_t *srmmu_context_table;
1da177e4
LT		 90
91int viking_mxcc_present;
92static DEFINE_SPINLOCK(srmmu_context_spinlock);
93
50215d65 94static int is_hypersparc;
1da177e4 95
50215d65 96static int srmmu_cache_pagetables;
1da177e4
LT		 97
98/* these will be initialized in srmmu_nocache_calcsize() */
50215d65
AB		 99static unsigned long srmmu_nocache_size;
100static unsigned long srmmu_nocache_end;
1da177e4
LT		 101
102/* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
103#define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
104
105/* The context table is a nocache user with the biggest alignment needs. */
106#define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
107
108void *srmmu_nocache_pool;
109void *srmmu_nocache_bitmap;
110static struct bit_map srmmu_nocache_map;
111
1da177e4
LT		 112static inline unsigned long srmmu_pgd_page(pgd_t pgd)
113{ return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
114
115
116static inline int srmmu_pte_none(pte_t pte)
117{ return !(pte_val(pte) & 0xFFFFFFF); }
118
1da177e4
LT		 119static inline int srmmu_pmd_none(pmd_t pmd)
120{ return !(pmd_val(pmd) & 0xFFFFFFF); }
121
1da177e4
LT		 122static inline pte_t srmmu_pte_wrprotect(pte_t pte)
123{ return __pte(pte_val(pte) & ~SRMMU_WRITE);}
124
125static inline pte_t srmmu_pte_mkclean(pte_t pte)
126{ return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
127
128static inline pte_t srmmu_pte_mkold(pte_t pte)
129{ return __pte(pte_val(pte) & ~SRMMU_REF);}
130
1da177e4
LT		 131/* XXX should we hyper_flush_whole_icache here - Anton */
132static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
62875cff 133{ set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
1da177e4
LT		 134
135static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
62875cff 136{ set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
1da177e4
LT		 137
138static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
139{
140 unsigned long ptp; /* Physical address, shifted right by 4 */
141 int i;
142
143 ptp = __nocache_pa((unsigned long) ptep) >> 4;
144 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
62875cff 145 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
1da177e4
LT		 146 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
147 }
148}
149
150static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
151{
152 unsigned long ptp; /* Physical address, shifted right by 4 */
153 int i;
154
155 ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */
156 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
62875cff 157 set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
1da177e4
LT		 158 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
159 }
160}
161
162static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
163{ return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
164
165/* to find an entry in a top-level page table... */
3115624e 166static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
1da177e4
LT		 167{ return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
168
169/* Find an entry in the second-level page table.. */
170static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
171{
172 return (pmd_t *) srmmu_pgd_page(*dir) +
173 ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
174}
175
176/* Find an entry in the third-level page table.. */
177static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
178{
179 void *pte;
180
181 pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
182 return (pte_t *) pte +
183 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
184}
185
186static unsigned long srmmu_swp_type(swp_entry_t entry)
187{
188 return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
189}
190
191static unsigned long srmmu_swp_offset(swp_entry_t entry)
192{
193 return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
194}
195
196static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
197{
198 return (swp_entry_t) {
199 (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
200 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
201}
202
203/*
204 * size: bytes to allocate in the nocache area.
205 * align: bytes, number to align at.
206 * Returns the virtual address of the allocated area.
207 */
208static unsigned long __srmmu_get_nocache(int size, int align)
209{
210 int offset;
211
212 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
213 printk("Size 0x%x too small for nocache request\n", size);
214 size = SRMMU_NOCACHE_BITMAP_SHIFT;
215 }
216 if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
217 printk("Size 0x%x unaligned int nocache request\n", size);
218 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
219 }
220 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
221
222 offset = bit_map_string_get(&srmmu_nocache_map,
223 size >> SRMMU_NOCACHE_BITMAP_SHIFT,
224 align >> SRMMU_NOCACHE_BITMAP_SHIFT);
225 if (offset == -1) {
226 printk("srmmu: out of nocache %d: %d/%d\n",
227 size, (int) srmmu_nocache_size,
228 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
229 return 0;
230 }
231
232 return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
233}
234
50215d65 235static unsigned long srmmu_get_nocache(int size, int align)
1da177e4
LT		 236{
237 unsigned long tmp;
238
239 tmp = __srmmu_get_nocache(size, align);
240
241 if (tmp)
242 memset((void *)tmp, 0, size);
243
244 return tmp;
245}
246
50215d65 247static void srmmu_free_nocache(unsigned long vaddr, int size)
1da177e4
LT		 248{
249 int offset;
250
251 if (vaddr < SRMMU_NOCACHE_VADDR) {
252 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
253 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
254 BUG();
255 }
256 if (vaddr+size > srmmu_nocache_end) {
257 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
258 vaddr, srmmu_nocache_end);
259 BUG();
260 }
949e8274 261 if (!is_power_of_2(size)) {
1da177e4
LT		 262 printk("Size 0x%x is not a power of 2\n", size);
263 BUG();
264 }
265 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
266 printk("Size 0x%x is too small\n", size);
267 BUG();
268 }
269 if (vaddr & (size-1)) {
270 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
271 BUG();
272 }
273
274 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
275 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
276
277 bit_map_clear(&srmmu_nocache_map, offset, size);
278}
279
50215d65
AB		 280static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
281 unsigned long end);
1da177e4
LT		 282
283extern unsigned long probe_memory(void); /* in fault.c */
284
285/*
286 * Reserve nocache dynamically proportionally to the amount of
287 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
288 */
50215d65 289static void srmmu_nocache_calcsize(void)
1da177e4
LT		 290{
291 unsigned long sysmemavail = probe_memory() / 1024;
292 int srmmu_nocache_npages;
293
294 srmmu_nocache_npages =
295 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
296
297 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
298 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
299 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
300 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
301
302 /* anything above 1280 blows up */
303 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
304 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
305
306 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
307 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
308}
309
50215d65 310static void __init srmmu_nocache_init(void)
1da177e4
LT		 311{
312 unsigned int bitmap_bits;
313 pgd_t *pgd;
314 pmd_t *pmd;
315 pte_t *pte;
316 unsigned long paddr, vaddr;
317 unsigned long pteval;
318
319 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
320
321 srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
322 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
323 memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
324
325 srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
326 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
327
328 srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
329 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
330 init_mm.pgd = srmmu_swapper_pg_dir;
331
332 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
333
334 paddr = __pa((unsigned long)srmmu_nocache_pool);
335 vaddr = SRMMU_NOCACHE_VADDR;
336
337 while (vaddr < srmmu_nocache_end) {
338 pgd = pgd_offset_k(vaddr);
339 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
340 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
341
342 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
343
344 if (srmmu_cache_pagetables)
345 pteval |= SRMMU_CACHE;
346
62875cff 347 set_pte(__nocache_fix(pte), __pte(pteval));
1da177e4
LT		 348
349 vaddr += PAGE_SIZE;
350 paddr += PAGE_SIZE;
351 }
352
353 flush_cache_all();
354 flush_tlb_all();
355}
356
357static inline pgd_t *srmmu_get_pgd_fast(void)
358{
359 pgd_t *pgd = NULL;
360
361 pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
362 if (pgd) {
363 pgd_t *init = pgd_offset_k(0);
364 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
365 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
366 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
367 }
368
369 return pgd;
370}
371
372static void srmmu_free_pgd_fast(pgd_t *pgd)
373{
374 srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
375}
376
377static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
378{
379 return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
380}
381
382static void srmmu_pmd_free(pmd_t * pmd)
383{
384 srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
385}
386
387/*
388 * Hardware needs alignment to 256 only, but we align to whole page size
389 * to reduce fragmentation problems due to the buddy principle.
390 * XXX Provide actual fragmentation statistics in /proc.
391 *
392 * Alignments up to the page size are the same for physical and virtual
393 * addresses of the nocache area.
394 */
395static pte_t *
396srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
397{
398 return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
399}
400
2f569afd 401static pgtable_t
1da177e4
LT		 402srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
403{
404 unsigned long pte;
2f569afd 405 struct page *page;
1da177e4
LT		 406
407 if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
408 return NULL;
2f569afd
MS		 409 page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
410 pgtable_page_ctor(page);
411 return page;
1da177e4
LT		 412}
413
414static void srmmu_free_pte_fast(pte_t *pte)
415{
416 srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
417}
418
2f569afd 419static void srmmu_pte_free(pgtable_t pte)
1da177e4
LT		 420{
421 unsigned long p;
422
2f569afd 423 pgtable_page_dtor(pte);
1da177e4
LT		 424 p = (unsigned long)page_address(pte); /* Cached address (for test) */
425 if (p == 0)
426 BUG();
427 p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */
428 p = (unsigned long) __nocache_va(p); /* Nocached virtual */
429 srmmu_free_nocache(p, PTE_SIZE);
430}
431
432/*
433 */
434static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
435{
436 struct ctx_list *ctxp;
437
438 ctxp = ctx_free.next;
439 if(ctxp != &ctx_free) {
440 remove_from_ctx_list(ctxp);
441 add_to_used_ctxlist(ctxp);
442 mm->context = ctxp->ctx_number;
443 ctxp->ctx_mm = mm;
444 return;
445 }
446 ctxp = ctx_used.next;
447 if(ctxp->ctx_mm == old_mm)
448 ctxp = ctxp->next;
449 if(ctxp == &ctx_used)
450 panic("out of mmu contexts");
451 flush_cache_mm(ctxp->ctx_mm);
452 flush_tlb_mm(ctxp->ctx_mm);
453 remove_from_ctx_list(ctxp);
454 add_to_used_ctxlist(ctxp);
455 ctxp->ctx_mm->context = NO_CONTEXT;
456 ctxp->ctx_mm = mm;
457 mm->context = ctxp->ctx_number;
458}
459
460static inline void free_context(int context)
461{
462 struct ctx_list *ctx_old;
463
464 ctx_old = ctx_list_pool + context;
465 remove_from_ctx_list(ctx_old);
466 add_to_free_ctxlist(ctx_old);
467}
468
469
34d4accf
SR		 470void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
471 struct task_struct *tsk)
1da177e4
LT		 472{
473 if(mm->context == NO_CONTEXT) {
474 spin_lock(&srmmu_context_spinlock);
475 alloc_context(old_mm, mm);
476 spin_unlock(&srmmu_context_spinlock);
477 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
478 }
479
75d9e346
KE		 480 if (sparc_cpu_model == sparc_leon)
481 leon_switch_mm();
482
1da177e4
LT		 483 if (is_hypersparc)
484 hyper_flush_whole_icache();
485
486 srmmu_set_context(mm->context);
487}
488
489/* Low level IO area allocation on the SRMMU. */
490static inline void srmmu_mapioaddr(unsigned long physaddr,
491 unsigned long virt_addr, int bus_type)
492{
493 pgd_t *pgdp;
494 pmd_t *pmdp;
495 pte_t *ptep;
496 unsigned long tmp;
497
498 physaddr &= PAGE_MASK;
499 pgdp = pgd_offset_k(virt_addr);
500 pmdp = srmmu_pmd_offset(pgdp, virt_addr);
501 ptep = srmmu_pte_offset(pmdp, virt_addr);
502 tmp = (physaddr >> 4) | SRMMU_ET_PTE;
503
504 /*
505 * I need to test whether this is consistent over all
506 * sun4m's. The bus_type represents the upper 4 bits of
507 * 36-bit physical address on the I/O space lines...
508 */
509 tmp |= (bus_type << 28);
510 tmp |= SRMMU_PRIV;
511 __flush_page_to_ram(virt_addr);
62875cff 512 set_pte(ptep, __pte(tmp));
1da177e4
LT		 513}
514
515static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
516 unsigned long xva, unsigned int len)
517{
518 while (len != 0) {
519 len -= PAGE_SIZE;
520 srmmu_mapioaddr(xpa, xva, bus);
521 xva += PAGE_SIZE;
522 xpa += PAGE_SIZE;
523 }
524 flush_tlb_all();
525}
526
527static inline void srmmu_unmapioaddr(unsigned long virt_addr)
528{
529 pgd_t *pgdp;
530 pmd_t *pmdp;
531 pte_t *ptep;
532
533 pgdp = pgd_offset_k(virt_addr);
534 pmdp = srmmu_pmd_offset(pgdp, virt_addr);
535 ptep = srmmu_pte_offset(pmdp, virt_addr);
536
537 /* No need to flush uncacheable page. */
a46d6056 538 __pte_clear(ptep);
1da177e4
LT		 539}
540
541static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
542{
543 while (len != 0) {
544 len -= PAGE_SIZE;
545 srmmu_unmapioaddr(virt_addr);
546 virt_addr += PAGE_SIZE;
547 }
548 flush_tlb_all();
549}
550
551/*
552 * On the SRMMU we do not have the problems with limited tlb entries
553 * for mapping kernel pages, so we just take things from the free page
554 * pool. As a side effect we are putting a little too much pressure
555 * on the gfp() subsystem. This setup also makes the logic of the
556 * iommu mapping code a lot easier as we can transparently handle
ee906c9e 557 * mappings on the kernel stack without any special code.
1da177e4 558 */
e7b7e0c3 559struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
1da177e4
LT		 560{
561 struct thread_info *ret;
562
563 ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
564 THREAD_INFO_ORDER);
565#ifdef CONFIG_DEBUG_STACK_USAGE
566 if (ret)
567 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
568#endif /* DEBUG_STACK_USAGE */
569
570 return ret;
571}
572
e7b7e0c3 573void free_thread_info(struct thread_info *ti)
1da177e4
LT		 574{
575 free_pages((unsigned long)ti, THREAD_INFO_ORDER);
576}
577
578/* tsunami.S */
579extern void tsunami_flush_cache_all(void);
580extern void tsunami_flush_cache_mm(struct mm_struct *mm);
581extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
582extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
583extern void tsunami_flush_page_to_ram(unsigned long page);
584extern void tsunami_flush_page_for_dma(unsigned long page);
585extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
586extern void tsunami_flush_tlb_all(void);
587extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
588extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
589extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
590extern void tsunami_setup_blockops(void);
591
592/*
593 * Workaround, until we find what's going on with Swift. When low on memory,
594 * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
595 * out it is already in page tables/ fault again on the same instruction.
596 * I really don't understand it, have checked it and contexts
597 * are right, flush_tlb_all is done as well, and it faults again...
598 * Strange. -jj
599 *
600 * The following code is a deadwood that may be necessary when
601 * we start to make precise page flushes again. --zaitcev
602 */
4b3073e1 603static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep)
1da177e4
LT		 604{
605#if 0
606 static unsigned long last;
607 unsigned int val;
608 /* unsigned int n; */
609
610 if (address == last) {
611 val = srmmu_hwprobe(address);
4b3073e1 612 if (val != 0 && pte_val(*ptep) != val) {
1da177e4 613 printk("swift_update_mmu_cache: "
e9b57cca 614 "addr %lx put %08x probed %08x from %pf\n",
4b3073e1 615 address, pte_val(*ptep), val,
1da177e4
LT		 616 __builtin_return_address(0));
617 srmmu_flush_whole_tlb();
618 }
619 }
620 last = address;
621#endif
622}
623
624/* swift.S */
625extern void swift_flush_cache_all(void);
626extern void swift_flush_cache_mm(struct mm_struct *mm);
627extern void swift_flush_cache_range(struct vm_area_struct *vma,
628 unsigned long start, unsigned long end);
629extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
630extern void swift_flush_page_to_ram(unsigned long page);
631extern void swift_flush_page_for_dma(unsigned long page);
632extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
633extern void swift_flush_tlb_all(void);
634extern void swift_flush_tlb_mm(struct mm_struct *mm);
635extern void swift_flush_tlb_range(struct vm_area_struct *vma,
636 unsigned long start, unsigned long end);
637extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
638
639#if 0 /* P3: deadwood to debug precise flushes on Swift. */
640void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
641{
642 int cctx, ctx1;
643
644 page &= PAGE_MASK;
645 if ((ctx1 = vma->vm_mm->context) != -1) {
646 cctx = srmmu_get_context();
647/* Is context # ever different from current context? P3 */
648 if (cctx != ctx1) {
649 printk("flush ctx %02x curr %02x\n", ctx1, cctx);
650 srmmu_set_context(ctx1);
651 swift_flush_page(page);
652 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
653 "r" (page), "i" (ASI_M_FLUSH_PROBE));
654 srmmu_set_context(cctx);
655 } else {
656 /* Rm. prot. bits from virt. c. */
657 /* swift_flush_cache_all(); */
658 /* swift_flush_cache_page(vma, page); */
659 swift_flush_page(page);
660
661 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
662 "r" (page), "i" (ASI_M_FLUSH_PROBE));
663 /* same as above: srmmu_flush_tlb_page() */
664 }
665 }
666}
667#endif
668
669/*
670 * The following are all MBUS based SRMMU modules, and therefore could
671 * be found in a multiprocessor configuration. On the whole, these
672 * chips seems to be much more touchy about DVMA and page tables
673 * with respect to cache coherency.
674 */
675
676/* Cypress flushes. */
677static void cypress_flush_cache_all(void)
678{
679 volatile unsigned long cypress_sucks;
680 unsigned long faddr, tagval;
681
682 flush_user_windows();
683 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
684 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
685 "=r" (tagval) :
686 "r" (faddr), "r" (0x40000),
687 "i" (ASI_M_DATAC_TAG));
688
689 /* If modified and valid, kick it. */
690 if((tagval & 0x60) == 0x60)
691 cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
692 }
693}
694
695static void cypress_flush_cache_mm(struct mm_struct *mm)
696{
697 register unsigned long a, b, c, d, e, f, g;
698 unsigned long flags, faddr;
699 int octx;
700
701 FLUSH_BEGIN(mm)
702 flush_user_windows();
703 local_irq_save(flags);
704 octx = srmmu_get_context();
705 srmmu_set_context(mm->context);
706 a = 0x20; b = 0x40; c = 0x60;
707 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
708
709 faddr = (0x10000 - 0x100);
710 goto inside;
711 do {
712 faddr -= 0x100;
713 inside:
714 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
715 "sta %%g0, [%0 + %2] %1\n\t"
716 "sta %%g0, [%0 + %3] %1\n\t"
717 "sta %%g0, [%0 + %4] %1\n\t"
718 "sta %%g0, [%0 + %5] %1\n\t"
719 "sta %%g0, [%0 + %6] %1\n\t"
720 "sta %%g0, [%0 + %7] %1\n\t"
721 "sta %%g0, [%0 + %8] %1\n\t" : :
722 "r" (faddr), "i" (ASI_M_FLUSH_CTX),
723 "r" (a), "r" (b), "r" (c), "r" (d),
724 "r" (e), "r" (f), "r" (g));
725 } while(faddr);
726 srmmu_set_context(octx);
727 local_irq_restore(flags);
728 FLUSH_END
729}
730
731static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
732{
733 struct mm_struct *mm = vma->vm_mm;
734 register unsigned long a, b, c, d, e, f, g;
735 unsigned long flags, faddr;
736 int octx;
737
738 FLUSH_BEGIN(mm)
739 flush_user_windows();
740 local_irq_save(flags);
741 octx = srmmu_get_context();
742 srmmu_set_context(mm->context);
743 a = 0x20; b = 0x40; c = 0x60;
744 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
745
746 start &= SRMMU_REAL_PMD_MASK;
747 while(start < end) {
748 faddr = (start + (0x10000 - 0x100));
749 goto inside;
750 do {
751 faddr -= 0x100;
752 inside:
753 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
754 "sta %%g0, [%0 + %2] %1\n\t"
755 "sta %%g0, [%0 + %3] %1\n\t"
756 "sta %%g0, [%0 + %4] %1\n\t"
757 "sta %%g0, [%0 + %5] %1\n\t"
758 "sta %%g0, [%0 + %6] %1\n\t"
759 "sta %%g0, [%0 + %7] %1\n\t"
760 "sta %%g0, [%0 + %8] %1\n\t" : :
761 "r" (faddr),
762 "i" (ASI_M_FLUSH_SEG),
763 "r" (a), "r" (b), "r" (c), "r" (d),
764 "r" (e), "r" (f), "r" (g));
765 } while (faddr != start);
766 start += SRMMU_REAL_PMD_SIZE;
767 }
768 srmmu_set_context(octx);
769 local_irq_restore(flags);
770 FLUSH_END
771}
772
773static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
774{
775 register unsigned long a, b, c, d, e, f, g;
776 struct mm_struct *mm = vma->vm_mm;
777 unsigned long flags, line;
778 int octx;
779
780 FLUSH_BEGIN(mm)
781 flush_user_windows();
782 local_irq_save(flags);
783 octx = srmmu_get_context();
784 srmmu_set_context(mm->context);
785 a = 0x20; b = 0x40; c = 0x60;
786 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
787
788 page &= PAGE_MASK;
789 line = (page + PAGE_SIZE) - 0x100;
790 goto inside;
791 do {
792 line -= 0x100;
793 inside:
794 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
795 "sta %%g0, [%0 + %2] %1\n\t"
796 "sta %%g0, [%0 + %3] %1\n\t"
797 "sta %%g0, [%0 + %4] %1\n\t"
798 "sta %%g0, [%0 + %5] %1\n\t"
799 "sta %%g0, [%0 + %6] %1\n\t"
800 "sta %%g0, [%0 + %7] %1\n\t"
801 "sta %%g0, [%0 + %8] %1\n\t" : :
802 "r" (line),
803 "i" (ASI_M_FLUSH_PAGE),
804 "r" (a), "r" (b), "r" (c), "r" (d),
805 "r" (e), "r" (f), "r" (g));
806 } while(line != page);
807 srmmu_set_context(octx);
808 local_irq_restore(flags);
809 FLUSH_END
810}
811
812/* Cypress is copy-back, at least that is how we configure it. */
813static void cypress_flush_page_to_ram(unsigned long page)
814{
815 register unsigned long a, b, c, d, e, f, g;
816 unsigned long line;
817
818 a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
819 page &= PAGE_MASK;
820 line = (page + PAGE_SIZE) - 0x100;
821 goto inside;
822 do {
823 line -= 0x100;
824 inside:
825 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
826 "sta %%g0, [%0 + %2] %1\n\t"
827 "sta %%g0, [%0 + %3] %1\n\t"
828 "sta %%g0, [%0 + %4] %1\n\t"
829 "sta %%g0, [%0 + %5] %1\n\t"
830 "sta %%g0, [%0 + %6] %1\n\t"
831 "sta %%g0, [%0 + %7] %1\n\t"
832 "sta %%g0, [%0 + %8] %1\n\t" : :
833 "r" (line),
834 "i" (ASI_M_FLUSH_PAGE),
835 "r" (a), "r" (b), "r" (c), "r" (d),
836 "r" (e), "r" (f), "r" (g));
837 } while(line != page);
838}
839
840/* Cypress is also IO cache coherent. */
841static void cypress_flush_page_for_dma(unsigned long page)
842{
843}
844
845/* Cypress has unified L2 VIPT, from which both instructions and data
846 * are stored. It does not have an onboard icache of any sort, therefore
847 * no flush is necessary.
848 */
849static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
850{
851}
852
853static void cypress_flush_tlb_all(void)
854{
855 srmmu_flush_whole_tlb();
856}
857
858static void cypress_flush_tlb_mm(struct mm_struct *mm)
859{
860 FLUSH_BEGIN(mm)
861 __asm__ __volatile__(
862 "lda [%0] %3, %%g5\n\t"
863 "sta %2, [%0] %3\n\t"
864 "sta %%g0, [%1] %4\n\t"
865 "sta %%g5, [%0] %3\n"
866 : /* no outputs */
867 : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
868 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
869 : "g5");
870 FLUSH_END
871}
872
873static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
874{
875 struct mm_struct *mm = vma->vm_mm;
876 unsigned long size;
877
878 FLUSH_BEGIN(mm)
879 start &= SRMMU_PGDIR_MASK;
880 size = SRMMU_PGDIR_ALIGN(end) - start;
881 __asm__ __volatile__(
882 "lda [%0] %5, %%g5\n\t"
883 "sta %1, [%0] %5\n"
884 "1:\n\t"
885 "subcc %3, %4, %3\n\t"
886 "bne 1b\n\t"
887 " sta %%g0, [%2 + %3] %6\n\t"
888 "sta %%g5, [%0] %5\n"
889 : /* no outputs */
890 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
891 "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
892 "i" (ASI_M_FLUSH_PROBE)
893 : "g5", "cc");
894 FLUSH_END
895}
896
897static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
898{
899 struct mm_struct *mm = vma->vm_mm;
900
901 FLUSH_BEGIN(mm)
902 __asm__ __volatile__(
903 "lda [%0] %3, %%g5\n\t"
904 "sta %1, [%0] %3\n\t"
905 "sta %%g0, [%2] %4\n\t"
906 "sta %%g5, [%0] %3\n"
907 : /* no outputs */
908 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
909 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
910 : "g5");
911 FLUSH_END
912}
913
914/* viking.S */
915extern void viking_flush_cache_all(void);
916extern void viking_flush_cache_mm(struct mm_struct *mm);
917extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
918 unsigned long end);
919extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
920extern void viking_flush_page_to_ram(unsigned long page);
921extern void viking_flush_page_for_dma(unsigned long page);
922extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
923extern void viking_flush_page(unsigned long page);
924extern void viking_mxcc_flush_page(unsigned long page);
925extern void viking_flush_tlb_all(void);
926extern void viking_flush_tlb_mm(struct mm_struct *mm);
927extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
928 unsigned long end);
929extern void viking_flush_tlb_page(struct vm_area_struct *vma,
930 unsigned long page);
931extern void sun4dsmp_flush_tlb_all(void);
932extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
933extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
934 unsigned long end);
935extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
936 unsigned long page);
937
938/* hypersparc.S */
939extern void hypersparc_flush_cache_all(void);
940extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
941extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
942extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
943extern void hypersparc_flush_page_to_ram(unsigned long page);
944extern void hypersparc_flush_page_for_dma(unsigned long page);
945extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
946extern void hypersparc_flush_tlb_all(void);
947extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
948extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
949extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
950extern void hypersparc_setup_blockops(void);
951
952/*
953 * NOTE: All of this startup code assumes the low 16mb (approx.) of
954 * kernel mappings are done with one single contiguous chunk of
955 * ram. On small ram machines (classics mainly) we only get
956 * around 8mb mapped for us.
957 */
958
50215d65 959static void __init early_pgtable_allocfail(char *type)
1da177e4
LT		 960{
961 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
962 prom_halt();
963}
964
50215d65
AB		 965static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
966 unsigned long end)
1da177e4
LT		 967{
968 pgd_t *pgdp;
969 pmd_t *pmdp;
970 pte_t *ptep;
971
972 while(start < end) {
973 pgdp = pgd_offset_k(start);
7d9fa4aa 974 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1da177e4
LT		 975 pmdp = (pmd_t *) __srmmu_get_nocache(
976 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
977 if (pmdp == NULL)
978 early_pgtable_allocfail("pmd");
979 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
980 srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
981 }
982 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
983 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
984 ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
985 if (ptep == NULL)
986 early_pgtable_allocfail("pte");
987 memset(__nocache_fix(ptep), 0, PTE_SIZE);
988 srmmu_pmd_set(__nocache_fix(pmdp), ptep);
989 }
990 if (start > (0xffffffffUL - PMD_SIZE))
991 break;
992 start = (start + PMD_SIZE) & PMD_MASK;
993 }
994}
995
50215d65
AB		 996static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
997 unsigned long end)
1da177e4
LT		 998{
999 pgd_t *pgdp;
1000 pmd_t *pmdp;
1001 pte_t *ptep;
1002
1003 while(start < end) {
1004 pgdp = pgd_offset_k(start);
7d9fa4aa 1005 if (pgd_none(*pgdp)) {
1da177e4
LT		 1006 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1007 if (pmdp == NULL)
1008 early_pgtable_allocfail("pmd");
1009 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1010 srmmu_pgd_set(pgdp, pmdp);
1011 }
1012 pmdp = srmmu_pmd_offset(pgdp, start);
1013 if(srmmu_pmd_none(*pmdp)) {
1014 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1015 PTE_SIZE);
1016 if (ptep == NULL)
1017 early_pgtable_allocfail("pte");
1018 memset(ptep, 0, PTE_SIZE);
1019 srmmu_pmd_set(pmdp, ptep);
1020 }
1021 if (start > (0xffffffffUL - PMD_SIZE))
1022 break;
1023 start = (start + PMD_SIZE) & PMD_MASK;
1024 }
1025}
1026
1027/*
1028 * This is much cleaner than poking around physical address space
1029 * looking at the prom's page table directly which is what most
1030 * other OS's do. Yuck... this is much better.
1031 */
50215d65
AB		 1032static void __init srmmu_inherit_prom_mappings(unsigned long start,
1033 unsigned long end)
1da177e4
LT		 1034{
1035 pgd_t *pgdp;
1036 pmd_t *pmdp;
1037 pte_t *ptep;
1038 int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1039 unsigned long prompte;
1040
1041 while(start <= end) {
1042 if (start == 0)
1043 break; /* probably wrap around */
1044 if(start == 0xfef00000)
1045 start = KADB_DEBUGGER_BEGVM;
1046 if(!(prompte = srmmu_hwprobe(start))) {
1047 start += PAGE_SIZE;
1048 continue;
1049 }
1050
1051 /* A red snapper, see what it really is. */
1052 what = 0;
1053
1054 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1055 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1056 what = 1;
1057 }
1058
1059 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1060 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1061 prompte)
1062 what = 2;
1063 }
1064
1065 pgdp = pgd_offset_k(start);
1066 if(what == 2) {
1067 *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1068 start += SRMMU_PGDIR_SIZE;
1069 continue;
1070 }
7d9fa4aa 1071 if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1da177e4
LT		 1072 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1073 if (pmdp == NULL)
1074 early_pgtable_allocfail("pmd");
1075 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1076 srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1077 }
1078 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1079 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1080 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1081 PTE_SIZE);
1082 if (ptep == NULL)
1083 early_pgtable_allocfail("pte");
1084 memset(__nocache_fix(ptep), 0, PTE_SIZE);
1085 srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1086 }
1087 if(what == 1) {
1088 /*
1089 * We bend the rule where all 16 PTPs in a pmd_t point
1090 * inside the same PTE page, and we leak a perfectly
1091 * good hardware PTE piece. Alternatives seem worse.
1092 */
1093 unsigned int x; /* Index of HW PMD in soft cluster */
1094 x = (start >> PMD_SHIFT) & 15;
1095 *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1096 start += SRMMU_REAL_PMD_SIZE;
1097 continue;
1098 }
1099 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1100 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1101 start += PAGE_SIZE;
1102 }
1103}
1104
1105#define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1106
1107/* Create a third-level SRMMU 16MB page mapping. */
1108static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1109{
1110 pgd_t *pgdp = pgd_offset_k(vaddr);
1111 unsigned long big_pte;
1112
1113 big_pte = KERNEL_PTE(phys_base >> 4);
1114 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1115}
1116
1117/* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1118static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1119{
1120 unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1121 unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1122 unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1123 /* Map "low" memory only */
1124 const unsigned long min_vaddr = PAGE_OFFSET;
1125 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1126
1127 if (vstart < min_vaddr || vstart >= max_vaddr)
1128 return vstart;
1129
1130 if (vend > max_vaddr || vend < min_vaddr)
1131 vend = max_vaddr;
1132
1133 while(vstart < vend) {
1134 do_large_mapping(vstart, pstart);
1135 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1136 }
1137 return vstart;
1138}
1139
1140static inline void memprobe_error(char *msg)
1141{
1142 prom_printf(msg);
1143 prom_printf("Halting now...\n");
1144 prom_halt();
1145}
1146
1147static inline void map_kernel(void)
1148{
1149 int i;
1150
1151 if (phys_base > 0) {
1152 do_large_mapping(PAGE_OFFSET, phys_base);
1153 }
1154
1155 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1156 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1157 }
1da177e4
LT		 1158}
1159
1160/* Paging initialization on the Sparc Reference MMU. */
1161extern void sparc_context_init(int);
1162
409832f5 1163void (*poke_srmmu)(void) __cpuinitdata = NULL;
1da177e4
LT		 1164
1165extern unsigned long bootmem_init(unsigned long *pages_avail);
1166
1167void __init srmmu_paging_init(void)
1168{
8d125562
AS		 1169 int i;
1170 phandle cpunode;
1da177e4
LT		 1171 char node_str[128];
1172 pgd_t *pgd;
1173 pmd_t *pmd;
1174 pte_t *pte;
1175 unsigned long pages_avail;
1176
1177 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1178
1179 if (sparc_cpu_model == sun4d)
1180 num_contexts = 65536; /* We know it is Viking */
1181 else {
1182 /* Find the number of contexts on the srmmu. */
1183 cpunode = prom_getchild(prom_root_node);
1184 num_contexts = 0;
1185 while(cpunode != 0) {
1186 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1187 if(!strcmp(node_str, "cpu")) {
1188 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1189 break;
1190 }
1191 cpunode = prom_getsibling(cpunode);
1192 }
1193 }
1194
1195 if(!num_contexts) {
1196 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1197 prom_halt();
1198 }
1199
1200 pages_avail = 0;
1201 last_valid_pfn = bootmem_init(&pages_avail);
1202
1203 srmmu_nocache_calcsize();
1204 srmmu_nocache_init();
1205 srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1206 map_kernel();
1207
1208 /* ctx table has to be physically aligned to its size */
1209 srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1210 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1211
1212 for(i = 0; i < num_contexts; i++)
1213 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1214
1215 flush_cache_all();
1216 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
a54123e2
BB		 1217#ifdef CONFIG_SMP
1218 /* Stop from hanging here... */
1219 local_flush_tlb_all();
1220#else
1da177e4 1221 flush_tlb_all();
a54123e2 1222#endif
1da177e4
LT		 1223 poke_srmmu();
1224
1da177e4
LT		 1225 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1226 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1da177e4
LT		 1227
1228 srmmu_allocate_ptable_skeleton(
1229 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1230 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1231
1232 pgd = pgd_offset_k(PKMAP_BASE);
1233 pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1234 pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1235 pkmap_page_table = pte;
1236
1237 flush_cache_all();
1238 flush_tlb_all();
1239
1240 sparc_context_init(num_contexts);
1241
1242 kmap_init();
1243
1244 {
1245 unsigned long zones_size[MAX_NR_ZONES];
1246 unsigned long zholes_size[MAX_NR_ZONES];
1247 unsigned long npages;
1248 int znum;
1249
1250 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1251 zones_size[znum] = zholes_size[znum] = 0;
1252
1253 npages = max_low_pfn - pfn_base;
1254
1255 zones_size[ZONE_DMA] = npages;
1256 zholes_size[ZONE_DMA] = npages - pages_avail;
1257
1258 npages = highend_pfn - max_low_pfn;
1259 zones_size[ZONE_HIGHMEM] = npages;
1260 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1261
9109fb7b 1262 free_area_init_node(0, zones_size, pfn_base, zholes_size);
1da177e4
LT		 1263 }
1264}
1265
1266static void srmmu_mmu_info(struct seq_file *m)
1267{
1268 seq_printf(m,
1269 "MMU type\t: %s\n"
1270 "contexts\t: %d\n"
1271 "nocache total\t: %ld\n"
1272 "nocache used\t: %d\n",
1273 srmmu_name,
1274 num_contexts,
1275 srmmu_nocache_size,
1276 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1277}
1278
1279static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1280{
1281}
1282
1283static void srmmu_destroy_context(struct mm_struct *mm)
1284{
1285
1286 if(mm->context != NO_CONTEXT) {
1287 flush_cache_mm(mm);
1288 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1289 flush_tlb_mm(mm);
1290 spin_lock(&srmmu_context_spinlock);
1291 free_context(mm->context);
1292 spin_unlock(&srmmu_context_spinlock);
1293 mm->context = NO_CONTEXT;
1294 }
1295}
1296
1297/* Init various srmmu chip types. */
1298static void __init srmmu_is_bad(void)
1299{
1300 prom_printf("Could not determine SRMMU chip type.\n");
1301 prom_halt();
1302}
1303
1304static void __init init_vac_layout(void)
1305{
8d125562
AS		 1306 phandle nd;
1307 int cache_lines;
1da177e4
LT		 1308 char node_str[128];
1309#ifdef CONFIG_SMP
1310 int cpu = 0;
1311 unsigned long max_size = 0;
1312 unsigned long min_line_size = 0x10000000;
1313#endif
1314
1315 nd = prom_getchild(prom_root_node);
1316 while((nd = prom_getsibling(nd)) != 0) {
1317 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1318 if(!strcmp(node_str, "cpu")) {
1319 vac_line_size = prom_getint(nd, "cache-line-size");
1320 if (vac_line_size == -1) {
1321 prom_printf("can't determine cache-line-size, "
1322 "halting.\n");
1323 prom_halt();
1324 }
1325 cache_lines = prom_getint(nd, "cache-nlines");
1326 if (cache_lines == -1) {
1327 prom_printf("can't determine cache-nlines, halting.\n");
1328 prom_halt();
1329 }
1330
1331 vac_cache_size = cache_lines * vac_line_size;
1332#ifdef CONFIG_SMP
1333 if(vac_cache_size > max_size)
1334 max_size = vac_cache_size;
1335 if(vac_line_size < min_line_size)
1336 min_line_size = vac_line_size;
a54123e2 1337 //FIXME: cpus not contiguous!!
1da177e4 1338 cpu++;
ec7c14bd 1339 if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1da177e4
LT		 1340 break;
1341#else
1342 break;
1343#endif
1344 }
1345 }
1346 if(nd == 0) {
1347 prom_printf("No CPU nodes found, halting.\n");
1348 prom_halt();
1349 }
1350#ifdef CONFIG_SMP
1351 vac_cache_size = max_size;
1352 vac_line_size = min_line_size;
1353#endif
1354 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1355 (int)vac_cache_size, (int)vac_line_size);
1356}
1357
409832f5 1358static void __cpuinit poke_hypersparc(void)
1da177e4
LT		 1359{
1360 volatile unsigned long clear;
1361 unsigned long mreg = srmmu_get_mmureg();
1362
1363 hyper_flush_unconditional_combined();
1364
1365 mreg &= ~(HYPERSPARC_CWENABLE);
1366 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1367 mreg |= (HYPERSPARC_CMODE);
1368
1369 srmmu_set_mmureg(mreg);
1370
1371#if 0 /* XXX I think this is bad news... -DaveM */
1372 hyper_clear_all_tags();
1373#endif
1374
1375 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1376 hyper_flush_whole_icache();
1377 clear = srmmu_get_faddr();
1378 clear = srmmu_get_fstatus();
1379}
1380
1381static void __init init_hypersparc(void)
1382{
1383 srmmu_name = "ROSS HyperSparc";
1384 srmmu_modtype = HyperSparc;
1385
1386 init_vac_layout();
1387
1388 is_hypersparc = 1;
1389
1da177e4
LT		 1390 BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1391 BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1392 BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1393 BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1394
1395 BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1396 BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1397 BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1398 BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1399
1400 BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1401 BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1402 BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1403
1404
1405 poke_srmmu = poke_hypersparc;
1406
1407 hypersparc_setup_blockops();
1408}
1409
409832f5 1410static void __cpuinit poke_cypress(void)
1da177e4
LT		 1411{
1412 unsigned long mreg = srmmu_get_mmureg();
1413 unsigned long faddr, tagval;
1414 volatile unsigned long cypress_sucks;
1415 volatile unsigned long clear;
1416
1417 clear = srmmu_get_faddr();
1418 clear = srmmu_get_fstatus();
1419
1420 if (!(mreg & CYPRESS_CENABLE)) {
1421 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1422 __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1423 "sta %%g0, [%0] %2\n\t" : :
1424 "r" (faddr), "r" (0x40000),
1425 "i" (ASI_M_DATAC_TAG));
1426 }
1427 } else {
1428 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1429 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1430 "=r" (tagval) :
1431 "r" (faddr), "r" (0x40000),
1432 "i" (ASI_M_DATAC_TAG));
1433
1434 /* If modified and valid, kick it. */
1435 if((tagval & 0x60) == 0x60)
1436 cypress_sucks = *(unsigned long *)
1437 (0xf0020000 + faddr);
1438 }
1439 }
1440
1441 /* And one more, for our good neighbor, Mr. Broken Cypress. */
1442 clear = srmmu_get_faddr();
1443 clear = srmmu_get_fstatus();
1444
1445 mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1446 srmmu_set_mmureg(mreg);
1447}
1448
1449static void __init init_cypress_common(void)
1450{
1451 init_vac_layout();
1452
1da177e4
LT		 1453 BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1454 BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1455 BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1456 BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1457
1458 BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1459 BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1460 BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1461 BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1462
1463
1464 BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1465 BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1466 BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1467
1468 poke_srmmu = poke_cypress;
1469}
1470
1471static void __init init_cypress_604(void)
1472{
1473 srmmu_name = "ROSS Cypress-604(UP)";
1474 srmmu_modtype = Cypress;
1475 init_cypress_common();
1476}
1477
1478static void __init init_cypress_605(unsigned long mrev)
1479{
1480 srmmu_name = "ROSS Cypress-605(MP)";
1481 if(mrev == 0xe) {
1482 srmmu_modtype = Cypress_vE;
1483 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1484 } else {
1485 if(mrev == 0xd) {
1486 srmmu_modtype = Cypress_vD;
1487 hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1488 } else {
1489 srmmu_modtype = Cypress;
1490 }
1491 }
1492 init_cypress_common();
1493}
1494
409832f5 1495static void __cpuinit poke_swift(void)
1da177e4
LT		 1496{
1497 unsigned long mreg;
1498
1499 /* Clear any crap from the cache or else... */
1500 swift_flush_cache_all();
1501
1502 /* Enable I & D caches */
1503 mreg = srmmu_get_mmureg();
1504 mreg |= (SWIFT_IE | SWIFT_DE);
1505 /*
1506 * The Swift branch folding logic is completely broken. At
1507 * trap time, if things are just right, if can mistakenly
1508 * think that a trap is coming from kernel mode when in fact
1509 * it is coming from user mode (it mis-executes the branch in
1510 * the trap code). So you see things like crashme completely
1511 * hosing your machine which is completely unacceptable. Turn
1512 * this shit off... nice job Fujitsu.
1513 */
1514 mreg &= ~(SWIFT_BF);
1515 srmmu_set_mmureg(mreg);
1516}
1517
1518#define SWIFT_MASKID_ADDR 0x10003018
1519static void __init init_swift(void)
1520{
1521 unsigned long swift_rev;
1522
1523 __asm__ __volatile__("lda [%1] %2, %0\n\t"
1524 "srl %0, 0x18, %0\n\t" :
1525 "=r" (swift_rev) :
1526 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1527 srmmu_name = "Fujitsu Swift";
1528 switch(swift_rev) {
1529 case 0x11:
1530 case 0x20:
1531 case 0x23:
1532 case 0x30:
1533 srmmu_modtype = Swift_lots_o_bugs;
1534 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1535 /*
1536 * Gee george, I wonder why Sun is so hush hush about
1537 * this hardware bug... really braindamage stuff going
1538 * on here. However I think we can find a way to avoid
1539 * all of the workaround overhead under Linux. Basically,
1540 * any page fault can cause kernel pages to become user
1541 * accessible (the mmu gets confused and clears some of
1542 * the ACC bits in kernel ptes). Aha, sounds pretty
1543 * horrible eh? But wait, after extensive testing it appears
1544 * that if you use pgd_t level large kernel pte's (like the
1545 * 4MB pages on the Pentium) the bug does not get tripped
1546 * at all. This avoids almost all of the major overhead.
1547 * Welcome to a world where your vendor tells you to,
1548 * "apply this kernel patch" instead of "sorry for the
1549 * broken hardware, send it back and we'll give you
1550 * properly functioning parts"
1551 */
1552 break;
1553 case 0x25:
1554 case 0x31:
1555 srmmu_modtype = Swift_bad_c;
1556 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1557 /*
1558 * You see Sun allude to this hardware bug but never
1559 * admit things directly, they'll say things like,
1560 * "the Swift chip cache problems" or similar.
1561 */
1562 break;
1563 default:
1564 srmmu_modtype = Swift_ok;
1565 break;
6cb79b3f 1566 }
1da177e4
LT		 1567
1568 BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1569 BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1570 BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1571 BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1572
1573
1574 BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1575 BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1576 BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1577 BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1578
1579 BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1580 BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1581 BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1582
1583 BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1584
1585 flush_page_for_dma_global = 0;
1586
1587 /*
1588 * Are you now convinced that the Swift is one of the
1589 * biggest VLSI abortions of all time? Bravo Fujitsu!
1590 * Fujitsu, the !#?!%$'d up processor people. I bet if
1591 * you examined the microcode of the Swift you'd find
1592 * XXX's all over the place.
1593 */
1594 poke_srmmu = poke_swift;
1595}
1596
1597static void turbosparc_flush_cache_all(void)
1598{
1599 flush_user_windows();
1600 turbosparc_idflash_clear();
1601}
1602
1603static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1604{
1605 FLUSH_BEGIN(mm)
1606 flush_user_windows();
1607 turbosparc_idflash_clear();
1608 FLUSH_END
1609}
1610
1611static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1612{
1613 FLUSH_BEGIN(vma->vm_mm)
1614 flush_user_windows();
1615 turbosparc_idflash_clear();
1616 FLUSH_END
1617}
1618
1619static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1620{
1621 FLUSH_BEGIN(vma->vm_mm)
1622 flush_user_windows();
1623 if (vma->vm_flags & VM_EXEC)
1624 turbosparc_flush_icache();
1625 turbosparc_flush_dcache();
1626 FLUSH_END
1627}
1628
1629/* TurboSparc is copy-back, if we turn it on, but this does not work. */
1630static void turbosparc_flush_page_to_ram(unsigned long page)
1631{
1632#ifdef TURBOSPARC_WRITEBACK
1633 volatile unsigned long clear;
1634
1635 if (srmmu_hwprobe(page))
1636 turbosparc_flush_page_cache(page);
1637 clear = srmmu_get_fstatus();
1638#endif
1639}
1640
1641static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1642{
1643}
1644
1645static void turbosparc_flush_page_for_dma(unsigned long page)
1646{
1647 turbosparc_flush_dcache();
1648}
1649
1650static void turbosparc_flush_tlb_all(void)
1651{
1652 srmmu_flush_whole_tlb();
1653}
1654
1655static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1656{
1657 FLUSH_BEGIN(mm)
1658 srmmu_flush_whole_tlb();
1659 FLUSH_END
1660}
1661
1662static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1663{
1664 FLUSH_BEGIN(vma->vm_mm)
1665 srmmu_flush_whole_tlb();
1666 FLUSH_END
1667}
1668
1669static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1670{
1671 FLUSH_BEGIN(vma->vm_mm)
1672 srmmu_flush_whole_tlb();
1673 FLUSH_END
1674}
1675
1676
409832f5 1677static void __cpuinit poke_turbosparc(void)
1da177e4
LT		 1678{
1679 unsigned long mreg = srmmu_get_mmureg();
1680 unsigned long ccreg;
1681
1682 /* Clear any crap from the cache or else... */
1683 turbosparc_flush_cache_all();
1684 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1685 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
1686 srmmu_set_mmureg(mreg);
1687
1688 ccreg = turbosparc_get_ccreg();
1689
1690#ifdef TURBOSPARC_WRITEBACK
1691 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
1692 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1693 /* Write-back D-cache, emulate VLSI
1694 * abortion number three, not number one */
1695#else
1696 /* For now let's play safe, optimize later */
1697 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1698 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1699 ccreg &= ~(TURBOSPARC_uS2);
1700 /* Emulate VLSI abortion number three, not number one */
1701#endif
1702
1703 switch (ccreg & 7) {
1704 case 0: /* No SE cache */
1705 case 7: /* Test mode */
1706 break;
1707 default:
1708 ccreg |= (TURBOSPARC_SCENABLE);
1709 }
1710 turbosparc_set_ccreg (ccreg);
1711
1712 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1713 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
1714 srmmu_set_mmureg(mreg);
1715}
1716
1717static void __init init_turbosparc(void)
1718{
1719 srmmu_name = "Fujitsu TurboSparc";
1720 srmmu_modtype = TurboSparc;
1721
1722 BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1723 BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1724 BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1725 BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1726
1727 BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1728 BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1729 BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1730 BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1731
1732 BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1733
1734 BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1735 BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1736
1737 poke_srmmu = poke_turbosparc;
1738}
1739
409832f5 1740static void __cpuinit poke_tsunami(void)
1da177e4
LT		 1741{
1742 unsigned long mreg = srmmu_get_mmureg();
1743
1744 tsunami_flush_icache();
1745 tsunami_flush_dcache();
1746 mreg &= ~TSUNAMI_ITD;
1747 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1748 srmmu_set_mmureg(mreg);
1749}
1750
1751static void __init init_tsunami(void)
1752{
1753 /*
1754 * Tsunami's pretty sane, Sun and TI actually got it
1755 * somewhat right this time. Fujitsu should have
1756 * taken some lessons from them.
1757 */
1758
1759 srmmu_name = "TI Tsunami";
1760 srmmu_modtype = Tsunami;
1761
1762 BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1763 BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1764 BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1765 BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1766
1767
1768 BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1769 BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1770 BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1771 BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1772
1773 BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1774 BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1775 BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1776
1777 poke_srmmu = poke_tsunami;
1778
1779 tsunami_setup_blockops();
1780}
1781
409832f5 1782static void __cpuinit poke_viking(void)
1da177e4
LT		 1783{
1784 unsigned long mreg = srmmu_get_mmureg();
1785 static int smp_catch;
1786
1787 if(viking_mxcc_present) {
1788 unsigned long mxcc_control = mxcc_get_creg();
1789
1790 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1791 mxcc_control &= ~(MXCC_CTL_RRC);
1792 mxcc_set_creg(mxcc_control);
1793
1794 /*
1795 * We don't need memory parity checks.
1796 * XXX This is a mess, have to dig out later. ecd.
1797 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1798 */
1799
1800 /* We do cache ptables on MXCC. */
1801 mreg |= VIKING_TCENABLE;
1802 } else {
1803 unsigned long bpreg;
1804
1805 mreg &= ~(VIKING_TCENABLE);
1806 if(smp_catch++) {
1807 /* Must disable mixed-cmd mode here for other cpu's. */
1808 bpreg = viking_get_bpreg();
1809 bpreg &= ~(VIKING_ACTION_MIX);
1810 viking_set_bpreg(bpreg);
1811
1812 /* Just in case PROM does something funny. */
1813 msi_set_sync();
1814 }
1815 }
1816
1817 mreg |= VIKING_SPENABLE;
1818 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1819 mreg |= VIKING_SBENABLE;
1820 mreg &= ~(VIKING_ACENABLE);
1821 srmmu_set_mmureg(mreg);
1da177e4
LT		 1822}
1823
1824static void __init init_viking(void)
1825{
1826 unsigned long mreg = srmmu_get_mmureg();
1827
1828 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1829 if(mreg & VIKING_MMODE) {
1830 srmmu_name = "TI Viking";
1831 viking_mxcc_present = 0;
1832 msi_set_sync();
1833
1da177e4
LT		 1834 /*
1835 * We need this to make sure old viking takes no hits
1836 * on it's cache for dma snoops to workaround the
1837 * "load from non-cacheable memory" interrupt bug.
1838 * This is only necessary because of the new way in
1839 * which we use the IOMMU.
1840 */
1841 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1842
1843 flush_page_for_dma_global = 0;
1844 } else {
1845 srmmu_name = "TI Viking/MXCC";
1846 viking_mxcc_present = 1;
1847
1848 srmmu_cache_pagetables = 1;
1849
1850 /* MXCC vikings lack the DMA snooping bug. */
1851 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1852 }
1853
1854 BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1855 BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1856 BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1857 BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1858
1859#ifdef CONFIG_SMP
1860 if (sparc_cpu_model == sun4d) {
1861 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1862 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1863 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1864 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1865 } else
1866#endif
1867 {
1868 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1869 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1870 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1871 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1872 }
1873
1874 BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1875 BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1876
1877 poke_srmmu = poke_viking;
1878}
1879
75d9e346
KE		 1880#ifdef CONFIG_SPARC_LEON
1881
1882void __init poke_leonsparc(void)
1883{
1884}
1885
1886void __init init_leon(void)
1887{
1888
c803ba90 1889 srmmu_name = "LEON";
75d9e346
KE		 1890
1891 BTFIXUPSET_CALL(flush_cache_all, leon_flush_cache_all,
1892 BTFIXUPCALL_NORM);
1893 BTFIXUPSET_CALL(flush_cache_mm, leon_flush_cache_all,
1894 BTFIXUPCALL_NORM);
1895 BTFIXUPSET_CALL(flush_cache_page, leon_flush_pcache_all,
1896 BTFIXUPCALL_NORM);
1897 BTFIXUPSET_CALL(flush_cache_range, leon_flush_cache_all,
1898 BTFIXUPCALL_NORM);
1899 BTFIXUPSET_CALL(flush_page_for_dma, leon_flush_dcache_all,
1900 BTFIXUPCALL_NORM);
1901
1902 BTFIXUPSET_CALL(flush_tlb_all, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1903 BTFIXUPSET_CALL(flush_tlb_mm, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1904 BTFIXUPSET_CALL(flush_tlb_page, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1905 BTFIXUPSET_CALL(flush_tlb_range, leon_flush_tlb_all, BTFIXUPCALL_NORM);
1906
1907 BTFIXUPSET_CALL(__flush_page_to_ram, leon_flush_cache_all,
1908 BTFIXUPCALL_NOP);
1909 BTFIXUPSET_CALL(flush_sig_insns, leon_flush_cache_all, BTFIXUPCALL_NOP);
1910
1911 poke_srmmu = poke_leonsparc;
1912
1913 srmmu_cache_pagetables = 0;
1914
1915 leon_flush_during_switch = leon_flush_needed();
1916}
1917#endif
1918
1da177e4
LT		 1919/* Probe for the srmmu chip version. */
1920static void __init get_srmmu_type(void)
1921{
1922 unsigned long mreg, psr;
1923 unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1924
1925 srmmu_modtype = SRMMU_INVAL_MOD;
1926 hwbug_bitmask = 0;
1927
1928 mreg = srmmu_get_mmureg(); psr = get_psr();
1929 mod_typ = (mreg & 0xf0000000) >> 28;
1930 mod_rev = (mreg & 0x0f000000) >> 24;
1931 psr_typ = (psr >> 28) & 0xf;
1932 psr_vers = (psr >> 24) & 0xf;
1933
75d9e346
KE		 1934 /* First, check for sparc-leon. */
1935 if (sparc_cpu_model == sparc_leon) {
75d9e346
KE		 1936 init_leon();
1937 return;
1938 }
1939
1940 /* Second, check for HyperSparc or Cypress. */
1da177e4
LT		 1941 if(mod_typ == 1) {
1942 switch(mod_rev) {
1943 case 7:
1944 /* UP or MP Hypersparc */
1945 init_hypersparc();
1946 break;
1947 case 0:
1948 case 2:
1949 /* Uniprocessor Cypress */
1950 init_cypress_604();
1951 break;
1952 case 10:
1953 case 11:
1954 case 12:
1955 /* _REALLY OLD_ Cypress MP chips... */
1956 case 13:
1957 case 14:
1958 case 15:
1959 /* MP Cypress mmu/cache-controller */
1960 init_cypress_605(mod_rev);
1961 break;
1962 default:
1963 /* Some other Cypress revision, assume a 605. */
1964 init_cypress_605(mod_rev);
1965 break;
6cb79b3f 1966 }
1da177e4
LT		 1967 return;
1968 }
1969
1970 /*
1971 * Now Fujitsu TurboSparc. It might happen that it is
1972 * in Swift emulation mode, so we will check later...
1973 */
1974 if (psr_typ == 0 && psr_vers == 5) {
1975 init_turbosparc();
1976 return;
1977 }
1978
1979 /* Next check for Fujitsu Swift. */
1980 if(psr_typ == 0 && psr_vers == 4) {
8d125562 1981 phandle cpunode;
1da177e4
LT		 1982 char node_str[128];
1983
1984 /* Look if it is not a TurboSparc emulating Swift... */
1985 cpunode = prom_getchild(prom_root_node);
1986 while((cpunode = prom_getsibling(cpunode)) != 0) {
1987 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1988 if(!strcmp(node_str, "cpu")) {
1989 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
1990 prom_getintdefault(cpunode, "psr-version", 1) == 5) {
1991 init_turbosparc();
1992 return;
1993 }
1994 break;
1995 }
1996 }
1997
1998 init_swift();
1999 return;
2000 }
2001
2002 /* Now the Viking family of srmmu. */
2003 if(psr_typ == 4 &&
2004 ((psr_vers == 0) ||
2005 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2006 init_viking();
2007 return;
2008 }
2009
2010 /* Finally the Tsunami. */
2011 if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2012 init_tsunami();
2013 return;
2014 }
2015
2016 /* Oh well */
2017 srmmu_is_bad();
2018}
2019
1da177e4
LT		 2020extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2021 tsetup_mmu_patchme, rtrap_mmu_patchme;
2022
2023extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2024 tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2025
1da177e4
LT		 2026#ifdef CONFIG_SMP
2027/* Local cross-calls. */
2028static void smp_flush_page_for_dma(unsigned long page)
2029{
2030 xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2031 local_flush_page_for_dma(page);
2032}
2033
2034#endif
2035
1da177e4 2036/* Load up routines and constants for sun4m and sun4d mmu */
a3c5c663 2037void __init load_mmu(void)
1da177e4
LT		 2038{
2039 extern void ld_mmu_iommu(void);
2040 extern void ld_mmu_iounit(void);
2041 extern void ___xchg32_sun4md(void);
2042
1da177e4
LT		 2043 /* Functions */
2044#ifndef CONFIG_SMP
2045 BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2046#endif
1da177e4 2047
46a82b2d 2048 BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
1da177e4 2049
1da177e4
LT		 2050 BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2051 BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2052 BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2053
2054 BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2055 BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2056 BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2057
2058 BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2059 BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2060 BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2061 BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2062 BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2063 BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2064 BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2065 BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2066
1da177e4
LT		 2067 BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2068 BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2069
2070 BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2071 BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2072
2073 BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2074 BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2075 BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2076
2077 BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2078
1da177e4 2079 get_srmmu_type();
1da177e4
LT		 2080
2081#ifdef CONFIG_SMP
2082 /* El switcheroo... */
2083
2084 BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2085 BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2086 BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2087 BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2088 BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2089 BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2090 BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2091 BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2092 BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2093 BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2094 BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2095
2096 BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2097 BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2098 BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2099 BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
8401707f
KE		 2100 if (sparc_cpu_model != sun4d &&
2101 sparc_cpu_model != sparc_leon) {
1da177e4
LT		 2102 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2103 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2104 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2105 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2106 }
2107 BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2108 BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2109 BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
64273d08
DM		 2110
2111 if (poke_srmmu == poke_viking) {
2112 /* Avoid unnecessary cross calls. */
2113 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
2114 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
2115 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
2116 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
2117 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
2118 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
2119 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
2120 }
1da177e4
LT		 2121#endif
2122
2123 if (sparc_cpu_model == sun4d)
2124 ld_mmu_iounit();
2125 else
2126 ld_mmu_iommu();
2127#ifdef CONFIG_SMP
2128 if (sparc_cpu_model == sun4d)
2129 sun4d_init_smp();
8401707f
KE		 2130 else if (sparc_cpu_model == sparc_leon)
2131 leon_init_smp();
1da177e4
LT		 2132 else
2133 sun4m_init_smp();
2134#endif
a3c5c663 2135 btfixup();
1da177e4 2136}
Linux 6.x block layer and io_uring tree(s)