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sparc32: Un-btfixup PGDIR_{SHIFT,SIZE,MASK} {USER_,}PTRS_PER_{PGD,PMD}
[linux-block.git] / arch / sparc / mm / srmmu.c
CommitLineData
1da177e4
LT		 1/*
2 * srmmu.c: SRMMU specific routines for memory management.
3 *
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
9 */
10
1da177e4
LT		 11#include <linux/kernel.h>
12#include <linux/mm.h>
1da177e4
LT		 13#include <linux/vmalloc.h>
14#include <linux/pagemap.h>
15#include <linux/init.h>
16#include <linux/spinlock.h>
17#include <linux/bootmem.h>
18#include <linux/fs.h>
19#include <linux/seq_file.h>
1eeb66a1 20#include <linux/kdebug.h>
949e8274 21#include <linux/log2.h>
5a0e3ad6 22#include <linux/gfp.h>
1da177e4
LT		 23
24#include <asm/bitext.h>
25#include <asm/page.h>
26#include <asm/pgalloc.h>
27#include <asm/pgtable.h>
28#include <asm/io.h>
1da177e4
LT		 29#include <asm/vaddrs.h>
30#include <asm/traps.h>
31#include <asm/smp.h>
32#include <asm/mbus.h>
33#include <asm/cache.h>
34#include <asm/oplib.h>
1da177e4
LT		 35#include <asm/asi.h>
36#include <asm/msi.h>
1da177e4
LT		 37#include <asm/mmu_context.h>
38#include <asm/io-unit.h>
39#include <asm/cacheflush.h>
40#include <asm/tlbflush.h>
41
42/* Now the cpu specific definitions. */
43#include <asm/viking.h>
44#include <asm/mxcc.h>
45#include <asm/ross.h>
46#include <asm/tsunami.h>
47#include <asm/swift.h>
48#include <asm/turbosparc.h>
75d9e346 49#include <asm/leon.h>
1da177e4
LT		 50
51#include <asm/btfixup.h>
52
53enum mbus_module srmmu_modtype;
50215d65 54static unsigned int hwbug_bitmask;
1da177e4
LT		 55int vac_cache_size;
56int vac_line_size;
57
58extern struct resource sparc_iomap;
59
60extern unsigned long last_valid_pfn;
61
62extern unsigned long page_kernel;
63
50215d65 64static pgd_t *srmmu_swapper_pg_dir;
1da177e4
LT		 65
66#ifdef CONFIG_SMP
67#define FLUSH_BEGIN(mm)
68#define FLUSH_END
69#else
70#define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
71#define FLUSH_END }
72#endif
73
74BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
75#define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
76
77int flush_page_for_dma_global = 1;
78
79#ifdef CONFIG_SMP
80BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
81#define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
82#endif
83
84char *srmmu_name;
85
86ctxd_t *srmmu_ctx_table_phys;
50215d65 87static ctxd_t *srmmu_context_table;
1da177e4
LT		 88
89int viking_mxcc_present;
90static DEFINE_SPINLOCK(srmmu_context_spinlock);
91
50215d65 92static int is_hypersparc;
1da177e4
LT		 93
94/*
95 * In general all page table modifications should use the V8 atomic
96 * swap instruction. This insures the mmu and the cpu are in sync
97 * with respect to ref/mod bits in the page tables.
98 */
99static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
100{
101 __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
102 return value;
103}
104
105static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
106{
107 srmmu_swap((unsigned long *)ptep, pte_val(pteval));
108}
109
110/* The very generic SRMMU page table operations. */
111static inline int srmmu_device_memory(unsigned long x)
112{
113 return ((x & 0xF0000000) != 0);
114}
115
50215d65 116static int srmmu_cache_pagetables;
1da177e4
LT		 117
118/* these will be initialized in srmmu_nocache_calcsize() */
50215d65
AB		 119static unsigned long srmmu_nocache_size;
120static unsigned long srmmu_nocache_end;
1da177e4
LT		 121
122/* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
123#define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
124
125/* The context table is a nocache user with the biggest alignment needs. */
126#define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
127
128void *srmmu_nocache_pool;
129void *srmmu_nocache_bitmap;
130static struct bit_map srmmu_nocache_map;
131
132static unsigned long srmmu_pte_pfn(pte_t pte)
133{
134 if (srmmu_device_memory(pte_val(pte))) {
135 /* Just return something that will cause
136 * pfn_valid() to return false. This makes
137 * copy_one_pte() to just directly copy to
138 * PTE over.
139 */
140 return ~0UL;
141 }
142 return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
143}
144
145static struct page *srmmu_pmd_page(pmd_t pmd)
146{
147
148 if (srmmu_device_memory(pmd_val(pmd)))
149 BUG();
150 return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
151}
152
153static inline unsigned long srmmu_pgd_page(pgd_t pgd)
154{ return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
155
156
157static inline int srmmu_pte_none(pte_t pte)
158{ return !(pte_val(pte) & 0xFFFFFFF); }
159
160static inline int srmmu_pte_present(pte_t pte)
161{ return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
162
1da177e4
LT		 163static inline void srmmu_pte_clear(pte_t *ptep)
164{ srmmu_set_pte(ptep, __pte(0)); }
165
166static inline int srmmu_pmd_none(pmd_t pmd)
167{ return !(pmd_val(pmd) & 0xFFFFFFF); }
168
169static inline int srmmu_pmd_bad(pmd_t pmd)
170{ return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
171
172static inline int srmmu_pmd_present(pmd_t pmd)
173{ return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
174
175static inline void srmmu_pmd_clear(pmd_t *pmdp) {
176 int i;
177 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
178 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
179}
180
181static inline int srmmu_pgd_none(pgd_t pgd)
182{ return !(pgd_val(pgd) & 0xFFFFFFF); }
183
184static inline int srmmu_pgd_bad(pgd_t pgd)
185{ return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
186
187static inline int srmmu_pgd_present(pgd_t pgd)
188{ return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
189
190static inline void srmmu_pgd_clear(pgd_t * pgdp)
191{ srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
192
193static inline pte_t srmmu_pte_wrprotect(pte_t pte)
194{ return __pte(pte_val(pte) & ~SRMMU_WRITE);}
195
196static inline pte_t srmmu_pte_mkclean(pte_t pte)
197{ return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
198
199static inline pte_t srmmu_pte_mkold(pte_t pte)
200{ return __pte(pte_val(pte) & ~SRMMU_REF);}
201
202static inline pte_t srmmu_pte_mkwrite(pte_t pte)
203{ return __pte(pte_val(pte) | SRMMU_WRITE);}
204
205static inline pte_t srmmu_pte_mkdirty(pte_t pte)
206{ return __pte(pte_val(pte) | SRMMU_DIRTY);}
207
208static inline pte_t srmmu_pte_mkyoung(pte_t pte)
209{ return __pte(pte_val(pte) | SRMMU_REF);}
210
211/*
212 * Conversion functions: convert a page and protection to a page entry,
213 * and a page entry and page directory to the page they refer to.
214 */
215static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
216{ return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
217
218static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
219{ return __pte(((page) >> 4) | pgprot_val(pgprot)); }
220
221static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
222{ return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
223
224/* XXX should we hyper_flush_whole_icache here - Anton */
225static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
226{ srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
227
228static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
229{ srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
230
231static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
232{
233 unsigned long ptp; /* Physical address, shifted right by 4 */
234 int i;
235
236 ptp = __nocache_pa((unsigned long) ptep) >> 4;
237 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
238 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
239 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
240 }
241}
242
243static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
244{
245 unsigned long ptp; /* Physical address, shifted right by 4 */
246 int i;
247
248 ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */
249 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
250 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
251 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
252 }
253}
254
255static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
256{ return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
257
258/* to find an entry in a top-level page table... */
3115624e 259static inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
1da177e4
LT		 260{ return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
261
262/* Find an entry in the second-level page table.. */
263static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
264{
265 return (pmd_t *) srmmu_pgd_page(*dir) +
266 ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
267}
268
269/* Find an entry in the third-level page table.. */
270static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
271{
272 void *pte;
273
274 pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
275 return (pte_t *) pte +
276 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
277}
278
279static unsigned long srmmu_swp_type(swp_entry_t entry)
280{
281 return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
282}
283
284static unsigned long srmmu_swp_offset(swp_entry_t entry)
285{
286 return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
287}
288
289static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
290{
291 return (swp_entry_t) {
292 (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
293 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
294}
295
296/*
297 * size: bytes to allocate in the nocache area.
298 * align: bytes, number to align at.
299 * Returns the virtual address of the allocated area.
300 */
301static unsigned long __srmmu_get_nocache(int size, int align)
302{
303 int offset;
304
305 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
306 printk("Size 0x%x too small for nocache request\n", size);
307 size = SRMMU_NOCACHE_BITMAP_SHIFT;
308 }
309 if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
310 printk("Size 0x%x unaligned int nocache request\n", size);
311 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
312 }
313 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
314
315 offset = bit_map_string_get(&srmmu_nocache_map,
316 size >> SRMMU_NOCACHE_BITMAP_SHIFT,
317 align >> SRMMU_NOCACHE_BITMAP_SHIFT);
318 if (offset == -1) {
319 printk("srmmu: out of nocache %d: %d/%d\n",
320 size, (int) srmmu_nocache_size,
321 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
322 return 0;
323 }
324
325 return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
326}
327
50215d65 328static unsigned long srmmu_get_nocache(int size, int align)
1da177e4
LT		 329{
330 unsigned long tmp;
331
332 tmp = __srmmu_get_nocache(size, align);
333
334 if (tmp)
335 memset((void *)tmp, 0, size);
336
337 return tmp;
338}
339
50215d65 340static void srmmu_free_nocache(unsigned long vaddr, int size)
1da177e4
LT		 341{
342 int offset;
343
344 if (vaddr < SRMMU_NOCACHE_VADDR) {
345 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
346 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
347 BUG();
348 }
349 if (vaddr+size > srmmu_nocache_end) {
350 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
351 vaddr, srmmu_nocache_end);
352 BUG();
353 }
949e8274 354 if (!is_power_of_2(size)) {
1da177e4
LT		 355 printk("Size 0x%x is not a power of 2\n", size);
356 BUG();
357 }
358 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
359 printk("Size 0x%x is too small\n", size);
360 BUG();
361 }
362 if (vaddr & (size-1)) {
363 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
364 BUG();
365 }
366
367 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
368 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
369
370 bit_map_clear(&srmmu_nocache_map, offset, size);
371}
372
50215d65
AB		 373static void srmmu_early_allocate_ptable_skeleton(unsigned long start,
374 unsigned long end);
1da177e4
LT		 375
376extern unsigned long probe_memory(void); /* in fault.c */
377
378/*
379 * Reserve nocache dynamically proportionally to the amount of
380 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
381 */
50215d65 382static void srmmu_nocache_calcsize(void)
1da177e4
LT		 383{
384 unsigned long sysmemavail = probe_memory() / 1024;
385 int srmmu_nocache_npages;
386
387 srmmu_nocache_npages =
388 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
389
390 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
391 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
392 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
393 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
394
395 /* anything above 1280 blows up */
396 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
397 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
398
399 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
400 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
401}
402
50215d65 403static void __init srmmu_nocache_init(void)
1da177e4
LT		 404{
405 unsigned int bitmap_bits;
406 pgd_t *pgd;
407 pmd_t *pmd;
408 pte_t *pte;
409 unsigned long paddr, vaddr;
410 unsigned long pteval;
411
412 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
413
414 srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
415 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
416 memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
417
418 srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
419 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
420
421 srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
422 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
423 init_mm.pgd = srmmu_swapper_pg_dir;
424
425 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
426
427 paddr = __pa((unsigned long)srmmu_nocache_pool);
428 vaddr = SRMMU_NOCACHE_VADDR;
429
430 while (vaddr < srmmu_nocache_end) {
431 pgd = pgd_offset_k(vaddr);
432 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
433 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
434
435 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
436
437 if (srmmu_cache_pagetables)
438 pteval |= SRMMU_CACHE;
439
440 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
441
442 vaddr += PAGE_SIZE;
443 paddr += PAGE_SIZE;
444 }
445
446 flush_cache_all();
447 flush_tlb_all();
448}
449
450static inline pgd_t *srmmu_get_pgd_fast(void)
451{
452 pgd_t *pgd = NULL;
453
454 pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
455 if (pgd) {
456 pgd_t *init = pgd_offset_k(0);
457 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
458 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
459 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
460 }
461
462 return pgd;
463}
464
465static void srmmu_free_pgd_fast(pgd_t *pgd)
466{
467 srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
468}
469
470static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
471{
472 return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
473}
474
475static void srmmu_pmd_free(pmd_t * pmd)
476{
477 srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
478}
479
480/*
481 * Hardware needs alignment to 256 only, but we align to whole page size
482 * to reduce fragmentation problems due to the buddy principle.
483 * XXX Provide actual fragmentation statistics in /proc.
484 *
485 * Alignments up to the page size are the same for physical and virtual
486 * addresses of the nocache area.
487 */
488static pte_t *
489srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
490{
491 return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
492}
493
2f569afd 494static pgtable_t
1da177e4
LT		 495srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
496{
497 unsigned long pte;
2f569afd 498 struct page *page;
1da177e4
LT		 499
500 if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
501 return NULL;
2f569afd
MS		 502 page = pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
503 pgtable_page_ctor(page);
504 return page;
1da177e4
LT		 505}
506
507static void srmmu_free_pte_fast(pte_t *pte)
508{
509 srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
510}
511
2f569afd 512static void srmmu_pte_free(pgtable_t pte)
1da177e4
LT		 513{
514 unsigned long p;
515
2f569afd 516 pgtable_page_dtor(pte);
1da177e4
LT		 517 p = (unsigned long)page_address(pte); /* Cached address (for test) */
518 if (p == 0)
519 BUG();
520 p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */
521 p = (unsigned long) __nocache_va(p); /* Nocached virtual */
522 srmmu_free_nocache(p, PTE_SIZE);
523}
524
525/*
526 */
527static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
528{
529 struct ctx_list *ctxp;
530
531 ctxp = ctx_free.next;
532 if(ctxp != &ctx_free) {
533 remove_from_ctx_list(ctxp);
534 add_to_used_ctxlist(ctxp);
535 mm->context = ctxp->ctx_number;
536 ctxp->ctx_mm = mm;
537 return;
538 }
539 ctxp = ctx_used.next;
540 if(ctxp->ctx_mm == old_mm)
541 ctxp = ctxp->next;
542 if(ctxp == &ctx_used)
543 panic("out of mmu contexts");
544 flush_cache_mm(ctxp->ctx_mm);
545 flush_tlb_mm(ctxp->ctx_mm);
546 remove_from_ctx_list(ctxp);
547 add_to_used_ctxlist(ctxp);
548 ctxp->ctx_mm->context = NO_CONTEXT;
549 ctxp->ctx_mm = mm;
550 mm->context = ctxp->ctx_number;
551}
552
553static inline void free_context(int context)
554{
555 struct ctx_list *ctx_old;
556
557 ctx_old = ctx_list_pool + context;
558 remove_from_ctx_list(ctx_old);
559 add_to_free_ctxlist(ctx_old);
560}
561
562
34d4accf
SR		 563void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
564 struct task_struct *tsk)
1da177e4
LT		 565{
566 if(mm->context == NO_CONTEXT) {
567 spin_lock(&srmmu_context_spinlock);
568 alloc_context(old_mm, mm);
569 spin_unlock(&srmmu_context_spinlock);
570 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
571 }
572
75d9e346
KE		 573 if (sparc_cpu_model == sparc_leon)
574 leon_switch_mm();
575
1da177e4
LT		 576 if (is_hypersparc)
577 hyper_flush_whole_icache();
578
579 srmmu_set_context(mm->context);
580}
581
582/* Low level IO area allocation on the SRMMU. */
583static inline void srmmu_mapioaddr(unsigned long physaddr,
584 unsigned long virt_addr, int bus_type)
585{
586 pgd_t *pgdp;
587 pmd_t *pmdp;
588 pte_t *ptep;
589 unsigned long tmp;
590
591 physaddr &= PAGE_MASK;
592 pgdp = pgd_offset_k(virt_addr);
593 pmdp = srmmu_pmd_offset(pgdp, virt_addr);
594 ptep = srmmu_pte_offset(pmdp, virt_addr);
595 tmp = (physaddr >> 4) | SRMMU_ET_PTE;
596
597 /*
598 * I need to test whether this is consistent over all
599 * sun4m's. The bus_type represents the upper 4 bits of
600 * 36-bit physical address on the I/O space lines...
601 */
602 tmp |= (bus_type << 28);
603 tmp |= SRMMU_PRIV;
604 __flush_page_to_ram(virt_addr);
605 srmmu_set_pte(ptep, __pte(tmp));
606}
607
608static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
609 unsigned long xva, unsigned int len)
610{
611 while (len != 0) {
612 len -= PAGE_SIZE;
613 srmmu_mapioaddr(xpa, xva, bus);
614 xva += PAGE_SIZE;
615 xpa += PAGE_SIZE;
616 }
617 flush_tlb_all();
618}
619
620static inline void srmmu_unmapioaddr(unsigned long virt_addr)
621{
622 pgd_t *pgdp;
623 pmd_t *pmdp;
624 pte_t *ptep;
625
626 pgdp = pgd_offset_k(virt_addr);
627 pmdp = srmmu_pmd_offset(pgdp, virt_addr);
628 ptep = srmmu_pte_offset(pmdp, virt_addr);
629
630 /* No need to flush uncacheable page. */
631 srmmu_pte_clear(ptep);
632}
633
634static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
635{
636 while (len != 0) {
637 len -= PAGE_SIZE;
638 srmmu_unmapioaddr(virt_addr);
639 virt_addr += PAGE_SIZE;
640 }
641 flush_tlb_all();
642}
643
644/*
645 * On the SRMMU we do not have the problems with limited tlb entries
646 * for mapping kernel pages, so we just take things from the free page
647 * pool. As a side effect we are putting a little too much pressure
648 * on the gfp() subsystem. This setup also makes the logic of the
649 * iommu mapping code a lot easier as we can transparently handle
ee906c9e 650 * mappings on the kernel stack without any special code.
1da177e4 651 */
e7b7e0c3 652struct thread_info *alloc_thread_info_node(struct task_struct *tsk, int node)
1da177e4
LT		 653{
654 struct thread_info *ret;
655
656 ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
657 THREAD_INFO_ORDER);
658#ifdef CONFIG_DEBUG_STACK_USAGE
659 if (ret)
660 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
661#endif /* DEBUG_STACK_USAGE */
662
663 return ret;
664}
665
e7b7e0c3 666void free_thread_info(struct thread_info *ti)
1da177e4
LT		 667{
668 free_pages((unsigned long)ti, THREAD_INFO_ORDER);
669}
670
671/* tsunami.S */
672extern void tsunami_flush_cache_all(void);
673extern void tsunami_flush_cache_mm(struct mm_struct *mm);
674extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
675extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
676extern void tsunami_flush_page_to_ram(unsigned long page);
677extern void tsunami_flush_page_for_dma(unsigned long page);
678extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
679extern void tsunami_flush_tlb_all(void);
680extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
681extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
682extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
683extern void tsunami_setup_blockops(void);
684
685/*
686 * Workaround, until we find what's going on with Swift. When low on memory,
687 * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
688 * out it is already in page tables/ fault again on the same instruction.
689 * I really don't understand it, have checked it and contexts
690 * are right, flush_tlb_all is done as well, and it faults again...
691 * Strange. -jj
692 *
693 * The following code is a deadwood that may be necessary when
694 * we start to make precise page flushes again. --zaitcev
695 */
4b3073e1 696static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t *ptep)
1da177e4
LT		 697{
698#if 0
699 static unsigned long last;
700 unsigned int val;
701 /* unsigned int n; */
702
703 if (address == last) {
704 val = srmmu_hwprobe(address);
4b3073e1 705 if (val != 0 && pte_val(*ptep) != val) {
1da177e4 706 printk("swift_update_mmu_cache: "
e9b57cca 707 "addr %lx put %08x probed %08x from %pf\n",
4b3073e1 708 address, pte_val(*ptep), val,
1da177e4
LT		 709 __builtin_return_address(0));
710 srmmu_flush_whole_tlb();
711 }
712 }
713 last = address;
714#endif
715}
716
717/* swift.S */
718extern void swift_flush_cache_all(void);
719extern void swift_flush_cache_mm(struct mm_struct *mm);
720extern void swift_flush_cache_range(struct vm_area_struct *vma,
721 unsigned long start, unsigned long end);
722extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
723extern void swift_flush_page_to_ram(unsigned long page);
724extern void swift_flush_page_for_dma(unsigned long page);
725extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
726extern void swift_flush_tlb_all(void);
727extern void swift_flush_tlb_mm(struct mm_struct *mm);
728extern void swift_flush_tlb_range(struct vm_area_struct *vma,
729 unsigned long start, unsigned long end);
730extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
731
732#if 0 /* P3: deadwood to debug precise flushes on Swift. */
733void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
734{
735 int cctx, ctx1;
736
737 page &= PAGE_MASK;
738 if ((ctx1 = vma->vm_mm->context) != -1) {
739 cctx = srmmu_get_context();
740/* Is context # ever different from current context? P3 */
741 if (cctx != ctx1) {
742 printk("flush ctx %02x curr %02x\n", ctx1, cctx);
743 srmmu_set_context(ctx1);
744 swift_flush_page(page);
745 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
746 "r" (page), "i" (ASI_M_FLUSH_PROBE));
747 srmmu_set_context(cctx);
748 } else {
749 /* Rm. prot. bits from virt. c. */
750 /* swift_flush_cache_all(); */
751 /* swift_flush_cache_page(vma, page); */
752 swift_flush_page(page);
753
754 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
755 "r" (page), "i" (ASI_M_FLUSH_PROBE));
756 /* same as above: srmmu_flush_tlb_page() */
757 }
758 }
759}
760#endif
761
762/*
763 * The following are all MBUS based SRMMU modules, and therefore could
764 * be found in a multiprocessor configuration. On the whole, these
765 * chips seems to be much more touchy about DVMA and page tables
766 * with respect to cache coherency.
767 */
768
769/* Cypress flushes. */
770static void cypress_flush_cache_all(void)
771{
772 volatile unsigned long cypress_sucks;
773 unsigned long faddr, tagval;
774
775 flush_user_windows();
776 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
777 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
778 "=r" (tagval) :
779 "r" (faddr), "r" (0x40000),
780 "i" (ASI_M_DATAC_TAG));
781
782 /* If modified and valid, kick it. */
783 if((tagval & 0x60) == 0x60)
784 cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
785 }
786}
787
788static void cypress_flush_cache_mm(struct mm_struct *mm)
789{
790 register unsigned long a, b, c, d, e, f, g;
791 unsigned long flags, faddr;
792 int octx;
793
794 FLUSH_BEGIN(mm)
795 flush_user_windows();
796 local_irq_save(flags);
797 octx = srmmu_get_context();
798 srmmu_set_context(mm->context);
799 a = 0x20; b = 0x40; c = 0x60;
800 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
801
802 faddr = (0x10000 - 0x100);
803 goto inside;
804 do {
805 faddr -= 0x100;
806 inside:
807 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
808 "sta %%g0, [%0 + %2] %1\n\t"
809 "sta %%g0, [%0 + %3] %1\n\t"
810 "sta %%g0, [%0 + %4] %1\n\t"
811 "sta %%g0, [%0 + %5] %1\n\t"
812 "sta %%g0, [%0 + %6] %1\n\t"
813 "sta %%g0, [%0 + %7] %1\n\t"
814 "sta %%g0, [%0 + %8] %1\n\t" : :
815 "r" (faddr), "i" (ASI_M_FLUSH_CTX),
816 "r" (a), "r" (b), "r" (c), "r" (d),
817 "r" (e), "r" (f), "r" (g));
818 } while(faddr);
819 srmmu_set_context(octx);
820 local_irq_restore(flags);
821 FLUSH_END
822}
823
824static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
825{
826 struct mm_struct *mm = vma->vm_mm;
827 register unsigned long a, b, c, d, e, f, g;
828 unsigned long flags, faddr;
829 int octx;
830
831 FLUSH_BEGIN(mm)
832 flush_user_windows();
833 local_irq_save(flags);
834 octx = srmmu_get_context();
835 srmmu_set_context(mm->context);
836 a = 0x20; b = 0x40; c = 0x60;
837 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
838
839 start &= SRMMU_REAL_PMD_MASK;
840 while(start < end) {
841 faddr = (start + (0x10000 - 0x100));
842 goto inside;
843 do {
844 faddr -= 0x100;
845 inside:
846 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
847 "sta %%g0, [%0 + %2] %1\n\t"
848 "sta %%g0, [%0 + %3] %1\n\t"
849 "sta %%g0, [%0 + %4] %1\n\t"
850 "sta %%g0, [%0 + %5] %1\n\t"
851 "sta %%g0, [%0 + %6] %1\n\t"
852 "sta %%g0, [%0 + %7] %1\n\t"
853 "sta %%g0, [%0 + %8] %1\n\t" : :
854 "r" (faddr),
855 "i" (ASI_M_FLUSH_SEG),
856 "r" (a), "r" (b), "r" (c), "r" (d),
857 "r" (e), "r" (f), "r" (g));
858 } while (faddr != start);
859 start += SRMMU_REAL_PMD_SIZE;
860 }
861 srmmu_set_context(octx);
862 local_irq_restore(flags);
863 FLUSH_END
864}
865
866static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
867{
868 register unsigned long a, b, c, d, e, f, g;
869 struct mm_struct *mm = vma->vm_mm;
870 unsigned long flags, line;
871 int octx;
872
873 FLUSH_BEGIN(mm)
874 flush_user_windows();
875 local_irq_save(flags);
876 octx = srmmu_get_context();
877 srmmu_set_context(mm->context);
878 a = 0x20; b = 0x40; c = 0x60;
879 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
880
881 page &= PAGE_MASK;
882 line = (page + PAGE_SIZE) - 0x100;
883 goto inside;
884 do {
885 line -= 0x100;
886 inside:
887 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
888 "sta %%g0, [%0 + %2] %1\n\t"
889 "sta %%g0, [%0 + %3] %1\n\t"
890 "sta %%g0, [%0 + %4] %1\n\t"
891 "sta %%g0, [%0 + %5] %1\n\t"
892 "sta %%g0, [%0 + %6] %1\n\t"
893 "sta %%g0, [%0 + %7] %1\n\t"
894 "sta %%g0, [%0 + %8] %1\n\t" : :
895 "r" (line),
896 "i" (ASI_M_FLUSH_PAGE),
897 "r" (a), "r" (b), "r" (c), "r" (d),
898 "r" (e), "r" (f), "r" (g));
899 } while(line != page);
900 srmmu_set_context(octx);
901 local_irq_restore(flags);
902 FLUSH_END
903}
904
905/* Cypress is copy-back, at least that is how we configure it. */
906static void cypress_flush_page_to_ram(unsigned long page)
907{
908 register unsigned long a, b, c, d, e, f, g;
909 unsigned long line;
910
911 a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
912 page &= PAGE_MASK;
913 line = (page + PAGE_SIZE) - 0x100;
914 goto inside;
915 do {
916 line -= 0x100;
917 inside:
918 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
919 "sta %%g0, [%0 + %2] %1\n\t"
920 "sta %%g0, [%0 + %3] %1\n\t"
921 "sta %%g0, [%0 + %4] %1\n\t"
922 "sta %%g0, [%0 + %5] %1\n\t"
923 "sta %%g0, [%0 + %6] %1\n\t"
924 "sta %%g0, [%0 + %7] %1\n\t"
925 "sta %%g0, [%0 + %8] %1\n\t" : :
926 "r" (line),
927 "i" (ASI_M_FLUSH_PAGE),
928 "r" (a), "r" (b), "r" (c), "r" (d),
929 "r" (e), "r" (f), "r" (g));
930 } while(line != page);
931}
932
933/* Cypress is also IO cache coherent. */
934static void cypress_flush_page_for_dma(unsigned long page)
935{
936}
937
938/* Cypress has unified L2 VIPT, from which both instructions and data
939 * are stored. It does not have an onboard icache of any sort, therefore
940 * no flush is necessary.
941 */
942static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
943{
944}
945
946static void cypress_flush_tlb_all(void)
947{
948 srmmu_flush_whole_tlb();
949}
950
951static void cypress_flush_tlb_mm(struct mm_struct *mm)
952{
953 FLUSH_BEGIN(mm)
954 __asm__ __volatile__(
955 "lda [%0] %3, %%g5\n\t"
956 "sta %2, [%0] %3\n\t"
957 "sta %%g0, [%1] %4\n\t"
958 "sta %%g5, [%0] %3\n"
959 : /* no outputs */
960 : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
961 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
962 : "g5");
963 FLUSH_END
964}
965
966static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
967{
968 struct mm_struct *mm = vma->vm_mm;
969 unsigned long size;
970
971 FLUSH_BEGIN(mm)
972 start &= SRMMU_PGDIR_MASK;
973 size = SRMMU_PGDIR_ALIGN(end) - start;
974 __asm__ __volatile__(
975 "lda [%0] %5, %%g5\n\t"
976 "sta %1, [%0] %5\n"
977 "1:\n\t"
978 "subcc %3, %4, %3\n\t"
979 "bne 1b\n\t"
980 " sta %%g0, [%2 + %3] %6\n\t"
981 "sta %%g5, [%0] %5\n"
982 : /* no outputs */
983 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
984 "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
985 "i" (ASI_M_FLUSH_PROBE)
986 : "g5", "cc");
987 FLUSH_END
988}
989
990static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
991{
992 struct mm_struct *mm = vma->vm_mm;
993
994 FLUSH_BEGIN(mm)
995 __asm__ __volatile__(
996 "lda [%0] %3, %%g5\n\t"
997 "sta %1, [%0] %3\n\t"
998 "sta %%g0, [%2] %4\n\t"
999 "sta %%g5, [%0] %3\n"
1000 : /* no outputs */
1001 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
1002 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
1003 : "g5");
1004 FLUSH_END
1005}
1006
1007/* viking.S */
1008extern void viking_flush_cache_all(void);
1009extern void viking_flush_cache_mm(struct mm_struct *mm);
1010extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1011 unsigned long end);
1012extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1013extern void viking_flush_page_to_ram(unsigned long page);
1014extern void viking_flush_page_for_dma(unsigned long page);
1015extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
1016extern void viking_flush_page(unsigned long page);
1017extern void viking_mxcc_flush_page(unsigned long page);
1018extern void viking_flush_tlb_all(void);
1019extern void viking_flush_tlb_mm(struct mm_struct *mm);
1020extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1021 unsigned long end);
1022extern void viking_flush_tlb_page(struct vm_area_struct *vma,
1023 unsigned long page);
1024extern void sun4dsmp_flush_tlb_all(void);
1025extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
1026extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1027 unsigned long end);
1028extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
1029 unsigned long page);
1030
1031/* hypersparc.S */
1032extern void hypersparc_flush_cache_all(void);
1033extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
1034extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1035extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1036extern void hypersparc_flush_page_to_ram(unsigned long page);
1037extern void hypersparc_flush_page_for_dma(unsigned long page);
1038extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
1039extern void hypersparc_flush_tlb_all(void);
1040extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
1041extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1042extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
1043extern void hypersparc_setup_blockops(void);
1044
1045/*
1046 * NOTE: All of this startup code assumes the low 16mb (approx.) of
1047 * kernel mappings are done with one single contiguous chunk of
1048 * ram. On small ram machines (classics mainly) we only get
1049 * around 8mb mapped for us.
1050 */
1051
50215d65 1052static void __init early_pgtable_allocfail(char *type)
1da177e4
LT		 1053{
1054 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1055 prom_halt();
1056}
1057
50215d65
AB		 1058static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start,
1059 unsigned long end)
1da177e4
LT		 1060{
1061 pgd_t *pgdp;
1062 pmd_t *pmdp;
1063 pte_t *ptep;
1064
1065 while(start < end) {
1066 pgdp = pgd_offset_k(start);
1067 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1068 pmdp = (pmd_t *) __srmmu_get_nocache(
1069 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1070 if (pmdp == NULL)
1071 early_pgtable_allocfail("pmd");
1072 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1073 srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1074 }
1075 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1076 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1077 ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1078 if (ptep == NULL)
1079 early_pgtable_allocfail("pte");
1080 memset(__nocache_fix(ptep), 0, PTE_SIZE);
1081 srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1082 }
1083 if (start > (0xffffffffUL - PMD_SIZE))
1084 break;
1085 start = (start + PMD_SIZE) & PMD_MASK;
1086 }
1087}
1088
50215d65
AB		 1089static void __init srmmu_allocate_ptable_skeleton(unsigned long start,
1090 unsigned long end)
1da177e4
LT		 1091{
1092 pgd_t *pgdp;
1093 pmd_t *pmdp;
1094 pte_t *ptep;
1095
1096 while(start < end) {
1097 pgdp = pgd_offset_k(start);
1098 if(srmmu_pgd_none(*pgdp)) {
1099 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1100 if (pmdp == NULL)
1101 early_pgtable_allocfail("pmd");
1102 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1103 srmmu_pgd_set(pgdp, pmdp);
1104 }
1105 pmdp = srmmu_pmd_offset(pgdp, start);
1106 if(srmmu_pmd_none(*pmdp)) {
1107 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1108 PTE_SIZE);
1109 if (ptep == NULL)
1110 early_pgtable_allocfail("pte");
1111 memset(ptep, 0, PTE_SIZE);
1112 srmmu_pmd_set(pmdp, ptep);
1113 }
1114 if (start > (0xffffffffUL - PMD_SIZE))
1115 break;
1116 start = (start + PMD_SIZE) & PMD_MASK;
1117 }
1118}
1119
1120/*
1121 * This is much cleaner than poking around physical address space
1122 * looking at the prom's page table directly which is what most
1123 * other OS's do. Yuck... this is much better.
1124 */
50215d65
AB		 1125static void __init srmmu_inherit_prom_mappings(unsigned long start,
1126 unsigned long end)
1da177e4
LT		 1127{
1128 pgd_t *pgdp;
1129 pmd_t *pmdp;
1130 pte_t *ptep;
1131 int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1132 unsigned long prompte;
1133
1134 while(start <= end) {
1135 if (start == 0)
1136 break; /* probably wrap around */
1137 if(start == 0xfef00000)
1138 start = KADB_DEBUGGER_BEGVM;
1139 if(!(prompte = srmmu_hwprobe(start))) {
1140 start += PAGE_SIZE;
1141 continue;
1142 }
1143
1144 /* A red snapper, see what it really is. */
1145 what = 0;
1146
1147 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1148 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1149 what = 1;
1150 }
1151
1152 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1153 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1154 prompte)
1155 what = 2;
1156 }
1157
1158 pgdp = pgd_offset_k(start);
1159 if(what == 2) {
1160 *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1161 start += SRMMU_PGDIR_SIZE;
1162 continue;
1163 }
1164 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1165 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1166 if (pmdp == NULL)
1167 early_pgtable_allocfail("pmd");
1168 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1169 srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1170 }
1171 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1172 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1173 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1174 PTE_SIZE);
1175 if (ptep == NULL)
1176 early_pgtable_allocfail("pte");
1177 memset(__nocache_fix(ptep), 0, PTE_SIZE);
1178 srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1179 }
1180 if(what == 1) {
1181 /*
1182 * We bend the rule where all 16 PTPs in a pmd_t point
1183 * inside the same PTE page, and we leak a perfectly
1184 * good hardware PTE piece. Alternatives seem worse.
1185 */
1186 unsigned int x; /* Index of HW PMD in soft cluster */
1187 x = (start >> PMD_SHIFT) & 15;
1188 *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1189 start += SRMMU_REAL_PMD_SIZE;
1190 continue;
1191 }
1192 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1193 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1194 start += PAGE_SIZE;
1195 }
1196}
1197
1198#define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1199
1200/* Create a third-level SRMMU 16MB page mapping. */
1201static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1202{
1203 pgd_t *pgdp = pgd_offset_k(vaddr);
1204 unsigned long big_pte;
1205
1206 big_pte = KERNEL_PTE(phys_base >> 4);
1207 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1208}
1209
1210/* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1211static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1212{
1213 unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1214 unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1215 unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1216 /* Map "low" memory only */
1217 const unsigned long min_vaddr = PAGE_OFFSET;
1218 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1219
1220 if (vstart < min_vaddr || vstart >= max_vaddr)
1221 return vstart;
1222
1223 if (vend > max_vaddr || vend < min_vaddr)
1224 vend = max_vaddr;
1225
1226 while(vstart < vend) {
1227 do_large_mapping(vstart, pstart);
1228 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1229 }
1230 return vstart;
1231}
1232
1233static inline void memprobe_error(char *msg)
1234{
1235 prom_printf(msg);
1236 prom_printf("Halting now...\n");
1237 prom_halt();
1238}
1239
1240static inline void map_kernel(void)
1241{
1242 int i;
1243
1244 if (phys_base > 0) {
1245 do_large_mapping(PAGE_OFFSET, phys_base);
1246 }
1247
1248 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1249 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1250 }
1da177e4
LT		 1251}
1252
1253/* Paging initialization on the Sparc Reference MMU. */
1254extern void sparc_context_init(int);
1255
409832f5 1256void (*poke_srmmu)(void) __cpuinitdata = NULL;
1da177e4
LT		 1257
1258extern unsigned long bootmem_init(unsigned long *pages_avail);
1259
1260void __init srmmu_paging_init(void)
1261{
8d125562
AS		 1262 int i;
1263 phandle cpunode;
1da177e4
LT		 1264 char node_str[128];
1265 pgd_t *pgd;
1266 pmd_t *pmd;
1267 pte_t *pte;
1268 unsigned long pages_avail;
1269
1270 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1271
1272 if (sparc_cpu_model == sun4d)
1273 num_contexts = 65536; /* We know it is Viking */
1274 else {
1275 /* Find the number of contexts on the srmmu. */
1276 cpunode = prom_getchild(prom_root_node);
1277 num_contexts = 0;
1278 while(cpunode != 0) {
1279 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1280 if(!strcmp(node_str, "cpu")) {
1281 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1282 break;
1283 }
1284 cpunode = prom_getsibling(cpunode);
1285 }
1286 }
1287
1288 if(!num_contexts) {
1289 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1290 prom_halt();
1291 }
1292
1293 pages_avail = 0;
1294 last_valid_pfn = bootmem_init(&pages_avail);
1295
1296 srmmu_nocache_calcsize();
1297 srmmu_nocache_init();
1298 srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1299 map_kernel();
1300
1301 /* ctx table has to be physically aligned to its size */
1302 srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1303 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1304
1305 for(i = 0; i < num_contexts; i++)
1306 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1307
1308 flush_cache_all();
1309 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
a54123e2
BB		 1310#ifdef CONFIG_SMP
1311 /* Stop from hanging here... */
1312 local_flush_tlb_all();
1313#else
1da177e4 1314 flush_tlb_all();
a54123e2 1315#endif
1da177e4
LT		 1316 poke_srmmu();
1317
1da177e4
LT		 1318 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1319 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1da177e4
LT		 1320
1321 srmmu_allocate_ptable_skeleton(
1322 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1323 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1324
1325 pgd = pgd_offset_k(PKMAP_BASE);
1326 pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1327 pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1328 pkmap_page_table = pte;
1329
1330 flush_cache_all();
1331 flush_tlb_all();
1332
1333 sparc_context_init(num_contexts);
1334
1335 kmap_init();
1336
1337 {
1338 unsigned long zones_size[MAX_NR_ZONES];
1339 unsigned long zholes_size[MAX_NR_ZONES];
1340 unsigned long npages;
1341 int znum;
1342
1343 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1344 zones_size[znum] = zholes_size[znum] = 0;
1345
1346 npages = max_low_pfn - pfn_base;
1347
1348 zones_size[ZONE_DMA] = npages;
1349 zholes_size[ZONE_DMA] = npages - pages_avail;
1350
1351 npages = highend_pfn - max_low_pfn;
1352 zones_size[ZONE_HIGHMEM] = npages;
1353 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1354
9109fb7b 1355 free_area_init_node(0, zones_size, pfn_base, zholes_size);
1da177e4
LT		 1356 }
1357}
1358
1359static void srmmu_mmu_info(struct seq_file *m)
1360{
1361 seq_printf(m,
1362 "MMU type\t: %s\n"
1363 "contexts\t: %d\n"
1364 "nocache total\t: %ld\n"
1365 "nocache used\t: %d\n",
1366 srmmu_name,
1367 num_contexts,
1368 srmmu_nocache_size,
1369 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1370}
1371
1372static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1373{
1374}
1375
1376static void srmmu_destroy_context(struct mm_struct *mm)
1377{
1378
1379 if(mm->context != NO_CONTEXT) {
1380 flush_cache_mm(mm);
1381 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1382 flush_tlb_mm(mm);
1383 spin_lock(&srmmu_context_spinlock);
1384 free_context(mm->context);
1385 spin_unlock(&srmmu_context_spinlock);
1386 mm->context = NO_CONTEXT;
1387 }
1388}
1389
1390/* Init various srmmu chip types. */
1391static void __init srmmu_is_bad(void)
1392{
1393 prom_printf("Could not determine SRMMU chip type.\n");
1394 prom_halt();
1395}
1396
1397static void __init init_vac_layout(void)
1398{
8d125562
AS		 1399 phandle nd;
1400 int cache_lines;
1da177e4
LT		 1401 char node_str[128];
1402#ifdef CONFIG_SMP
1403 int cpu = 0;
1404 unsigned long max_size = 0;
1405 unsigned long min_line_size = 0x10000000;
1406#endif
1407
1408 nd = prom_getchild(prom_root_node);
1409 while((nd = prom_getsibling(nd)) != 0) {
1410 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1411 if(!strcmp(node_str, "cpu")) {
1412 vac_line_size = prom_getint(nd, "cache-line-size");
1413 if (vac_line_size == -1) {
1414 prom_printf("can't determine cache-line-size, "
1415 "halting.\n");
1416 prom_halt();
1417 }
1418 cache_lines = prom_getint(nd, "cache-nlines");
1419 if (cache_lines == -1) {
1420 prom_printf("can't determine cache-nlines, halting.\n");
1421 prom_halt();
1422 }
1423
1424 vac_cache_size = cache_lines * vac_line_size;
1425#ifdef CONFIG_SMP
1426 if(vac_cache_size > max_size)
1427 max_size = vac_cache_size;
1428 if(vac_line_size < min_line_size)
1429 min_line_size = vac_line_size;
a54123e2 1430 //FIXME: cpus not contiguous!!
1da177e4 1431 cpu++;
ec7c14bd 1432 if (cpu >= nr_cpu_ids || !cpu_online(cpu))
1da177e4
LT		 1433 break;
1434#else
1435 break;
1436#endif
1437 }
1438 }
1439 if(nd == 0) {
1440 prom_printf("No CPU nodes found, halting.\n");
1441 prom_halt();
1442 }
1443#ifdef CONFIG_SMP
1444 vac_cache_size = max_size;
1445 vac_line_size = min_line_size;
1446#endif
1447 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1448 (int)vac_cache_size, (int)vac_line_size);
1449}
1450
409832f5 1451static void __cpuinit poke_hypersparc(void)
1da177e4
LT		 1452{
1453 volatile unsigned long clear;
1454 unsigned long mreg = srmmu_get_mmureg();
1455
1456 hyper_flush_unconditional_combined();
1457
1458 mreg &= ~(HYPERSPARC_CWENABLE);
1459 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1460 mreg |= (HYPERSPARC_CMODE);
1461
1462 srmmu_set_mmureg(mreg);
1463
1464#if 0 /* XXX I think this is bad news... -DaveM */
1465 hyper_clear_all_tags();
1466#endif
1467
1468 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1469 hyper_flush_whole_icache();
1470 clear = srmmu_get_faddr();
1471 clear = srmmu_get_fstatus();
1472}
1473
1474static void __init init_hypersparc(void)
1475{
1476 srmmu_name = "ROSS HyperSparc";
1477 srmmu_modtype = HyperSparc;
1478
1479 init_vac_layout();
1480
1481 is_hypersparc = 1;
1482
1483 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1484 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1485 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1486 BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1487 BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1488 BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1489 BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1490
1491 BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1492 BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1493 BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1494 BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1495
1496 BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1497 BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1498 BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1499
1500
1501 poke_srmmu = poke_hypersparc;
1502
1503 hypersparc_setup_blockops();
1504}
1505
409832f5 1506static void __cpuinit poke_cypress(void)
1da177e4
LT		 1507{
1508 unsigned long mreg = srmmu_get_mmureg();
1509 unsigned long faddr, tagval;
1510 volatile unsigned long cypress_sucks;
1511 volatile unsigned long clear;
1512
1513 clear = srmmu_get_faddr();
1514 clear = srmmu_get_fstatus();
1515
1516 if (!(mreg & CYPRESS_CENABLE)) {
1517 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1518 __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1519 "sta %%g0, [%0] %2\n\t" : :
1520 "r" (faddr), "r" (0x40000),
1521 "i" (ASI_M_DATAC_TAG));
1522 }
1523 } else {
1524 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1525 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1526 "=r" (tagval) :
1527 "r" (faddr), "r" (0x40000),
1528 "i" (ASI_M_DATAC_TAG));
1529
1530 /* If modified and valid, kick it. */
1531 if((tagval & 0x60) == 0x60)
1532 cypress_sucks = *(unsigned long *)
1533 (0xf0020000 + faddr);
1534 }
1535 }
1536
1537 /* And one more, for our good neighbor, Mr. Broken Cypress. */
1538 clear = srmmu_get_faddr();
1539 clear = srmmu_get_fstatus();
1540
1541 mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1542 srmmu_set_mmureg(mreg);
1543}
1544
1545static void __init init_cypress_common(void)
1546{
1547 init_vac_layout();
1548
1549 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1550 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1551 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1552 BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1553 BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1554 BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1555 BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1556
1557 BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1558 BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1559 BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1560 BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1561
1562
1563 BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1564 BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1565 BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1566
1567 poke_srmmu = poke_cypress;
1568}
1569
1570static void __init init_cypress_604(void)
1571{
1572 srmmu_name = "ROSS Cypress-604(UP)";
1573 srmmu_modtype = Cypress;
1574 init_cypress_common();
1575}
1576
1577static void __init init_cypress_605(unsigned long mrev)
1578{
1579 srmmu_name = "ROSS Cypress-605(MP)";
1580 if(mrev == 0xe) {
1581 srmmu_modtype = Cypress_vE;
1582 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1583 } else {
1584 if(mrev == 0xd) {
1585 srmmu_modtype = Cypress_vD;
1586 hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1587 } else {
1588 srmmu_modtype = Cypress;
1589 }
1590 }
1591 init_cypress_common();
1592}
1593
409832f5 1594static void __cpuinit poke_swift(void)
1da177e4
LT		 1595{
1596 unsigned long mreg;
1597
1598 /* Clear any crap from the cache or else... */
1599 swift_flush_cache_all();
1600
1601 /* Enable I & D caches */
1602 mreg = srmmu_get_mmureg();
1603 mreg |= (SWIFT_IE | SWIFT_DE);
1604 /*
1605 * The Swift branch folding logic is completely broken. At
1606 * trap time, if things are just right, if can mistakenly
1607 * think that a trap is coming from kernel mode when in fact
1608 * it is coming from user mode (it mis-executes the branch in
1609 * the trap code). So you see things like crashme completely
1610 * hosing your machine which is completely unacceptable. Turn
1611 * this shit off... nice job Fujitsu.
1612 */
1613 mreg &= ~(SWIFT_BF);
1614 srmmu_set_mmureg(mreg);
1615}
1616
1617#define SWIFT_MASKID_ADDR 0x10003018
1618static void __init init_swift(void)
1619{
1620 unsigned long swift_rev;
1621
1622 __asm__ __volatile__("lda [%1] %2, %0\n\t"
1623 "srl %0, 0x18, %0\n\t" :
1624 "=r" (swift_rev) :
1625 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1626 srmmu_name = "Fujitsu Swift";
1627 switch(swift_rev) {
1628 case 0x11:
1629 case 0x20:
1630 case 0x23:
1631 case 0x30:
1632 srmmu_modtype = Swift_lots_o_bugs;
1633 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1634 /*
1635 * Gee george, I wonder why Sun is so hush hush about
1636 * this hardware bug... really braindamage stuff going
1637 * on here. However I think we can find a way to avoid
1638 * all of the workaround overhead under Linux. Basically,
1639 * any page fault can cause kernel pages to become user
1640 * accessible (the mmu gets confused and clears some of
1641 * the ACC bits in kernel ptes). Aha, sounds pretty
1642 * horrible eh? But wait, after extensive testing it appears
1643 * that if you use pgd_t level large kernel pte's (like the
1644 * 4MB pages on the Pentium) the bug does not get tripped
1645 * at all. This avoids almost all of the major overhead.
1646 * Welcome to a world where your vendor tells you to,
1647 * "apply this kernel patch" instead of "sorry for the
1648 * broken hardware, send it back and we'll give you
1649 * properly functioning parts"
1650 */
1651 break;
1652 case 0x25:
1653 case 0x31:
1654 srmmu_modtype = Swift_bad_c;
1655 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1656 /*
1657 * You see Sun allude to this hardware bug but never
1658 * admit things directly, they'll say things like,
1659 * "the Swift chip cache problems" or similar.
1660 */
1661 break;
1662 default:
1663 srmmu_modtype = Swift_ok;
1664 break;
6cb79b3f 1665 }
1da177e4
LT		 1666
1667 BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1668 BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1669 BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1670 BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1671
1672
1673 BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1674 BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1675 BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1676 BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1677
1678 BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1679 BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1680 BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1681
1682 BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1683
1684 flush_page_for_dma_global = 0;
1685
1686 /*
1687 * Are you now convinced that the Swift is one of the
1688 * biggest VLSI abortions of all time? Bravo Fujitsu!
1689 * Fujitsu, the !#?!%$'d up processor people. I bet if
1690 * you examined the microcode of the Swift you'd find
1691 * XXX's all over the place.
1692 */
1693 poke_srmmu = poke_swift;
1694}
1695
1696static void turbosparc_flush_cache_all(void)
1697{
1698 flush_user_windows();
1699 turbosparc_idflash_clear();
1700}
1701
1702static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1703{
1704 FLUSH_BEGIN(mm)
1705 flush_user_windows();
1706 turbosparc_idflash_clear();
1707 FLUSH_END
1708}
1709
1710static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1711{
1712 FLUSH_BEGIN(vma->vm_mm)
1713 flush_user_windows();
1714 turbosparc_idflash_clear();
1715 FLUSH_END
1716}
1717
1718static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1719{
1720 FLUSH_BEGIN(vma->vm_mm)
1721 flush_user_windows();
1722 if (vma->vm_flags & VM_EXEC)
1723 turbosparc_flush_icache();
1724 turbosparc_flush_dcache();
1725 FLUSH_END
1726}
1727
1728/* TurboSparc is copy-back, if we turn it on, but this does not work. */
1729static void turbosparc_flush_page_to_ram(unsigned long page)
1730{
1731#ifdef TURBOSPARC_WRITEBACK
1732 volatile unsigned long clear;
1733
1734 if (srmmu_hwprobe(page))
1735 turbosparc_flush_page_cache(page);
1736 clear = srmmu_get_fstatus();
1737#endif
1738}
1739
1740static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1741{
1742}
1743
1744static void turbosparc_flush_page_for_dma(unsigned long page)
1745{
1746 turbosparc_flush_dcache();
1747}
1748
1749static void turbosparc_flush_tlb_all(void)
1750{
1751 srmmu_flush_whole_tlb();
1752}
1753
1754static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1755{
1756 FLUSH_BEGIN(mm)
1757 srmmu_flush_whole_tlb();
1758 FLUSH_END
1759}
1760
1761static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1762{
1763 FLUSH_BEGIN(vma->vm_mm)
1764 srmmu_flush_whole_tlb();
1765 FLUSH_END
1766}
1767
1768static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1769{
1770 FLUSH_BEGIN(vma->vm_mm)
1771 srmmu_flush_whole_tlb();
1772 FLUSH_END
1773}
1774
1775
409832f5 1776static void __cpuinit poke_turbosparc(void)
1da177e4
LT		 1777{
1778 unsigned long mreg = srmmu_get_mmureg();
1779 unsigned long ccreg;
1780
1781 /* Clear any crap from the cache or else... */
1782 turbosparc_flush_cache_all();
1783 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1784 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
1785 srmmu_set_mmureg(mreg);
1786
1787 ccreg = turbosparc_get_ccreg();
1788
1789#ifdef TURBOSPARC_WRITEBACK
1790 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
1791 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1792 /* Write-back D-cache, emulate VLSI
1793 * abortion number three, not number one */
1794#else
1795 /* For now let's play safe, optimize later */
1796 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1797 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1798 ccreg &= ~(TURBOSPARC_uS2);
1799 /* Emulate VLSI abortion number three, not number one */
1800#endif
1801
1802 switch (ccreg & 7) {
1803 case 0: /* No SE cache */
1804 case 7: /* Test mode */
1805 break;
1806 default:
1807 ccreg |= (TURBOSPARC_SCENABLE);
1808 }
1809 turbosparc_set_ccreg (ccreg);
1810
1811 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1812 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
1813 srmmu_set_mmureg(mreg);
1814}
1815
1816static void __init init_turbosparc(void)
1817{
1818 srmmu_name = "Fujitsu TurboSparc";
1819 srmmu_modtype = TurboSparc;
1820
1821 BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1822 BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1823 BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1824 BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1825
1826 BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1827 BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1828 BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1829 BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1830
1831 BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1832
1833 BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1834 BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1835
1836 poke_srmmu = poke_turbosparc;
1837}
1838
409832f5 1839static void __cpuinit poke_tsunami(void)
1da177e4
LT		 1840{
1841 unsigned long mreg = srmmu_get_mmureg();
1842
1843 tsunami_flush_icache();
1844 tsunami_flush_dcache();
1845 mreg &= ~TSUNAMI_ITD;
1846 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1847 srmmu_set_mmureg(mreg);
1848}
1849
1850static void __init init_tsunami(void)
1851{
1852 /*
1853 * Tsunami's pretty sane, Sun and TI actually got it
1854 * somewhat right this time. Fujitsu should have
1855 * taken some lessons from them.
1856 */
1857
1858 srmmu_name = "TI Tsunami";
1859 srmmu_modtype = Tsunami;
1860
1861 BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1862 BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1863 BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1864 BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1865
1866
1867 BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1868 BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1869 BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1870 BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1871
1872 BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1873 BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1874 BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1875
1876 poke_srmmu = poke_tsunami;
1877
1878 tsunami_setup_blockops();
1879}
1880
409832f5 1881static void __cpuinit poke_viking(void)
1da177e4
LT		 1882{
1883 unsigned long mreg = srmmu_get_mmureg();
1884 static int smp_catch;
1885
1886 if(viking_mxcc_present) {
1887 unsigned long mxcc_control = mxcc_get_creg();
1888
1889 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1890 mxcc_control &= ~(MXCC_CTL_RRC);
1891 mxcc_set_creg(mxcc_control);
1892
1893 /*
1894 * We don't need memory parity checks.
1895 * XXX This is a mess, have to dig out later. ecd.
1896 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1897 */
1898
1899 /* We do cache ptables on MXCC. */
1900 mreg |= VIKING_TCENABLE;
1901 } else {
1902 unsigned long bpreg;
1903
1904 mreg &= ~(VIKING_TCENABLE);
1905 if(smp_catch++) {
1906 /* Must disable mixed-cmd mode here for other cpu's. */
1907 bpreg = viking_get_bpreg();
1908 bpreg &= ~(VIKING_ACTION_MIX);
1909 viking_set_bpreg(bpreg);
1910
1911 /* Just in case PROM does something funny. */
1912 msi_set_sync();
1913 }
1914 }
1915
1916 mreg |= VIKING_SPENABLE;
1917 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1918 mreg |= VIKING_SBENABLE;
1919 mreg &= ~(VIKING_ACENABLE);
1920 srmmu_set_mmureg(mreg);
1da177e4
LT		 1921}
1922
1923static void __init init_viking(void)
1924{
1925 unsigned long mreg = srmmu_get_mmureg();
1926
1927 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1928 if(mreg & VIKING_MMODE) {
1929 srmmu_name = "TI Viking";
1930 viking_mxcc_present = 0;
1931 msi_set_sync();
1932
1933 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1934 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1935 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1936
1937 /*
1938 * We need this to make sure old viking takes no hits
1939 * on it's cache for dma snoops to workaround the
1940 * "load from non-cacheable memory" interrupt bug.
1941 * This is only necessary because of the new way in
1942 * which we use the IOMMU.
1943 */
1944 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1945
1946 flush_page_for_dma_global = 0;
1947 } else {
1948 srmmu_name = "TI Viking/MXCC";
1949 viking_mxcc_present = 1;
1950
1951 srmmu_cache_pagetables = 1;
1952
1953 /* MXCC vikings lack the DMA snooping bug. */
1954 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1955 }
1956
1957 BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1958 BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1959 BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1960 BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1961
1962#ifdef CONFIG_SMP
1963 if (sparc_cpu_model == sun4d) {
1964 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1965 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1966 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1967 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1968 } else
1969#endif
1970 {
1971 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1972 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1973 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1974 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1975 }
1976
1977 BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1978 BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1979
1980 poke_srmmu = poke_viking;
1981}
1982
75d9e346
KE		 1983#ifdef CONFIG_SPARC_LEON
1984
1985void __init poke_leonsparc(void)
1986{
1987}
1988
1989void __init init_leon(void)
1990{
1991
c803ba90 1992 srmmu_name = "LEON";
75d9e346
KE		 1993
1994 BTFIXUPSET_CALL(flush_cache_all, leon_flush_cache_all,
1995 BTFIXUPCALL_NORM);
1996 BTFIXUPSET_CALL(flush_cache_mm, leon_flush_cache_all,
1997 BTFIXUPCALL_NORM);
1998 BTFIXUPSET_CALL(flush_cache_page, leon_flush_pcache_all,
1999 BTFIXUPCALL_NORM);
2000 BTFIXUPSET_CALL(flush_cache_range, leon_flush_cache_all,
2001 BTFIXUPCALL_NORM);
2002 BTFIXUPSET_CALL(flush_page_for_dma, leon_flush_dcache_all,
2003 BTFIXUPCALL_NORM);
2004
2005 BTFIXUPSET_CALL(flush_tlb_all, leon_flush_tlb_all, BTFIXUPCALL_NORM);
2006 BTFIXUPSET_CALL(flush_tlb_mm, leon_flush_tlb_all, BTFIXUPCALL_NORM);
2007 BTFIXUPSET_CALL(flush_tlb_page, leon_flush_tlb_all, BTFIXUPCALL_NORM);
2008 BTFIXUPSET_CALL(flush_tlb_range, leon_flush_tlb_all, BTFIXUPCALL_NORM);
2009
2010 BTFIXUPSET_CALL(__flush_page_to_ram, leon_flush_cache_all,
2011 BTFIXUPCALL_NOP);
2012 BTFIXUPSET_CALL(flush_sig_insns, leon_flush_cache_all, BTFIXUPCALL_NOP);
2013
2014 poke_srmmu = poke_leonsparc;
2015
2016 srmmu_cache_pagetables = 0;
2017
2018 leon_flush_during_switch = leon_flush_needed();
2019}
2020#endif
2021
1da177e4
LT		 2022/* Probe for the srmmu chip version. */
2023static void __init get_srmmu_type(void)
2024{
2025 unsigned long mreg, psr;
2026 unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
2027
2028 srmmu_modtype = SRMMU_INVAL_MOD;
2029 hwbug_bitmask = 0;
2030
2031 mreg = srmmu_get_mmureg(); psr = get_psr();
2032 mod_typ = (mreg & 0xf0000000) >> 28;
2033 mod_rev = (mreg & 0x0f000000) >> 24;
2034 psr_typ = (psr >> 28) & 0xf;
2035 psr_vers = (psr >> 24) & 0xf;
2036
75d9e346
KE		 2037 /* First, check for sparc-leon. */
2038 if (sparc_cpu_model == sparc_leon) {
75d9e346
KE		 2039 init_leon();
2040 return;
2041 }
2042
2043 /* Second, check for HyperSparc or Cypress. */
1da177e4
LT		 2044 if(mod_typ == 1) {
2045 switch(mod_rev) {
2046 case 7:
2047 /* UP or MP Hypersparc */
2048 init_hypersparc();
2049 break;
2050 case 0:
2051 case 2:
2052 /* Uniprocessor Cypress */
2053 init_cypress_604();
2054 break;
2055 case 10:
2056 case 11:
2057 case 12:
2058 /* _REALLY OLD_ Cypress MP chips... */
2059 case 13:
2060 case 14:
2061 case 15:
2062 /* MP Cypress mmu/cache-controller */
2063 init_cypress_605(mod_rev);
2064 break;
2065 default:
2066 /* Some other Cypress revision, assume a 605. */
2067 init_cypress_605(mod_rev);
2068 break;
6cb79b3f 2069 }
1da177e4
LT		 2070 return;
2071 }
2072
2073 /*
2074 * Now Fujitsu TurboSparc. It might happen that it is
2075 * in Swift emulation mode, so we will check later...
2076 */
2077 if (psr_typ == 0 && psr_vers == 5) {
2078 init_turbosparc();
2079 return;
2080 }
2081
2082 /* Next check for Fujitsu Swift. */
2083 if(psr_typ == 0 && psr_vers == 4) {
8d125562 2084 phandle cpunode;
1da177e4
LT		 2085 char node_str[128];
2086
2087 /* Look if it is not a TurboSparc emulating Swift... */
2088 cpunode = prom_getchild(prom_root_node);
2089 while((cpunode = prom_getsibling(cpunode)) != 0) {
2090 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2091 if(!strcmp(node_str, "cpu")) {
2092 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2093 prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2094 init_turbosparc();
2095 return;
2096 }
2097 break;
2098 }
2099 }
2100
2101 init_swift();
2102 return;
2103 }
2104
2105 /* Now the Viking family of srmmu. */
2106 if(psr_typ == 4 &&
2107 ((psr_vers == 0) ||
2108 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2109 init_viking();
2110 return;
2111 }
2112
2113 /* Finally the Tsunami. */
2114 if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2115 init_tsunami();
2116 return;
2117 }
2118
2119 /* Oh well */
2120 srmmu_is_bad();
2121}
2122
1da177e4
LT		 2123extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2124 tsetup_mmu_patchme, rtrap_mmu_patchme;
2125
2126extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2127 tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2128
1da177e4
LT		 2129#ifdef CONFIG_SMP
2130/* Local cross-calls. */
2131static void smp_flush_page_for_dma(unsigned long page)
2132{
2133 xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2134 local_flush_page_for_dma(page);
2135}
2136
2137#endif
2138
1da177e4
LT		 2139/* Load up routines and constants for sun4m and sun4d mmu */
2140void __init ld_mmu_srmmu(void)
2141{
2142 extern void ld_mmu_iommu(void);
2143 extern void ld_mmu_iounit(void);
2144 extern void ___xchg32_sun4md(void);
2145
1da177e4 2146 BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
378e515c 2147 PAGE_SHARED = pgprot_val(SRMMU_PAGE_SHARED);
1da177e4
LT		 2148 BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2149 BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2150 BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2151 page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
1da177e4
LT		 2152
2153 /* Functions */
2154#ifndef CONFIG_SMP
2155 BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2156#endif
1da177e4
LT		 2157
2158 BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
1da177e4
LT		 2159
2160 BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
2161 BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
46a82b2d 2162 BTFIXUPSET_CALL(pgd_page_vaddr, srmmu_pgd_page, BTFIXUPCALL_NORM);
1da177e4 2163
1da177e4
LT		 2164 BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2165 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
1da177e4
LT		 2166
2167 BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2168 BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2169 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2170
2171 BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2172 BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2173 BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2174 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2175
2176 BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2177 BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2178 BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2179 BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2180 BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2181 BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2182
2183 BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2184 BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2185 BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2186
2187 BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2188 BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2189 BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2190 BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2191 BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2192 BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2193 BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2194 BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2195
2196 BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2197 BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2198 BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2199 BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2200 BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2201 BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2202 BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2203 BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2204 BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2205 BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2206 BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2207 BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2208
2209 BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2210 BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2211
2212 BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2213 BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2214 BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2215
2216 BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2217
1da177e4 2218 get_srmmu_type();
1da177e4
LT		 2219
2220#ifdef CONFIG_SMP
2221 /* El switcheroo... */
2222
2223 BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2224 BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2225 BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2226 BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2227 BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2228 BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2229 BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2230 BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2231 BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2232 BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2233 BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2234
2235 BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2236 BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2237 BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2238 BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
8401707f
KE		 2239 if (sparc_cpu_model != sun4d &&
2240 sparc_cpu_model != sparc_leon) {
1da177e4
LT		 2241 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2242 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2243 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2244 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2245 }
2246 BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2247 BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2248 BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
64273d08
DM		 2249
2250 if (poke_srmmu == poke_viking) {
2251 /* Avoid unnecessary cross calls. */
2252 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
2253 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
2254 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
2255 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
2256 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
2257 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
2258 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
2259 }
1da177e4
LT		 2260#endif
2261
2262 if (sparc_cpu_model == sun4d)
2263 ld_mmu_iounit();
2264 else
2265 ld_mmu_iommu();
2266#ifdef CONFIG_SMP
2267 if (sparc_cpu_model == sun4d)
2268 sun4d_init_smp();
8401707f
KE		 2269 else if (sparc_cpu_model == sparc_leon)
2270 leon_init_smp();
1da177e4
LT		 2271 else
2272 sun4m_init_smp();
2273#endif
2274}
Linux 6.x block layer and io_uring tree(s)