Commit | Line | Data |
---|---|---|
b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
1da177e4 LT |
2 | /* |
3 | * srmmu.c: SRMMU specific routines for memory management. | |
4 | * | |
5 | * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu) | |
6 | * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com) | |
7 | * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be) | |
8 | * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
9 | * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org) | |
10 | */ | |
11 | ||
4a049b03 | 12 | #include <linux/seq_file.h> |
1da177e4 LT |
13 | #include <linux/spinlock.h> |
14 | #include <linux/bootmem.h> | |
4a049b03 SR |
15 | #include <linux/pagemap.h> |
16 | #include <linux/vmalloc.h> | |
1eeb66a1 | 17 | #include <linux/kdebug.h> |
a56b072f | 18 | #include <linux/export.h> |
4a049b03 SR |
19 | #include <linux/kernel.h> |
20 | #include <linux/init.h> | |
949e8274 | 21 | #include <linux/log2.h> |
5a0e3ad6 | 22 | #include <linux/gfp.h> |
4a049b03 SR |
23 | #include <linux/fs.h> |
24 | #include <linux/mm.h> | |
1da177e4 | 25 | |
4a049b03 SR |
26 | #include <asm/mmu_context.h> |
27 | #include <asm/cacheflush.h> | |
28 | #include <asm/tlbflush.h> | |
29 | #include <asm/io-unit.h> | |
1da177e4 LT |
30 | #include <asm/pgalloc.h> |
31 | #include <asm/pgtable.h> | |
4a049b03 | 32 | #include <asm/bitext.h> |
1da177e4 | 33 | #include <asm/vaddrs.h> |
1da177e4 | 34 | #include <asm/cache.h> |
4a049b03 | 35 | #include <asm/traps.h> |
1da177e4 | 36 | #include <asm/oplib.h> |
4a049b03 SR |
37 | #include <asm/mbus.h> |
38 | #include <asm/page.h> | |
1da177e4 | 39 | #include <asm/asi.h> |
4a049b03 SR |
40 | #include <asm/smp.h> |
41 | #include <asm/io.h> | |
1da177e4 LT |
42 | |
43 | /* Now the cpu specific definitions. */ | |
4a049b03 | 44 | #include <asm/turbosparc.h> |
1da177e4 | 45 | #include <asm/tsunami.h> |
4a049b03 | 46 | #include <asm/viking.h> |
1da177e4 | 47 | #include <asm/swift.h> |
75d9e346 | 48 | #include <asm/leon.h> |
4a049b03 SR |
49 | #include <asm/mxcc.h> |
50 | #include <asm/ross.h> | |
1da177e4 | 51 | |
ddb7417e | 52 | #include "mm_32.h" |
accf032c | 53 | |
1da177e4 | 54 | enum mbus_module srmmu_modtype; |
50215d65 | 55 | static unsigned int hwbug_bitmask; |
1da177e4 | 56 | int vac_cache_size; |
9d262d95 | 57 | EXPORT_SYMBOL(vac_cache_size); |
1da177e4 LT |
58 | int vac_line_size; |
59 | ||
60 | extern struct resource sparc_iomap; | |
61 | ||
62 | extern unsigned long last_valid_pfn; | |
63 | ||
50215d65 | 64 | static pgd_t *srmmu_swapper_pg_dir; |
1da177e4 | 65 | |
5d83d666 | 66 | const struct sparc32_cachetlb_ops *sparc32_cachetlb_ops; |
a56b072f | 67 | EXPORT_SYMBOL(sparc32_cachetlb_ops); |
5d83d666 | 68 | |
1da177e4 | 69 | #ifdef CONFIG_SMP |
5d83d666 DM |
70 | const struct sparc32_cachetlb_ops *local_ops; |
71 | ||
1da177e4 LT |
72 | #define FLUSH_BEGIN(mm) |
73 | #define FLUSH_END | |
74 | #else | |
5d83d666 | 75 | #define FLUSH_BEGIN(mm) if ((mm)->context != NO_CONTEXT) { |
1da177e4 LT |
76 | #define FLUSH_END } |
77 | #endif | |
78 | ||
1da177e4 LT |
79 | int flush_page_for_dma_global = 1; |
80 | ||
1da177e4 LT |
81 | char *srmmu_name; |
82 | ||
83 | ctxd_t *srmmu_ctx_table_phys; | |
50215d65 | 84 | static ctxd_t *srmmu_context_table; |
1da177e4 LT |
85 | |
86 | int viking_mxcc_present; | |
87 | static DEFINE_SPINLOCK(srmmu_context_spinlock); | |
88 | ||
50215d65 | 89 | static int is_hypersparc; |
1da177e4 | 90 | |
50215d65 | 91 | static int srmmu_cache_pagetables; |
1da177e4 LT |
92 | |
93 | /* these will be initialized in srmmu_nocache_calcsize() */ | |
50215d65 AB |
94 | static unsigned long srmmu_nocache_size; |
95 | static unsigned long srmmu_nocache_end; | |
1da177e4 LT |
96 | |
97 | /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */ | |
98 | #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4) | |
99 | ||
100 | /* The context table is a nocache user with the biggest alignment needs. */ | |
101 | #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS) | |
102 | ||
103 | void *srmmu_nocache_pool; | |
1da177e4 LT |
104 | static struct bit_map srmmu_nocache_map; |
105 | ||
1da177e4 LT |
106 | static inline int srmmu_pmd_none(pmd_t pmd) |
107 | { return !(pmd_val(pmd) & 0xFFFFFFF); } | |
108 | ||
1da177e4 LT |
109 | /* XXX should we hyper_flush_whole_icache here - Anton */ |
110 | static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp) | |
6e6e4187 SR |
111 | { |
112 | pte_t pte; | |
113 | ||
114 | pte = __pte((SRMMU_ET_PTD | (__nocache_pa(pgdp) >> 4))); | |
115 | set_pte((pte_t *)ctxp, pte); | |
116 | } | |
1da177e4 | 117 | |
f0afc6b1 TP |
118 | /* |
119 | * Locations of MSI Registers. | |
120 | */ | |
121 | #define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */ | |
122 | ||
123 | /* | |
124 | * Useful bits in the MSI Registers. | |
125 | */ | |
126 | #define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */ | |
127 | ||
128 | static void msi_set_sync(void) | |
129 | { | |
130 | __asm__ __volatile__ ("lda [%0] %1, %%g3\n\t" | |
131 | "andn %%g3, %2, %%g3\n\t" | |
132 | "sta %%g3, [%0] %1\n\t" : : | |
133 | "r" (MSI_MBUS_ARBEN), | |
134 | "i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3"); | |
135 | } | |
136 | ||
642ea3ed | 137 | void pmd_set(pmd_t *pmdp, pte_t *ptep) |
1da177e4 LT |
138 | { |
139 | unsigned long ptp; /* Physical address, shifted right by 4 */ | |
140 | int i; | |
141 | ||
6b1cabe8 | 142 | ptp = __nocache_pa(ptep) >> 4; |
1da177e4 | 143 | for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) { |
6e6e4187 SR |
144 | set_pte((pte_t *)&pmdp->pmdv[i], __pte(SRMMU_ET_PTD | ptp)); |
145 | ptp += (SRMMU_REAL_PTRS_PER_PTE * sizeof(pte_t) >> 4); | |
1da177e4 LT |
146 | } |
147 | } | |
148 | ||
642ea3ed | 149 | void pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep) |
1da177e4 LT |
150 | { |
151 | unsigned long ptp; /* Physical address, shifted right by 4 */ | |
152 | int i; | |
153 | ||
154 | ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */ | |
155 | for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) { | |
6e6e4187 SR |
156 | set_pte((pte_t *)&pmdp->pmdv[i], __pte(SRMMU_ET_PTD | ptp)); |
157 | ptp += (SRMMU_REAL_PTRS_PER_PTE * sizeof(pte_t) >> 4); | |
1da177e4 LT |
158 | } |
159 | } | |
160 | ||
605ae962 SR |
161 | /* Find an entry in the third-level page table.. */ |
162 | pte_t *pte_offset_kernel(pmd_t *dir, unsigned long address) | |
1da177e4 LT |
163 | { |
164 | void *pte; | |
165 | ||
166 | pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4); | |
167 | return (pte_t *) pte + | |
168 | ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)); | |
169 | } | |
170 | ||
1da177e4 LT |
171 | /* |
172 | * size: bytes to allocate in the nocache area. | |
173 | * align: bytes, number to align at. | |
174 | * Returns the virtual address of the allocated area. | |
175 | */ | |
f71a2aac | 176 | static void *__srmmu_get_nocache(int size, int align) |
1da177e4 LT |
177 | { |
178 | int offset; | |
f71a2aac | 179 | unsigned long addr; |
1da177e4 LT |
180 | |
181 | if (size < SRMMU_NOCACHE_BITMAP_SHIFT) { | |
f71a2aac SR |
182 | printk(KERN_ERR "Size 0x%x too small for nocache request\n", |
183 | size); | |
1da177e4 LT |
184 | size = SRMMU_NOCACHE_BITMAP_SHIFT; |
185 | } | |
f71a2aac SR |
186 | if (size & (SRMMU_NOCACHE_BITMAP_SHIFT - 1)) { |
187 | printk(KERN_ERR "Size 0x%x unaligned int nocache request\n", | |
188 | size); | |
189 | size += SRMMU_NOCACHE_BITMAP_SHIFT - 1; | |
1da177e4 LT |
190 | } |
191 | BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX); | |
192 | ||
193 | offset = bit_map_string_get(&srmmu_nocache_map, | |
f71a2aac SR |
194 | size >> SRMMU_NOCACHE_BITMAP_SHIFT, |
195 | align >> SRMMU_NOCACHE_BITMAP_SHIFT); | |
1da177e4 | 196 | if (offset == -1) { |
f71a2aac SR |
197 | printk(KERN_ERR "srmmu: out of nocache %d: %d/%d\n", |
198 | size, (int) srmmu_nocache_size, | |
199 | srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); | |
e8c29c83 | 200 | return NULL; |
1da177e4 LT |
201 | } |
202 | ||
f71a2aac SR |
203 | addr = SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT); |
204 | return (void *)addr; | |
1da177e4 LT |
205 | } |
206 | ||
f71a2aac | 207 | void *srmmu_get_nocache(int size, int align) |
1da177e4 | 208 | { |
f71a2aac | 209 | void *tmp; |
1da177e4 LT |
210 | |
211 | tmp = __srmmu_get_nocache(size, align); | |
212 | ||
213 | if (tmp) | |
f71a2aac | 214 | memset(tmp, 0, size); |
1da177e4 LT |
215 | |
216 | return tmp; | |
217 | } | |
218 | ||
f71a2aac | 219 | void srmmu_free_nocache(void *addr, int size) |
1da177e4 | 220 | { |
f71a2aac | 221 | unsigned long vaddr; |
1da177e4 LT |
222 | int offset; |
223 | ||
f71a2aac | 224 | vaddr = (unsigned long)addr; |
1da177e4 LT |
225 | if (vaddr < SRMMU_NOCACHE_VADDR) { |
226 | printk("Vaddr %lx is smaller than nocache base 0x%lx\n", | |
227 | vaddr, (unsigned long)SRMMU_NOCACHE_VADDR); | |
228 | BUG(); | |
229 | } | |
605ae962 | 230 | if (vaddr + size > srmmu_nocache_end) { |
1da177e4 LT |
231 | printk("Vaddr %lx is bigger than nocache end 0x%lx\n", |
232 | vaddr, srmmu_nocache_end); | |
233 | BUG(); | |
234 | } | |
949e8274 | 235 | if (!is_power_of_2(size)) { |
1da177e4 LT |
236 | printk("Size 0x%x is not a power of 2\n", size); |
237 | BUG(); | |
238 | } | |
239 | if (size < SRMMU_NOCACHE_BITMAP_SHIFT) { | |
240 | printk("Size 0x%x is too small\n", size); | |
241 | BUG(); | |
242 | } | |
605ae962 | 243 | if (vaddr & (size - 1)) { |
1da177e4 LT |
244 | printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size); |
245 | BUG(); | |
246 | } | |
247 | ||
248 | offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT; | |
249 | size = size >> SRMMU_NOCACHE_BITMAP_SHIFT; | |
250 | ||
251 | bit_map_clear(&srmmu_nocache_map, offset, size); | |
252 | } | |
253 | ||
50215d65 AB |
254 | static void srmmu_early_allocate_ptable_skeleton(unsigned long start, |
255 | unsigned long end); | |
1da177e4 | 256 | |
d8a1b2b9 SR |
257 | /* Return how much physical memory we have. */ |
258 | static unsigned long __init probe_memory(void) | |
259 | { | |
260 | unsigned long total = 0; | |
261 | int i; | |
262 | ||
263 | for (i = 0; sp_banks[i].num_bytes; i++) | |
264 | total += sp_banks[i].num_bytes; | |
265 | ||
266 | return total; | |
267 | } | |
1da177e4 LT |
268 | |
269 | /* | |
270 | * Reserve nocache dynamically proportionally to the amount of | |
271 | * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002 | |
272 | */ | |
32442467 | 273 | static void __init srmmu_nocache_calcsize(void) |
1da177e4 LT |
274 | { |
275 | unsigned long sysmemavail = probe_memory() / 1024; | |
276 | int srmmu_nocache_npages; | |
277 | ||
278 | srmmu_nocache_npages = | |
279 | sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256; | |
280 | ||
281 | /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */ | |
282 | // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256; | |
283 | if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES) | |
284 | srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES; | |
285 | ||
286 | /* anything above 1280 blows up */ | |
287 | if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES) | |
288 | srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES; | |
289 | ||
290 | srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE; | |
291 | srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size; | |
292 | } | |
293 | ||
50215d65 | 294 | static void __init srmmu_nocache_init(void) |
1da177e4 | 295 | { |
e8c29c83 | 296 | void *srmmu_nocache_bitmap; |
1da177e4 LT |
297 | unsigned int bitmap_bits; |
298 | pgd_t *pgd; | |
299 | pmd_t *pmd; | |
300 | pte_t *pte; | |
301 | unsigned long paddr, vaddr; | |
302 | unsigned long pteval; | |
303 | ||
304 | bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT; | |
305 | ||
306 | srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size, | |
307 | SRMMU_NOCACHE_ALIGN_MAX, 0UL); | |
308 | memset(srmmu_nocache_pool, 0, srmmu_nocache_size); | |
309 | ||
54df2db3 AM |
310 | srmmu_nocache_bitmap = |
311 | __alloc_bootmem(BITS_TO_LONGS(bitmap_bits) * sizeof(long), | |
312 | SMP_CACHE_BYTES, 0UL); | |
1da177e4 LT |
313 | bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits); |
314 | ||
f71a2aac | 315 | srmmu_swapper_pg_dir = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE); |
1da177e4 LT |
316 | memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE); |
317 | init_mm.pgd = srmmu_swapper_pg_dir; | |
318 | ||
319 | srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end); | |
320 | ||
321 | paddr = __pa((unsigned long)srmmu_nocache_pool); | |
322 | vaddr = SRMMU_NOCACHE_VADDR; | |
323 | ||
324 | while (vaddr < srmmu_nocache_end) { | |
325 | pgd = pgd_offset_k(vaddr); | |
9701b264 SR |
326 | pmd = pmd_offset(__nocache_fix(pgd), vaddr); |
327 | pte = pte_offset_kernel(__nocache_fix(pmd), vaddr); | |
1da177e4 LT |
328 | |
329 | pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV); | |
330 | ||
331 | if (srmmu_cache_pagetables) | |
332 | pteval |= SRMMU_CACHE; | |
333 | ||
62875cff | 334 | set_pte(__nocache_fix(pte), __pte(pteval)); |
1da177e4 LT |
335 | |
336 | vaddr += PAGE_SIZE; | |
337 | paddr += PAGE_SIZE; | |
338 | } | |
339 | ||
340 | flush_cache_all(); | |
341 | flush_tlb_all(); | |
342 | } | |
343 | ||
642ea3ed | 344 | pgd_t *get_pgd_fast(void) |
1da177e4 LT |
345 | { |
346 | pgd_t *pgd = NULL; | |
347 | ||
f71a2aac | 348 | pgd = __srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE); |
1da177e4 LT |
349 | if (pgd) { |
350 | pgd_t *init = pgd_offset_k(0); | |
351 | memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t)); | |
352 | memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD, | |
353 | (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t)); | |
354 | } | |
355 | ||
356 | return pgd; | |
357 | } | |
358 | ||
1da177e4 LT |
359 | /* |
360 | * Hardware needs alignment to 256 only, but we align to whole page size | |
361 | * to reduce fragmentation problems due to the buddy principle. | |
362 | * XXX Provide actual fragmentation statistics in /proc. | |
363 | * | |
364 | * Alignments up to the page size are the same for physical and virtual | |
365 | * addresses of the nocache area. | |
366 | */ | |
642ea3ed | 367 | pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) |
1da177e4 LT |
368 | { |
369 | unsigned long pte; | |
2f569afd | 370 | struct page *page; |
1da177e4 | 371 | |
642ea3ed | 372 | if ((pte = (unsigned long)pte_alloc_one_kernel(mm, address)) == 0) |
1da177e4 | 373 | return NULL; |
605ae962 | 374 | page = pfn_to_page(__nocache_pa(pte) >> PAGE_SHIFT); |
1ae9ae5f KS |
375 | if (!pgtable_page_ctor(page)) { |
376 | __free_page(page); | |
377 | return NULL; | |
378 | } | |
2f569afd | 379 | return page; |
1da177e4 LT |
380 | } |
381 | ||
642ea3ed | 382 | void pte_free(struct mm_struct *mm, pgtable_t pte) |
1da177e4 LT |
383 | { |
384 | unsigned long p; | |
385 | ||
2f569afd | 386 | pgtable_page_dtor(pte); |
1da177e4 LT |
387 | p = (unsigned long)page_address(pte); /* Cached address (for test) */ |
388 | if (p == 0) | |
389 | BUG(); | |
390 | p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */ | |
f71a2aac SR |
391 | |
392 | /* free non cached virtual address*/ | |
393 | srmmu_free_nocache(__nocache_va(p), PTE_SIZE); | |
1da177e4 LT |
394 | } |
395 | ||
b585e855 SR |
396 | /* context handling - a dynamically sized pool is used */ |
397 | #define NO_CONTEXT -1 | |
398 | ||
399 | struct ctx_list { | |
400 | struct ctx_list *next; | |
401 | struct ctx_list *prev; | |
402 | unsigned int ctx_number; | |
403 | struct mm_struct *ctx_mm; | |
404 | }; | |
405 | ||
406 | static struct ctx_list *ctx_list_pool; | |
407 | static struct ctx_list ctx_free; | |
408 | static struct ctx_list ctx_used; | |
409 | ||
410 | /* At boot time we determine the number of contexts */ | |
411 | static int num_contexts; | |
412 | ||
413 | static inline void remove_from_ctx_list(struct ctx_list *entry) | |
414 | { | |
415 | entry->next->prev = entry->prev; | |
416 | entry->prev->next = entry->next; | |
417 | } | |
418 | ||
419 | static inline void add_to_ctx_list(struct ctx_list *head, struct ctx_list *entry) | |
420 | { | |
421 | entry->next = head; | |
422 | (entry->prev = head->prev)->next = entry; | |
423 | head->prev = entry; | |
424 | } | |
425 | #define add_to_free_ctxlist(entry) add_to_ctx_list(&ctx_free, entry) | |
426 | #define add_to_used_ctxlist(entry) add_to_ctx_list(&ctx_used, entry) | |
427 | ||
428 | ||
1da177e4 LT |
429 | static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm) |
430 | { | |
431 | struct ctx_list *ctxp; | |
432 | ||
433 | ctxp = ctx_free.next; | |
605ae962 | 434 | if (ctxp != &ctx_free) { |
1da177e4 LT |
435 | remove_from_ctx_list(ctxp); |
436 | add_to_used_ctxlist(ctxp); | |
437 | mm->context = ctxp->ctx_number; | |
438 | ctxp->ctx_mm = mm; | |
439 | return; | |
440 | } | |
441 | ctxp = ctx_used.next; | |
605ae962 | 442 | if (ctxp->ctx_mm == old_mm) |
1da177e4 | 443 | ctxp = ctxp->next; |
605ae962 | 444 | if (ctxp == &ctx_used) |
1da177e4 LT |
445 | panic("out of mmu contexts"); |
446 | flush_cache_mm(ctxp->ctx_mm); | |
447 | flush_tlb_mm(ctxp->ctx_mm); | |
448 | remove_from_ctx_list(ctxp); | |
449 | add_to_used_ctxlist(ctxp); | |
450 | ctxp->ctx_mm->context = NO_CONTEXT; | |
451 | ctxp->ctx_mm = mm; | |
452 | mm->context = ctxp->ctx_number; | |
453 | } | |
454 | ||
455 | static inline void free_context(int context) | |
456 | { | |
457 | struct ctx_list *ctx_old; | |
458 | ||
459 | ctx_old = ctx_list_pool + context; | |
460 | remove_from_ctx_list(ctx_old); | |
461 | add_to_free_ctxlist(ctx_old); | |
462 | } | |
463 | ||
b585e855 SR |
464 | static void __init sparc_context_init(int numctx) |
465 | { | |
466 | int ctx; | |
467 | unsigned long size; | |
468 | ||
469 | size = numctx * sizeof(struct ctx_list); | |
470 | ctx_list_pool = __alloc_bootmem(size, SMP_CACHE_BYTES, 0UL); | |
471 | ||
472 | for (ctx = 0; ctx < numctx; ctx++) { | |
473 | struct ctx_list *clist; | |
474 | ||
475 | clist = (ctx_list_pool + ctx); | |
476 | clist->ctx_number = ctx; | |
477 | clist->ctx_mm = NULL; | |
478 | } | |
479 | ctx_free.next = ctx_free.prev = &ctx_free; | |
480 | ctx_used.next = ctx_used.prev = &ctx_used; | |
481 | for (ctx = 0; ctx < numctx; ctx++) | |
482 | add_to_free_ctxlist(ctx_list_pool + ctx); | |
483 | } | |
1da177e4 | 484 | |
34d4accf SR |
485 | void switch_mm(struct mm_struct *old_mm, struct mm_struct *mm, |
486 | struct task_struct *tsk) | |
1da177e4 | 487 | { |
66d0f7ec AL |
488 | unsigned long flags; |
489 | ||
605ae962 | 490 | if (mm->context == NO_CONTEXT) { |
66d0f7ec | 491 | spin_lock_irqsave(&srmmu_context_spinlock, flags); |
1da177e4 | 492 | alloc_context(old_mm, mm); |
66d0f7ec | 493 | spin_unlock_irqrestore(&srmmu_context_spinlock, flags); |
1da177e4 LT |
494 | srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd); |
495 | } | |
496 | ||
75d9e346 KE |
497 | if (sparc_cpu_model == sparc_leon) |
498 | leon_switch_mm(); | |
499 | ||
1da177e4 LT |
500 | if (is_hypersparc) |
501 | hyper_flush_whole_icache(); | |
502 | ||
503 | srmmu_set_context(mm->context); | |
504 | } | |
505 | ||
506 | /* Low level IO area allocation on the SRMMU. */ | |
507 | static inline void srmmu_mapioaddr(unsigned long physaddr, | |
605ae962 | 508 | unsigned long virt_addr, int bus_type) |
1da177e4 LT |
509 | { |
510 | pgd_t *pgdp; | |
511 | pmd_t *pmdp; | |
512 | pte_t *ptep; | |
513 | unsigned long tmp; | |
514 | ||
515 | physaddr &= PAGE_MASK; | |
516 | pgdp = pgd_offset_k(virt_addr); | |
9701b264 SR |
517 | pmdp = pmd_offset(pgdp, virt_addr); |
518 | ptep = pte_offset_kernel(pmdp, virt_addr); | |
1da177e4 LT |
519 | tmp = (physaddr >> 4) | SRMMU_ET_PTE; |
520 | ||
605ae962 | 521 | /* I need to test whether this is consistent over all |
1da177e4 LT |
522 | * sun4m's. The bus_type represents the upper 4 bits of |
523 | * 36-bit physical address on the I/O space lines... | |
524 | */ | |
525 | tmp |= (bus_type << 28); | |
526 | tmp |= SRMMU_PRIV; | |
527 | __flush_page_to_ram(virt_addr); | |
62875cff | 528 | set_pte(ptep, __pte(tmp)); |
1da177e4 LT |
529 | } |
530 | ||
9701b264 SR |
531 | void srmmu_mapiorange(unsigned int bus, unsigned long xpa, |
532 | unsigned long xva, unsigned int len) | |
1da177e4 LT |
533 | { |
534 | while (len != 0) { | |
535 | len -= PAGE_SIZE; | |
536 | srmmu_mapioaddr(xpa, xva, bus); | |
537 | xva += PAGE_SIZE; | |
538 | xpa += PAGE_SIZE; | |
539 | } | |
540 | flush_tlb_all(); | |
541 | } | |
542 | ||
543 | static inline void srmmu_unmapioaddr(unsigned long virt_addr) | |
544 | { | |
545 | pgd_t *pgdp; | |
546 | pmd_t *pmdp; | |
547 | pte_t *ptep; | |
548 | ||
549 | pgdp = pgd_offset_k(virt_addr); | |
9701b264 SR |
550 | pmdp = pmd_offset(pgdp, virt_addr); |
551 | ptep = pte_offset_kernel(pmdp, virt_addr); | |
1da177e4 LT |
552 | |
553 | /* No need to flush uncacheable page. */ | |
a46d6056 | 554 | __pte_clear(ptep); |
1da177e4 LT |
555 | } |
556 | ||
9701b264 | 557 | void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len) |
1da177e4 LT |
558 | { |
559 | while (len != 0) { | |
560 | len -= PAGE_SIZE; | |
561 | srmmu_unmapioaddr(virt_addr); | |
562 | virt_addr += PAGE_SIZE; | |
563 | } | |
564 | flush_tlb_all(); | |
565 | } | |
566 | ||
1da177e4 LT |
567 | /* tsunami.S */ |
568 | extern void tsunami_flush_cache_all(void); | |
569 | extern void tsunami_flush_cache_mm(struct mm_struct *mm); | |
570 | extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | |
571 | extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page); | |
572 | extern void tsunami_flush_page_to_ram(unsigned long page); | |
573 | extern void tsunami_flush_page_for_dma(unsigned long page); | |
574 | extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); | |
575 | extern void tsunami_flush_tlb_all(void); | |
576 | extern void tsunami_flush_tlb_mm(struct mm_struct *mm); | |
577 | extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | |
578 | extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); | |
579 | extern void tsunami_setup_blockops(void); | |
580 | ||
1da177e4 LT |
581 | /* swift.S */ |
582 | extern void swift_flush_cache_all(void); | |
583 | extern void swift_flush_cache_mm(struct mm_struct *mm); | |
584 | extern void swift_flush_cache_range(struct vm_area_struct *vma, | |
585 | unsigned long start, unsigned long end); | |
586 | extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page); | |
587 | extern void swift_flush_page_to_ram(unsigned long page); | |
588 | extern void swift_flush_page_for_dma(unsigned long page); | |
589 | extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); | |
590 | extern void swift_flush_tlb_all(void); | |
591 | extern void swift_flush_tlb_mm(struct mm_struct *mm); | |
592 | extern void swift_flush_tlb_range(struct vm_area_struct *vma, | |
593 | unsigned long start, unsigned long end); | |
594 | extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); | |
595 | ||
596 | #if 0 /* P3: deadwood to debug precise flushes on Swift. */ | |
597 | void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
598 | { | |
599 | int cctx, ctx1; | |
600 | ||
601 | page &= PAGE_MASK; | |
602 | if ((ctx1 = vma->vm_mm->context) != -1) { | |
603 | cctx = srmmu_get_context(); | |
604 | /* Is context # ever different from current context? P3 */ | |
605 | if (cctx != ctx1) { | |
606 | printk("flush ctx %02x curr %02x\n", ctx1, cctx); | |
607 | srmmu_set_context(ctx1); | |
608 | swift_flush_page(page); | |
609 | __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : | |
610 | "r" (page), "i" (ASI_M_FLUSH_PROBE)); | |
611 | srmmu_set_context(cctx); | |
612 | } else { | |
613 | /* Rm. prot. bits from virt. c. */ | |
614 | /* swift_flush_cache_all(); */ | |
615 | /* swift_flush_cache_page(vma, page); */ | |
616 | swift_flush_page(page); | |
617 | ||
618 | __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : | |
619 | "r" (page), "i" (ASI_M_FLUSH_PROBE)); | |
620 | /* same as above: srmmu_flush_tlb_page() */ | |
621 | } | |
622 | } | |
623 | } | |
624 | #endif | |
625 | ||
626 | /* | |
627 | * The following are all MBUS based SRMMU modules, and therefore could | |
628 | * be found in a multiprocessor configuration. On the whole, these | |
629 | * chips seems to be much more touchy about DVMA and page tables | |
630 | * with respect to cache coherency. | |
631 | */ | |
632 | ||
1da177e4 LT |
633 | /* viking.S */ |
634 | extern void viking_flush_cache_all(void); | |
635 | extern void viking_flush_cache_mm(struct mm_struct *mm); | |
636 | extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start, | |
637 | unsigned long end); | |
638 | extern void viking_flush_cache_page(struct vm_area_struct *vma, unsigned long page); | |
639 | extern void viking_flush_page_to_ram(unsigned long page); | |
640 | extern void viking_flush_page_for_dma(unsigned long page); | |
641 | extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr); | |
642 | extern void viking_flush_page(unsigned long page); | |
643 | extern void viking_mxcc_flush_page(unsigned long page); | |
644 | extern void viking_flush_tlb_all(void); | |
645 | extern void viking_flush_tlb_mm(struct mm_struct *mm); | |
646 | extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
647 | unsigned long end); | |
648 | extern void viking_flush_tlb_page(struct vm_area_struct *vma, | |
649 | unsigned long page); | |
650 | extern void sun4dsmp_flush_tlb_all(void); | |
651 | extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm); | |
652 | extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |
653 | unsigned long end); | |
654 | extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma, | |
655 | unsigned long page); | |
656 | ||
657 | /* hypersparc.S */ | |
658 | extern void hypersparc_flush_cache_all(void); | |
659 | extern void hypersparc_flush_cache_mm(struct mm_struct *mm); | |
660 | extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | |
661 | extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page); | |
662 | extern void hypersparc_flush_page_to_ram(unsigned long page); | |
663 | extern void hypersparc_flush_page_for_dma(unsigned long page); | |
664 | extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr); | |
665 | extern void hypersparc_flush_tlb_all(void); | |
666 | extern void hypersparc_flush_tlb_mm(struct mm_struct *mm); | |
667 | extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end); | |
668 | extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page); | |
669 | extern void hypersparc_setup_blockops(void); | |
670 | ||
671 | /* | |
672 | * NOTE: All of this startup code assumes the low 16mb (approx.) of | |
673 | * kernel mappings are done with one single contiguous chunk of | |
674 | * ram. On small ram machines (classics mainly) we only get | |
675 | * around 8mb mapped for us. | |
676 | */ | |
677 | ||
50215d65 | 678 | static void __init early_pgtable_allocfail(char *type) |
1da177e4 LT |
679 | { |
680 | prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type); | |
681 | prom_halt(); | |
682 | } | |
683 | ||
50215d65 AB |
684 | static void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, |
685 | unsigned long end) | |
1da177e4 LT |
686 | { |
687 | pgd_t *pgdp; | |
688 | pmd_t *pmdp; | |
689 | pte_t *ptep; | |
690 | ||
605ae962 | 691 | while (start < end) { |
1da177e4 | 692 | pgdp = pgd_offset_k(start); |
7d9fa4aa | 693 | if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { |
f71a2aac | 694 | pmdp = __srmmu_get_nocache( |
1da177e4 LT |
695 | SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); |
696 | if (pmdp == NULL) | |
697 | early_pgtable_allocfail("pmd"); | |
698 | memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); | |
642ea3ed | 699 | pgd_set(__nocache_fix(pgdp), pmdp); |
1da177e4 | 700 | } |
9701b264 | 701 | pmdp = pmd_offset(__nocache_fix(pgdp), start); |
605ae962 | 702 | if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) { |
f71a2aac | 703 | ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); |
1da177e4 LT |
704 | if (ptep == NULL) |
705 | early_pgtable_allocfail("pte"); | |
706 | memset(__nocache_fix(ptep), 0, PTE_SIZE); | |
642ea3ed | 707 | pmd_set(__nocache_fix(pmdp), ptep); |
1da177e4 LT |
708 | } |
709 | if (start > (0xffffffffUL - PMD_SIZE)) | |
710 | break; | |
711 | start = (start + PMD_SIZE) & PMD_MASK; | |
712 | } | |
713 | } | |
714 | ||
50215d65 AB |
715 | static void __init srmmu_allocate_ptable_skeleton(unsigned long start, |
716 | unsigned long end) | |
1da177e4 LT |
717 | { |
718 | pgd_t *pgdp; | |
719 | pmd_t *pmdp; | |
720 | pte_t *ptep; | |
721 | ||
605ae962 | 722 | while (start < end) { |
1da177e4 | 723 | pgdp = pgd_offset_k(start); |
7d9fa4aa | 724 | if (pgd_none(*pgdp)) { |
f71a2aac | 725 | pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE); |
1da177e4 LT |
726 | if (pmdp == NULL) |
727 | early_pgtable_allocfail("pmd"); | |
728 | memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE); | |
642ea3ed | 729 | pgd_set(pgdp, pmdp); |
1da177e4 | 730 | } |
9701b264 | 731 | pmdp = pmd_offset(pgdp, start); |
605ae962 | 732 | if (srmmu_pmd_none(*pmdp)) { |
f71a2aac | 733 | ptep = __srmmu_get_nocache(PTE_SIZE, |
1da177e4 LT |
734 | PTE_SIZE); |
735 | if (ptep == NULL) | |
736 | early_pgtable_allocfail("pte"); | |
737 | memset(ptep, 0, PTE_SIZE); | |
642ea3ed | 738 | pmd_set(pmdp, ptep); |
1da177e4 LT |
739 | } |
740 | if (start > (0xffffffffUL - PMD_SIZE)) | |
741 | break; | |
742 | start = (start + PMD_SIZE) & PMD_MASK; | |
743 | } | |
744 | } | |
745 | ||
805918f8 SR |
746 | /* These flush types are not available on all chips... */ |
747 | static inline unsigned long srmmu_probe(unsigned long vaddr) | |
748 | { | |
749 | unsigned long retval; | |
750 | ||
751 | if (sparc_cpu_model != sparc_leon) { | |
752 | ||
753 | vaddr &= PAGE_MASK; | |
754 | __asm__ __volatile__("lda [%1] %2, %0\n\t" : | |
755 | "=r" (retval) : | |
756 | "r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE)); | |
757 | } else { | |
e8c29c83 | 758 | retval = leon_swprobe(vaddr, NULL); |
805918f8 SR |
759 | } |
760 | return retval; | |
761 | } | |
762 | ||
1da177e4 LT |
763 | /* |
764 | * This is much cleaner than poking around physical address space | |
765 | * looking at the prom's page table directly which is what most | |
766 | * other OS's do. Yuck... this is much better. | |
767 | */ | |
50215d65 AB |
768 | static void __init srmmu_inherit_prom_mappings(unsigned long start, |
769 | unsigned long end) | |
1da177e4 | 770 | { |
7cdfbc74 SR |
771 | unsigned long probed; |
772 | unsigned long addr; | |
1da177e4 LT |
773 | pgd_t *pgdp; |
774 | pmd_t *pmdp; | |
775 | pte_t *ptep; | |
7cdfbc74 | 776 | int what; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */ |
1da177e4 | 777 | |
605ae962 | 778 | while (start <= end) { |
1da177e4 LT |
779 | if (start == 0) |
780 | break; /* probably wrap around */ | |
605ae962 | 781 | if (start == 0xfef00000) |
1da177e4 | 782 | start = KADB_DEBUGGER_BEGVM; |
7cdfbc74 SR |
783 | probed = srmmu_probe(start); |
784 | if (!probed) { | |
785 | /* continue probing until we find an entry */ | |
1da177e4 LT |
786 | start += PAGE_SIZE; |
787 | continue; | |
788 | } | |
605ae962 | 789 | |
1da177e4 LT |
790 | /* A red snapper, see what it really is. */ |
791 | what = 0; | |
7cdfbc74 | 792 | addr = start - PAGE_SIZE; |
605ae962 SR |
793 | |
794 | if (!(start & ~(SRMMU_REAL_PMD_MASK))) { | |
7cdfbc74 | 795 | if (srmmu_probe(addr + SRMMU_REAL_PMD_SIZE) == probed) |
1da177e4 LT |
796 | what = 1; |
797 | } | |
605ae962 SR |
798 | |
799 | if (!(start & ~(SRMMU_PGDIR_MASK))) { | |
7cdfbc74 | 800 | if (srmmu_probe(addr + SRMMU_PGDIR_SIZE) == probed) |
1da177e4 LT |
801 | what = 2; |
802 | } | |
605ae962 | 803 | |
1da177e4 | 804 | pgdp = pgd_offset_k(start); |
605ae962 | 805 | if (what == 2) { |
7cdfbc74 | 806 | *(pgd_t *)__nocache_fix(pgdp) = __pgd(probed); |
1da177e4 LT |
807 | start += SRMMU_PGDIR_SIZE; |
808 | continue; | |
809 | } | |
7d9fa4aa | 810 | if (pgd_none(*(pgd_t *)__nocache_fix(pgdp))) { |
7cdfbc74 SR |
811 | pmdp = __srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, |
812 | SRMMU_PMD_TABLE_SIZE); | |
1da177e4 LT |
813 | if (pmdp == NULL) |
814 | early_pgtable_allocfail("pmd"); | |
815 | memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE); | |
642ea3ed | 816 | pgd_set(__nocache_fix(pgdp), pmdp); |
1da177e4 | 817 | } |
9701b264 | 818 | pmdp = pmd_offset(__nocache_fix(pgdp), start); |
605ae962 | 819 | if (srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) { |
f71a2aac | 820 | ptep = __srmmu_get_nocache(PTE_SIZE, PTE_SIZE); |
1da177e4 LT |
821 | if (ptep == NULL) |
822 | early_pgtable_allocfail("pte"); | |
823 | memset(__nocache_fix(ptep), 0, PTE_SIZE); | |
642ea3ed | 824 | pmd_set(__nocache_fix(pmdp), ptep); |
1da177e4 | 825 | } |
605ae962 SR |
826 | if (what == 1) { |
827 | /* We bend the rule where all 16 PTPs in a pmd_t point | |
1da177e4 LT |
828 | * inside the same PTE page, and we leak a perfectly |
829 | * good hardware PTE piece. Alternatives seem worse. | |
830 | */ | |
831 | unsigned int x; /* Index of HW PMD in soft cluster */ | |
7cdfbc74 | 832 | unsigned long *val; |
1da177e4 | 833 | x = (start >> PMD_SHIFT) & 15; |
7cdfbc74 SR |
834 | val = &pmdp->pmdv[x]; |
835 | *(unsigned long *)__nocache_fix(val) = probed; | |
1da177e4 LT |
836 | start += SRMMU_REAL_PMD_SIZE; |
837 | continue; | |
838 | } | |
9701b264 | 839 | ptep = pte_offset_kernel(__nocache_fix(pmdp), start); |
7cdfbc74 | 840 | *(pte_t *)__nocache_fix(ptep) = __pte(probed); |
1da177e4 LT |
841 | start += PAGE_SIZE; |
842 | } | |
843 | } | |
844 | ||
845 | #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID) | |
846 | ||
847 | /* Create a third-level SRMMU 16MB page mapping. */ | |
848 | static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base) | |
849 | { | |
850 | pgd_t *pgdp = pgd_offset_k(vaddr); | |
851 | unsigned long big_pte; | |
852 | ||
853 | big_pte = KERNEL_PTE(phys_base >> 4); | |
854 | *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte); | |
855 | } | |
856 | ||
857 | /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */ | |
858 | static unsigned long __init map_spbank(unsigned long vbase, int sp_entry) | |
859 | { | |
860 | unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK); | |
861 | unsigned long vstart = (vbase & SRMMU_PGDIR_MASK); | |
862 | unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes); | |
863 | /* Map "low" memory only */ | |
864 | const unsigned long min_vaddr = PAGE_OFFSET; | |
865 | const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM; | |
866 | ||
867 | if (vstart < min_vaddr || vstart >= max_vaddr) | |
868 | return vstart; | |
605ae962 | 869 | |
1da177e4 LT |
870 | if (vend > max_vaddr || vend < min_vaddr) |
871 | vend = max_vaddr; | |
872 | ||
605ae962 | 873 | while (vstart < vend) { |
1da177e4 LT |
874 | do_large_mapping(vstart, pstart); |
875 | vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE; | |
876 | } | |
877 | return vstart; | |
878 | } | |
879 | ||
32442467 | 880 | static void __init map_kernel(void) |
1da177e4 LT |
881 | { |
882 | int i; | |
883 | ||
884 | if (phys_base > 0) { | |
885 | do_large_mapping(PAGE_OFFSET, phys_base); | |
886 | } | |
887 | ||
888 | for (i = 0; sp_banks[i].num_bytes != 0; i++) { | |
889 | map_spbank((unsigned long)__va(sp_banks[i].base_addr), i); | |
890 | } | |
1da177e4 LT |
891 | } |
892 | ||
2066aadd | 893 | void (*poke_srmmu)(void) = NULL; |
1da177e4 | 894 | |
1da177e4 LT |
895 | void __init srmmu_paging_init(void) |
896 | { | |
8d125562 AS |
897 | int i; |
898 | phandle cpunode; | |
1da177e4 LT |
899 | char node_str[128]; |
900 | pgd_t *pgd; | |
901 | pmd_t *pmd; | |
902 | pte_t *pte; | |
903 | unsigned long pages_avail; | |
904 | ||
b585e855 | 905 | init_mm.context = (unsigned long) NO_CONTEXT; |
1da177e4 LT |
906 | sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */ |
907 | ||
908 | if (sparc_cpu_model == sun4d) | |
909 | num_contexts = 65536; /* We know it is Viking */ | |
910 | else { | |
911 | /* Find the number of contexts on the srmmu. */ | |
912 | cpunode = prom_getchild(prom_root_node); | |
913 | num_contexts = 0; | |
605ae962 | 914 | while (cpunode != 0) { |
1da177e4 | 915 | prom_getstring(cpunode, "device_type", node_str, sizeof(node_str)); |
605ae962 | 916 | if (!strcmp(node_str, "cpu")) { |
1da177e4 LT |
917 | num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8); |
918 | break; | |
919 | } | |
920 | cpunode = prom_getsibling(cpunode); | |
921 | } | |
922 | } | |
923 | ||
605ae962 | 924 | if (!num_contexts) { |
1da177e4 LT |
925 | prom_printf("Something wrong, can't find cpu node in paging_init.\n"); |
926 | prom_halt(); | |
927 | } | |
928 | ||
929 | pages_avail = 0; | |
930 | last_valid_pfn = bootmem_init(&pages_avail); | |
931 | ||
932 | srmmu_nocache_calcsize(); | |
933 | srmmu_nocache_init(); | |
f71a2aac | 934 | srmmu_inherit_prom_mappings(0xfe400000, (LINUX_OPPROM_ENDVM - PAGE_SIZE)); |
1da177e4 LT |
935 | map_kernel(); |
936 | ||
937 | /* ctx table has to be physically aligned to its size */ | |
f71a2aac | 938 | srmmu_context_table = __srmmu_get_nocache(num_contexts * sizeof(ctxd_t), num_contexts * sizeof(ctxd_t)); |
6b1cabe8 | 939 | srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa(srmmu_context_table); |
1da177e4 | 940 | |
605ae962 | 941 | for (i = 0; i < num_contexts; i++) |
1da177e4 LT |
942 | srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir); |
943 | ||
944 | flush_cache_all(); | |
945 | srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys); | |
a54123e2 BB |
946 | #ifdef CONFIG_SMP |
947 | /* Stop from hanging here... */ | |
5d83d666 | 948 | local_ops->tlb_all(); |
a54123e2 | 949 | #else |
1da177e4 | 950 | flush_tlb_all(); |
a54123e2 | 951 | #endif |
1da177e4 LT |
952 | poke_srmmu(); |
953 | ||
1da177e4 LT |
954 | srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END); |
955 | srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END); | |
1da177e4 LT |
956 | |
957 | srmmu_allocate_ptable_skeleton( | |
958 | __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP); | |
959 | srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END); | |
960 | ||
961 | pgd = pgd_offset_k(PKMAP_BASE); | |
9701b264 SR |
962 | pmd = pmd_offset(pgd, PKMAP_BASE); |
963 | pte = pte_offset_kernel(pmd, PKMAP_BASE); | |
1da177e4 LT |
964 | pkmap_page_table = pte; |
965 | ||
966 | flush_cache_all(); | |
967 | flush_tlb_all(); | |
968 | ||
969 | sparc_context_init(num_contexts); | |
970 | ||
971 | kmap_init(); | |
972 | ||
973 | { | |
974 | unsigned long zones_size[MAX_NR_ZONES]; | |
975 | unsigned long zholes_size[MAX_NR_ZONES]; | |
976 | unsigned long npages; | |
977 | int znum; | |
978 | ||
979 | for (znum = 0; znum < MAX_NR_ZONES; znum++) | |
980 | zones_size[znum] = zholes_size[znum] = 0; | |
981 | ||
982 | npages = max_low_pfn - pfn_base; | |
983 | ||
984 | zones_size[ZONE_DMA] = npages; | |
985 | zholes_size[ZONE_DMA] = npages - pages_avail; | |
986 | ||
987 | npages = highend_pfn - max_low_pfn; | |
988 | zones_size[ZONE_HIGHMEM] = npages; | |
989 | zholes_size[ZONE_HIGHMEM] = npages - calc_highpages(); | |
990 | ||
9109fb7b | 991 | free_area_init_node(0, zones_size, pfn_base, zholes_size); |
1da177e4 LT |
992 | } |
993 | } | |
994 | ||
9701b264 | 995 | void mmu_info(struct seq_file *m) |
1da177e4 | 996 | { |
605ae962 | 997 | seq_printf(m, |
1da177e4 LT |
998 | "MMU type\t: %s\n" |
999 | "contexts\t: %d\n" | |
1000 | "nocache total\t: %ld\n" | |
1001 | "nocache used\t: %d\n", | |
1002 | srmmu_name, | |
1003 | num_contexts, | |
1004 | srmmu_nocache_size, | |
1005 | srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT); | |
1006 | } | |
1007 | ||
b585e855 SR |
1008 | int init_new_context(struct task_struct *tsk, struct mm_struct *mm) |
1009 | { | |
1010 | mm->context = NO_CONTEXT; | |
1011 | return 0; | |
1012 | } | |
1013 | ||
b796c6da | 1014 | void destroy_context(struct mm_struct *mm) |
1da177e4 | 1015 | { |
66d0f7ec | 1016 | unsigned long flags; |
1da177e4 | 1017 | |
605ae962 | 1018 | if (mm->context != NO_CONTEXT) { |
1da177e4 LT |
1019 | flush_cache_mm(mm); |
1020 | srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir); | |
1021 | flush_tlb_mm(mm); | |
66d0f7ec | 1022 | spin_lock_irqsave(&srmmu_context_spinlock, flags); |
1da177e4 | 1023 | free_context(mm->context); |
66d0f7ec | 1024 | spin_unlock_irqrestore(&srmmu_context_spinlock, flags); |
1da177e4 LT |
1025 | mm->context = NO_CONTEXT; |
1026 | } | |
1027 | } | |
1028 | ||
1029 | /* Init various srmmu chip types. */ | |
1030 | static void __init srmmu_is_bad(void) | |
1031 | { | |
1032 | prom_printf("Could not determine SRMMU chip type.\n"); | |
1033 | prom_halt(); | |
1034 | } | |
1035 | ||
1036 | static void __init init_vac_layout(void) | |
1037 | { | |
8d125562 AS |
1038 | phandle nd; |
1039 | int cache_lines; | |
1da177e4 LT |
1040 | char node_str[128]; |
1041 | #ifdef CONFIG_SMP | |
1042 | int cpu = 0; | |
1043 | unsigned long max_size = 0; | |
1044 | unsigned long min_line_size = 0x10000000; | |
1045 | #endif | |
1046 | ||
1047 | nd = prom_getchild(prom_root_node); | |
605ae962 | 1048 | while ((nd = prom_getsibling(nd)) != 0) { |
1da177e4 | 1049 | prom_getstring(nd, "device_type", node_str, sizeof(node_str)); |
605ae962 | 1050 | if (!strcmp(node_str, "cpu")) { |
1da177e4 LT |
1051 | vac_line_size = prom_getint(nd, "cache-line-size"); |
1052 | if (vac_line_size == -1) { | |
605ae962 | 1053 | prom_printf("can't determine cache-line-size, halting.\n"); |
1da177e4 LT |
1054 | prom_halt(); |
1055 | } | |
1056 | cache_lines = prom_getint(nd, "cache-nlines"); | |
1057 | if (cache_lines == -1) { | |
1058 | prom_printf("can't determine cache-nlines, halting.\n"); | |
1059 | prom_halt(); | |
1060 | } | |
1061 | ||
1062 | vac_cache_size = cache_lines * vac_line_size; | |
1063 | #ifdef CONFIG_SMP | |
605ae962 | 1064 | if (vac_cache_size > max_size) |
1da177e4 | 1065 | max_size = vac_cache_size; |
605ae962 | 1066 | if (vac_line_size < min_line_size) |
1da177e4 | 1067 | min_line_size = vac_line_size; |
a54123e2 | 1068 | //FIXME: cpus not contiguous!! |
1da177e4 | 1069 | cpu++; |
ec7c14bd | 1070 | if (cpu >= nr_cpu_ids || !cpu_online(cpu)) |
1da177e4 LT |
1071 | break; |
1072 | #else | |
1073 | break; | |
1074 | #endif | |
1075 | } | |
1076 | } | |
605ae962 | 1077 | if (nd == 0) { |
1da177e4 LT |
1078 | prom_printf("No CPU nodes found, halting.\n"); |
1079 | prom_halt(); | |
1080 | } | |
1081 | #ifdef CONFIG_SMP | |
1082 | vac_cache_size = max_size; | |
1083 | vac_line_size = min_line_size; | |
1084 | #endif | |
1085 | printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n", | |
1086 | (int)vac_cache_size, (int)vac_line_size); | |
1087 | } | |
1088 | ||
2066aadd | 1089 | static void poke_hypersparc(void) |
1da177e4 LT |
1090 | { |
1091 | volatile unsigned long clear; | |
1092 | unsigned long mreg = srmmu_get_mmureg(); | |
1093 | ||
1094 | hyper_flush_unconditional_combined(); | |
1095 | ||
1096 | mreg &= ~(HYPERSPARC_CWENABLE); | |
1097 | mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE); | |
1098 | mreg |= (HYPERSPARC_CMODE); | |
1099 | ||
1100 | srmmu_set_mmureg(mreg); | |
1101 | ||
1102 | #if 0 /* XXX I think this is bad news... -DaveM */ | |
1103 | hyper_clear_all_tags(); | |
1104 | #endif | |
1105 | ||
1106 | put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE); | |
1107 | hyper_flush_whole_icache(); | |
1108 | clear = srmmu_get_faddr(); | |
1109 | clear = srmmu_get_fstatus(); | |
1110 | } | |
1111 | ||
5d83d666 DM |
1112 | static const struct sparc32_cachetlb_ops hypersparc_ops = { |
1113 | .cache_all = hypersparc_flush_cache_all, | |
1114 | .cache_mm = hypersparc_flush_cache_mm, | |
1115 | .cache_page = hypersparc_flush_cache_page, | |
1116 | .cache_range = hypersparc_flush_cache_range, | |
1117 | .tlb_all = hypersparc_flush_tlb_all, | |
1118 | .tlb_mm = hypersparc_flush_tlb_mm, | |
1119 | .tlb_page = hypersparc_flush_tlb_page, | |
1120 | .tlb_range = hypersparc_flush_tlb_range, | |
1121 | .page_to_ram = hypersparc_flush_page_to_ram, | |
1122 | .sig_insns = hypersparc_flush_sig_insns, | |
1123 | .page_for_dma = hypersparc_flush_page_for_dma, | |
1124 | }; | |
1125 | ||
1da177e4 LT |
1126 | static void __init init_hypersparc(void) |
1127 | { | |
1128 | srmmu_name = "ROSS HyperSparc"; | |
1129 | srmmu_modtype = HyperSparc; | |
1130 | ||
1131 | init_vac_layout(); | |
1132 | ||
1133 | is_hypersparc = 1; | |
5d83d666 | 1134 | sparc32_cachetlb_ops = &hypersparc_ops; |
1da177e4 LT |
1135 | |
1136 | poke_srmmu = poke_hypersparc; | |
1137 | ||
1138 | hypersparc_setup_blockops(); | |
1139 | } | |
1140 | ||
2066aadd | 1141 | static void poke_swift(void) |
1da177e4 LT |
1142 | { |
1143 | unsigned long mreg; | |
1144 | ||
1145 | /* Clear any crap from the cache or else... */ | |
1146 | swift_flush_cache_all(); | |
1147 | ||
1148 | /* Enable I & D caches */ | |
1149 | mreg = srmmu_get_mmureg(); | |
1150 | mreg |= (SWIFT_IE | SWIFT_DE); | |
1151 | /* | |
1152 | * The Swift branch folding logic is completely broken. At | |
1153 | * trap time, if things are just right, if can mistakenly | |
1154 | * think that a trap is coming from kernel mode when in fact | |
1155 | * it is coming from user mode (it mis-executes the branch in | |
1156 | * the trap code). So you see things like crashme completely | |
1157 | * hosing your machine which is completely unacceptable. Turn | |
1158 | * this shit off... nice job Fujitsu. | |
1159 | */ | |
1160 | mreg &= ~(SWIFT_BF); | |
1161 | srmmu_set_mmureg(mreg); | |
1162 | } | |
1163 | ||
5d83d666 DM |
1164 | static const struct sparc32_cachetlb_ops swift_ops = { |
1165 | .cache_all = swift_flush_cache_all, | |
1166 | .cache_mm = swift_flush_cache_mm, | |
1167 | .cache_page = swift_flush_cache_page, | |
1168 | .cache_range = swift_flush_cache_range, | |
1169 | .tlb_all = swift_flush_tlb_all, | |
1170 | .tlb_mm = swift_flush_tlb_mm, | |
1171 | .tlb_page = swift_flush_tlb_page, | |
1172 | .tlb_range = swift_flush_tlb_range, | |
1173 | .page_to_ram = swift_flush_page_to_ram, | |
1174 | .sig_insns = swift_flush_sig_insns, | |
1175 | .page_for_dma = swift_flush_page_for_dma, | |
1176 | }; | |
1177 | ||
1da177e4 LT |
1178 | #define SWIFT_MASKID_ADDR 0x10003018 |
1179 | static void __init init_swift(void) | |
1180 | { | |
1181 | unsigned long swift_rev; | |
1182 | ||
1183 | __asm__ __volatile__("lda [%1] %2, %0\n\t" | |
1184 | "srl %0, 0x18, %0\n\t" : | |
1185 | "=r" (swift_rev) : | |
1186 | "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS)); | |
1187 | srmmu_name = "Fujitsu Swift"; | |
605ae962 | 1188 | switch (swift_rev) { |
1da177e4 LT |
1189 | case 0x11: |
1190 | case 0x20: | |
1191 | case 0x23: | |
1192 | case 0x30: | |
1193 | srmmu_modtype = Swift_lots_o_bugs; | |
1194 | hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN); | |
1195 | /* | |
1196 | * Gee george, I wonder why Sun is so hush hush about | |
1197 | * this hardware bug... really braindamage stuff going | |
1198 | * on here. However I think we can find a way to avoid | |
1199 | * all of the workaround overhead under Linux. Basically, | |
1200 | * any page fault can cause kernel pages to become user | |
1201 | * accessible (the mmu gets confused and clears some of | |
1202 | * the ACC bits in kernel ptes). Aha, sounds pretty | |
1203 | * horrible eh? But wait, after extensive testing it appears | |
1204 | * that if you use pgd_t level large kernel pte's (like the | |
1205 | * 4MB pages on the Pentium) the bug does not get tripped | |
1206 | * at all. This avoids almost all of the major overhead. | |
1207 | * Welcome to a world where your vendor tells you to, | |
1208 | * "apply this kernel patch" instead of "sorry for the | |
1209 | * broken hardware, send it back and we'll give you | |
1210 | * properly functioning parts" | |
1211 | */ | |
1212 | break; | |
1213 | case 0x25: | |
1214 | case 0x31: | |
1215 | srmmu_modtype = Swift_bad_c; | |
1216 | hwbug_bitmask |= HWBUG_KERN_CBITBROKEN; | |
1217 | /* | |
1218 | * You see Sun allude to this hardware bug but never | |
1219 | * admit things directly, they'll say things like, | |
1220 | * "the Swift chip cache problems" or similar. | |
1221 | */ | |
1222 | break; | |
1223 | default: | |
1224 | srmmu_modtype = Swift_ok; | |
1225 | break; | |
6cb79b3f | 1226 | } |
1da177e4 | 1227 | |
5d83d666 | 1228 | sparc32_cachetlb_ops = &swift_ops; |
1da177e4 LT |
1229 | flush_page_for_dma_global = 0; |
1230 | ||
1231 | /* | |
1232 | * Are you now convinced that the Swift is one of the | |
1233 | * biggest VLSI abortions of all time? Bravo Fujitsu! | |
1234 | * Fujitsu, the !#?!%$'d up processor people. I bet if | |
1235 | * you examined the microcode of the Swift you'd find | |
1236 | * XXX's all over the place. | |
1237 | */ | |
1238 | poke_srmmu = poke_swift; | |
1239 | } | |
1240 | ||
1241 | static void turbosparc_flush_cache_all(void) | |
1242 | { | |
1243 | flush_user_windows(); | |
1244 | turbosparc_idflash_clear(); | |
1245 | } | |
1246 | ||
1247 | static void turbosparc_flush_cache_mm(struct mm_struct *mm) | |
1248 | { | |
1249 | FLUSH_BEGIN(mm) | |
1250 | flush_user_windows(); | |
1251 | turbosparc_idflash_clear(); | |
1252 | FLUSH_END | |
1253 | } | |
1254 | ||
1255 | static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
1256 | { | |
1257 | FLUSH_BEGIN(vma->vm_mm) | |
1258 | flush_user_windows(); | |
1259 | turbosparc_idflash_clear(); | |
1260 | FLUSH_END | |
1261 | } | |
1262 | ||
1263 | static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page) | |
1264 | { | |
1265 | FLUSH_BEGIN(vma->vm_mm) | |
1266 | flush_user_windows(); | |
1267 | if (vma->vm_flags & VM_EXEC) | |
1268 | turbosparc_flush_icache(); | |
1269 | turbosparc_flush_dcache(); | |
1270 | FLUSH_END | |
1271 | } | |
1272 | ||
1273 | /* TurboSparc is copy-back, if we turn it on, but this does not work. */ | |
1274 | static void turbosparc_flush_page_to_ram(unsigned long page) | |
1275 | { | |
1276 | #ifdef TURBOSPARC_WRITEBACK | |
1277 | volatile unsigned long clear; | |
1278 | ||
805918f8 | 1279 | if (srmmu_probe(page)) |
1da177e4 LT |
1280 | turbosparc_flush_page_cache(page); |
1281 | clear = srmmu_get_fstatus(); | |
1282 | #endif | |
1283 | } | |
1284 | ||
1285 | static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) | |
1286 | { | |
1287 | } | |
1288 | ||
1289 | static void turbosparc_flush_page_for_dma(unsigned long page) | |
1290 | { | |
1291 | turbosparc_flush_dcache(); | |
1292 | } | |
1293 | ||
1294 | static void turbosparc_flush_tlb_all(void) | |
1295 | { | |
1296 | srmmu_flush_whole_tlb(); | |
1297 | } | |
1298 | ||
1299 | static void turbosparc_flush_tlb_mm(struct mm_struct *mm) | |
1300 | { | |
1301 | FLUSH_BEGIN(mm) | |
1302 | srmmu_flush_whole_tlb(); | |
1303 | FLUSH_END | |
1304 | } | |
1305 | ||
1306 | static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) | |
1307 | { | |
1308 | FLUSH_BEGIN(vma->vm_mm) | |
1309 | srmmu_flush_whole_tlb(); | |
1310 | FLUSH_END | |
1311 | } | |
1312 | ||
1313 | static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
1314 | { | |
1315 | FLUSH_BEGIN(vma->vm_mm) | |
1316 | srmmu_flush_whole_tlb(); | |
1317 | FLUSH_END | |
1318 | } | |
1319 | ||
1320 | ||
2066aadd | 1321 | static void poke_turbosparc(void) |
1da177e4 LT |
1322 | { |
1323 | unsigned long mreg = srmmu_get_mmureg(); | |
1324 | unsigned long ccreg; | |
1325 | ||
1326 | /* Clear any crap from the cache or else... */ | |
1327 | turbosparc_flush_cache_all(); | |
605ae962 SR |
1328 | /* Temporarily disable I & D caches */ |
1329 | mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); | |
1da177e4 LT |
1330 | mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */ |
1331 | srmmu_set_mmureg(mreg); | |
605ae962 | 1332 | |
1da177e4 LT |
1333 | ccreg = turbosparc_get_ccreg(); |
1334 | ||
1335 | #ifdef TURBOSPARC_WRITEBACK | |
1336 | ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */ | |
1337 | ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE); | |
1338 | /* Write-back D-cache, emulate VLSI | |
1339 | * abortion number three, not number one */ | |
1340 | #else | |
1341 | /* For now let's play safe, optimize later */ | |
1342 | ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE); | |
1343 | /* Do DVMA snooping in Dcache, Write-thru D-cache */ | |
1344 | ccreg &= ~(TURBOSPARC_uS2); | |
1345 | /* Emulate VLSI abortion number three, not number one */ | |
1346 | #endif | |
1347 | ||
1348 | switch (ccreg & 7) { | |
1349 | case 0: /* No SE cache */ | |
1350 | case 7: /* Test mode */ | |
1351 | break; | |
1352 | default: | |
1353 | ccreg |= (TURBOSPARC_SCENABLE); | |
1354 | } | |
605ae962 | 1355 | turbosparc_set_ccreg(ccreg); |
1da177e4 LT |
1356 | |
1357 | mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */ | |
1358 | mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */ | |
1359 | srmmu_set_mmureg(mreg); | |
1360 | } | |
1361 | ||
5d83d666 DM |
1362 | static const struct sparc32_cachetlb_ops turbosparc_ops = { |
1363 | .cache_all = turbosparc_flush_cache_all, | |
1364 | .cache_mm = turbosparc_flush_cache_mm, | |
1365 | .cache_page = turbosparc_flush_cache_page, | |
1366 | .cache_range = turbosparc_flush_cache_range, | |
1367 | .tlb_all = turbosparc_flush_tlb_all, | |
1368 | .tlb_mm = turbosparc_flush_tlb_mm, | |
1369 | .tlb_page = turbosparc_flush_tlb_page, | |
1370 | .tlb_range = turbosparc_flush_tlb_range, | |
1371 | .page_to_ram = turbosparc_flush_page_to_ram, | |
1372 | .sig_insns = turbosparc_flush_sig_insns, | |
1373 | .page_for_dma = turbosparc_flush_page_for_dma, | |
1374 | }; | |
1375 | ||
1da177e4 LT |
1376 | static void __init init_turbosparc(void) |
1377 | { | |
1378 | srmmu_name = "Fujitsu TurboSparc"; | |
1379 | srmmu_modtype = TurboSparc; | |
5d83d666 | 1380 | sparc32_cachetlb_ops = &turbosparc_ops; |
1da177e4 LT |
1381 | poke_srmmu = poke_turbosparc; |
1382 | } | |
1383 | ||
2066aadd | 1384 | static void poke_tsunami(void) |
1da177e4 LT |
1385 | { |
1386 | unsigned long mreg = srmmu_get_mmureg(); | |
1387 | ||
1388 | tsunami_flush_icache(); | |
1389 | tsunami_flush_dcache(); | |
1390 | mreg &= ~TSUNAMI_ITD; | |
1391 | mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB); | |
1392 | srmmu_set_mmureg(mreg); | |
1393 | } | |
1394 | ||
5d83d666 DM |
1395 | static const struct sparc32_cachetlb_ops tsunami_ops = { |
1396 | .cache_all = tsunami_flush_cache_all, | |
1397 | .cache_mm = tsunami_flush_cache_mm, | |
1398 | .cache_page = tsunami_flush_cache_page, | |
1399 | .cache_range = tsunami_flush_cache_range, | |
1400 | .tlb_all = tsunami_flush_tlb_all, | |
1401 | .tlb_mm = tsunami_flush_tlb_mm, | |
1402 | .tlb_page = tsunami_flush_tlb_page, | |
1403 | .tlb_range = tsunami_flush_tlb_range, | |
1404 | .page_to_ram = tsunami_flush_page_to_ram, | |
1405 | .sig_insns = tsunami_flush_sig_insns, | |
1406 | .page_for_dma = tsunami_flush_page_for_dma, | |
1407 | }; | |
1408 | ||
1da177e4 LT |
1409 | static void __init init_tsunami(void) |
1410 | { | |
1411 | /* | |
1412 | * Tsunami's pretty sane, Sun and TI actually got it | |
1413 | * somewhat right this time. Fujitsu should have | |
1414 | * taken some lessons from them. | |
1415 | */ | |
1416 | ||
1417 | srmmu_name = "TI Tsunami"; | |
1418 | srmmu_modtype = Tsunami; | |
5d83d666 | 1419 | sparc32_cachetlb_ops = &tsunami_ops; |
1da177e4 LT |
1420 | poke_srmmu = poke_tsunami; |
1421 | ||
1422 | tsunami_setup_blockops(); | |
1423 | } | |
1424 | ||
2066aadd | 1425 | static void poke_viking(void) |
1da177e4 LT |
1426 | { |
1427 | unsigned long mreg = srmmu_get_mmureg(); | |
1428 | static int smp_catch; | |
1429 | ||
5d83d666 | 1430 | if (viking_mxcc_present) { |
1da177e4 LT |
1431 | unsigned long mxcc_control = mxcc_get_creg(); |
1432 | ||
1433 | mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE); | |
1434 | mxcc_control &= ~(MXCC_CTL_RRC); | |
1435 | mxcc_set_creg(mxcc_control); | |
1436 | ||
1437 | /* | |
1438 | * We don't need memory parity checks. | |
1439 | * XXX This is a mess, have to dig out later. ecd. | |
1440 | viking_mxcc_turn_off_parity(&mreg, &mxcc_control); | |
1441 | */ | |
1442 | ||
1443 | /* We do cache ptables on MXCC. */ | |
1444 | mreg |= VIKING_TCENABLE; | |
1445 | } else { | |
1446 | unsigned long bpreg; | |
1447 | ||
1448 | mreg &= ~(VIKING_TCENABLE); | |
605ae962 | 1449 | if (smp_catch++) { |
1da177e4 LT |
1450 | /* Must disable mixed-cmd mode here for other cpu's. */ |
1451 | bpreg = viking_get_bpreg(); | |
1452 | bpreg &= ~(VIKING_ACTION_MIX); | |
1453 | viking_set_bpreg(bpreg); | |
1454 | ||
1455 | /* Just in case PROM does something funny. */ | |
1456 | msi_set_sync(); | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | mreg |= VIKING_SPENABLE; | |
1461 | mreg |= (VIKING_ICENABLE | VIKING_DCENABLE); | |
1462 | mreg |= VIKING_SBENABLE; | |
1463 | mreg &= ~(VIKING_ACENABLE); | |
1464 | srmmu_set_mmureg(mreg); | |
1da177e4 LT |
1465 | } |
1466 | ||
cbc41b43 | 1467 | static struct sparc32_cachetlb_ops viking_ops __ro_after_init = { |
5d83d666 DM |
1468 | .cache_all = viking_flush_cache_all, |
1469 | .cache_mm = viking_flush_cache_mm, | |
1470 | .cache_page = viking_flush_cache_page, | |
1471 | .cache_range = viking_flush_cache_range, | |
1472 | .tlb_all = viking_flush_tlb_all, | |
1473 | .tlb_mm = viking_flush_tlb_mm, | |
1474 | .tlb_page = viking_flush_tlb_page, | |
1475 | .tlb_range = viking_flush_tlb_range, | |
1476 | .page_to_ram = viking_flush_page_to_ram, | |
1477 | .sig_insns = viking_flush_sig_insns, | |
1478 | .page_for_dma = viking_flush_page_for_dma, | |
1479 | }; | |
1480 | ||
1481 | #ifdef CONFIG_SMP | |
1482 | /* On sun4d the cpu broadcasts local TLB flushes, so we can just | |
1483 | * perform the local TLB flush and all the other cpus will see it. | |
1484 | * But, unfortunately, there is a bug in the sun4d XBUS backplane | |
1485 | * that requires that we add some synchronization to these flushes. | |
1486 | * | |
1487 | * The bug is that the fifo which keeps track of all the pending TLB | |
1488 | * broadcasts in the system is an entry or two too small, so if we | |
1489 | * have too many going at once we'll overflow that fifo and lose a TLB | |
1490 | * flush resulting in corruption. | |
1491 | * | |
1492 | * Our workaround is to take a global spinlock around the TLB flushes, | |
1493 | * which guarentees we won't ever have too many pending. It's a big | |
1494 | * hammer, but a semaphore like system to make sure we only have N TLB | |
1495 | * flushes going at once will require SMP locking anyways so there's | |
1496 | * no real value in trying any harder than this. | |
1497 | */ | |
cbc41b43 | 1498 | static struct sparc32_cachetlb_ops viking_sun4d_smp_ops __ro_after_init = { |
5d83d666 DM |
1499 | .cache_all = viking_flush_cache_all, |
1500 | .cache_mm = viking_flush_cache_mm, | |
1501 | .cache_page = viking_flush_cache_page, | |
1502 | .cache_range = viking_flush_cache_range, | |
1503 | .tlb_all = sun4dsmp_flush_tlb_all, | |
1504 | .tlb_mm = sun4dsmp_flush_tlb_mm, | |
1505 | .tlb_page = sun4dsmp_flush_tlb_page, | |
1506 | .tlb_range = sun4dsmp_flush_tlb_range, | |
1507 | .page_to_ram = viking_flush_page_to_ram, | |
1508 | .sig_insns = viking_flush_sig_insns, | |
1509 | .page_for_dma = viking_flush_page_for_dma, | |
1510 | }; | |
1511 | #endif | |
1512 | ||
1da177e4 LT |
1513 | static void __init init_viking(void) |
1514 | { | |
1515 | unsigned long mreg = srmmu_get_mmureg(); | |
1516 | ||
1517 | /* Ahhh, the viking. SRMMU VLSI abortion number two... */ | |
605ae962 | 1518 | if (mreg & VIKING_MMODE) { |
1da177e4 LT |
1519 | srmmu_name = "TI Viking"; |
1520 | viking_mxcc_present = 0; | |
1521 | msi_set_sync(); | |
1522 | ||
1da177e4 LT |
1523 | /* |
1524 | * We need this to make sure old viking takes no hits | |
1525 | * on it's cache for dma snoops to workaround the | |
1526 | * "load from non-cacheable memory" interrupt bug. | |
1527 | * This is only necessary because of the new way in | |
1528 | * which we use the IOMMU. | |
1529 | */ | |
5d83d666 DM |
1530 | viking_ops.page_for_dma = viking_flush_page; |
1531 | #ifdef CONFIG_SMP | |
1532 | viking_sun4d_smp_ops.page_for_dma = viking_flush_page; | |
1533 | #endif | |
1da177e4 LT |
1534 | flush_page_for_dma_global = 0; |
1535 | } else { | |
1536 | srmmu_name = "TI Viking/MXCC"; | |
1537 | viking_mxcc_present = 1; | |
1da177e4 | 1538 | srmmu_cache_pagetables = 1; |
1da177e4 LT |
1539 | } |
1540 | ||
5d83d666 DM |
1541 | sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) |
1542 | &viking_ops; | |
1da177e4 | 1543 | #ifdef CONFIG_SMP |
5d83d666 DM |
1544 | if (sparc_cpu_model == sun4d) |
1545 | sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) | |
1546 | &viking_sun4d_smp_ops; | |
1da177e4 | 1547 | #endif |
1da177e4 LT |
1548 | |
1549 | poke_srmmu = poke_viking; | |
1550 | } | |
1551 | ||
1552 | /* Probe for the srmmu chip version. */ | |
1553 | static void __init get_srmmu_type(void) | |
1554 | { | |
1555 | unsigned long mreg, psr; | |
1556 | unsigned long mod_typ, mod_rev, psr_typ, psr_vers; | |
1557 | ||
1558 | srmmu_modtype = SRMMU_INVAL_MOD; | |
1559 | hwbug_bitmask = 0; | |
1560 | ||
1561 | mreg = srmmu_get_mmureg(); psr = get_psr(); | |
1562 | mod_typ = (mreg & 0xf0000000) >> 28; | |
1563 | mod_rev = (mreg & 0x0f000000) >> 24; | |
1564 | psr_typ = (psr >> 28) & 0xf; | |
1565 | psr_vers = (psr >> 24) & 0xf; | |
1566 | ||
75d9e346 KE |
1567 | /* First, check for sparc-leon. */ |
1568 | if (sparc_cpu_model == sparc_leon) { | |
75d9e346 KE |
1569 | init_leon(); |
1570 | return; | |
1571 | } | |
1572 | ||
1573 | /* Second, check for HyperSparc or Cypress. */ | |
605ae962 SR |
1574 | if (mod_typ == 1) { |
1575 | switch (mod_rev) { | |
1da177e4 LT |
1576 | case 7: |
1577 | /* UP or MP Hypersparc */ | |
1578 | init_hypersparc(); | |
1579 | break; | |
1580 | case 0: | |
1581 | case 2: | |
1da177e4 LT |
1582 | case 10: |
1583 | case 11: | |
1584 | case 12: | |
1da177e4 LT |
1585 | case 13: |
1586 | case 14: | |
1587 | case 15: | |
1da177e4 | 1588 | default: |
c7020eb4 DM |
1589 | prom_printf("Sparc-Linux Cypress support does not longer exit.\n"); |
1590 | prom_halt(); | |
1da177e4 | 1591 | break; |
6cb79b3f | 1592 | } |
1da177e4 LT |
1593 | return; |
1594 | } | |
605ae962 SR |
1595 | |
1596 | /* Now Fujitsu TurboSparc. It might happen that it is | |
1da177e4 LT |
1597 | * in Swift emulation mode, so we will check later... |
1598 | */ | |
1599 | if (psr_typ == 0 && psr_vers == 5) { | |
1600 | init_turbosparc(); | |
1601 | return; | |
1602 | } | |
1603 | ||
1604 | /* Next check for Fujitsu Swift. */ | |
605ae962 | 1605 | if (psr_typ == 0 && psr_vers == 4) { |
8d125562 | 1606 | phandle cpunode; |
1da177e4 LT |
1607 | char node_str[128]; |
1608 | ||
1609 | /* Look if it is not a TurboSparc emulating Swift... */ | |
1610 | cpunode = prom_getchild(prom_root_node); | |
605ae962 | 1611 | while ((cpunode = prom_getsibling(cpunode)) != 0) { |
1da177e4 | 1612 | prom_getstring(cpunode, "device_type", node_str, sizeof(node_str)); |
605ae962 | 1613 | if (!strcmp(node_str, "cpu")) { |
1da177e4 LT |
1614 | if (!prom_getintdefault(cpunode, "psr-implementation", 1) && |
1615 | prom_getintdefault(cpunode, "psr-version", 1) == 5) { | |
1616 | init_turbosparc(); | |
1617 | return; | |
1618 | } | |
1619 | break; | |
1620 | } | |
1621 | } | |
605ae962 | 1622 | |
1da177e4 LT |
1623 | init_swift(); |
1624 | return; | |
1625 | } | |
1626 | ||
1627 | /* Now the Viking family of srmmu. */ | |
605ae962 | 1628 | if (psr_typ == 4 && |
1da177e4 LT |
1629 | ((psr_vers == 0) || |
1630 | ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) { | |
1631 | init_viking(); | |
1632 | return; | |
1633 | } | |
1634 | ||
1635 | /* Finally the Tsunami. */ | |
605ae962 | 1636 | if (psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) { |
1da177e4 LT |
1637 | init_tsunami(); |
1638 | return; | |
1639 | } | |
1640 | ||
1641 | /* Oh well */ | |
1642 | srmmu_is_bad(); | |
1643 | } | |
1644 | ||
1da177e4 LT |
1645 | #ifdef CONFIG_SMP |
1646 | /* Local cross-calls. */ | |
1647 | static void smp_flush_page_for_dma(unsigned long page) | |
1648 | { | |
5d83d666 DM |
1649 | xc1((smpfunc_t) local_ops->page_for_dma, page); |
1650 | local_ops->page_for_dma(page); | |
1651 | } | |
1652 | ||
1653 | static void smp_flush_cache_all(void) | |
1654 | { | |
1655 | xc0((smpfunc_t) local_ops->cache_all); | |
1656 | local_ops->cache_all(); | |
1657 | } | |
1658 | ||
1659 | static void smp_flush_tlb_all(void) | |
1660 | { | |
1661 | xc0((smpfunc_t) local_ops->tlb_all); | |
1662 | local_ops->tlb_all(); | |
1663 | } | |
1664 | ||
1665 | static void smp_flush_cache_mm(struct mm_struct *mm) | |
1666 | { | |
1667 | if (mm->context != NO_CONTEXT) { | |
1668 | cpumask_t cpu_mask; | |
1669 | cpumask_copy(&cpu_mask, mm_cpumask(mm)); | |
1670 | cpumask_clear_cpu(smp_processor_id(), &cpu_mask); | |
1671 | if (!cpumask_empty(&cpu_mask)) | |
1672 | xc1((smpfunc_t) local_ops->cache_mm, (unsigned long) mm); | |
1673 | local_ops->cache_mm(mm); | |
1674 | } | |
1675 | } | |
1676 | ||
1677 | static void smp_flush_tlb_mm(struct mm_struct *mm) | |
1678 | { | |
1679 | if (mm->context != NO_CONTEXT) { | |
1680 | cpumask_t cpu_mask; | |
1681 | cpumask_copy(&cpu_mask, mm_cpumask(mm)); | |
1682 | cpumask_clear_cpu(smp_processor_id(), &cpu_mask); | |
1683 | if (!cpumask_empty(&cpu_mask)) { | |
1684 | xc1((smpfunc_t) local_ops->tlb_mm, (unsigned long) mm); | |
1685 | if (atomic_read(&mm->mm_users) == 1 && current->active_mm == mm) | |
1686 | cpumask_copy(mm_cpumask(mm), | |
1687 | cpumask_of(smp_processor_id())); | |
1688 | } | |
1689 | local_ops->tlb_mm(mm); | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | static void smp_flush_cache_range(struct vm_area_struct *vma, | |
1694 | unsigned long start, | |
1695 | unsigned long end) | |
1696 | { | |
1697 | struct mm_struct *mm = vma->vm_mm; | |
1698 | ||
1699 | if (mm->context != NO_CONTEXT) { | |
1700 | cpumask_t cpu_mask; | |
1701 | cpumask_copy(&cpu_mask, mm_cpumask(mm)); | |
1702 | cpumask_clear_cpu(smp_processor_id(), &cpu_mask); | |
1703 | if (!cpumask_empty(&cpu_mask)) | |
1704 | xc3((smpfunc_t) local_ops->cache_range, | |
1705 | (unsigned long) vma, start, end); | |
1706 | local_ops->cache_range(vma, start, end); | |
1707 | } | |
1708 | } | |
1709 | ||
1710 | static void smp_flush_tlb_range(struct vm_area_struct *vma, | |
1711 | unsigned long start, | |
1712 | unsigned long end) | |
1713 | { | |
1714 | struct mm_struct *mm = vma->vm_mm; | |
1715 | ||
1716 | if (mm->context != NO_CONTEXT) { | |
1717 | cpumask_t cpu_mask; | |
1718 | cpumask_copy(&cpu_mask, mm_cpumask(mm)); | |
1719 | cpumask_clear_cpu(smp_processor_id(), &cpu_mask); | |
1720 | if (!cpumask_empty(&cpu_mask)) | |
1721 | xc3((smpfunc_t) local_ops->tlb_range, | |
1722 | (unsigned long) vma, start, end); | |
1723 | local_ops->tlb_range(vma, start, end); | |
1724 | } | |
1da177e4 LT |
1725 | } |
1726 | ||
5d83d666 DM |
1727 | static void smp_flush_cache_page(struct vm_area_struct *vma, unsigned long page) |
1728 | { | |
1729 | struct mm_struct *mm = vma->vm_mm; | |
1730 | ||
1731 | if (mm->context != NO_CONTEXT) { | |
1732 | cpumask_t cpu_mask; | |
1733 | cpumask_copy(&cpu_mask, mm_cpumask(mm)); | |
1734 | cpumask_clear_cpu(smp_processor_id(), &cpu_mask); | |
1735 | if (!cpumask_empty(&cpu_mask)) | |
1736 | xc2((smpfunc_t) local_ops->cache_page, | |
1737 | (unsigned long) vma, page); | |
1738 | local_ops->cache_page(vma, page); | |
1739 | } | |
1740 | } | |
1741 | ||
1742 | static void smp_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) | |
1743 | { | |
1744 | struct mm_struct *mm = vma->vm_mm; | |
1745 | ||
1746 | if (mm->context != NO_CONTEXT) { | |
1747 | cpumask_t cpu_mask; | |
1748 | cpumask_copy(&cpu_mask, mm_cpumask(mm)); | |
1749 | cpumask_clear_cpu(smp_processor_id(), &cpu_mask); | |
1750 | if (!cpumask_empty(&cpu_mask)) | |
1751 | xc2((smpfunc_t) local_ops->tlb_page, | |
1752 | (unsigned long) vma, page); | |
1753 | local_ops->tlb_page(vma, page); | |
1754 | } | |
1755 | } | |
1756 | ||
1757 | static void smp_flush_page_to_ram(unsigned long page) | |
1758 | { | |
1759 | /* Current theory is that those who call this are the one's | |
1760 | * who have just dirtied their cache with the pages contents | |
1761 | * in kernel space, therefore we only run this on local cpu. | |
1762 | * | |
1763 | * XXX This experiment failed, research further... -DaveM | |
1764 | */ | |
1765 | #if 1 | |
1766 | xc1((smpfunc_t) local_ops->page_to_ram, page); | |
1767 | #endif | |
1768 | local_ops->page_to_ram(page); | |
1769 | } | |
1770 | ||
1771 | static void smp_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr) | |
1772 | { | |
1773 | cpumask_t cpu_mask; | |
1774 | cpumask_copy(&cpu_mask, mm_cpumask(mm)); | |
1775 | cpumask_clear_cpu(smp_processor_id(), &cpu_mask); | |
1776 | if (!cpumask_empty(&cpu_mask)) | |
1777 | xc2((smpfunc_t) local_ops->sig_insns, | |
1778 | (unsigned long) mm, insn_addr); | |
1779 | local_ops->sig_insns(mm, insn_addr); | |
1780 | } | |
1781 | ||
cbc41b43 | 1782 | static struct sparc32_cachetlb_ops smp_cachetlb_ops __ro_after_init = { |
5d83d666 DM |
1783 | .cache_all = smp_flush_cache_all, |
1784 | .cache_mm = smp_flush_cache_mm, | |
1785 | .cache_page = smp_flush_cache_page, | |
1786 | .cache_range = smp_flush_cache_range, | |
1787 | .tlb_all = smp_flush_tlb_all, | |
1788 | .tlb_mm = smp_flush_tlb_mm, | |
1789 | .tlb_page = smp_flush_tlb_page, | |
1790 | .tlb_range = smp_flush_tlb_range, | |
1791 | .page_to_ram = smp_flush_page_to_ram, | |
1792 | .sig_insns = smp_flush_sig_insns, | |
1793 | .page_for_dma = smp_flush_page_for_dma, | |
1794 | }; | |
1da177e4 LT |
1795 | #endif |
1796 | ||
1da177e4 | 1797 | /* Load up routines and constants for sun4m and sun4d mmu */ |
a3c5c663 | 1798 | void __init load_mmu(void) |
1da177e4 | 1799 | { |
1da177e4 | 1800 | /* Functions */ |
1da177e4 | 1801 | get_srmmu_type(); |
1da177e4 LT |
1802 | |
1803 | #ifdef CONFIG_SMP | |
1804 | /* El switcheroo... */ | |
5d83d666 | 1805 | local_ops = sparc32_cachetlb_ops; |
1da177e4 | 1806 | |
5d83d666 DM |
1807 | if (sparc_cpu_model == sun4d || sparc_cpu_model == sparc_leon) { |
1808 | smp_cachetlb_ops.tlb_all = local_ops->tlb_all; | |
1809 | smp_cachetlb_ops.tlb_mm = local_ops->tlb_mm; | |
1810 | smp_cachetlb_ops.tlb_range = local_ops->tlb_range; | |
1811 | smp_cachetlb_ops.tlb_page = local_ops->tlb_page; | |
1da177e4 | 1812 | } |
64273d08 DM |
1813 | |
1814 | if (poke_srmmu == poke_viking) { | |
1815 | /* Avoid unnecessary cross calls. */ | |
5d83d666 DM |
1816 | smp_cachetlb_ops.cache_all = local_ops->cache_all; |
1817 | smp_cachetlb_ops.cache_mm = local_ops->cache_mm; | |
1818 | smp_cachetlb_ops.cache_range = local_ops->cache_range; | |
1819 | smp_cachetlb_ops.cache_page = local_ops->cache_page; | |
1820 | ||
1821 | smp_cachetlb_ops.page_to_ram = local_ops->page_to_ram; | |
1822 | smp_cachetlb_ops.sig_insns = local_ops->sig_insns; | |
1823 | smp_cachetlb_ops.page_for_dma = local_ops->page_for_dma; | |
64273d08 | 1824 | } |
5d83d666 DM |
1825 | |
1826 | /* It really is const after this point. */ | |
1827 | sparc32_cachetlb_ops = (const struct sparc32_cachetlb_ops *) | |
1828 | &smp_cachetlb_ops; | |
1da177e4 LT |
1829 | #endif |
1830 | ||
1831 | if (sparc_cpu_model == sun4d) | |
1832 | ld_mmu_iounit(); | |
1833 | else | |
1834 | ld_mmu_iommu(); | |
1835 | #ifdef CONFIG_SMP | |
1836 | if (sparc_cpu_model == sun4d) | |
1837 | sun4d_init_smp(); | |
8401707f KE |
1838 | else if (sparc_cpu_model == sparc_leon) |
1839 | leon_init_smp(); | |
1da177e4 LT |
1840 | else |
1841 | sun4m_init_smp(); | |
1842 | #endif | |
1843 | } |