[linux-block.git] / arch / sparc / kernel / sun4d_smp.c

// SPDX-License-Identifier: GPL-2.0
/* Sparc SS1000/SC2000 SMP support.
 *
 * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 *
 * Based on sun4m's smp.c, which is:
 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
 */

#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/profile.h>
#include <linux/delay.h>
#include <linux/sched/mm.h>
#include <linux/cpu.h>

#include <asm/cacheflush.h>
#include <asm/switch_to.h>
#include <asm/tlbflush.h>
#include <asm/timer.h>
#include <asm/oplib.h>
#include <asm/sbi.h>
#include <asm/mmu.h>

#include "kernel.h"
#include "irq.h"

#define IRQ_CROSS_CALL		15

static volatile int smp_processors_ready;
static int smp_highest_cpu;

static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
{
	__asm__ __volatile__("swap [%1], %0\n\t" :
			     "=&r" (val), "=&r" (ptr) :
			     "0" (val), "1" (ptr));
	return val;
}

static void smp4d_ipi_init(void);

static unsigned char cpu_leds[32];

static inline void show_leds(int cpuid)
{
	cpuid &= 0x1e;
	__asm__ __volatile__ ("stba %0, [%1] %2" : :
			      "r" ((cpu_leds[cpuid] << 4) | cpu_leds[cpuid+1]),
			      "r" (ECSR_BASE(cpuid) | BB_LEDS),
			      "i" (ASI_M_CTL));
}

void sun4d_cpu_pre_starting(void *arg)
{
	int cpuid = hard_smp_processor_id();

	/* Show we are alive */
	cpu_leds[cpuid] = 0x6;
	show_leds(cpuid);

	/* Enable level15 interrupt, disable level14 interrupt for now */
	cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000);
}

void sun4d_cpu_pre_online(void *arg)
{
	unsigned long flags;
	int cpuid;

	cpuid = hard_smp_processor_id();

	/* Unblock the master CPU _only_ when the scheduler state
	 * of all secondary CPUs will be up-to-date, so after
	 * the SMP initialization the master will be just allowed
	 * to call the scheduler code.
	 */
	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
	local_ops->cache_all();
	local_ops->tlb_all();

	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
		barrier();

	while (current_set[cpuid]->cpu != cpuid)
		barrier();

	/* Fix idle thread fields. */
	__asm__ __volatile__("ld [%0], %%g6\n\t"
			     : : "r" (&current_set[cpuid])
			     : "memory" /* paranoid */);

	cpu_leds[cpuid] = 0x9;
	show_leds(cpuid);

	/* Attach to the address space of init_task. */
	mmgrab(&init_mm);
	current->active_mm = &init_mm;

	local_ops->cache_all();
	local_ops->tlb_all();

	while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
		barrier();

	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
}

/*
 *	Cycle through the processors asking the PROM to start each one.
 */
void __init smp4d_boot_cpus(void)
{
	smp4d_ipi_init();
	if (boot_cpu_id)
		current_set[0] = NULL;
	local_ops->cache_all();
}

int smp4d_boot_one_cpu(int i, struct task_struct *idle)
{
	unsigned long *entry = &sun4d_cpu_startup;
	int timeout;
	int cpu_node;

	cpu_find_by_instance(i, &cpu_node, NULL);
	current_set[i] = task_thread_info(idle);
	/*
	 * Initialize the contexts table
	 * Since the call to prom_startcpu() trashes the structure,
	 * we need to re-initialize it for each cpu
	 */
	smp_penguin_ctable.which_io = 0;
	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	smp_penguin_ctable.reg_size = 0;

	/* whirrr, whirrr, whirrrrrrrrr... */
	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
	local_ops->cache_all();
	prom_startcpu(cpu_node,
		      &smp_penguin_ctable, 0, (char *)entry);

	printk(KERN_INFO "prom_startcpu returned :)\n");

	/* wheee... it's going... */
	for (timeout = 0; timeout < 10000; timeout++) {
		if (cpu_callin_map[i])
			break;
		udelay(200);
	}

	if (!(cpu_callin_map[i])) {
		printk(KERN_ERR "Processor %d is stuck.\n", i);
		return -ENODEV;

	}
	local_ops->cache_all();
	return 0;
}

void __init smp4d_smp_done(void)
{
	int i, first;
	int *prev;

	/* setup cpu list for irq rotation */
	first = 0;
	prev = &first;
	for_each_online_cpu(i) {
		*prev = i;
		prev = &cpu_data(i).next;
	}
	*prev = first;
	local_ops->cache_all();

	/* Ok, they are spinning and ready to go. */
	smp_processors_ready = 1;
	sun4d_distribute_irqs();
}

/* Memory structure giving interrupt handler information about IPI generated */
struct sun4d_ipi_work {
	int single;
	int msk;
	int resched;
};

static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);

/* Initialize IPIs on the SUN4D SMP machine */
static void __init smp4d_ipi_init(void)
{
	int cpu;
	struct sun4d_ipi_work *work;

	printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);

	for_each_possible_cpu(cpu) {
		work = &per_cpu(sun4d_ipi_work, cpu);
		work->single = work->msk = work->resched = 0;
	}
}

void sun4d_ipi_interrupt(void)
{
	struct sun4d_ipi_work *work = this_cpu_ptr(&sun4d_ipi_work);

	if (work->single) {
		work->single = 0;
		smp_call_function_single_interrupt();
	}
	if (work->msk) {
		work->msk = 0;
		smp_call_function_interrupt();
	}
	if (work->resched) {
		work->resched = 0;
		smp_resched_interrupt();
	}
}

/* +-------+-------------+-----------+------------------------------------+
 * | bcast |  devid      |   sid     |              levels mask           |
 * +-------+-------------+-----------+------------------------------------+
 *  31      30         23 22       15 14                                 0
 */
#define IGEN_MESSAGE(bcast, devid, sid, levels) \
	(((bcast) << 31) | ((devid) << 23) | ((sid) << 15) | (levels))

static void sun4d_send_ipi(int cpu, int level)
{
	cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
}

static void sun4d_ipi_single(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->single = 1;

	/* Generate IRQ on the CPU */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static void sun4d_ipi_mask_one(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->msk = 1;

	/* Generate IRQ on the CPU */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static void sun4d_ipi_resched(int cpu)
{
	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);

	/* Mark work */
	work->resched = 1;

	/* Generate IRQ on the CPU (any IRQ will cause resched) */
	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
}

static struct smp_funcall {
	void *func;
	unsigned long arg1;
	unsigned long arg2;
	unsigned long arg3;
	unsigned long arg4;
	unsigned long arg5;
	unsigned char processors_in[NR_CPUS];  /* Set when ipi entered. */
	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
} ccall_info __attribute__((aligned(8)));

static DEFINE_SPINLOCK(cross_call_lock);

/* Cross calls must be serialized, at least currently. */
static void sun4d_cross_call(void *func, cpumask_t mask, unsigned long arg1,
			     unsigned long arg2, unsigned long arg3,
			     unsigned long arg4)
{
	if (smp_processors_ready) {
		register int high = smp_highest_cpu;
		unsigned long flags;

		spin_lock_irqsave(&cross_call_lock, flags);

		{
			/*
			 * If you make changes here, make sure
			 * gcc generates proper code...
			 */
			register void *f asm("i0") = func;
			register unsigned long a1 asm("i1") = arg1;
			register unsigned long a2 asm("i2") = arg2;
			register unsigned long a3 asm("i3") = arg3;
			register unsigned long a4 asm("i4") = arg4;
			register unsigned long a5 asm("i5") = 0;

			__asm__ __volatile__(
				"std %0, [%6]\n\t"
				"std %2, [%6 + 8]\n\t"
				"std %4, [%6 + 16]\n\t" : :
				"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
				"r" (&ccall_info.func));
		}

		/* Init receive/complete mapping, plus fire the IPI's off. */
		{
			register int i;

			cpumask_clear_cpu(smp_processor_id(), &mask);
			cpumask_and(&mask, cpu_online_mask, &mask);
			for (i = 0; i <= high; i++) {
				if (cpumask_test_cpu(i, &mask)) {
					ccall_info.processors_in[i] = 0;
					ccall_info.processors_out[i] = 0;
					sun4d_send_ipi(i, IRQ_CROSS_CALL);
				}
			}
		}

		{
			register int i;

			i = 0;
			do {
				if (!cpumask_test_cpu(i, &mask))
					continue;
				while (!ccall_info.processors_in[i])
					barrier();
			} while (++i <= high);

			i = 0;
			do {
				if (!cpumask_test_cpu(i, &mask))
					continue;
				while (!ccall_info.processors_out[i])
					barrier();
			} while (++i <= high);
		}

		spin_unlock_irqrestore(&cross_call_lock, flags);
	}
}

/* Running cross calls. */
void smp4d_cross_call_irq(void)
{
	void (*func)(unsigned long, unsigned long, unsigned long, unsigned long,
		     unsigned long) = ccall_info.func;
	int i = hard_smp_processor_id();

	ccall_info.processors_in[i] = 1;
	func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, ccall_info.arg4,
	     ccall_info.arg5);
	ccall_info.processors_out[i] = 1;
}

void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
{
	struct pt_regs *old_regs;
	int cpu = hard_smp_processor_id();
	struct clock_event_device *ce;
	static int cpu_tick[NR_CPUS];
	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };

	old_regs = set_irq_regs(regs);
	bw_get_prof_limit(cpu);
	bw_clear_intr_mask(0, 1);	/* INTR_TABLE[0] & 1 is Profile IRQ */

	cpu_tick[cpu]++;
	if (!(cpu_tick[cpu] & 15)) {
		if (cpu_tick[cpu] == 0x60)
			cpu_tick[cpu] = 0;
		cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
		show_leds(cpu);
	}

	ce = &per_cpu(sparc32_clockevent, cpu);

	irq_enter();
	ce->event_handler(ce);
	irq_exit();

	set_irq_regs(old_regs);
}

static const struct sparc32_ipi_ops sun4d_ipi_ops = {
	.cross_call = sun4d_cross_call,
	.resched    = sun4d_ipi_resched,
	.single     = sun4d_ipi_single,
	.mask_one   = sun4d_ipi_mask_one,
};

void __init sun4d_init_smp(void)
{
	int i;

	/* Patch ipi15 trap table */
	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);

	sparc32_ipi_ops = &sun4d_ipi_ops;

	for (i = 0; i < NR_CPUS; i++) {
		ccall_info.processors_in[i] = 1;
		ccall_info.processors_out[i] = 1;
	}
}
Commit	Line	Data
b2441318	1	// SPDX-License-Identifier: GPL-2.0
e54f8548	2	/* Sparc SS1000/SC2000 SMP support.
1da177e4 LT	3	*
	4	* Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	5	*
	6	* Based on sun4m's smp.c, which is:
	7	* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
	8	*/
	9
62f08283	10	#include <linux/clockchips.h>
1da177e4	11	#include <linux/interrupt.h>
1da177e4	12	#include <linux/profile.h>
6c81c32f	13	#include <linux/delay.h>
68e21be2	14	#include <linux/sched/mm.h>
4245e59d	15	#include <linux/cpu.h>
1da177e4	16
62f08283 TK	17	#include <asm/cacheflush.h>
	18	#include <asm/switch_to.h>
	19	#include <asm/tlbflush.h>
	20	#include <asm/timer.h>
5d83d666	21	#include <asm/oplib.h>
1da177e4	22	#include <asm/sbi.h>
e54f8548	23	#include <asm/mmu.h>
1da177e4	24
e54f8548	25	#include "kernel.h"
32231a66	26	#include "irq.h"
1da177e4	27
e54f8548	28	#define IRQ_CROSS_CALL 15
1da177e4	29
e54f8548	30	static volatile int smp_processors_ready;
1da177e4	31	static int smp_highest_cpu;
1da177e4	32
a638f25a	33	static inline unsigned long sun4d_swap(volatile unsigned long *ptr, unsigned long val)
1da177e4 LT	34	{
	35	__asm__ __volatile__("swap [%1], %0\n\t" :
	36	"=&r" (val), "=&r" (ptr) :
	37	"0" (val), "1" (ptr));
	38	return val;
	39	}
	40
55dd23ec	41	static void smp4d_ipi_init(void);
1da177e4	42
7b1af32f DM	43	static unsigned char cpu_leds[32];
	44
	45	static inline void show_leds(int cpuid)
	46	{
	47	cpuid &= 0x1e;
	48	__asm__ __volatile__ ("stba %0, [%1] %2" : :
	49	"r" ((cpu_leds[cpuid] << 4) \| cpu_leds[cpuid+1]),
	50	"r" (ECSR_BASE(cpuid) \| BB_LEDS),
	51	"i" (ASI_M_CTL));
	52	}
	53
2066aadd	54	void sun4d_cpu_pre_starting(void *arg)
1da177e4	55	{
c68e5d39	56	int cpuid = hard_smp_processor_id();
e54f8548	57
1da177e4 LT	58	/* Show we are alive */
	59	cpu_leds[cpuid] = 0x6;
	60	show_leds(cpuid);
	61
	62	/* Enable level15 interrupt, disable level14 interrupt for now */
	63	cc_set_imsk((cc_get_imsk() & ~0x8000) \| 0x4000);
f9fd3488	64	}
1da177e4	65
2066aadd	66	void sun4d_cpu_pre_online(void *arg)
f9fd3488 SR	67	{
	68	unsigned long flags;
	69	int cpuid;
	70
	71	cpuid = hard_smp_processor_id();
1da177e4	72
f9fd3488	73	/* Unblock the master CPU _only_ when the scheduler state
1da177e4 LT	74	* of all secondary CPUs will be up-to-date, so after
	75	* the SMP initialization the master will be just allowed
	76	* to call the scheduler code.
	77	*/
a638f25a	78	sun4d_swap((unsigned long *)&cpu_callin_map[cpuid], 1);
5d83d666 DM	79	local_ops->cache_all();
5d83d666 DM	80	local_ops->tlb_all();
e54f8548	81
e54f8548	82	while ((unsigned long)current_set[cpuid] < PAGE_OFFSET)
1da177e4	83	barrier();
e54f8548 SR	84
e54f8548 SR	85	while (current_set[cpuid]->cpu != cpuid)
1da177e4	86	barrier();
e54f8548	87
1da177e4 LT	88	/* Fix idle thread fields. */
	89	__asm__ __volatile__("ld [%0], %%g6\n\t"
	90	: : "r" (&current_set[cpuid])
	91	: "memory" /* paranoid */);
	92
	93	cpu_leds[cpuid] = 0x9;
	94	show_leds(cpuid);
e54f8548	95
1da177e4	96	/* Attach to the address space of init_task. */
f1f10076	97	mmgrab(&init_mm);
1da177e4 LT	98	current->active_mm = &init_mm;
1da177e4 LT	99
5d83d666 DM	100	local_ops->cache_all();
5d83d666 DM	101	local_ops->tlb_all();
e54f8548	102
fb1fece5	103	while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
1da177e4 LT	104	barrier();
	105
	106	spin_lock_irqsave(&sun4d_imsk_lock, flags);
	107	cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */
	108	spin_unlock_irqrestore(&sun4d_imsk_lock, flags);
	109	}
	110
1da177e4 LT	111	/*
	112	* Cycle through the processors asking the PROM to start each one.
	113	*/
1da177e4 LT	114	void __init smp4d_boot_cpus(void)
1da177e4 LT	115	{
55dd23ec	116	smp4d_ipi_init();
1da177e4 LT	117	if (boot_cpu_id)
1da177e4 LT	118	current_set[0] = NULL;
5d83d666	119	local_ops->cache_all();
8b3c848c RB	120	}
8b3c848c RB	121
2066aadd	122	int smp4d_boot_one_cpu(int i, struct task_struct *idle)
8b3c848c	123	{
e54f8548	124	unsigned long *entry = &sun4d_cpu_startup;
e54f8548 SR	125	int timeout;
e54f8548 SR	126	int cpu_node;
1da177e4	127
e54f8548	128	cpu_find_by_instance(i, &cpu_node, NULL);
f0a2bc7e	129	current_set[i] = task_thread_info(idle);
e54f8548 SR	130	/*
	131	* Initialize the contexts table
	132	* Since the call to prom_startcpu() trashes the structure,
	133	* we need to re-initialize it for each cpu
	134	*/
	135	smp_penguin_ctable.which_io = 0;
	136	smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys;
	137	smp_penguin_ctable.reg_size = 0;
	138
	139	/* whirrr, whirrr, whirrrrrrrrr... */
	140	printk(KERN_INFO "Starting CPU %d at %p\n", i, entry);
5d83d666	141	local_ops->cache_all();
e54f8548 SR	142	prom_startcpu(cpu_node,
	143	&smp_penguin_ctable, 0, (char *)entry);
	144
	145	printk(KERN_INFO "prom_startcpu returned :)\n");
	146
	147	/* wheee... it's going... */
	148	for (timeout = 0; timeout < 10000; timeout++) {
	149	if (cpu_callin_map[i])
	150	break;
	151	udelay(200);
	152	}
1da177e4	153
8b3c848c	154	if (!(cpu_callin_map[i])) {
e54f8548	155	printk(KERN_ERR "Processor %d is stuck.\n", i);
8b3c848c RB	156	return -ENODEV;
8b3c848c RB	157
1da177e4	158	}
5d83d666	159	local_ops->cache_all();
8b3c848c RB	160	return 0;
	161	}
	162
	163	void __init smp4d_smp_done(void)
	164	{
	165	int i, first;
	166	int *prev;
	167
	168	/* setup cpu list for irq rotation */
	169	first = 0;
	170	prev = &first;
ec7c14bd RR	171	for_each_online_cpu(i) {
	172	*prev = i;
	173	prev = &cpu_data(i).next;
	174	}
8b3c848c	175	*prev = first;
5d83d666	176	local_ops->cache_all();
1da177e4	177
1da177e4 LT	178	/* Ok, they are spinning and ready to go. */
	179	smp_processors_ready = 1;
	180	sun4d_distribute_irqs();
	181	}
	182
55dd23ec DH	183	/* Memory structure giving interrupt handler information about IPI generated */
	184	struct sun4d_ipi_work {
	185	int single;
	186	int msk;
	187	int resched;
	188	};
	189
	190	static DEFINE_PER_CPU_SHARED_ALIGNED(struct sun4d_ipi_work, sun4d_ipi_work);
	191
	192	/* Initialize IPIs on the SUN4D SMP machine */
	193	static void __init smp4d_ipi_init(void)
	194	{
	195	int cpu;
	196	struct sun4d_ipi_work *work;
	197
	198	printk(KERN_INFO "smp4d: setup IPI at IRQ %d\n", SUN4D_IPI_IRQ);
	199
	200	for_each_possible_cpu(cpu) {
	201	work = &per_cpu(sun4d_ipi_work, cpu);
	202	work->single = work->msk = work->resched = 0;
	203	}
	204	}
	205
	206	void sun4d_ipi_interrupt(void)
	207	{
494fc421	208	struct sun4d_ipi_work *work = this_cpu_ptr(&sun4d_ipi_work);
55dd23ec DH	209
	210	if (work->single) {
	211	work->single = 0;
	212	smp_call_function_single_interrupt();
	213	}
	214	if (work->msk) {
	215	work->msk = 0;
	216	smp_call_function_interrupt();
	217	}
	218	if (work->resched) {
	219	work->resched = 0;
	220	smp_resched_interrupt();
	221	}
	222	}
	223
4ba22b16 SR	224	/* +-------+-------------+-----------+------------------------------------+
	225	* \| bcast \| devid \| sid \| levels mask \|
	226	* +-------+-------------+-----------+------------------------------------+
	227	* 31 30 23 22 15 14 0
	228	*/
	229	#define IGEN_MESSAGE(bcast, devid, sid, levels) \
	230	(((bcast) << 31) \| ((devid) << 23) \| ((sid) << 15) \| (levels))
	231
	232	static void sun4d_send_ipi(int cpu, int level)
	233	{
	234	cc_set_igen(IGEN_MESSAGE(0, cpu << 3, 6 + ((level >> 1) & 7), 1 << (level - 1)));
	235	}
	236
	237	static void sun4d_ipi_single(int cpu)
55dd23ec DH	238	{
	239	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
	240
	241	/* Mark work */
	242	work->single = 1;
	243
	244	/* Generate IRQ on the CPU */
	245	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
	246	}
	247
4ba22b16	248	static void sun4d_ipi_mask_one(int cpu)
55dd23ec DH	249	{
	250	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
	251
	252	/* Mark work */
	253	work->msk = 1;
	254
	255	/* Generate IRQ on the CPU */
	256	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
	257	}
	258
4ba22b16	259	static void sun4d_ipi_resched(int cpu)
55dd23ec DH	260	{
	261	struct sun4d_ipi_work *work = &per_cpu(sun4d_ipi_work, cpu);
	262
	263	/* Mark work */
	264	work->resched = 1;
	265
	266	/* Generate IRQ on the CPU (any IRQ will cause resched) */
	267	sun4d_send_ipi(cpu, SUN4D_IPI_IRQ);
	268	}
	269
1da177e4	270	static struct smp_funcall {
17006e86	271	void *func;
1da177e4 LT	272	unsigned long arg1;
	273	unsigned long arg2;
	274	unsigned long arg3;
	275	unsigned long arg4;
	276	unsigned long arg5;
	277	unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */
	278	unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */
	279	} ccall_info __attribute__((aligned(8)));
	280
	281	static DEFINE_SPINLOCK(cross_call_lock);
	282
	283	/* Cross calls must be serialized, at least currently. */
17006e86	284	static void sun4d_cross_call(void *func, cpumask_t mask, unsigned long arg1,
66e4f8c0 DM	285	unsigned long arg2, unsigned long arg3,
66e4f8c0 DM	286	unsigned long arg4)
1da177e4	287	{
e54f8548	288	if (smp_processors_ready) {
1da177e4 LT	289	register int high = smp_highest_cpu;
	290	unsigned long flags;
	291
	292	spin_lock_irqsave(&cross_call_lock, flags);
	293
	294	{
e54f8548 SR	295	/*
	296	* If you make changes here, make sure
	297	* gcc generates proper code...
	298	*/
17006e86	299	register void *f asm("i0") = func;
1da177e4 LT	300	register unsigned long a1 asm("i1") = arg1;
	301	register unsigned long a2 asm("i2") = arg2;
	302	register unsigned long a3 asm("i3") = arg3;
	303	register unsigned long a4 asm("i4") = arg4;
66e4f8c0	304	register unsigned long a5 asm("i5") = 0;
1da177e4 LT	305
	306	__asm__ __volatile__(
	307	"std %0, [%6]\n\t"
	308	"std %2, [%6 + 8]\n\t"
	309	"std %4, [%6 + 16]\n\t" : :
	310	"r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5),
	311	"r" (&ccall_info.func));
	312	}
	313
	314	/* Init receive/complete mapping, plus fire the IPI's off. */
	315	{
1da177e4 LT	316	register int i;
1da177e4 LT	317
fb1fece5 KM	318	cpumask_clear_cpu(smp_processor_id(), &mask);
fb1fece5 KM	319	cpumask_and(&mask, cpu_online_mask, &mask);
e54f8548	320	for (i = 0; i <= high; i++) {
fb1fece5	321	if (cpumask_test_cpu(i, &mask)) {
1da177e4 LT	322	ccall_info.processors_in[i] = 0;
	323	ccall_info.processors_out[i] = 0;
	324	sun4d_send_ipi(i, IRQ_CROSS_CALL);
	325	}
	326	}
	327	}
	328
	329	{
	330	register int i;
	331
	332	i = 0;
	333	do {
fb1fece5	334	if (!cpumask_test_cpu(i, &mask))
66e4f8c0	335	continue;
e54f8548	336	while (!ccall_info.processors_in[i])
1da177e4	337	barrier();
e54f8548	338	} while (++i <= high);
1da177e4 LT	339
	340	i = 0;
	341	do {
fb1fece5	342	if (!cpumask_test_cpu(i, &mask))
66e4f8c0	343	continue;
e54f8548	344	while (!ccall_info.processors_out[i])
1da177e4	345	barrier();
e54f8548	346	} while (++i <= high);
1da177e4 LT	347	}
	348
	349	spin_unlock_irqrestore(&cross_call_lock, flags);
	350	}
	351	}
	352
	353	/* Running cross calls. */
	354	void smp4d_cross_call_irq(void)
	355	{
17006e86 BVA	356	void (*func)(unsigned long, unsigned long, unsigned long, unsigned long,
17006e86 BVA	357	unsigned long) = ccall_info.func;
c68e5d39	358	int i = hard_smp_processor_id();
1da177e4 LT	359
1da177e4 LT	360	ccall_info.processors_in[i] = 1;
17006e86 BVA	361	func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, ccall_info.arg4,
17006e86 BVA	362	ccall_info.arg5);
1da177e4 LT	363	ccall_info.processors_out[i] = 1;
	364	}
	365
1da177e4 LT	366	void smp4d_percpu_timer_interrupt(struct pt_regs *regs)
1da177e4 LT	367	{
0d84438d	368	struct pt_regs *old_regs;
c68e5d39	369	int cpu = hard_smp_processor_id();
62f08283	370	struct clock_event_device *ce;
1da177e4 LT	371	static int cpu_tick[NR_CPUS];
	372	static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd };
	373
0d84438d	374	old_regs = set_irq_regs(regs);
e54f8548	375	bw_get_prof_limit(cpu);
1da177e4 LT	376	bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */
	377
	378	cpu_tick[cpu]++;
	379	if (!(cpu_tick[cpu] & 15)) {
	380	if (cpu_tick[cpu] == 0x60)
	381	cpu_tick[cpu] = 0;
	382	cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4];
	383	show_leds(cpu);
	384	}
	385
62f08283	386	ce = &per_cpu(sparc32_clockevent, cpu);
1da177e4	387
62f08283 TK	388	irq_enter();
	389	ce->event_handler(ce);
	390	irq_exit();
1da177e4	391
0d84438d	392	set_irq_regs(old_regs);
1da177e4 LT	393	}
1da177e4 LT	394
4ba22b16 SR	395	static const struct sparc32_ipi_ops sun4d_ipi_ops = {
	396	.cross_call = sun4d_cross_call,
	397	.resched = sun4d_ipi_resched,
	398	.single = sun4d_ipi_single,
	399	.mask_one = sun4d_ipi_mask_one,
	400	};
	401
1da177e4 LT	402	void __init sun4d_init_smp(void)
	403	{
	404	int i;
1da177e4 LT	405
	406	/* Patch ipi15 trap table */
	407	t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m);
e54f8548	408
4ba22b16	409	sparc32_ipi_ops = &sun4d_ipi_ops;
e54f8548	410
1da177e4 LT	411	for (i = 0; i < NR_CPUS; i++) {
	412	ccall_info.processors_in[i] = 1;
	413	ccall_info.processors_out[i] = 1;
	414	}
	415	}